Memory device with laterally formed memory cells

Abstract

The invention relates to a memory device with laterally formed memory cells. A material stack may be formed that includes conductive layers between a plurality of dielectric layers, wherein the conductive layers and dielectric layers may form channels in sidewalls of the material stack. The channel may be filled with one or more materials, wherein a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the stack of materials that exposes a second side of at least one of the one or more materials. The opening may be used to replace a portion of the at least one material with a chalcogenide material, wherein an electrode material may be formed prior to replacing the portion of the at least one material with the chalcogenide material.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the invention name “Memory device having laterally formed memory cells”, application number 202280037225.7, and application date May 13, 2022.

[0003] Cross Reference

[0004] This patent application is a national phase application of International Patent Application No. PCT / US22 / 72318, entitled “MEMORY DEVICE WITH LATERALLY FORMED MEMORY CELLS,” filed by Graettinger et al. on May 13, 2022, and claims priority to U.S. Patent Application No. 17 / 332,628, entitled “MEMORY DEVICE WITH LATERALLY FORMED MEMORY CELLS,” filed by Graettinger et al. on May 27, 2021, the entire contents of each of which are expressly incorporated herein by reference.

[0005] The technical field relates to memory devices having laterally formed memory cells. Background Art

[0006] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, which are typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state into a memory device.

[0007] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-select memory, chalcogenide memory technology, etc. Memory cells may be volatile or non-volatile. Summary of the invention

[0008] A method is described. The method may include: forming a material stack including a conductive layer positioned between a first dielectric layer and a second dielectric layer, wherein the first dielectric layer, the second dielectric layer, and the conductive layer form a channel in a sidewall of the material stack; filling the channel with at least one material and a conductive material associated with a first electrode, wherein a first side of the first electrode is covered and a first side of the at least one material is exposed based at least in part on filling the channel with the at least one material; forming an opening through the at least one material exposing the conductive material and a second side of the at least one material; and replacing the at least one material with a chalcogenide material through the opening based at least in part on exposing the second side of the at least one material.

[0009] A method is described. The method may include: forming a channel in a sidewall of a material stack, the channel being bounded by a first dielectric layer, a second dielectric layer, and a conductive layer of the material stack; depositing a first material associated with a first electrode into the channel over the conductive layer and through a trench by the sidewall of the material stack; depositing a second material associated with a storage element into the channel over the first material and through the trench, wherein a first side of the first material is covered by the second material and the first side of the second material is exposed to the trench based at least in part on depositing the second material; depositing a third material associated with a second electrode into the channel over the second material and through the trench, wherein the first side of the second material is covered and the first side of the third material is exposed to the trench based at least in part on depositing the third material; forming an opening through the first, second, and third materials that exposes a second side of the second material; and replacing the second material with a chalcogenide material through the opening based at least in part on exposing the second side of the second material.

[0010] A method is described. The method may include: forming a channel in a sidewall of a material stack, the channel being bounded by a first dielectric layer, a second dielectric layer, and a conductive layer of the material stack; depositing a first material associated with a first electrode into the channel over the conductive layer and through a trench by the sidewall of the material stack; depositing a second material associated with a storage element into the channel over the first material and through the trench, wherein a first side of the first material is covered by the second material and exposed to the trench based at least in part on depositing the second material; forming a first opening through the first material and the second material to expose a second side of the second material; replacing the second material with a chalcogenide material to form the storage element through the first opening and based at least in part on exposing the second side of the second material, wherein the first side of the storage element is covered by a dielectric material and the second side of the storage element is exposed by the first opening; forming a second opening in the dielectric material, wherein the first side of the storage element is exposed by the second opening; and depositing a conductive material within the second opening and over the first side of the storage element to form a second electrode based at least in part on forming the second opening.

[0011] A method is described. The method may include: removing a first portion of a conductive layer positioned between a first dielectric layer and a second dielectric layer of a material stack, wherein a channel is formed in the material stack and a second portion of the conductive layer is exposed based at least in part on the removal of the first portion of the conductive layer; forming a first electrode on the second portion of the conductive layer and a second electrode opposite the first electrode, the first electrode and the second electrode forming at least a portion of a cavity; and after forming the first electrode and the second electrode, filling the cavity with a chalcogenide material to form a memory element.

[0012] An apparatus is described. The apparatus includes: a word line comprising a first conductive material; a first electrode comprising a second conductive material, the first electrode being positioned from a first side of the word line; a storage element comprising a chalcogenide material, the storage element being positioned from a first side of the first electrode and a first material layer; a second electrode comprising a third conductive material, the second electrode being positioned from a first side of the storage element and a second material layer positioned by the first material layer; and a bit line comprising a fourth conductive material, the bit line being positioned from a first side of the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example of a system supporting a memory device having laterally formed memory cells according to examples as disclosed herein is described.

[0014] Figure 2 An example of a memory die supporting a memory device having laterally formed memory cells according to examples as disclosed herein is illustrated.

[0015] Figure 3A and 3B Various views of a vertical memory array having horizontally disposed memory cells are illustrated according to examples as disclosed herein.

[0016] Figure 4A and 4B Various views illustrating material structures associated with laterally formed memory cells according to examples as disclosed herein.

[0017] Figure 5 Various views illustrating material structures associated with laterally formed memory cells according to examples as disclosed herein.

[0018] Figure 6 Various views illustrating material structures associated with laterally formed memory cells according to examples as disclosed herein.

[0019] Figure 7 Different stages of a process for laterally forming an electrode of a material structure according to examples as disclosed herein are illustrated.

[0020] Figure 8 Different stages of a process for laterally forming a storage element of a material structure according to examples as disclosed herein are illustrated.

[0021] Fig. 9 Different stages of a process for laterally forming an electrode of a material structure according to examples as disclosed herein are illustrated.

[0022] Fig.10 Various views illustrating material structures associated with laterally formed memory cells according to examples as disclosed herein.

[0023] Fig.11 Different stages of a process for laterally forming an electrode of a material structure according to examples as disclosed herein are illustrated.

[0024] Fig.12 Different stages of a process for laterally forming an electrode of a material structure according to examples as disclosed herein are illustrated.

[0025] Fig.13 Different stages of a process for laterally forming a storage element of a material structure according to examples as disclosed herein are illustrated.

[0026] Fig.14ADifferent stages of a process for laterally forming an electrode of a material structure according to examples as disclosed herein are illustrated.

[0027] Fig. 14B Various views illustrating material structures associated with laterally formed memory cells according to examples as disclosed herein.

[0028] Fig.15 Different stages of a process for laterally forming an electrode of a material structure according to examples as disclosed herein are illustrated.

[0029] Fig.16 Different stages of a process for laterally forming a storage element of a material structure according to examples as disclosed herein are illustrated.

[0030] Figures 17 to 20

[0013] Shown are flow charts illustrating one or several methods of supporting a memory device having laterally formed memory cells according to examples as disclosed herein. DETAILED DESCRIPTION

[0031] A vertical memory array may include vertically stacked horizontally disposed memory cells (e.g., with an intervening layer, such as a dielectric layer separating the vertically stacked horizontally disposed memory cells). A process for forming horizontally disposed memory cells in a vertical memory array may include creating a horizontally disposed cavity and filling the cavity from the inside out. For example, the process may involve filling a rear portion of the cavity by depositing a first material on a rear wall of the cavity, filling a second portion of the cavity by depositing a second material on the first material, and filling a third portion of the cavity by depositing a third material on the second material.

[0032] Larger cells may be associated with larger programming and leakage currents (e.g., four times the programming current and leakage current may be associated with a cell that is three times larger than another cell). Thus, a process for forming horizontally disposed memory cells having smaller dimensions may be desirable. However, filling the cavity from the inside out to form a horizontally disposed memory cell may present challenges when forming a memory cell having smaller dimensions (e.g., having a diameter or width in the range of 20 nanometers). In some examples, the process for creating a vertical opening aligned with the cavity for accessing the cavity may be subject to photolithographic processes and tight tolerances. Furthermore, as the size of the memory cell (and therefore the cavity) decreases, proper alignment of the vertical opening and cavity may be more difficult to obtain. Thus, a process for forming a vertical memory array involving filling the cavity from the inside out to form the memory cell may be limited to larger memory cell sizes. Additionally, filling the cavity from the inside out may involve forming an electrode after forming the storage element. To avoid damaging the storage element, a low temperature may be desirable to form the electrode, which may be unfeasible or may hinder the formation of the electrode.

[0033] In order to simplify the process for forming memory cells in a vertical array and to enable the formation of smaller memory cells, a formation process involving exposing and filling the cavity from the lateral side (rather than from the inside out) can be established. In some examples, the formation process can include depositing one or more placeholder materials for components of the memory cell into a channel formed by a material layer, such as via a trench. The formation process can also include forming a vertical opening that exposes the lateral side of the one or more placeholder materials. The vertical opening can be used to replace a portion of the one or more placeholder materials with a material of a corresponding component of the memory cell (e.g., an electrode or a storage element). In some examples, the formation process can replace a subset of the one or more placeholder materials with a material associated with an electrode before replacing the placeholder material of the one or more placeholder materials with a material associated with a storage element (which can be referred to as an "electrode first" filling process, in which the electrode structure is formed before the memory cell structure), which can minimize adverse effects that may otherwise occur when the memory cell structure is formed before the electrode structure, as well as other advantages.

[0034] By creating a vertical opening that exposes the lateral sides of the placeholder material, a larger opening can be used and operations for aligning the vertical opening with the cavity can be avoided. In addition, by exposing the lateral sides of the placeholder material, the placeholder material associated with the electrode can be replaced before the placeholder material associated with the storage element (e.g., thereby enabling the electrode to be formed using higher temperatures without damaging the storage element). In addition, forming the storage element from a lateral direction can prevent the sides of the storage element that intersect the conductive path through the storage element from being exposed to formation processes that may change the characteristics of the sides of the storage element.

[0035] Features of the present disclosure are first described in the context of memory systems, dies, and arrays. Features of the present disclosure are also described in the context of different perspectives of material structures and stages of one or more formation processes. These and other features of the present disclosure are further illustrated and described with reference to flow charts associated with memory devices having laterally formed memory cells.

[0036] Figure 1 An example of a system 100 supporting a memory device having laterally formed memory cells according to examples as disclosed herein is illustrated. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0037] System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data for one or more other components of system 100.

[0038] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system-on-a-chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or any combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0039] Memory device 110 may be a stand-alone device or component operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme used to modulate a signal; various pin configurations for communicating a signal; various form factors for the physical packaging of host device 105 and memory device 110; clock signaling and synchronization between host device 105 and memory device 110; timing conventions; or other factors.

[0040] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 may act as an auxiliary or dependent device for host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0041] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (such as one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using a bus 135.

[0042] The processor 125 is operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 may be implemented by or be part of the processor 125.

[0043] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0044] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more sectors), wherein each memory cell is operable to store at least one data bit. A memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0045] The memory die 160 may be an example of a two-dimensional (2D) memory cell array or may be an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may include a single memory array 170. A 3D memory die 160 may include two or more memory arrays 170 that may be stacked on top of each other or positioned adjacent to each other (e.g., relative to a substrate). In some examples, the memory arrays 170 in a 3D memory die 160 may be referred to as groups, tiers, layers, or dies. A 3D memory die 160 may include any number of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high). In some 3D memory dies 160, different groups may share at least one common access line so that some groups may share one or more of the row lines or column lines.

[0046] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0047] The local memory controller 165 (e.g., local to the memory die 160) may include circuits, logic, or components operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., to receive or transmit data or commands or both). In some examples, the memory device 110 may not include a device memory controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or any combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0048] The external memory controller 120 is operable to enable the transfer of one or more of information, data, or commands between a component of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or the functions thereof described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or the functions thereof described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0049] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium that carries information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path that is operable to carry a signal. For example, channel 115 may include a first terminal that includes one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be operable to serve as part of a channel.

[0050] The channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, the channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or any combination thereof. In some examples, signaling may be conveyed via the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on either the rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both the rising and falling edges of a clock signal).

[0051] The memory die 160 may include a memory array formed of a material stack (which may also be referred to as a material structure). In some examples, the material stack includes a conductive layer between a plurality of dielectric layers, wherein the conductive layer and the dielectric layer may form a channel in the sidewalls of the material stack. The channel may be filled with one or more materials (e.g., a conductive material, one or more placeholder materials, or any combination thereof), wherein a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second (e.g., lateral) side of at least one of the one or more materials (e.g., a placeholder material for a memory element). The opening may be used to replace a portion of the at least one material with a chalcogenide material (e.g., to form a memory element).

[0052] Figure 2 An example of a memory die 200 supporting a memory device having laterally formed memory cells according to an example as disclosed herein is illustrated. The memory die 200 may be a reference Figure 11 . An example of a memory die 160 is described. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, which may each be programmed to store a different logical state (e.g., a set of two or more possible states of programming state). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell 205) may be operable to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11). In some examples, the memory cells 205 may be arranged in an array, such as with reference to FIG. Figure 1 Memory array 170 is described.

[0053] The memory cell 205 may use a configurable material (which may be referred to as a memory element, a memory storage element, a material element, a material storage element, a material portion, or a polarity write material portion, etc.) to store a logic state. The configurable material of the memory cell 205 may refer to a chalcogenide-based storage component, such as the one described in reference to FIG. Figure 3A and 3B For example, chalcogenide storage elements can be used in phase change memory (PCM) cells, fixed-limit memory cells, or self-select memory cells.

[0054] Memory die 200 may include access lines (e.g., row lines 210 and column lines 215) arranged in a pattern (e.g., a grid-like pattern). The access lines may be formed of one or more conductive materials. In some examples, row lines 210 may be referred to as word lines. In some examples, column lines 215 may be referred to as digit lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, may be interchangeable without loss of understanding or operation. Memory cells 205 may be positioned at the intersection of row lines 210 and column lines 215.

[0055] Operations such as reading and writing can be performed on the memory cell 205 by activating or selecting an access line, such as one or more of the row lines 210 or the column lines 215. By biasing the row lines 210 and the column lines 215 (e.g., applying a voltage to the row lines 210 or the column lines 215), a single memory cell 205 can be accessed at their intersections. The intersection of the row lines 210 and the column lines 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of the memory cell 205. The access line can be a conductive line coupled to the memory cell 205 and can be used to perform access operations on the memory cell 205.

[0056] Access to memory cells 205 may be controlled by row decoder 220 or column decoder 225. For example, row decoder 220 may receive a row address from local memory controller 260 and activate row lines 210 based on the received row address. Column decoder 225 may receive a column address from local memory controller 260 and may activate column lines 215 based on the received column address.

[0057] The sensing component 230 is operable to detect the state of the memory cell 205 (e.g., material state, resistance, threshold state) and determine the logic state of the memory cell 205 based on the stored state. The sensing component 230 may include one or more sense amplifiers to amplify or otherwise convert the signal caused by accessing the memory cell 205. The sensing component 230 may compare the signal detected from the memory cell 205 with a reference 235 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sensing component 230 (e.g., to the input / output 240), and the detected logic state may be indicated to another component of the memory device including the memory die 200.

[0058] The local memory controller 260 can control access to the memory cell 205 through various components (eg, the row decoder 220, the column decoder 225, the sensing component 230). The local memory controller 260 can be a reference Figure 1 1. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 230 can be co-located with the local memory controller 260. The local memory controller 260 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the command or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 260 can generate row signals and column address signals to activate the target row line 210 and the target column line 215. The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may vary and may be different for the various operations discussed in operating the memory die 200 .

[0059] The local memory controller 260 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 is operable to perform other access operations not listed here or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0060] The memory die 200 may be formed of a material stack (which may also be referred to as a material structure). In some examples, the material stack includes a conductive layer between multiple dielectric layers, wherein the conductive layer and the dielectric layer may form a channel in the sidewalls of the material stack. The channel may be filled with one or more materials (e.g., conductive material, one or more placeholder materials, or any combination thereof), wherein a first side of an outermost material of the one or more materials may be exposed. An opening may be formed in the material stack that exposes a second (e.g., lateral) side of at least one of the one or more materials (e.g., a placeholder material for a memory element). As part of a process for forming one or more memory cells 205, the opening may be used to replace a portion of the at least one material with a chalcogenide material (e.g., to form a memory element).

[0061] Figure 3A and 3B 1 and 2 illustrate multiple views of a vertical memory array having horizontally arranged memory cells according to examples as disclosed herein. Figure 1 and 2 Examples of portions of a memory array or memory die are described.

[0062] The first perspective view 301-a shows a three-dimensional view of the memory array 300. The memory array 300 can include a first group 305 and a second group 310 of memory cells positioned above a substrate 335. The first group 305 can be positioned above the second group 310. Although the example of the memory array 300 includes three groups (including the first group 305 and the second group 310), the memory array 300 can include any number of groups (e.g., one group, two groups, or more than three groups).

[0063] The memory array 300 may also include row lines 210-a, row lines 210-b, column lines 215-a, and column lines 215-b, which may be as shown in FIG. Figure 2Examples of row lines 210 and column lines 215 are described. In some examples, row lines 210 may be referred to as word lines, and column lines 215 may be referred to as bit lines or digit lines. Column lines 215 may be formed as vertical pillars and extend orthogonal (or perpendicular) to a plane defined by substrate 335. Row lines 210 may extend parallel to a plane defined by substrate 335.

[0064] A first set of memory cells in the first group 305 may include one or more chalcogenide materials in laterally disposed pillars between a set of access lines (e.g., between row line 210-a and column line 215-a or between row line 210-a and column line 215-b), and a second set of memory cells in the first group 305 may include one or more chalcogenide materials in laterally oriented pillars between another set of access lines (e.g., between column line 215-a and row line 210-b or between column line 215-b and row line 210-b). For example, a single laterally oriented pillar (which may also be referred to as a bridge or rail) extending between the access lines may include a first electrode, a first chalcogenide material (e.g., a selector component), a second electrode, a second chalcogenide material (e.g., a storage element), a third electrode, or any combination thereof. To increase visibility and clarity of the depicted features, although Figure 3A and 3B Some of the elements contained therein are labeled with numerical indicators, but other corresponding elements are not labeled, although they are the same or would be understood to be similar.

[0065] The first memory cell of the first group 305 may include a first electrode 325-a, a storage element 320-a, a second electrode 330-a, or any combination thereof. The second memory cell of the first group 305 may include a first electrode 325-b, a storage element 320-b, a second electrode 330-b, or any combination thereof. The storage element 320 may be an example of a chalcogenide material, such as a phase change storage element, a fixed-limit storage element, or a self-select storage element. In some examples, the memory cells of the first group 305 may have a common conductive line so that corresponding memory cells of the first group 305 (e.g., a first memory cell and a second memory cell) may share a column line 215. For example, the first electrode 325-b of the second memory cell and the first electrode 325-a of the first memory cell may be combined with the column line 215-a. In some examples, the electrode contacting the column line 215 may be referred to as a top electrode (e.g., the first electrode 325) and the electrode contacting the row line 210 may be referred to as a bottom electrode (e.g., the second electrode 330). In some examples, the direction of the current path from the first electrode 325 through the memory element 320 to the second electrode 330 is parallel to the plane defined by the substrate 335 .

[0066] In some examples, the memory cells in the first group 305 can share a common row line while being connected to different column lines. Additionally, in some examples, the memory cells of the first group 305 can share a column line with the memory cells of the second group 310. For example, the memory cells in the first group 305 can share a column line 215 with the memory cells in the second group 310.

[0067] In some examples, the material of the storage element 320 may include a chalcogenide material or other alloys including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some examples, a SAG alloy may also include silicon (Si) and such a chalcogenide material may be referred to as a SiSAG alloy. In some examples, a SAG alloy may include silicon (Si) or indium (In) or any combination thereof, and such chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, respectively, or any combination thereof. In some examples, the chalcogenide glass may include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0068] In some examples, the storage element 320 may be an example of a phase change memory cell. In such examples, the material used in the storage element 320 may be based on an alloy (such as the alloys listed above) and may be operated so as to undergo a phase change (e.g., at least a portion of the material may change phase) or change to a different physical state during normal operation of the memory cell. For example, a phase change memory cell may have an amorphous state (e.g., a relatively disordered atomic configuration) and a crystalline state (e.g., a relatively ordered atomic configuration).

[0069] Phase change memory cells can exhibit significant differences between the resistance of a crystalline state and an amorphous state of a phase change material (which can be a chalcogenide material). The material in the crystalline state can have atoms arranged in a periodic structure, which can result in a relatively low resistance. In contrast, the material in the amorphous state can have no periodic atomic structure or a relatively small periodic atomic structure, which can have a relatively high resistance.

[0070] The difference in resistance value between the amorphous state and the crystalline state of the material can be substantial. For example, a material in an amorphous state can have a resistance that is one or more orders of magnitude greater than the resistance of the material in its crystalline state. In some examples, the material can be partially amorphous and partially crystalline, and the resistance can have a value somewhere between the resistance of the material in either a fully crystalline or fully amorphous state. In such examples, the material can be used to store more than two logic states (e.g., three or more logic states).

[0071] During a programming (writing) operation of a phase change memory cell (e.g., first electrode 325-a, storage element 320-a, second electrode 330-a), various parameters of a programming pulse may affect (e.g., determine, set, program) a particular behavior or characteristic of the material of the storage element 320, such as a threshold voltage of the material or a resistance of the material. To program a low resistance state (e.g., a relatively crystalline state) in a phase change memory cell, a programming pulse may be applied that heats or melts the material of the storage element 320, which may be associated with at least temporarily forming a relatively disordered (e.g., amorphous) atomic arrangement. The amplitude of the programming pulse may be reduced (e.g., relatively slowly) over a duration to allow the material to form a crystalline structure as it cools, thereby forming a stable crystalline material state.

[0072] To program a high resistance state (e.g., a relatively amorphous state) in a phase change memory cell, a programming pulse may be applied that heats and / or melts the material of the storage element 320. The amplitude of the programming pulse may be reduced more rapidly than the programming pulse for the low resistance state. In such cases, the material may cool with atoms in a more disordered atomic arrangement because the atoms cannot form a crystalline structure until the material reaches a stable state, thereby forming a stable amorphous material state. The difference in the threshold voltage or resistance of the material of the storage element 320 depending on the logical state stored by the material of the storage element 320 may correspond to a read window of the storage element 320. In some cases, portions of the storage element may undergo material changes associated with the logical state. In some examples, such as for limiting a memory cell or a self-select memory cell, some or all of the set of logical states supported by the memory cell may be associated with the amorphous state of the chalcogenide material (e.g., the material in a single state may be operable to store different logical states).

[0073] In some examples, the horizontally arranged memory cell may be an example of a self-select memory cell. In such examples, the material used in the storage element 320 may be based on an alloy (e.g., the alloys listed above). The storage element 320 may be operated so as to undergo changes to different physical states during normal operation of the memory cell. For example, the self-select memory cell may be programmed to have a high threshold voltage state or a low threshold voltage state. The high threshold voltage state may correspond to a first logical state (e.g., a reset state) and the low threshold voltage state may correspond to a second logical state (e.g., a set state). The difference in the threshold voltage of the material of the storage element 320 depending on the logical state stored by the material of the storage element 320 (e.g., the difference between the threshold voltage when the material stores a logical state "0" and the threshold voltage when the material stores a logical state "1") may correspond to a read window of the storage element 320.

[0074] With a programmable threshold voltage, when a voltage applied across the storage element 320 exceeds the programmed threshold voltage, current may flow through the storage element 320. Thus, an operation for accessing one self-selected memory cell may not interfere with the state of another self-selected memory cell (e.g., which has a higher threshold voltage) coupled to a common access line. Thus, the self-selected memory cell may not be coupled with a selection element (e.g., a transistor or a diode) for isolating the self-selected memory cell from a voltage applied to electrically coupled memory cells.

[0075] The architecture of the memory array 300 may be referred to as a cross-point architecture, in which memory cells are formed at the topological intersections between the row lines 210 and the column lines 215. This cross-point architecture may provide relatively high density data storage at a lower production cost than other memory architectures. For example, the cross-point architecture may have memory cells of reduced area and thus increased memory cell density than other architectures. For example, the architecture may have a 4F2 memory cell area, where F is the minimum feature size, compared to other architectures (e.g., architectures with three-terminal selector elements) having a 6F2 memory cell area. For example, a DRAM may use a transistor (which is a three-terminal device) as a selector element for each memory cell and may have a larger memory cell area than a cross-point architecture.

[0076] although Figure 3A The example of shows a memory group having two laterally adjacent layers of memory cells, but other configurations are possible. In some examples, the memory group includes a single layer disposed laterally, which may be referred to as a two-dimensional memory. Furthermore, in some cases, Figure 3A Shown or referenced in Figure 3A The elements described may be electrically coupled to each other as shown or described but physically reconfigured (eg, memory element 320 and possibly select elements or electrodes may be electrically in series between row and column lines 210, 215, but not necessarily in a pillar or stack).

[0077] The second perspective view 301-b shows a cross-sectional view of the memory array 300 viewed from the front of the memory array 300. The second perspective view 301-b shows additional material layers included in the memory array 300 that are not depicted in the first perspective view 301-a (to increase visibility and clarity of the depicted features). The second perspective view 301-b shows the dielectric layer 345 between the row lines 210. The second perspective view 301-b also shows the second substrate 340 on the opposite side of the memory array 300 relative to the substrate 335.

[0078] The architecture of memory array 300 may be referred to as a cross-point architecture, a vertical memory architecture, or both, and memory array 300 may be referred to as a vertical memory array. A vertical memory array may be formed by staggered deposition of conductive and insulating material layers stacked one on top of the other; forming trenches (e.g., in a serpentine manner by etching) through the staggered material layers; and using the trenches to form horizontally disposed memory cells relative to a substrate (e.g., substrate 335 or second substrate 340) by one or more deposition operations. In some examples, conductive contacts 350 are embedded within substrate 335 and may be used to access access lines (e.g., column lines 215). In some examples, a first material layer (e.g., an insulating material layer including dielectric layer 345) may be formed on top of substrate 335, a second material layer (e.g., a conductive material layer including row lines 210) may be formed on top of the first material layer, a third material layer (e.g., an insulating material layer including another dielectric layer) may be formed on top of the second material layer, and so on. After forming the interleaved material layers, portions of the material layers may be removed (eg, using an etching process) to form trenches.

[0079] In some examples, before forming the column lines 215, the trenches may extend through the space occupied by the column lines 215. In some examples, the trenches may be used to separate the conductive and insulating layers into two parts and horizontally (e.g., isotropically) etch away portions of the remaining conductive material layer, thereby forming a plurality of row lines 210 and channels in one or more sidewalls of the trenches. Before forming the storage element 320, the channels may extend through the space occupied by the storage element 320. The trenches and channels may then be filled with a filling material (e.g., with an insulating material, a dielectric material). The filling material may use an insulating material different from the dielectric layer 345.

[0080] A vertical opening (which may also be referred to as a via) may be created in a portion of the filled trench (e.g., above the conductive contact 350). The vertical opening of the vertical opening may be formed in the space occupied by the column line 215 before forming the column line 215. The vertical opening may be used to remove portions of the fill material, thereby forming a plurality of cavities separated from each other (e.g., by insulating material) in the horizontal, vertical, and inward / outward directions. The cavity may be formed in the space occupied by the memory element 320 before forming the memory element 320.

[0081] The cavities may then be filled through the vertical openings (e.g., from the inside out). In some examples, a chalcogenide material may be used to fill the plurality of cavities (forming the memory element 320), and a conductive material may be used to fill the vertical openings remaining after the cavities are filled (forming the column lines 215). In some examples, instead of filling the plurality of cavities with a chalcogenide material, a conductive material may be deposited into the plurality of cavities (forming the second electrode 330), then the chalcogenide material may be deposited into the plurality of cavities (forming the memory element 320), and then another conductive material may be used to fill the remainder of the cavities (forming the first electrode 325). In some examples, the second electrode 330 may contact the row line 210, and the first electrode 325 may contact the column line 215.

[0082] Thus, the process for forming a vertical memory array can result in a vertical stack of groups of horizontally disposed memory cells separated (e.g., isolated) from each other by insulating materials (e.g., dielectric materials). As described herein, the horizontally disposed memory cells can include a second electrode 330, a storage element 320, and a first electrode 325. In some examples, the horizontally disposed memory cells can be examples of self-selected memory cells. The self-selected memory cells can be programmed to have a high threshold voltage state or a low threshold voltage state, and no measures can be taken to isolate the self-selected memory cells from voltages applied to other electrically coupled memory cells.

[0083] Larger cells may be associated with larger programming and leakage currents (e.g., four times the programming current and leakage current may be associated with a cell that is three times larger than another cell). Thus, a process for forming horizontally disposed memory cells having smaller dimensions may be desirable. However, filling the cavity from the inside out to form a horizontally disposed memory cell may present challenges when forming a memory cell having smaller dimensions (e.g., having a diameter in the range of 20 nanometers). In some examples, the process for creating a vertical opening aligned with the cavity for accessing the cavity may be subject to photolithographic processes and tight tolerances. Furthermore, as the size of the memory cell (and therefore the cavity) decreases, proper alignment of the vertical opening and cavity may be more difficult to obtain. Thus, a process for forming a vertical memory array involving filling the cavity from the inside out to form the memory cell may be limited to larger memory cell sizes. Additionally, filling the cavity from the inside out may involve forming an electrode after forming the storage element. To avoid damaging the storage element, a low temperature may be desirable to form the electrode, which may be unfeasible or may hinder the formation of the electrode.

[0084] In order to simplify the process for forming memory cells in a vertical array and to enable the formation of smaller memory cells, a formation process involving exposing and filling the cavity from the lateral side (rather than from the inside out) can be established. In some examples, the established formation process can include operations for depositing one or more placeholder materials for components of the memory cell into a channel formed by a material layer via a trench. The formation process can also include operations for forming a vertical opening that exposes the lateral side of the one or more placeholder materials. The vertical opening can be used to replace a portion of the one or more placeholder materials with the material of a corresponding component of the memory cell (e.g., an electrode or a storage element). In some examples, the formation process can replace a subset of the one or more placeholder materials with a material associated with an electrode before replacing the placeholder material of the one or more placeholder materials with a material associated with a storage element (which can be referred to as an "electrode first" filling process).

[0085] By creating vertical openings that expose lateral sides of the placeholder material, larger openings can be used and operations for aligning the vertical openings with the cavity can be avoided. In addition, by exposing the lateral sides of the placeholder material, the placeholder material associated with the electrode can be replaced before the placeholder material associated with the storage element (e.g., thereby enabling the electrode to be formed using higher temperatures without damaging the storage element).

[0086] Figure 4A and 4B 4. A plurality of views illustrating material structures associated with laterally formed memory cells according to examples as disclosed herein. A first perspective view 401 depicts a memory cell for forming a memory array (eg, Figure 3A and 3B 4. A top view of a material structure 400 (e.g., a memory array 300) of FIG. 404 is shown in FIG. 405. A second perspective view 402 depicts a cross-sectional view of the material structure 400 obtained by omitting (e.g., cutting) the material structure 400 along line B from the top of the material structure 400 to the bottom of the material structure 400, viewing the exposed section in the direction of line A. Dashed lines 411 running in a serpentine manner along the dielectric material 407 and the openings 409 may represent previously formed trenches.

[0087] The material structure 400 may include a conductive material 405, a dielectric material 407, and an opening 409. In some examples, the conductive material 405 may be a conductive material (e.g., tungsten) used to form a word line. In addition, the dielectric material 407 may be an insulating material (e.g., silicon oxide) and may be used as a placeholder for subsequent openings that may be used to form a memory cell. The opening 409 may be a vertical opening extending from the top of the material structure 400 to the substrate 435 at the bottom of the material structure 400. The material structure 400 may also include a second substrate 445 at the top of the material structure 400. In some examples, the opening 409 may be used to form a conductive layer (e.g., conductive layer 410) through the material structure 400. In some examples, the conductive layer may correspond to a word line. A dielectric layer (e.g., dielectric layer 440) may also be formed when the conductive layer is formed. In some examples, a conductive contact 450 may be embedded in the substrate 435 at the bottom of the cross section shown in the second perspective view 402.

[0088] Figure 4B The same cross-sectional view as the second perspective view 402 of the material structure 400 is illustrated after removing portions of the dielectric material 407 and portions of the conductive layer. In some examples, one or more operations (e.g., wet etching, dry etching, photolithography) can be used to remove the pillars of the dielectric material 407, thereby exposing the dielectric and conductive layers. After exposing the dielectric and conductive layers, the opening 460 can be used to pull back the conductive layer (e.g., conductive layer 410) from the dielectric layer (e.g., first dielectric layer 440-1) so that the edge of the conductive layer is offset from the dielectric layer (e.g., by between 20 nanometers and 40 nanometers). In some examples, the conductive layer, along with the plurality of dielectric layers, forms a channel extending through the material structure 400 in a direction extending from the front of the material structure 400 to the back of the material structure 400 (e.g., into the page). For example, the conductive layer 410, the first dielectric layer 440-1, and the second dielectric layer 440-2 can form a channel 455.

[0089] Figure 5Multiple views of a material structure associated with a laterally formed memory cell according to examples as disclosed herein are illustrated. A first perspective view 501 depicts a three-dimensional view of a material structure 500 with an exposed cross section obtained by omitting (e.g., cutting) the material structure 500 from the top of the material structure 500 to the bottom of the material structure 500 and from the front of the material structure 500 to the back of the material structure 500. A second perspective view 502 depicts a cross-sectional view of the material structure 500 obtained by omitting (e.g., cutting) the material structure 500 from the top of the material structure 500 to the bottom of the material structure 500 and viewing the exposed cross section from the front of the material structure 500. A third perspective view 503 depicts another cross-sectional view of the material structure 500 obtained by omitting (e.g., cutting) the material structure 500 from the front of the material structure 500 to the back of the material structure 500 and viewing the exposed cross section from the top of the material structure 500.

[0090] The cross section of the third perspective view 503 may correspond to the dashed line through the cross section of the second perspective view 502, and the cross section of the second perspective view 502 may correspond to the dashed line through the cross section of the third perspective view 503. In some examples, the material structure 500 may be used to form a memory array and may be an example of a material structure, such as reference Figure 4A or as described in 4B.

[0091] In some examples, the opening (e.g., Figure 4B The opening 460 of the material structure 500 is filled with one or more materials (e.g., Figure 4B In some examples, the first material 530 may be formed in one or more channels (e.g., on the back wall thereof). The first material 530 may fill the inner portion of the channel, thereby covering the exposed surface of the one or more word lines 510. In some examples, the first material 530 is a conductive material (e.g., carbon) and is associated with (or forms) forming a first electrode (e.g., a bottom electrode). In some examples, forming the first material 530 in the channel includes depositing a large amount of the first material into the opening so that the channel is completely filled with the first material and the sides of the opening are covered with the first material.

[0092] Next, portions of the first material may be removed such that the remaining portions of the first material correspond to the first material 530 within the channel. In some examples, the first material 530 may extend from a front portion of the material structure 500 to a back portion of the material structure 500, as shown in the first perspective view 501 and the third perspective view 503. Furthermore, a first side of the first material 530 may be exposed to the opening after forming the first material 530. In some examples, the temperature associated with forming the first material 530 is approximately 400 degrees Celsius. In some examples, the thickness of the first material 530 (extending away from the word line 510) may be between 2 nanometers and 5 nanometers.

[0093] After forming the first material 530 in the channel, a second material 540 may be formed in the channel (e.g., on the first material 530). The second material 540 may fill an interior portion of the channel, thereby covering the exposed surface of the first material 530. In some examples, the second material 540 is a sacrificial (or placeholder) material (e.g., silicon nitride) and is associated with forming a storage element. In some examples, the second material 540 is an insulating material. In some examples, forming the second material 540 in the channel includes depositing a large amount of the second material into the opening such that the remaining portion of the channel is completely filled with the second material and the sides of the opening are covered by the second material.

[0094] Next, portions of the second material may be removed such that the remaining portions of the second material correspond to the second material 540 within the channel. In some examples, the second material 540 may extend from the front of the material structure 500 to the back of the material structure 500, as shown in the first perspective view 501 and the third perspective view 503. In addition, the first side of the first material 530 may be covered and the first side of the second material 540 may be exposed to the opening after forming the second material 540. In some examples, the thickness of the second material 540 (extending away from the word line 510) may be between 15 nanometers and 25 nanometers.

[0095] After forming the second material 540 in the channel, a third material 545 can be formed in the channel (e.g., on the second material 540). The third material 545 can fill the interior portion of the channel, thereby covering the exposed surface of the second material 540. In some examples, the third material 545 is a sacrificial (or placeholder) material (e.g., aluminum oxide) and is associated with forming a second electrode (e.g., a top electrode). In some examples, the third material 545 is an insulating material. In some examples, forming the third material 545 in the channel includes depositing a large amount of the third material into the opening so that the remaining portion of the channel is completely filled with the third material and the sides of the opening are covered by the third material.

[0096] Next, portions of the third material may be removed such that the remaining portions of the third material correspond to the third material 545 within the channel. In some examples, the third material 545 may extend from the front of the material structure 500 to the back of the material structure 500, as shown in the first perspective view 501 and the third perspective view 503. In addition, the first side of the second material 540 may be covered and the first side of the third material 545 may be exposed to the opening after forming the third material 545. In some examples, the thickness of the third material 545 (extending away from the word line 510) may be between 5 nanometers and 10 nanometers.

[0097] After forming the third material 545 in the channel, the opening (or trench) for accessing the channel may be filled with a dielectric material 547. Thus, a first side of the third material 545 may be covered by the dielectric material 547. In some examples, the dielectric material 547 is or includes an oxide material.

[0098] Figure 6 Illustrated are multiple views of a material structure associated with a laterally formed memory cell according to examples as disclosed herein. A first perspective view 601 depicts a cross-sectional view of the material structure 600 obtained by omitting (e.g., cutting) the material structure 600 from the front of the material structure 600 to the back of the material structure 600 and viewing the exposed cross-section from the top of the material structure 600. A second perspective view 602 depicts another cross-sectional view of the material structure 600 obtained by omitting (e.g., cutting) the material structure 600 from the top of the material structure 600 to the bottom of the material structure 600 and viewing the exposed cross-section from the front of the material structure 600.

[0099] The cross section of the first perspective view 601 may correspond to the dashed line (labeled as B) passing through the cross section of the second perspective view 602, and the cross section of the second perspective view 602 may correspond to the dashed line (labeled as B) passing through the cross section of the first perspective view 601. In addition, Figure 5 The cross section of the second perspective view 502 may correspond to the dashed line (labeled A) passing through the cross section of the first perspective view 601 .

[0100] In some examples, material structure 600 may be used to form a memory array and may be an example of a material structure, as described with reference to FIGS. 4 and 5. Material structure 600 may include word line 610, first material 630, second material 640, third material 645, and dielectric material 647. Figure 5, one or more openings 650 can be formed in material structure 600. Openings 650 can extend from the top of material structure 600 to the bottom of material structure 600 (e.g., to the substrate). Furthermore, the openings can expose a second side of one or more of first material 630, second material 640, and third material 645. In some examples, the second side can be referred to as a lateral side.

[0101] In some examples, the first material 630 is a conductive material and forms a bottom electrode. In some examples, an opening (e.g., a first opening 650-1) is formed that exposes the second side of the first material 630, the second side of the second material 640, and the second side of the third material 645. In such examples, the first material 630 can be broken across the material structure 600, thereby forming multiple electrodes (e.g., bottom electrodes) that each contact a corresponding group of one or more storage elements. In other examples, an opening (e.g., a second opening 650-2) is formed that exposes the second side of the second material 640 and the second side of the third material 645. In such examples, the first material 630 can extend across the material structure 600, thereby forming a single electrode that contacts multiple storage elements.

[0102] In some examples, forming the opening 650 may include performing a first etching operation (e.g., dry etching) to remove the dielectric material 647 and a second etching operation (e.g., wet etching) to remove the third material 645 and the second material 640. In some examples, the second etching operation is divided into two operations, for example, a first etching operation (e.g., wet etching) to remove the third material 645 and a second etching operation to remove the second material 640. In some examples, forming the opening 650 includes a third etching operation (e.g., wet etching) to remove the first material 630 (e.g., to form the first opening 650-1). In such cases, the initial opening may have a smaller size than the subsequent opening 650 (e.g., the length of the initial opening may be 25 nanometers smaller).

[0103] By exposing lateral sides of the first material 630, the second material 640, the third material 645, or any combination thereof, the process for forming the material structure 600 may be able to form specific cavities for different memory components (instead of one cavity for multiple memory components). In addition, the process for forming the material structure 600 may be able to form memory components in a desired order (rather than an order dictated by filling the cavity from the inside out). For example, the process for forming the material structure 600 may be configured to form an electrode before forming a chalcogenide component.

[0104] Figure 7The different stages of a process for laterally forming electrodes of a material structure according to examples as disclosed herein are illustrated. The first stage 701 shows the stages of the formation process associated with forming a cavity (e.g., cavity 755) for forming an electrode (e.g., top electrode 725). The second stage 702 shows the stages of the formation process associated with filling the cavity with a conductive material. The third stage 703 shows the stages of the formation process associated with removing excess portions of the conductive material to obtain a set of electrodes (e.g., top electrode 725).

[0105] In some examples, material structure 700 may be used to form a memory array and may be an example of a material structure, as described with reference to Figures 4 through 6. Material structure 700 may include word line 710, bottom electrode 730, second material 740, third material 745, and dielectric material 747. Material structure 700 may also include opening 750 formed during a previous stage of the formation process.

[0106] In some examples, the opening 750-1 can be used to form a cavity (e.g., cavity 755) in the third material 745. In some examples, the opening 750-1 can be used to perform an etching process that removes a portion of the third material 745 so that the edge of the third material 745 is offset from the edge of the second material 740 and the dielectric material 747. In some examples, in addition to the cavity shown in the first stage 701, multiple cavities are also formed in the vertical direction and separated by the dielectric material 747. In some examples, forming the cavity includes performing a wet etching operation to remove a portion of the third material 745 (e.g., removing approximately 20 nanometers of the third material 745).

[0107] After forming the cavity, a conductive material 760 may be deposited within the opening 750 and the cavity 755. The conductive material 760 may include carbon. In some examples, the conductive material 760 fills the cavity and excess conductive material 760 is deposited on the sidewalls of the opening 750. In some examples, the temperature associated with depositing the conductive material 760 is about 400 degrees Celsius (e.g., because the storage element has not yet been formed). After depositing the conductive material 760, the portion of the conductive material 760 on the sidewalls of the opening 750 may be removed (e.g., using a wet or dry etching technique) so that a separate portion of the conductive material 760 may be formed. The separate portion of the conductive material 760 may correspond to the top electrode 725. In some examples, a portion of the conductive material 760 that contacts the word line 710 may be left so that the bottom electrode 730 extends across the material structure 700.

[0108] In some examples, the temperature associated with depositing the conductive material 760 to form the top electrode 725 may be higher than other formation processes involving depositing the conductive material 760 after forming the memory element (eg, because the effects of temperature may primarily affect the sacrificial second material 740).

[0109] Figure 8 Different stages of a process for laterally forming storage elements of a material structure according to examples as disclosed herein are illustrated. A first stage 801 shows stages of a formation process associated with forming a cavity (e.g., cavity 855), associated with forming a storage element (e.g., storage element 820). A second stage 802 shows stages of a formation process associated with filling the cavity with a chalcogenide material. A third stage 803 shows stages of a formation process associated with removing excess portions of conductive material to obtain a set of storage elements (e.g., storage element 820).

[0110] In some examples, material structure 800 may be used to form a memory array and may be an example of a material structure, as described with reference to Figures 4 through 7. Material structure 800 may include word line 810, bottom electrode 830, second material 840, third material 845, dielectric material 847, and top electrode 825. Material structure 800 may also include opening 850 formed during a previous stage of the formation process.

[0111] In some examples, the opening 850-1 can be used to form a cavity (e.g., cavity 855) in the second material 840. In some examples, the opening 850-1 can be used to perform an etching process that removes a portion of the second material 840 so that the edge of the second material 840 is offset from the edge of the bottom electrode 830 and the top electrode 825. In some examples, in addition to the cavity created in the first stage 801, multiple cavities are also formed in the vertical direction and separated by the dielectric material 847. In some examples, forming the cavity includes performing a wet etching operation to remove a portion of the second material 840 (e.g., removing about 20 nanometers of the second material 840).

[0112] After forming the cavity, a chalcogenide material 860 may be deposited within the opening 850 and the cavity 855. In some examples, the chalcogenide material 860 fills the cavity and excess chalcogenide material 860 is deposited on the sidewalls of the opening 850. In some examples, the width of the excess portion of the chalcogenide material 860 may be about 10 nanometers to 15 nanometers, for example, to ensure that the cavity is filled.

[0113] In some examples, a protective material (e.g., an aluminum oxide material) may be deposited inside the cavity 855 or a nitridation process may be formed to harden the exposed surface of the second material 840, the top electrode 825, the bottom electrode 830, or any combination thereof, prior to depositing the chalcogenide material 860. In such cases, after the memory element 820 is formed, a protective liner may exist at least partially (if not completely) around the memory element 820.

[0114] Portions of the chalcogenide material 860 on the sidewalls of the opening 850 may be removed (e.g., using a wet etching technique) so that separate portions of the chalcogenide material 860 may be formed. In some examples, non-active sidewall portions of the chalcogenide material 860 are exposed to the wet etching. The separate portions of the chalcogenide material 860 may correspond to the storage element 820. In some examples, the conductive path 865 extends from the bottom electrode 830 through the storage element 820 to the top electrode 825. In some examples, the conductive path 865 through the storage element 820 may extend along an axis that does not intersect the opening 850. In some examples, the edges of the storage element are offset from the edges of the bottom and top electrodes. For example, the rightmost edge of the storage element 820 may be offset in a left direction from the rightmost edges of the bottom electrode 830 and the top electrode 825.

[0115] By using a lateral fill process to form the storage element 820, the cell size can be controlled more precisely than other formation processes involving depositing chalcogenide materials directly into the cavity. That is, for the lateral fill process, the front and back of the cavity 855 can be precisely controlled by the bottom and top electrode layers, and the depth of the cavity 855 can be precisely controlled by the etching process. In addition, unlike other formation processes, the opening for forming the cavity 855 does not need to be precisely aligned with an existing cavity.

[0116] Fig. 9 Different stages of a process for laterally forming an electrode of a material structure according to examples as disclosed herein are illustrated. A first stage 901 shows the stages of a formation process associated with filling an opening for forming a storage element (e.g., storage element 920) and a top electrode (e.g., top electrode 925). A second stage 902 shows the stages of a formation process associated with forming a second opening for forming a bit line (e.g., bit line 915). A third stage 903 shows the stages of a formation process associated with forming a bit line (e.g., bit line 915) in the second opening.

[0117] In some examples, material structure 900 may be used to form a memory array and may be an example of a material structure as described with reference to Figures 4 through 8. Material structure 900 may include word line 910, bottom electrode 930, second material 940, third material 945, dielectric material 947, and top electrode 925.

[0118] In some examples, the openings (eg, filled with dielectric material 947) used to form the storage element 920 and the top electrode 925 may be filled with dielectric material 947. Figure 7 and 8In some examples, the openings may be filled with a dielectric material different from dielectric material 947. In some examples, before filling the openings, a protective material (e.g., an aluminum oxide material, a silicon nitride material, etc.) may be deposited on the inner sidewalls of the openings to form a protective liner 950. The protective liner 950 may isolate the bottom electrode, the memory element, the top electrode, or any combination thereof from the dielectric material used to fill the openings.

[0119] After filling the opening, a second opening may be formed in line with the bottom electrode 930, the memory element 920, and the top electrode 925. In some examples, a conductive path 965 through the memory element 920 may extend along an axis through the second opening 955. In some examples, the second opening (e.g., second opening 955-2) may be formed using a first etching operation (e.g., a dry etching operation) to form a first portion of the second opening and a second etching operation (e.g., a wet etching operation) to form a second portion of the second opening that exposes the top electrode 925 (e.g., to reduce accidental etching / erosion of the top electrode). In such cases, the memory element may not be exposed to the wet etching operation (instead, the top electrode may be exposed to the wet etching operation).

[0120] The second opening 955 may be filled with a conductive material (e.g., tungsten) to form a bit line (e.g., bit line 915). In some examples, the bit line is hollow and the inner portion of the second opening 955 is filled with a dielectric material (e.g., dielectric material 947). Thus, a memory cell and a conductor for accessing the memory cell may be formed. In some examples, the material structure 900 may be a memory array (e.g., Figure 3A and 3B An example of a cross section of a memory array 300 ).

[0121] Fig.10 Illustrate multiple views of material structures associated with laterally formed memory cells according to examples as disclosed herein. A first perspective view 1001 depicts a portion of the memory cell formed by a lateral plane corresponding to the dashed line (labeled B and referenced Fig. 9 ) from the top of the material structure 1000 to the bottom of the material structure 1000 (which may correspond to Fig. 9 A cross-sectional view of the material structure 900 at the third stage 903 of the present invention. The second perspective view 1002 depicts a cross-sectional view of the material structure 900 at the third stage 903 of the present invention. Fig. 9 ) is another cross-sectional view of material structure 1000 obtained by omitting (eg, cutting) material structure 1000 from the top of material structure 1000 to the bottom of material structure 1000.

[0122] In the first perspective view 1001, alternating layers of dielectric material 1047 and word lines 1010 extend from the bottom to the top of the material structure 1000. In addition, protective material 1050 can separate dielectric material 1047 and word lines 1010 from dielectric material (which can be the same as dielectric material 1047) used to fill openings between opposing word lines.

[0123] In the second perspective view 1002, dielectric material 1047 and interleaved layers of horizontally disposed memory cells may extend from the bottom to the top of the material structure 1000. Each memory cell may include a bottom electrode (e.g., bottom electrode 1030), a storage element (e.g., storage element 1020), and a top electrode (e.g., top electrode 1025). The bottom electrode of the memory cell may contact a word line (e.g., word line 1010) and the top electrode of the memory cell may contact a bit line (e.g., bit line 1015). In some examples, the storage element may be encapsulated by a protective material, for example, to prevent reaction between the chalcogenide material of the storage element and the dielectric material 1047.

[0124] In another example for forming a memory array, a material structure may be formed by filling a channel with only one material (e.g., a placeholder material for a memory element). In such an example, operations associated with exposing lateral sides of the material to form a memory element may still be performed, while operations associated with forming a bottom electrode, a top electrode, or both may be omitted. For example, the top electrode may not be used. Figure 5 The first material 530 and the third material 545 are used to fill the channel, and the Figure 7 The operations associated with the first phase 701, the second phase 702 and the third phase 703. Figures 11 to 16 Additional options for forming memory arrays and other sections are described.

[0125] Fig.11 The different stages of a process for laterally forming an electrode of a material structure according to an example as disclosed herein are illustrated. The first stage 1101 shows the stage of the formation process associated with forming an opening in a material structure, the material structure including a first material 1128 as a placeholder for an electrode. That is, by virtue of Figure 6 601 , the first material 630 is replaced with the first material 1128 , wherein the first material 1128 may be a sacrificial material (eg, an aluminum oxide material).

[0126] The second stage 1102 shows the stages of the formation process associated with forming a cavity (e.g., cavity 1155) for forming electrodes (e.g., bottom electrode 1130 and top electrode 1125). The third stage 1103 shows the stages of the formation process associated with filling the cavity with a conductive material and removing excess portions of the conductive material to obtain a set of electrodes (e.g., bottom electrode 1130 and top electrode 1125). In some examples, the first stage 1101, the second stage 1102, and the third stage 1103 replace the stages in the formation process described herein. For example, the first stage 1101 may replace Figure 7 The first stage 701, the second stage 1102 can be replaced Figure 7 The second stage 702, and the third stage can be replaced Figure 7 The third stage 703.

[0127] In some examples, material structure 1100 may be used to form a memory array and may be an example of a material structure, such as reference Figure 4A The material structure 1100 may include a word line 1110, a first material 1128, a second material 1140, a third material 1145, and a dielectric material 1147. The material structure 1100 may also include an opening 1150 formed during a previous stage of the formation process.

[0128] In some examples, the opening 1150 may be used to form a cavity (eg, cavity 1155) in the first material 1128 and the third material 1145, as described with reference to FIG. Figure 7 In some examples, the opening 1150 can be used to perform an etching process (e.g., an isotropic etching process) that removes portions of the first material 1128 and portions of the third material 1145, such that edges of the first material 1128 and edges of the third material 1145 are offset from edges of the second material 1140 and the dielectric material 1147. In some examples, in addition to the cavity shown in the first stage 1101, multiple cavities are also formed in the vertical direction and separated by the dielectric material 1147.

[0129] After forming the cavity, a conductive material (eg, a carbon material) may be deposited in the opening 1150 and the cavity 1155, as shown in FIG. Figure 7The second stage 702 of the embodiment is similarly described. In some examples, the conductive material fills the cavity and excess conductive material is deposited on the sidewalls of the opening 1150. Portions of the conductive material on the sidewalls of the opening 1150 may be removed (e.g., using a wet or dry etching technique) so that separate portions of conductive material may be formed. The separate portions of conductive material may correspond to the bottom electrode 1130 and the top electrode 1125. In some examples, portions of the conductive material contacting the word line 1110 may be left so that the bottom electrode 1130 extends between multiple memory cells. In some examples, after completing the third stage 1103, the formation process proceeds to Figure 8 The first stage 801 is to form a storage element.

[0130] Fig.12 The different stages of a process for laterally forming an electrode of a material structure according to an example as disclosed herein are illustrated. The first stage 1201 shows the stage of a formation process associated with forming an opening in a material structure that includes a first material 1228 as a placeholder for a first electrode (e.g., a bottom electrode) and does not include a placeholder material for a second electrode (e.g., a top electrode). That is, by virtue of Figure 6 Compared to the first perspective view 601 of FIG. 6 , the first material 630 is replaced with the first material 1228 , wherein the first material 1228 may be a sacrificial material (eg, an aluminum oxide material), and the third material 645 is not deposited.

[0131] The second stage 1202 shows the stages of the formation process associated with forming a cavity (e.g., cavity 1255) for forming an electrode (e.g., bottom electrode 1230). The third stage 1203 shows the stages of the formation process associated with filling the cavity with a conductive material and removing excess portions of the conductive material to obtain a set of electrodes (e.g., bottom electrode 1230). In some examples, the first stage 1201, the second stage 1202, and the third stage 1203 replace the stages in the formation process described herein. For example, the first stage 1201 can replace Figure 7 The first stage is 701, the second stage is 1202 replaceable Figure 7 The second stage 702, and the third stage can be replaced Figure 7 The third stage 703.

[0132] In some examples, material structure 1200 may be used to form a memory array and may be an example of a material structure, such as that described in reference Figure 4A The material structure 1200 may include a word line 1210, a first material 1228, a second material 1240, and a dielectric material 1247. The material structure 1200 may also include an opening 1250 formed during a previous stage of the formation process.

[0133] In some examples, the opening 1250 may be used to form a cavity (eg, cavity 1255) in the first material 1228, as described with reference to Figure 7 In some examples, the opening 1250 can be used to perform an etching process (e.g., an isotropic etching process) that removes a portion of the first material 1228, such that the edge of the first material 1228 is offset from the edge of the second material 1240 and the dielectric material 1247. In some examples, in addition to the cavity shown in the first stage 1201, multiple cavities are also formed in the vertical direction and separated by the dielectric material 1247.

[0134] After forming the cavity, a conductive material (eg, a carbon material) may be deposited in the opening 1250 and the cavity 1255, as shown in FIG. Figure 7 12. The second stage 702 of the embodiment of the present invention is similarly described. In some examples, the conductive material fills the cavity and excess conductive material is deposited on the sidewalls of the opening 1250. Portions of the conductive material on the sidewalls of the opening 1250 may be removed (e.g., using a wet or dry etching technique) so that separate portions of the conductive material may be formed. The separate portions of the conductive material may correspond to the bottom electrode 1230. In some examples, portions of the conductive material contacting the word line 1210 may be left so that the bottom electrode 1230 extends between multiple memory cells.

[0135] Fig.13 Different stages of a process for laterally forming storage elements of a material structure according to examples as disclosed herein are illustrated. A first stage 1301 shows the stages of a formation process associated with forming a cavity (e.g., cavity 1355), associated with forming a storage element (e.g., storage element 1320). A second stage 1302 shows the stages of a formation process associated with filling the cavity with a chalcogenide material and removing excess portions of the conductive material to obtain a set of storage elements (e.g., storage element 1320). A third stage 1303 shows the stages of a formation process associated with forming a second opening in line with the bottom electrode and the storage element and used to form a top electrode and a bit line.

[0136] In some examples, material structure 1300 may be used to form a memory array and may be an example of a material structure, as described with reference to Figures 4 and 12. Material structure 1300 may include word lines 1310, first material 1328, bottom electrode 1330, second material 1340, and dielectric material 1347. Material structure 1300 may also include openings 1350 formed during a previous stage of the formation process.

[0137] In some examples, opening 1350 may be used to form a cavity (eg, cavity 1355) in second material 1340, as described with reference to Figure 8In some examples, the opening 1350 can be used to perform an etching process to remove a portion of the second material 1340 so that the edge of the second material 1340 is offset from the edge of the bottom electrode 1330. In some examples, in addition to the cavity created in the first stage 1301, multiple cavities are also formed in the vertical direction and separated by the dielectric material 1347.

[0138] After forming the cavity, a chalcogenide material may be deposited in the opening 1350 and the cavity 1355, as shown in FIG. Figure 8 Similarly described. In some examples, the chalcogenide material fills the cavity and excess chalcogenide material is deposited on the sidewalls of the opening 1350. In some examples, before depositing the chalcogenide material, a protective material (e.g., an aluminum oxide material) may be deposited inside the cavity 1355 or a nitridation process may be formed to harden the exposed surface of the second material 1340, the bottom electrode 1330, or both. In such cases, after forming the memory element 1320, a protective liner may exist at least partially (if not completely) around the memory element 1320.

[0139] Portions of the chalcogenide material on the sidewalls of the opening 1350 may be removed (e.g., using a wet or dry etching technique) so that a separate portion of the chalcogenide material may be formed. The separate portion of the chalcogenide material may correspond to the storage element 1320. In some examples, the edge of the storage element is offset from the edge of the bottom electrode. For example, the rightmost edge of the storage element 1320 may be offset in a left direction from the rightmost edge of the bottom electrode 1330.

[0140] After forming the memory element, the opening 1350 can be filled with a dielectric material, such as the same dielectric material as dielectric material 1347. In some examples, before filling the opening 1350, an aluminum oxide liner can be deposited on the sidewalls of the opening 1350.

[0141] After forming the storage element and filling the opening 1350, a second opening (e.g., second opening 1360) may be formed in line with the bottom electrode (e.g., bottom electrode 1330) and the storage element (e.g., storage element 1320). In some examples, the second opening 1360 may expose the surface of the storage element 1320. In some examples, forming the second opening includes forming a smaller portion of the second opening 1360 using a first etching process (e.g., dry etching) and forming the complete second opening 1360 using a second etching process (e.g., wet etching) to softly expose the surface of the storage element 1320.

[0142] Fig.14ADifferent stages of a process for laterally forming electrodes of a material structure are illustrated according to examples as disclosed herein.Stage 1401 shows the stages of a formation process associated with forming a top electrode (eg, top electrode 1425) and a bit line (eg, bit line 1415).

[0143] In some examples, material structure 1400 may be used to form a memory array and may be an example of a material structure, as described with reference to FIGS. 4, 12, and 13. Material structure 1400 may include word line 1410, first material 1428, bottom electrode 1430, second material 1440, and dielectric material 1447. Material structure 1400 may also include openings formed during previous stages of the formation process (e.g., Fig.13 of the second opening 1360).

[0144] In some examples, the second opening may be filled with a conductive material (e.g., carbon) to form a top electrode (e.g., top electrode 1425) and filled with another conductive material (e.g., tungsten) to form a bit line (e.g., bit line 1415). In some examples, a conductive path 1465 through the storage element 1420 may extend along an axis through the dielectric material 1447. In some examples, the top electrode may extend at least partially (if not completely) around the first portion of the second opening and may surround the bit line. In some examples, the bit line may be hollow and filled with a dielectric material (e.g., the same material as dielectric material 1447). In some examples, the conductive material used to form the top electrode may be deposited at a temperature of about 200 degrees Celsius. In some examples, the material structure 1400 may be a memory array (e.g., Figure 3A and 3B An example of a cross section of a memory array 300 ).

[0145] Fig. 14B 1402 depicts a perspective view of a material structure associated with a laterally formed memory cell according to an example as disclosed herein. The perspective view 1402 depicts a perspective view of a material structure 1400 obtained by omitting (e.g., cutting) the material structure 1400 from the top of the material structure 1400 to the bottom of the material structure 1400 at a location corresponding to the dashed line (labeled A). Fig.14A A cross-sectional view of the material structure 1400 shown in stage 1401 of the present invention.

[0146] In perspective 1402, dielectric material 1447 and interleaved layers of horizontally disposed memory cells may extend from the bottom to the top of material structure 1400. Each memory cell may include a bottom electrode (e.g., bottom electrode 1430), a storage element (e.g., storage element 1420), and a top electrode (e.g., top electrode 1425). The bottom electrode of the memory cell may contact a word line (e.g., word line 1410) and the top electrode of the memory cell may contact a bit line (e.g., bit line 1415). In some examples, the storage element may be encapsulated by a protective material, for example, to prevent reaction between the chalcogenide material of the storage element and dielectric material 1447. As shown in perspective 1402 and by comparison with second perspective 1002, the top electrode in material structure 1400 may extend from the top of material structure 1400 to the bottom of material structure 1400.

[0147] Fig.15 Different stages of a process for laterally forming an electrode of a material structure according to examples as disclosed herein are illustrated. A first stage 1501 shows stages of a formation process associated with filling a channel with one or more placeholder materials. A second stage 1502 shows stages of a formation process associated with forming an opening (e.g., opening 1550) in a dielectric material. A third stage 1503 shows stages of a formation process associated with filling the opening with a conductive material to form a top electrode (e.g., top electrode 1525) and filling the opening with another conductive material to form a bit line (e.g., bit line 1515).

[0148] In some examples, material structure 1500 may be used to form a memory array and may be an example of a material structure, such as that described in reference Figure 4A The material structure 1500 may include a word line 1510 , a bottom electrode 1530 , a second material 1540 , and a dielectric material 1547 .

[0149] In some examples, an opening 1550 may be formed in the dielectric material 1547. In some examples, the opening 1550 is formed using an etching process, a photolithography process, or both. The opening 1550 may then be filled with a conductive material (e.g., carbon and tungsten) to form a top electrode (e.g., top electrode 1525) and a bit line (e.g., bit line 1515). In some examples, a first conductive material (e.g., carbon) may be deposited on the sidewalls of the opening 1550 to form the top electrode 1525, and a smaller portion of the opening 1550 may remain empty. In some examples, the first conductive material is formed at a temperature of about 400 degrees Celsius. A second conductive material (e.g., tungsten) may then be deposited on the sidewalls of the remaining portion of the opening 1550 to form the bit line 1515. In some examples, an even smaller portion of the opening 1550 may remain empty and filled with a dielectric material (e.g., using the same material as the dielectric material 1547) after the bit line is formed.

[0150] Fig.16 Different stages of a process for laterally forming a storage element of a material structure according to examples as disclosed herein are illustrated. The first stage 1601 shows the stages of the formation process associated with forming a second opening (e.g., second opening 1660) for laterally forming a storage element. The second stage 1602 shows the stages of the formation process associated with filling the cavity with a chalcogenide material to form a storage element (e.g., storage element 1620). The third stage 1603 shows the stages of the formation process associated with filling the second opening.

[0151] In some examples, material structure 1600 may be used to form a memory array and may be an example of a material structure as described with reference to Figures 4 and 15. Material structure 1600 may include word line 1610, bottom electrode 1630, second material 1640, dielectric material 1647, top electrode 1625, and bit line 1615.

[0152] In some examples, second openings 1660 can be formed along sides of the top electrode and at least through second material 1640 (and in some examples through bottom electrode 1630 ). Thus, second openings 1660 can expose lateral sides of second material 1640 .

[0153] The second opening 1660 can be used to replace a portion of the second material 1640 with a chalcogenide material to form a memory element (eg, memory element 1620), as described with reference to Figure 8Similarly described. In some examples, forming the storage element 1620 may include etching away a portion of the second material 1640 so that the rightmost edge of the remaining portion of the second material 1640 is offset in a left direction from the rightmost edge of the top electrode, thereby forming a cavity. Forming the storage element 1620 may also include depositing a chalcogenide material into the cavity, wherein an excess portion of the chalcogenide material may be deposited on the sidewalls of the second opening 1660. Forming the storage element 1620 may further include removing an excess portion of the chalcogenide material from the sidewalls of the second opening 1660. In some examples, before forming the storage element 1620, a protective material liner may be formed between the storage element 1620 and the exposed surfaces of the second material 1640, the bottom electrode 1630, and the top electrode 1625, as similarly described herein. In some examples, the conductive path 1665 may extend from the bottom electrode 1630 to the top electrode 1625 and through the memory element 1620 in a direction extending parallel to the sides of the second opening 1660 exposing the lateral sides of the memory element 1620 .

[0154] After forming storage element 1620, the second opening can be filled. In some examples, filling the second opening includes filling the second opening with a dielectric material (e.g., using the same or different material as dielectric material 1647). In some examples, filling the second opening includes depositing a protective material liner (e.g., protective liner 1670) on sidewalls of the second opening before filling the second opening with the dielectric material, e.g., to avoid reaction between the chalcogenide material of storage element 1620 and the dielectric material.

[0155] The cross-section of the material structure 1600 obtained by omitting (eg, cutting) the material structure 1600 from top to bottom may be similar to that obtained by Fig. 14B In some examples, material structure 1600 may be a memory array (e.g., Figure 3A and 3B An example of a cross section of a memory array 300 ).

[0156] Fig.17 A flow chart illustrating a method 1700 for supporting a memory device having laterally formed memory cells according to examples as disclosed herein is shown. The operations of the method 1700 may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using dedicated hardware.

[0157] At 1705, the method may include forming a material stack including a conductive layer positioned between a first dielectric layer and a second dielectric layer, wherein the first dielectric layer, the second dielectric layer, and the conductive layer form a channel in a sidewall of the material stack. The operation of 1705 may be performed according to examples as disclosed herein.

[0158] At 1710, the method may include filling the channel with at least one material and a conductive material associated with a first electrode, wherein a first side of the first electrode is covered and a first side of the at least one material is exposed based at least in part on filling the channel with the at least one material. The operations of 1710 may be performed according to examples as disclosed herein.

[0159] At 1715, the method may include forming an opening through the at least one material exposing the conductive material and the second side of the at least one material. The operation of 1715 may be performed according to examples as disclosed herein.

[0160] At 1720, the method may include replacing the at least one material with a chalcogenide material through the opening based at least in part on exposing the second side of the at least one material. The operation of 1720 may be performed according to examples as disclosed herein.

[0161] In some examples, an apparatus as described herein may perform one or several methods, such as method 1700. The apparatus may include operations, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming a material stack including a conductive layer positioned between a first dielectric layer and a second dielectric layer, wherein the first dielectric layer, the second dielectric layer, and the conductive layer form a channel in a sidewall of the material stack; filling the channel with at least one material and a conductive material associated with a first electrode, wherein a first side of the first electrode is covered and a first side of the at least one material is exposed based at least in part on filling the channel with the at least one material; forming an opening through the at least one material exposing the conductive material and a second side of the at least one material; and replacing the at least one material with a chalcogenide material through the opening based at least in part on exposing the second side of the at least one material.

[0162] In some examples of method 1700 and apparatus described herein, filling the channel with the at least one material may include operations, features, circuit systems, logic, components, or instructions for depositing a first material associated with a storage element into the channel and over the conductive material; and depositing a second material associated with a second electrode into the channel and over a first side of the first material, and wherein the channel may be at least partially filled with the second material while covering the first side of the first material and exposing the first side of the second material.

[0163] In some examples of method 1700 and apparatus described herein, forming the opening may include operations, features, circuit systems, logic, components, or instructions for forming the opening through the first material and the second material, wherein a second side of the first material and a second side of the second material may be exposed at least in part based on forming the opening.

[0164] In some examples of the methods 1700 and apparatuses described herein, the first material includes silicon nitride and the second material includes aluminum oxide.

[0165] In some examples of the methods 1700 and apparatus described herein, the mutual etching selectivity between the first material, the second material, the first dielectric material, and the second dielectric material exceeds a threshold. The mutual etching selectivity may indicate the degree of resistance of one material to a chemical used to etch away another material.

[0166] In some examples of the method 1700 and apparatus described herein, the channel may be filled via a trench and the method, apparatus, and non-transitory computer-readable medium may further include operations, features, circuit systems, logic, components, or instructions for filling the trench with a dielectric material, wherein the first side of the at least one material may be covered at least in part based on filling the trench, and wherein the opening may be formed through the dielectric material.

[0167] In some examples of method 1700 and apparatus described herein, replacing the at least one material may include operations, features, circuit systems, logic, components, or instructions for: etching a first material of the at least one material and associated with the second electrode through the opening to form a cavity; and depositing a second conductive material into the cavity through the opening to form the second electrode.

[0168] In some examples of the method 1700 and apparatus described herein, replacing the at least one material with the chalcogenide material may include operations, features, circuit systems, logic, means, or instructions for: etching a second material of the at least one material and associated with a storage element through the opening and after forming the second electrode to form a second cavity; and depositing the chalcogenide material into the second cavity through the opening to form the storage element.

[0169] Some examples of method 1700 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for: prior to replacing the at least one material with the chalcogenide material, forming a liner on the interior of the second cavity that separates the chalcogenide material from the second material of the at least one material, the first electrode, the second electrode, or any combination thereof.

[0170] Some examples of method 1700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for filling the opening with an aluminum oxide material and a dielectric material based at least in part on replacing the at least one material, wherein the aluminum oxide material separates the at least one material from the dielectric material.

[0171] In some examples of the method 1700 and apparatus described herein, a trench for accessing the channel is filled before the opening is formed through the at least one material, wherein the first side of the at least one material may be covered based at least in part on filling the trench; the opening is filled with a dielectric material to form a second electrode and the chalcogenide material to form a storage element based at least in part on replacing the at least one material with a second conductive material, wherein a first side of the second electrode may be exposed by the opening before the opening is filled; and after the opening is filled with the dielectric material, a second opening is formed to expose a second side of the second electrode.

[0172] Some examples of method 1700 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for filling the second opening with at least a third conductive material to form a bit line.

[0173] In some examples of methods 1700 and apparatus described herein, the at least one material can be a placeholder for the chalcogenide material to form a storage element, a placeholder for a second conductive material to form a second electrode, or both.

[0174] In some examples of methods 1700 and apparatuses described herein, the second side of the at least one material extends in a first direction that may be parallel to a second direction of a current path through the chalcogenide material.

[0175] Some examples of method 1700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: filling a trench for filling the channel with a dielectric material based at least in part on filling the channel with the at least one material, wherein the first side of the at least one material may be covered based at least in part on filling the trench; forming a second opening exposing a portion of the first side of the at least one material before forming the opening exposing the second side of the at least one material and based at least in part on filling the trench; and filling the second opening with a first conductive material associated with a second electrode, a second conductive material associated with a bit line, or both before forming the opening.

[0176] Fig.18 A flow chart illustrating a method 1800 for supporting a memory device having laterally formed memory cells according to examples as disclosed herein is shown. The operations of the method 1800 may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using dedicated hardware.

[0177] At 1805, the method may include forming a channel in a sidewall of a material stack, the channel being bounded by a first dielectric layer, a second dielectric layer, and a conductive layer of the material stack. The operations of 1805 may be performed according to examples as disclosed herein.

[0178] At 1810, the method may include depositing a first material associated with a first electrode over the conductive layer by the sidewalls of the material stack and into the channel through the trench. The operations of 1810 may be performed according to examples as disclosed herein.

[0179] At 1815, the method may include depositing a second material associated with a storage element over the first material and into the channel through the trench, wherein a first side of the first material is covered by the second material and exposed to the trench based at least in part on depositing the second material. The operation of 1815 may be performed according to examples as disclosed herein.

[0180] At 1820, the method may include depositing a third material associated with a second electrode over the second material and into the channel through the trench, wherein the first side of the second material is covered and the first side of the third material is exposed to the trench based at least in part on depositing the third material. The operations of 1820 may be performed according to examples as disclosed herein.

[0181] At 1825, the method can include forming an opening through the first, second, and third materials exposing a second side of the second material. The operation of 1825 can be performed according to examples as disclosed herein.

[0182] At 1830, the method can include replacing the second material with a chalcogenide material through the opening based at least in part on exposing the second side of the second material. The operations of 1830 can be performed according to examples as disclosed herein.

[0183] In some examples, an apparatus as described herein may perform one or several methods, such as method 1800 . The apparatus may include operations, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming a channel in a sidewall of a material stack, the channel being bounded by a first dielectric layer, a second dielectric layer, and a conductive layer of the material stack; depositing a first material associated with a first electrode into the channel over the conductive layer and through a trench by the sidewall of the material stack; depositing a second material associated with a storage element into the channel over the first material and through the trench, wherein a first side of the first material is covered by the second material and the first side of the second material is exposed to the trench at least in part based on depositing the second material; depositing a third material associated with a second electrode into the channel over the second material and through the trench, wherein the first side of the second material is covered and the first side of the third material is exposed to the trench at least in part based on depositing the third material; forming an opening through the first, second, and third materials that exposes a second side of the second material; and replacing the second material with a chalcogenide material through the opening based at least in part on exposing the second side of the second material.

[0184] Some examples of method 1800 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for replacing the first material and the third material with a conductive material through the opening and before replacing the second material to form the first electrode and the second electrode.

[0185] In some examples of method 1800 and apparatus described herein, replacing the first material and the third material with the conductive material may include operations, features, circuit systems, logic, components, or instructions for: etching portions of the first material and the third material through the opening to form a first cavity associated with the first electrode and a second cavity associated with the second electrode; and depositing the conductive material into the first cavity and the second cavity through the opening to form the first electrode and the second electrode.

[0186] In some examples of the method 1800 and apparatus described herein, replacing the second material with the chalcogenide material may include operations, features, circuit systems, logic, means, or instructions for: etching a portion of the second material through the opening and after forming the first electrode and the second electrode to form a cavity; and depositing the chalcogenide material into the cavity through the opening to form the storage element.

[0187] Some examples of method 1800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for filling the trench with a dielectric material based at least in part on depositing the third material into the channel, wherein the first side of the third material may be covered based at least in part on filling the trench, and wherein the opening may be formed through the dielectric material.

[0188] In some examples of the methods 1800 and apparatus described herein, the opening exposes a second side of the first material and a second side of the third material.

[0189] In some examples of the methods 1800 and apparatuses described herein, the first material and the third material include aluminum oxide, and the second material includes silicon nitride.

[0190] In some examples of the method 1800 and apparatus described herein, the first material may be a placeholder for a conductive material for forming the first electrode, the second material may be a placeholder for the chalcogenide material for forming the storage element, and the third material may be a placeholder for a second conductive material for forming the second electrode.

[0191] Fig.19A flow chart illustrating a method 1900 for supporting a memory device having laterally formed memory cells according to examples as disclosed herein is shown. The operations of the method 1900 may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using dedicated hardware.

[0192] At 1905, the method may include forming a channel in a sidewall of a material stack, the channel being bounded by a first dielectric layer, a second dielectric layer, and a conductive layer of the material stack. The operations of 1905 may be performed according to examples as disclosed herein.

[0193] At 1910, the method may include depositing a first material associated with a first electrode over the conductive layer by the sidewalls of the material stack and into the channel through the trench. The operations of 1910 may be performed according to examples as disclosed herein.

[0194] At 1915, the method may include depositing a second material associated with a storage element over the first material and into the channel through the trench, wherein a first side of the first material is covered by the second material and exposed to the trench based at least in part on depositing the second material. The operation of 1915 may be performed according to examples as disclosed herein.

[0195] At 1920, the method may include forming a first opening through the first material and the second material exposing a second side of the second material. The operation of 1920 may be performed according to examples as disclosed herein.

[0196] At 1925, the method may include replacing the second material with a chalcogenide material through the first opening and based at least in part on exposing the second side of the second material to form the storage element, wherein the first side of the storage element is covered by a dielectric material and the second side of the storage element is exposed by the first opening. The operation of 1925 may be performed according to examples as disclosed herein.

[0197] At 1930, the method may include forming a second opening in the dielectric material, wherein the first side of the storage element is exposed by the second opening. The operation of 1930 may be performed according to examples as disclosed herein.

[0198] At 1935, the method may include depositing a conductive material within the second opening and over the first side of the storage element to form a second electrode based at least in part on forming the second opening. The operation of 1935 may be performed according to examples as disclosed herein.

[0199] In some examples, an apparatus as described herein may perform one or several methods, such as method 1900. The apparatus may include operations, features, circuit systems, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming a channel in a sidewall of a material stack, the channel being bounded by a first dielectric layer, a second dielectric layer, and a conductive layer of the material stack; depositing a first material associated with a first electrode into the channel over the conductive layer and through a trench by the sidewall of the material stack; depositing a second material associated with a storage element into the channel over the first material and through the trench, wherein a first side of the first material is covered by the second material and the first side of the first material is covered by the second material at least partially based on depositing the second material The first sides of the two materials are exposed to the trench; a first opening is formed through the first material and the second material to expose the second side of the second material; through the first opening and at least partially based on exposing the second side of the second material, the second material is replaced with a chalcogenide material to form the storage element, wherein the first side of the storage element is covered by a dielectric material and the second side of the storage element is exposed by the first opening; a second opening is formed in the dielectric material, wherein the first side of the storage element is exposed by the second opening; and at least partially based on forming the second opening, a conductive material is deposited inside the second opening and over the first side of the storage element to form a second electrode.

[0200] Some examples of method 1900 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for replacing the first material with a second conductive material to form the first electrode via the first opening and before replacing the second material.

[0201] Some examples of method 1900 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: filling the trench with the dielectric material based at least in part on depositing the second material into the channel; and filling the first opening with a second dielectric material based at least in part on replacing the second material with the chalcogenide material, wherein the second opening may be formed through the dielectric material and the second dielectric material.

[0202] In some examples of the methods 1900 and apparatus described herein, a second conductive material is deposited into the second opening over the conductive material to form a bit line.

[0203] In some examples of the method 1900 and apparatus described herein, depositing the conductive material may include operations, features, circuitry, logic, means, or instructions for depositing the conductive material while maintaining a temperature of the conductive material below a threshold associated with the chalcogenide material.

[0204] Fig. 20 A flow chart illustrating a method 2000 for supporting a memory device having laterally formed memory cells according to examples as disclosed herein is shown. The operations of the method 2000 may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, the one or more controllers may perform aspects of the described functions using dedicated hardware.

[0205] At 2005, the method may include removing a first portion of a conductive layer positioned between a first dielectric layer and a second dielectric layer of a material stack, wherein a channel is formed in the material stack and a second portion of the conductive layer is exposed based at least in part on removing the second portion of the conductive layer. The operation of 2005 may be performed according to examples as disclosed herein.

[0206] At 2010, the method may include forming a first electrode on the second portion of the conductive layer and a second electrode opposite the first electrode, the first electrode and the second electrode forming at least a portion of a cavity. The operation of 2010 may be performed according to examples as disclosed herein.

[0207] At 2015, the method may include, after forming the first electrode and the second electrode, filling the cavity with a chalcogenide material to form a storage element. The operations of 2015 may be performed according to examples as disclosed herein.

[0208] In some examples, an apparatus as described herein may perform one or several methods, such as method 2000. The apparatus may include operations, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for removing a first portion of a conductive layer positioned between a first dielectric layer and a second dielectric layer of a material stack, wherein a channel is formed in the material stack and a second portion of the conductive layer is exposed based at least in part on the removal of the first portion of the conductive layer; forming a first electrode on the second portion of the conductive layer and a second electrode opposite the first electrode, the first electrode and the second electrode forming at least a portion of a cavity; and after forming the first electrode and the second electrode, filling the cavity with a chalcogenide material to form a memory element.

[0209] Some examples of method 2000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: depositing a first material from the second portion of the conductive layer, depositing a second material from the first material, and depositing a third material from the second material; and forming an opening through the second material and the third material to expose a first side of the second material and a first side of the third material.

[0210] In some examples of method 2000 and apparatus described herein, forming the second electrode may include operations, features, circuit systems, logic, components, or instructions for replacing a portion of the third material with a conductive material through the opening to form the second electrode, wherein a first side of the second electrode may be exposed by the opening, and forming the cavity includes etching the first side of the second material after forming the second electrode to form the cavity.

[0211] Some examples of method 2000 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: forming a second opening exposing a second side of the second electrode; and filling the second opening with a second conductive material to form a bit line contacting the second side of the second electrode.

[0212] In some examples of the methods 2000 and apparatus described herein, the cavity can be filled through the opening from a first direction that can be perpendicular to a second direction of a current path through the storage element.

[0213] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. In addition, portions from two or more methods may be combined.

[0214] Another apparatus is described. The apparatus may include: a word line including a first conductive material; a first electrode including a second conductive material, the first electrode being positioned from a first side of the word line; a storage element including a chalcogenide material, the storage element being positioned from a first side of the first electrode and a first material layer; a second electrode including a third conductive material, the second electrode being positioned from a first side of the storage element and a second material layer positioned by the first material layer; and a bit line including a fourth conductive material, the bit line being positioned from a first side of the second electrode.

[0215] In some examples of the apparatus, an edge of the first side of the storage element may be offset from an edge of the first side of the first electrode and an edge of the first side of the second electrode.

[0216] In some examples of the apparatus, the edge of the first side of the first electrode can be aligned with the edge of the first side of the second electrode.

[0217] In some examples of the apparatus, the memory element can be formed by filling a cavity between the first electrode and the second electrode.

[0218] In some examples of the apparatus, the first material layer includes silicon nitride and can be positioned by the first electrode, and the second material layer includes aluminum oxide and can be positioned by the first material layer.

[0219] In some examples of the apparatus, a second side of the storage element and a second side of the second electrode can be coated with an aluminum oxide layer that separates the storage element and the second electrode from a dielectric material.

[0220] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have a variety of bit widths.

[0221] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other or connected to each other or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other or connected to each other or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0222] The term "coupled" refers to a state of moving from an open circuit relationship between components (where signals cannot currently pass between components via conductive paths) to a closed circuit relationship between components (where signals can pass between components via conductive paths). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0223] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between the components are isolated from one another when the switch is open. When a controller isolates two components, the controller brings about a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0224] As used herein, the term "layer" or "step" refers to a layer or sheet of a geometric structure (e.g., relative to a substrate). Each layer or step may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or step may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. A layer or step may include different elements, components, and / or materials. In some examples, a layer or step may be composed of two or more sub-layers or sub-steps.

[0225] As used herein, the term "about" means that the modified property (e.g., a verb or adjective modified by the term substantially) or related aspect (e.g., a related action or function) need not be absolute but is close enough to achieve the advantage of the property or related aspect (e.g., a related action or function).

[0226] As used herein, the term "electrode" may refer to an electrical conductor and, in some examples, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of a memory array.

[0227] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0228] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0229] The descriptions set forth herein, together with the accompanying drawings, describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "used as an example, instance, or illustration, rather than "preferred" or "superior to other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0230] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0231] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium as one or more instructions or codes or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0232] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0233] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0234] Computer-readable media include both non-transitory computer storage media and communication media, and communication media include any media that facilitates the transfer of computer processes from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory media. Moreover, any connection is appropriately referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0235] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a word line comprising a first conductive material; a first electrode comprising a second conductive material, the first electrode being positioned by a first side of the word line; a memory element comprising a chalcogenide material, the memory element being positioned by a first side of the first electrode and a first material layer; a second electrode comprising a third conductive material, the second electrode being positioned by a first side of the memory element and a second material layer positioned by the first material layer; and A bit line includes a fourth conductive material, the bit line being positioned by the first side of the second electrode.

2. The apparatus of claim 1, wherein an edge of the first side of the storage element is offset from an edge of the first side of the first electrode and an edge of the first side of the second electrode. 3 . The device of claim 2 , wherein the edge of the first side of the first electrode is aligned with the edge of the first side of the second electrode. 4 . The device of claim 1 , wherein the memory element is formed by filling a cavity between the first electrode and the second electrode.

5. The apparatus of claim 1, wherein: The first material layer includes silicon nitride and is positioned by the first electrode, and The second material layer includes aluminum oxide and is positioned by the first material layer.

6. The apparatus of claim 1, wherein a second side of the storage element and a second side of the second electrode are coated with an aluminum oxide layer that separates the storage element and the second electrode from a dielectric material.

7. A device comprising: word line; a first electrode positioned from a first side of the word line; a memory element positioned by the first side of the first electrode and the first material layer; a second electrode positioned by the first side of the memory element and by a second material layer positioned by the first material layer; and A bit line is positioned by a first side of the second electrode, wherein a first edge of the first side of the bit line is offset from a first edge of the first side of the storage element in a first direction, and a second edge of the first side of the bit line is offset from a second edge of the first side of the storage element in a second direction, the second direction being different from the first direction.

8. The apparatus of claim 7, wherein: The first edge of the first side of the storage element is offset in the first direction from the first edge of the first side of the first electrode and in the first direction from the first edge of the first side of the second electrode, and The second edge of the first side of the storage element is aligned with a second edge of the first side of the first electrode and a second edge of the first side of the second electrode.

9. The apparatus of claim 7, further comprising: A protective liner is positioned by the first electrode, the memory element, the second electrode, and the bit line.

10. The apparatus of claim 7, further comprising: a third electrode positioned from the first side of the bit line; a second storage element positioned by the first side of the third electrode, a fourth electrode positioned from the first side of the second storage element; as well as A second word line is positioned by the first side of the fourth electrode.

11. The apparatus of claim 10, further comprising: A protective liner is positioned by the first electrode, the memory element, the second electrode, and the bit line.

12. The apparatus of claim 7, wherein: The second electrode extends along the first perimeter, and The bit line extends along a second perimeter within the first perimeter.

13. The apparatus of claim 7, further comprising: a third electrode positioned by the first side of the word line; a second storage element positioned by the first side of the third electrode, a fourth electrode positioned from the first side of the second storage element; as well as A second word line is positioned by the first side of the fourth electrode.

14. The apparatus of claim 7, wherein: The first edge of the first side of the storage element is aligned with the first edge of the first side of the first electrode and offset from the first edge of the first side of the second electrode in the first direction, and The second edge of the first side of the storage element is aligned with the second edge of the first side of the first electrode and offset from the second edge of the first side of the second electrode in the second direction.

15. An apparatus comprising: word line; a first electrode positioned from a first side of the word line; a memory element positioned by the first side of the first electrode and the first material layer; a second electrode positioned by the first side of the memory element and by a second material layer positioned by the first material layer; a bit line located by a first side of the second electrode; and A protective liner, wherein a first edge of the first side of the second electrode and a first edge of the first side of the memory element are aligned and positioned by the protective liner.

16. The apparatus of claim 15, wherein: A second edge of the first side of the second electrode is offset from a second edge of the first side of the storage element.

17. The apparatus of claim 15, wherein: A first edge of a first side of the bit line is offset from a first edge of the first side of the storage element in a first direction, and A second edge of the first side of the bit line is offset from a second edge of the first side of the storage element in the first direction.

18. The apparatus of claim 15, wherein: The second electrode extends along the first perimeter, and The bit line extends along a second perimeter within the first perimeter.

19. The apparatus of claim 15, further comprising: a second storage element positioned by a second side of the second electrode, a third electrode positioned by the first side of the second storage element; as well as A second word line is positioned by the first side of the third electrode.

20. The apparatus of claim 15, further comprising: A second memory element is positioned by the first side of the first electrode, the second memory element being separated from the memory element by at least the protection liner.

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