Preparation method of drain electrode modulation GaN device and drain electrode modulation GaN device

Abstract

The invention discloses a preparation method of a drain modulation GaN device and the drain modulation GaN device, and the method comprises the steps: firstly depositing a P-GaN layer with a larger thickness when preparing two P-GaN layers with different thicknesses in the drain modulation GaN device, and then carrying out the etching of the P-GaN layers twice in different regions, so as to form a thicker first P-GaN layer and a thinner P-GaN layer; and the deposited metal on the grid electrode P-GaN is different from the metal of the drain electrode P-GaN, so that the grid electrode is in Schottky contact, and the drain electrode is in ohmic contact with the P-GaN, the source electrode and the drain electrode. According to the method provided by the invention, the two P-GaN layers with different thicknesses are formed through a two-step etching method, and compared with a traditional method for preparing a mixed drain type GaN transistor (HD-GIT) through growth after groove etching so as to reduce the dynamic on-resistance, the method provided by the invention has the advantages that the process steps are fewer, and the process complexity is lower; and the gate leakage current of Schottky contact is smaller.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and in particular relates to a preparation method of a drain modulated GaN device and a drain modulated GaN device. Background Art

[0002] GaN high electron mobility transistor (HEMT) has the advantages of high breakdown voltage, good thermal stability, high electron drift velocity, and wide band gap due to the heterojunction grown at the AlGaN / GaN interface. It is more suitable for high-power, high-voltage, and high-speed electronic products than traditional silicon power devices.

[0003] In current practical applications, the dynamic conduction characteristics of devices using conventional P-GaN gates are poor. Dynamic resistance degradation is a phenomenon in which, during the switching process of GaN power devices, traps on the surface or in the buffer layer of the material capture electrons, causing the carriers in its conductive channel to be partially depleted, thereby weakening the current carrying capacity and increasing the on-resistance.

[0004] Conventional hybrid drain GaN transistor (HD-GIT) is a GaN transistor that adds a P-GaN near the drain to inject holes into the conductive channel and modulate the carrier concentration of the channel to alleviate the trend of dynamic resistance degradation. Although conventional HD-GIT can improve the on-resistance increase, in order to simultaneously achieve gate P-GaN depletion of two-dimensional electron gas and drain P-GaN injection, the P-GaN regrowth process is adopted after etching AlGaN under the gate. The process is relatively complex, and because there is an ohmic contact between the gate metal and P-GaN, the gate leakage current is relatively large.

[0005] Therefore, the current method for preparing a mixed drain GaN transistor is complex and the gate leakage current of the prepared transistor is relatively large. Summary of the invention

[0006] The embodiments of the present invention provide a method for preparing a drain modulated GaN device and a drain modulated GaN device, which can solve the problem that the current method for preparing a mixed drain type GaN transistor is complicated and the gate leakage current of the prepared transistor is large, and can also effectively reduce the dynamic on-resistance of the device.

[0007] In a first aspect, an embodiment of the present invention provides a method for preparing a drain modulated GaN device, the method comprising:

[0008] preparing a substrate;

[0009] Depositing a P-GaN layer on the upper surface of the substrate, and etching and thinning a non-first P-GaN region on the upper surface of the P-GaN layer to form a partially thinned P-GaN layer;

[0010] Etching the non-first P-GaN region and the non-second P-GaN region on the upper surface of the partially thinned P-GaN layer until the upper surface of the substrate, so as to form a first P-GaN layer in the first P-GaN region and a second P-GaN layer in the second P-GaN region;

[0011] Performing ion implantation on both sides of the substrate to form a first isolation region and a second isolation region;

[0012] Depositing an ohmic contact metal on the upper surface of the second P-GaN layer and performing annealing to form a metal layer in ohmic contact with the second P-GaN layer;

[0013] Depositing a continuous passivation layer on the substrate, the first P-GaN layer and the upper surface of the metal layer;

[0014] Etching the gate groove region on the upper surface of the continuous passivation layer until the first P-GaN layer is formed to form a gate groove; and depositing a gate in Schottky contact with the first P-GaN layer in the gate groove;

[0015] Etching the source groove region, the P-GaN groove region and the drain groove region on the upper surface of the continuous passivation layer to form a source groove, a P-GaN groove and a drain groove, respectively, wherein the source groove, the gate groove, the P-GaN groove and the drain groove are sequentially arranged along a first direction, and the first direction is parallel to the horizontal direction;

[0016] Ohmic contact metals are deposited in the source groove, the drain groove and the P-GaN groove respectively to form a source in ohmic contact with the substrate in the source groove, and a drain extending laterally to the upper surface of the metal layer is formed in the drain groove.

[0017] In a second aspect, an embodiment of the present invention provides a drain modulated GaN device prepared according to the method provided in the first aspect, comprising:

[0018] A substrate, wherein a first isolation region and a second isolation region are respectively arranged on two sides of the substrate;

[0019] A first P-GaN layer, a second P-GaN layer, a first P-GaN layer, and a second P-GaN layer are sequentially arranged on the upper surface of the substrate along a first direction, between the first isolation region and the second isolation region; wherein the first direction is parallel to the horizontal direction, and the thickness of the first P-GaN layer is greater than that of the second P-GaN layer;

[0020] A metal layer, the metal layer is disposed on the upper surface of the second P-GaN layer and forms an ohmic contact with the second P-GaN layer;

[0021] A passivation layer, the passivation layer is arranged on the upper surfaces of the substrate, the first P-GaN layer and the metal layer, and covers the side surfaces of the first P-GaN layer, the second P-GaN layer and the metal layer, and the upper surface of the passivation layer is sequentially provided with a source groove, a gate groove, a P-GaN groove and a drain groove along a first direction;

[0022] The source groove and the drain groove penetrate the passivation layer and extend into the substrate; the gate groove penetrates the passivation layer and extends to the upper surface of the first P-GaN layer, and the P-GaN groove penetrates the passivation layer and extends to the upper surface of the metal layer; the P-GaN groove is adjacent to the drain groove and is connected in the horizontal direction;

[0023] A source electrode is arranged in the source electrode groove and is in ohmic contact with the substrate;

[0024] A gate is disposed in the gate groove, the gate is in Schottky contact with the upper surface of the first P-GaN layer and the first P-GaN layer;

[0025] The drain electrode is arranged in the drain electrode groove and extends laterally to the upper surface of the metal layer.

[0026] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: according to the method provided by the present invention, two P-GaN layers with different thicknesses are formed by a two-step etching method. Compared with the traditional method of etching grooves and then growing again to reduce the dynamic on-resistance of the device, the process steps of the present invention are fewer, the process complexity is lower, and the dynamic on-resistance of the device can be effectively reduced; and the gate leakage current of the Schottky contact is smaller. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic structural diagram of a drain modulated GaN device provided by an embodiment of the present invention;

[0028] Figure 2 A schematic diagram of a groove on a passivation layer provided by an embodiment of the present invention;

[0029] Figure 3 A flowchart of a method for preparing a drain modulated GaN device provided by an embodiment of the present invention;

[0030] Figure 4a-4h A schematic diagram of a preparation scenario of a drain modulated GaN device provided in an embodiment of the present invention.

[0031] Reference numerals:

[0032] 1: substrate; 11: substrate layer; 12: buffer layer; 13: channel layer; 14: barrier layer; 141: first isolation region; 142: second isolation region; 2: first P-GaN layer; 3: second P-GaN layer; 4: metal layer; 5: passivation layer; 51: source groove; 52: gate groove; 53: P-GaN groove; 54: drain groove; 6: source; 7: gate; 8: drain. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0034] Figure 1 The structure diagram of a drain modulated GaN device provided by an embodiment of the present invention is shown. As an example but not a limitation, see Figure 1 The device 100 may include a substrate 1 , a first P-GaN layer 2 , a second P-GaN layer 3 , a metal layer 4 , a passivation layer 5 , a source electrode 6 , a gate electrode 7 and a drain electrode 8 .

[0035] For details, see Figure 1 The first isolation region 141 and the second isolation region 142 may be respectively disposed on both sides of the substrate 1. The first P-GaN layer 2 and the second P-GaN layer 3 are disposed along the first direction (see Figure 2 The first P-GaN layer 2 and the second P-GaN layer 3 are sequentially arranged on the upper surface of the substrate 1 and are located between the first isolation region 141 and the second isolation region 142. The metal layer 4 is arranged on the upper surface of the second P-GaN layer 3 to form an ohmic contact with the second P-GaN layer 3. The passivation layer 5 is arranged on the upper surfaces of the substrate 1, the first P-GaN layer 2 and the metal layer 3, and covers the side surfaces of the first P-GaN layer 2, the second P-GaN layer 3 and the metal layer 4. Figure 2 The upper surface of the passivation layer 5 is also provided with a source groove 51, a gate groove 52, a P-GaN groove 53, and a drain groove 54 along the first direction. The source 6 can be arranged in the source groove 51 and in ohmic contact with the substrate 1. The gate 7 can be arranged in the gate groove 52, located on the upper surface of the first P-GaN layer 2 and in Schottky contact with the first P-GaN layer 2. The drain 8 can be arranged in the drain groove 54 and extend laterally to the upper surface of the metal layer 4.

[0036] Exemplarily, the first direction is parallel to the horizontal direction.

[0037] For example, see Figure 2 The source groove 51 and the drain groove 54 can penetrate the passivation layer 5 and extend into the substrate 1 , the gate groove 52 can extend to the upper surface of the first P-GaN layer 2 , and the P-GaN groove 53 can extend to the upper surface of the metal layer 4 .

[0038] Exemplarily, the P-GaN groove 53 is adjacent to the drain groove 54 and is connected to the drain groove 54 in the horizontal direction.

[0039] In one possible implementation, see Figure 1 The substrate 1 may include a substrate layer 11, a buffer layer 12, a channel layer 13 and a barrier layer 14 stacked in sequence from bottom to top.

[0040] For example, see Figure 2 , the source groove 51 and the drain groove 54 may extend into the channel layer 13 .

[0041] In one example, the material of the buffer layer 12 may include high-resistance GaN or AlGaN, and the thickness thereof may range from 600 nm to 6000 nm.

[0042] In one example, the material of the channel layer 13 may include undoped GaN, and the thickness thereof may range from 50 nm to 500 nm.

[0043] In one example, the material of the barrier layer 14 may include Al x Ga 1-x N, wherein x=0.1-0.5; and its thickness range may include 5nm-50nm.

[0044] In a possible implementation, the material of the passivation layer 5 may include dielectric materials such as SiO2, SiN, AlON, Al2O3, etc. The thickness thereof may range from 10 nm to 400 nm.

[0045] In a possible implementation, the source electrode 6 and the drain electrode 8 may both be made of ohmic contact metal.

[0046] In one possible implementation, see Figure 1 Due to the overlay error of the two-step etching, the pattern of the P-GaN gate etched in the first time is slightly smaller than the pattern of the second etching, that is, the first P-GaN layer 2 can be divided into two layers, and the size of the bottom layer is larger.

[0047] Exemplarily, the thickness of the first P-GaN layer 2 is greater than that of the second P-GaN layer 3 .

[0048] In one example, the material of the first P-GaN layer 2 may include Mg-doped GaN.

[0049] Exemplarily, the material of the second P-GaN layer 3 may be the same as that of the first P-GaN layer 2 , and the thickness may be the same as that of the bottom layer of the first P-GaN layer 2 .

[0050] In a possible implementation, the thickness of the second P-GaN layer 3 is not a constant value.

[0051] Specifically, depending on the doping concentration and activation degree of Mg in P-GaN, the second P-GaN layer 3 of different thicknesses is used to ensure that the device 100 can achieve hole injection in the off state while preventing the two-dimensional electron gas in the channel from being depleted by the P-GaN on the drain side.

[0052] In a possible implementation, the material of the metal layer 4 may include Ni / Au laminated metal, wherein the thickness of the Ni layer may range from 5 nm to 50 nm, and the thickness of the Au layer may range from 5 nm to 50 nm.

[0053] Since the gate of the drain-modulated GaN device in the present invention is a Schottky contact, and the source and drain are ohmic contacts, the leakage current of the gate of the present invention is relatively small.

[0054] Figure 3 The flowchart shown is a method for manufacturing a drain modulated GaN device provided by an embodiment of the present invention. As an example but not a limitation, the manufacturing method can be used to manufacture the above device 100. The manufacturing method can include S301-S309, and each step is described below.

[0055] S301, preparing a substrate.

[0056] In one example, see Figure 4a , a buffer layer 12 , a channel layer 13 and a barrier layer 14 may be sequentially grown on a substrate layer 11 to obtain a substrate 1 .

[0057] For example, the buffer layer 12 , the channel layer 13 and the barrier layer 14 may be grown in sequence by using a metal-organic chemical vapor deposition (MOCVD) technique.

[0058] S302, depositing a P-GaN layer on the upper surface of the substrate, and etching and thinning the non-first P-GaN region on the upper surface of the P-GaN layer to form a partially thinned P-GaN layer.

[0059] In one example, similarly, a P-GaN layer can be deposited on the upper surface of the substrate 1 by using MOCVD technology, and then the non-first P-GaN region on the upper surface of the P-GaN layer (see Figure 4b The region selected by the frame 401 is etched and thinned to form a partially thinned P-GaN layer. Figure 4b The structure shown.

[0060] For example, the thickness of the thinned P-GaN layer may be less than the thickness of the remaining P-GaN layer. The hole injection amount of the P-GaN layer may be determined according to the thickness of the partially thinned P-GaN layer (ie, the remaining P-GaN layer).

[0061] S303, etching the non-first P-GaN region and the non-second P-GaN region on the upper surface of the partially thinned P-GaN layer until the upper surface of the substrate, so as to form a first P-GaN layer in the first P-GaN region and a second P-GaN layer in the second P-GaN region.

[0062] In one example, the non-first P-GaN region and the non-second P-GaN region on the upper surface of the partially thinned P-GaN layer may be etched (see Figure 4c 402 and 403) until the upper surface of the substrate layer, forming a Figure 4c The structure shown.

[0063] Based on the method of steps S302 and S303, the P-GaN layer is etched in two steps to form a first P-GaN layer 2 and a second P-GaN layer 3 of different thicknesses; while ensuring that the device 100 can achieve hole injection, the two-dimensional electron gas in the channel on the drain side will not be depleted by the P-GaN on this side. Compared with the current method of performing groove processing on the AlGaN layer at the gate and then regrowing to achieve the first P-GaN layer 2 and the second P-GaN layer 3 of different thicknesses, the preparation method of the present invention has fewer process steps and lower process complexity, and can effectively achieve the purpose of reducing the dynamic on-resistance of the device.

[0064] S304, performing ion implantation on both sides of the substrate to form a first isolation region and a second isolation region.

[0065] In one example, a plasma implantation process can be used to implant N ions on both sides of the substrate 1 to form N ion implantation regions (ie, the first isolation region 141 and the second isolation region 142), and the following is obtained: Figure 4d The structure shown.

[0066] Exemplarily, the depth of the two isolation regions may extend downward from the upper surface of the barrier layer 14 (ie, the upper surface of the substrate 1 ) to the upper surface of the buffer layer 12 , thereby achieving planar device isolation.

[0067] S305 , depositing an ohmic contact metal on the upper surface of the second P-GaN layer and performing annealing to form a metal layer in ohmic contact with the second P-GaN layer.

[0068] In one example, a metal layer 4 can be formed by sputtering a metal on the upper surface of the second P-GaN layer 3 by a physical vapor deposition (PVD) process, and an ohmic contact between the metal layer 4 and the second P-GaN layer 3 can be achieved by annealing. Figure 4e The structure shown.

[0069] Exemplarily, the annealing may be performed at an annealing temperature of 400° C.-800° C., for 30 seconds-200 seconds, and in an annealing atmosphere of a mixed gas of N 2 / O 2 .

[0070] Since the P-GaN layer has been etched in two steps in steps S302 and S303, it is difficult to achieve ohmic contact between the metal layer 4 and the second P-GaN layer 3 subsequently. Annealing the metal layer 4 composed of Ni / Au stacked metal under the above-mentioned annealing conditions can effectively achieve ohmic contact between the metal layer 4 and the second P-GaN layer 3.

[0071] S306, depositing a continuous passivation layer on the substrate, the first P-GaN layer and the upper surface of the metal layer.

[0072] In one example, a continuous passivation layer 5 (see FIG. 5 ) can be deposited on the upper surface of the substrate 1, the first P-GaN layer 2, and the metal layer 4 by using a plasma enhanced atomic layer deposition (PEALD) or atomic layer deposition (ALD) or enhanced chemical vapor deposition (ECVD) or low pressure chemical vapor deposition (LPCVD) process. Figure 4f ); so that the passivation layer 5 can cover the side surfaces of the first P-GaN layer 2, the second P-GaN layer 3 and the metal layer 4.

[0073] S307, etching the gate groove region on the upper surface of the continuous passivation layer until the first P-GaN layer, to form a gate groove; and depositing a gate in Schottky contact with the first P-GaN layer in the gate groove.

[0074] In one example, photolithography and development technology can be used to cover the non-gate groove area on the upper surface of the continuous passivation layer with photoresist as a mask layer, and then the uncovered gate groove area is etched until the first P-GaN layer 2 is reached by reactive plasma etching (RIE) or inductively coupled plasma etching (ICP) to form a gate groove 52. Then, in the gate groove 52, a gate metal is deposited on the upper surface of the first P-GaN layer 2 to form a gate 7 in Schottky contact with the first P-GaN layer 2, and the gate 7 is obtained as shown in FIG. Figure 4g The structure shown.

[0075] S308, etching the source groove region, the P-GaN groove region and the drain groove region on the upper surface of the continuous passivation layer to form a source groove, a P-GaN groove and a drain groove respectively.

[0076] In one example, the passivation layer of the source groove region, the P-GaN groove region and the drain groove region can be etched away first to form a P-GaN groove 53; then the etching is continued in the source groove region and the drain groove region until the channel layer 13 is formed to form a source groove 51 and a drain groove 54, and the following is obtained: Figure 4h The structure shown.

[0077] S309, depositing ohmic contact metals in the source groove, the drain groove and the P-GaN groove respectively to form a source in ohmic contact with the substrate in the source groove, and a drain extending laterally to the upper surface of the metal layer in the drain groove.

[0078] Exemplarily, an ohmic contact metal can be deposited in the source groove 51, the drain groove 54 and the P-GaN groove 53 and annealed to form a source 6 in ohmic contact with the substrate in the source groove 51, and a drain 8 extending laterally to the upper surface of the metal layer 4 is formed in the drain groove 52, so as to obtain Figure 1 The structure shown (i.e., drain-modulated GaN device).

[0079] According to the method provided by the present invention, two P-GaN layers with different thicknesses are formed by a two-step etching method. Compared with the traditional method of etching grooves and then growing to reduce the dynamic on-resistance of the device, the process steps of the present invention are fewer, the process complexity is lower, and the dynamic on-resistance of the device can be effectively reduced; and the gate leakage current of the Schottky contact is smaller.

[0080] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0081] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0082] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0083] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, any modifications made without departing from the concept of the present invention should be deemed to belong to the protection scope of the present invention.

Claims

1. A method for preparing a drain modulated GaN device, characterized in that: include: preparing a substrate; Depositing a P-GaN layer on the upper surface of the substrate, and etching and thinning a non-first P-GaN region on the upper surface of the P-GaN layer to form a partially thinned P-GaN layer; Etching the non-first P-GaN region and the non-second P-GaN region on the upper surface of the partially thinned P-GaN layer until the upper surface of the substrate, so as to form a first P-GaN layer in the first P-GaN region and a second P-GaN layer in the second P-GaN region; Performing ion implantation on both sides of the substrate to form a first isolation region and a second isolation region; Depositing an ohmic contact metal on the upper surface of the second P-GaN layer and performing annealing to form a metal layer in ohmic contact with the second P-GaN layer; Depositing a continuous passivation layer on the substrate, the first P-GaN layer and the upper surface of the metal layer; Etching the gate groove region on the upper surface of the continuous passivation layer until the first P-GaN layer is formed to form a gate groove; and depositing a gate in Schottky contact with the first P-GaN layer in the gate groove; Etching the source groove region, the P-GaN groove region and the drain groove region on the upper surface of the continuous passivation layer to form a source groove, a P-GaN groove and a drain groove, respectively, wherein the source groove, the gate groove, the P-GaN groove and the drain groove are sequentially arranged along a first direction, and the first direction is parallel to the horizontal direction; Ohmic contact metals are deposited in the source groove, the drain groove and the P-GaN groove respectively to form a source in the source groove in ohmic contact with the substrate, and a drain extending laterally to the upper surface of the metal layer is formed in the drain groove.

2. The preparation method according to claim 1, characterized in that: When the metal layer is annealed, the annealing temperature ranges from 400° C. to 800° C., the annealing time ranges from 30s to 200s, and the annealing atmosphere is a mixed gas of N2 / O2.

3. A drain-modulated GaN device, characterized in that: The GaN device is prepared according to the method of claim 1 or 2, and the GaN device comprises: A substrate, wherein a first isolation region and a second isolation region are respectively disposed on two sides of the substrate; A first P-GaN layer and a second P-GaN layer, wherein the first P-GaN layer and the second P-GaN layer are sequentially arranged on the upper surface of the substrate along a first direction, between the first isolation region and the second isolation region; wherein the first direction is parallel to a horizontal direction, and the thickness of the first P-GaN layer is greater than that of the second P-GaN layer; a metal layer, the metal layer being disposed on an upper surface of the second P-GaN layer and forming an ohmic contact with the second P-GaN layer; A passivation layer, the passivation layer is arranged on the upper surfaces of the substrate, the first P-GaN layer and the metal layer, and covers the side surfaces of the first P-GaN layer, the second P-GaN layer and the metal layer, and the upper surface of the passivation layer is sequentially provided with a source groove, a gate groove, a P-GaN groove, and a drain groove along the first direction; The source groove and the drain groove penetrate the passivation layer and extend into the substrate; the gate groove penetrates the passivation layer and extends to the upper surface of the first P-GaN layer, and the P-GaN groove penetrates the passivation layer and extends to the upper surface of the metal layer; the P-GaN groove is adjacent to the drain groove and is connected in the horizontal direction; A source electrode, the source electrode being arranged in the source electrode groove and in ohmic contact with the substrate; A gate, the gate being disposed in the gate groove, and an upper surface of the first P-GaN layer and the first P-GaN layer forming a Schottky contact; A drain electrode is disposed in the drain groove and extends laterally to an upper surface of the metal layer.

4. The GaN device according to claim 3, characterized in that: The substrate comprises a substrate layer, a buffer layer, a channel layer and a barrier layer which are sequentially stacked from bottom to top, and the source groove and the drain groove both extend into the channel layer.

5. The GaN device according to claim 4, characterized in that: The material of the barrier layer includes Al x Ga 1-x The range of N,x includes 0.1-0.

5.

6. The GaN device according to claim 3, characterized in that: The material of the metal layer includes Ni / Au laminated metal.

7. The GaN device according to claim 6, characterized in that: The thickness of the Ni layer in the metal layer ranges from 5nm to 50nm, and the thickness of the Au layer ranges from 5nm to 50nm.

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