Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a method of forming the semiconductor device. The method includes forming a nanostructured channel stack on a substrate by forming source / drain openings. The method further includes forming a sacrificial source / drain in the source / drain opening. The method further includes increasing the tensile stress of the nanostructure channel stack by replacing the sacrificial source / drain with a replacement source / drain having a germanium concentration exceeding the sacrificial source / drain.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each smaller and more complex than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking has also increased the complexity of processing and manufacturing ICs. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a nanostructure channel stack on a substrate by forming a source / drain opening; forming a sacrificial source / drain in the source / drain opening; and increasing the tensile stress of the nanostructure channel stack by replacing the sacrificial source / drain with a replacement source / drain having a germanium concentration greater than that of the sacrificial source / drain.

[0004] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a nanostructure stack on a substrate by forming a source / drain opening through a multilayer lattice comprising alternating first and second semiconductor layers; forming a sacrificial gate structure on the nanostructure stack; forming a gate spacer adjacent to the sacrificial gate structure; forming a sacrificial source / drain in the source / drain opening; forming an etch stop layer on the sacrificial source / drain; forming an interlayer dielectric on the etch stop layer; exposing an upper surface of the sacrificial source / drain by removing an upper portion of the interlayer dielectric and an upper portion of the etch stop layer; replacing the sacrificial source / drain with a replacement source / drain; and, after replacing the sacrificial source / drain, forming an active gate by replacing the sacrificial gate structure and an intermediate layer of the nanostructure stack.

[0005] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a first nanostructure channel; a second nanostructure channel located above the first nanostructure channel; an internal spacer located between the first nanostructure channel and the second nanostructure channel; a gate spacer located on the second nanostructure channel; a source / drain adjacent to the first nanostructure channel and the second nanostructure channel, the source / drain comprising an upper recess extending to a first depth, the drain / source having a germanium concentration exceeding about 75%; a source / drain contact located on the source / drain, the source / drain contact extending into the upper recess; a covering layer located between the source / drain contact and the gate spacer, the covering layer extending into the upper recess to reach a second depth higher than the first depth; and a protective layer located between the gate spacer and the covering layer, the protective layer extending to a level higher than the bottom surface of the gate spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B is a schematic cross-sectional side view of a portion of an IC device according to an embodiment of the present disclosure.

[0008] Figure 2A-23 are views of various embodiments of IC devices at different stages of fabrication in accordance with various aspects of the present disclosure.

[0009] Fig.24 is a flow chart of a method of forming an IC device according to various embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] In addition, for ease of description, spacing relation terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spacing relation terms are intended to encompass different orientations of the device in use or operating processes. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spacing relation descriptors used herein should be interpreted accordingly.

[0012] Terms expressing relative degrees, such as "about", "substantially", etc., should be interpreted as terms that would be understood by a person of ordinary skill in the art based on the current technical specifications.

[0013] The terms "first", "second", and "third" etc. may be used herein to describe a sequence of events or an order of elements, but may be interchanged or varied in some cases. For example, a second layer may be formed on a first layer (e.g., sequentially after the first layer), but in some cases, the first layer may be referred to as a "second layer", "third layer", or "fourth layer", etc., and the second layer may also be referred to as a first layer, a third layer, a fourth layer, etc.

[0014] The term "surrounding" may be used to describe a structure that completely or partially surrounds another element or structure, such as in three-dimensional space. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) without surrounding the second structure on two vertical sides (e.g., top and bottom). In another example, a first structure may partially wrap around a second structure, for example, by wrapping around three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0015] The source / drain regions may be referred to individually or collectively as source / drain, depending on the context.

[0016] The present disclosure generally relates to semiconductor devices, and more specifically to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs) or nanostructured FETs (e.g., nanosheet FETs (NSFETs), nanowire FETs (NWFETs)), gate-all-around FETs (GAAFETs), etc.

[0017] In nanosheet FETs, SiGe can be used as the semiconductor material for the source / drain. To avoid epitaxial damage during source / drain formation, a SiB layer and a SiGe layer with a lower Ge concentration are first grown before growing a high Ge concentration layer. This reduces the stress that can be applied to the channel, causing the transistor current to drop.

[0018] The embodiments of the present disclosure form a SiGe sacrificial source / drain, which is later replaced with a pure Ge or high Ge concentration source / drain. Therefore, the lattice constant can be increased, the stress applied to the channel is increased, and the drive current is increased. Pure Ge or high concentration Ge source / drain can also reduce the source / drain contact resistance, which is beneficial to increase the current output.

[0019] Figure 1A and Figure 1B A schematic cross-sectional side view of a portion of a nanostructure device 10 is shown, which may be an integrated circuit (IC) device 10 according to various embodiments. Figure 1A The view in the XZ plane is shown. Figure 2A The view in the YZ plane is shown. Figure 1A and Figure 1B 10 of nanostructured devices to provide understanding Figure 2A-23 Background of the technical features and benefits of the various embodiments shown in .

[0020] The nanostructure device 10 includes a source / drain region (or "source / drain") 82P that includes a high Ge concentration semiconductor material to improve stress in the nanostructure channel 22 adjacent thereto. Although the nanostructure device 10 is described with reference to a nanosheet transistor or "nanostructure device" 20A, it should be understood that embodiments may also include planar field effect transistors (FETs), fin FETs (or FinFETs), etc., each of which may include a plurality of transistors as described in reference to the embodiment of the present invention. Figure 2A-23 The source / drain region.

[0021] refer to Figure 1A , the device 10 may be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). The nanostructure device 20A is formed on and / or in the substrate 110 and generally includes a gate structure 200 spanning and / or surrounding semiconductor channels 22A, 22B, 22C (also referred to as "nanostructures"), semiconductor fins 32 (see Figure 1B ) protrude from the isolation structure 36 and are isolated by the isolation structure 36. The gate structure 200 controls the current flowing between the source / drain 82P on either side of its channel 22A, 22B, 22C.

[0022] The nanostructured device 20A shown includes three channels 22A, 22B, 22C, which are laterally adjacent to source / drain components 82P and are covered and surrounded by a gate structure 200. Generally, the number of channels 22 is two or more, such as three or four or more. In some embodiments, the channel 22A stack is on corresponding fins 32, and channels above the channel 22A (e.g., channels 22B, 22C) are omitted, and the number of channels 22 corresponding to each transistor (e.g., nanostructured device 20A) is 1. The gate structure 200 controls the flow of current through channels 22A, 22B, 22C to and from the source / drain components 82P based on the voltages applied at the gate structure 200 and the source / drain components 82P.

[0023] In some embodiments, the fin structure 32 includes silicon. In some embodiments, the nanostructured device 20A includes a PFET, and its source / drain components 82P include silicon germanium (SiGe), Ge, GeSn, SiGeSn, etc., which may be undoped or doped to form, for example, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or another suitable semiconductor material. Generally, the source / drain components 82P may include any combination of suitable semiconductor materials and suitable dopants. In some embodiments, the source / drain components 82P include Si x C y 、Si x Ge y 、Si x Sb y 、Si x P y 、Si x As y , where 0 < x < 1 and 0 < y < 1 (as appropriate). The source / drain components 82P can be replacement source / drains 82P formed by a process of removing sacrificial source / drains 82L ( Figure 8A-8C ), and then forming the replacement source / drains 82P. The process of forming the replacement source / drains 82P is described in more detail with reference to Figures 11A-22B .

[0024] Channels 22A, 22B, 22C each include a semiconductor material, such as silicon or germanium, or may include a silicon compound or alloy, such as SiGe, SiGeSn, GeSn, etc. Channels 22A, 22B, 22C are nanostructures (e.g., having at least one dimension in the range of 0.1 nm to 10 nm), and may also each have an elongated shape and extend in the X direction. In some embodiments, channels 22A, 22B, 22C each have a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shapes. The cross-sectional profile of channels 22A, 22B, 22C may be rectangular, circular, square, circular, elliptical, hexagonal, or a combination thereof.

[0025] In some embodiments, for example due to tapering in the fin etch process (see Figure 3A , Figure 3B ), the lengths of channels 22A, 22B, 22C (e.g., measured in the X-axis direction) may be different from each other. In some embodiments, the length of channel 22C may be smaller than the length of channel 22B, and channel 22B may be smaller than the length of channel 22A. For example, due to a channel trimming process used to expand the spacing between channels 22A, 22B, 22C (e.g., measured in the Z-axis direction) to increase the gate structure manufacturing process window, each of channels 22A, 22B, 22C may not have a uniform thickness (e.g., along the X-axis direction). For example, the middle portion of each of channels 22A, 22B, 22C may be thinner than the ends of each of channels 22A, 22B, 22C. This shape may be collectively referred to as a "dog bone" shape, such as Figure 1A shown.

[0026] In some embodiments, the spacing between channels 22A, 22B, 22C (e.g., between channel 22B and channel 22A or channel 22C) in a vertical direction (e.g., in the Z-axis direction) is in a range between about 8 nanometers (nm) and about 12 nm, although ranges above or below the range may also be beneficial. In some embodiments, the thickness of each of channels 22A, 22B, 22C (e.g., measured in the Z-direction) is in a range between about 5 nm and about 8 nm, although ranges above or below the range may also be beneficial. In some embodiments, the width of each of channels 22A, 22B, 22C (e.g., in Figure 1B The width may be at least about 8 nm as measured in the Y direction as shown, orthogonal to the XZ plane, but in some embodiments the width may be less than 8 nm.

[0027] The gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, respectively. In some embodiments, the gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, which are silicon channels for N-type devices or germanium silicon channels for P-type devices. In some embodiments, the gate structure 200 includes an interfacial layer (IL) 210, one or more gate dielectric layers 600 on the interfacial layer 210, and one or more work function tuning layers 900 (see FIG. 1 ) that are optionally disposed on the gate dielectric layer 600. Fig.23 ) and a metal core layer 290 located on the gate dielectric layer 600 and optionally on the work function tuning layer 900.

[0028] An interfacial layer 210 is formed on the exposed areas of the channels 22A, 22B, 22C and the top surface of the fin 32. The interfacial layer 210 may be an oxide of the material of the channels 22A, 22B, 22C. The interfacial layer 210 promotes adhesion of the gate dielectric layer 600 to the channels 22A, 22B, 22C. In some embodiments, the thickness of the interfacial layer 210 is about 5 angstroms. to about In some embodiments, the thickness of the interface layer 210 is about An interface layer 210 that is too thin may have voids or insufficient adhesion. An interface layer 210 that is too thick may consume the gate fill window, which is related to threshold voltage tuning and resistance. In some embodiments, the interface layer 210 is doped with a dipole, such as lanthanum, for threshold voltage tuning.

[0029] In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination thereof. In some embodiments, the thickness of the gate dielectric layer 600 is about to about The gate dielectric layer 600 may be a single layer or multiple layers.

[0030] The gate structure 200 also includes a metal layer 290. The metal layer 290 may include a conductive material, such as Co, W, Ru, combinations thereof, and the like. In some embodiments, the metal core layer 290 is or includes a Co, W, or Ru-based compound or alloy, which includes one or more elements, such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, and the like. Between the channels 22A, 22B, 22C, the metal layer 290 (in the cross-sectional view) is surrounded by one or more work function metal layers 900, which are then surrounded by a gate dielectric layer 600, which is surrounded by an interface layer 210. The gate structure 200 may also include a glue layer formed between the one or more work function layers 900 and the metal layer 290 to increase adhesion. For simplicity, Figure 1A The glue layer is not specifically shown.

[0031] Nanostructure device 20A may also include source / drain contacts 120 formed on source / drain features 82P. Source / drain contacts 120 may include a conductive layer that is or includes a conductive material, such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination thereof. The conductive layer may be surrounded by one or more liner (or "barrier") layers, such as SiN or TiN, which helps prevent or reduce material from diffusing from source / drain contacts 120 into source / source contacts 120. In some embodiments, the height of source / drain contacts 120 may be in the range of about 1 nm to about 50 nm.

[0032] The silicide layer 118 is located between the source / drain component 82P and the source / source contact 120 to at least reduce the source / drain contact resistance. In some embodiments, the silicide layer 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. In some embodiments, the silicide layer 118 is or includes NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The thickness of the silicide layer 118 can be in the range of about 1nm to about 10nm. A thickness lower than about 1nm may result in insufficient reduction of the contact resistance. A thickness greater than about 10nm may result in an electrical short circuit with the nanostructure 22.

[0033] refer to Figure 1B, the nanostructure device 20A may further include an interlayer dielectric (ILD) 130. The ILD 130 provides electrical isolation between various components of the nanostructure device 20A described above, such as between adjacent source / drain contacts 120. An etch stop layer 131 may be formed before forming the ILD 130, and may be positioned laterally between the ILD 130 and the gate spacer 41, and vertically between the ILD 130 and the source / drain features 82P. In some embodiments, the etch stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO x 、HfAlO x 、HfSiO x , Al2O3 or other suitable materials. In some embodiments, the thickness of the etch stop layer is in the range of about 1 nm to about 5 nm. In some embodiments, in the absence of ILD 130 (e.g., the ILD 130 is completely removed before forming the source / drain contact 120), the etch stop layer 131 can contact the source / source contact 120. For example, before forming the source / drain contact 120, the etch stop layer 131 can be trimmed in the X-axis direction to improve the filling quality of the source / source contact 120.

[0034] The additional ILD layer 135, the additional etch stop layer 136, and the protective layer 132 may be present on the upper surface and / or the side surfaces of the gate structure 200 and the gate spacer 41. The additional ILD layer 135 may be similar to the ILD 130 in most respects. The additional etch stop layer 136 and the protective layer 132 may be similar to the etch stop layer 131 in most respects. The capping layer 133 is a dielectric layer (e.g., formed of SiON) and may be present between the source / drain contacts 120 and the etch stop layer 131 and the protective layer 132. The capping layer 133 may extend to a level below the bottom surface of the etch stop layer 131, such as Figure 1A shown.

[0035] Nanostructure device 20A includes gate spacer 41 (disposed on the sidewalls of gate dielectric layer 600 and IL 210 above metal layer 290, channel 22A), and internal spacer 74 (disposed on the sidewalls of IL 210 and / or gate dielectric layer 600 between channels 22A, 22B, 22C). Internal spacer 74 is also disposed between channels 22A, 22B, 22C. In some embodiments, gate spacer 41 includes multiple layers, for example, a double layer including first and second spacer layers. The first and second spacer layers may each include a dielectric material, for example, a low-k material such as SiOCN, SiON, SiN, SiCN, SiOC, etc. In some embodiments, the second spacer layer does not exist. The materials of the first and second spacer layers may be the same or different from each other. In some embodiments, the upper portion of the second spacer layer may be partially or completely removed (or the first spacer layer may be removed when the second spacer layer does not exist) to increase the aspect ratio of the opening for forming source / drain 82P. Figure 1A An embodiment is depicted in which the upper portion of the gate spacer 41 is not thinned.

[0036] Figure 1A A p-type source / drain 82P associated with nanostructure device 20A as a PFET is depicted. In some embodiments, device 10 includes an additional nanostructure device that is an NFET. Although not shown, the NFET may have an n-type source / drain that is or includes a different material than the PFET. For example, the source / drain 82P of the PFET may be a replacement source / drain 82P, and the source / drain of the NFET may not be a replacement source / drain. That is, the germanium concentration of the replacement source / drain 82P may exceed the germanium concentration of the source / drain of the NFET.

[0037] exist Figure 1A In the embodiment of the present invention, the recessed source / drain portion 82B may be located between the source / drain 82P and the adjacent channel 22. In some embodiments, the recessed source / drain portion 82B is or includes SiB.

[0038] Fig.24 A flow chart of a method 1000 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of the present disclosure is shown. The method 1000 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 1000. Additional actions may be provided before, during, and after the method 1000, and some of the actions described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all actions are described in detail. Figure 2A-23Partial perspective views and / or cross-sectional views of a workpiece at various stages of fabrication according to an embodiment of the method 1000 are shown to describe the method 1000. For the avoidance of doubt, throughout the figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. It should be noted that since the workpiece can be fabricated into a semiconductor device, the workpiece may be referred to as a semiconductor device as the context requires.

[0039] Figures 2A to 23 is a diagram of an intermediate stage in the fabrication of a FET (eg, a nanostructure FET) according to some embodiments.

[0040] exist Figure 2A and Figure 2B In the embodiment of the present invention, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 110 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may be used, such as single-layer, multi-layer, or gradient substrates.

[0041] In addition, Figure 2A and Figure 2B In the embodiment of the present invention, a multilayer stack 25 or "lattice" is formed on a substrate 110 of alternating layers of first semiconductor layers 21A, 21B, 21C (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23. In some embodiments, the first semiconductor layer 21 can be or include a first semiconductor material, such as silicon, silicon carbide, germanium, SiGe, GeSn, SiGeSn, etc., and the second semiconductor layer 23 can be formed of a second semiconductor material having an etching selectivity different from that of the first semiconductor material. In most embodiments, the second semiconductor material is silicon germanium. Each layer 21, 23 of the multilayer stack 25 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0042] Three first semiconductor layers 21 and four second semiconductor layers 23 are shown. In some embodiments, the multilayer stack 25 may include fewer or more pairs of first semiconductor layers 21 and second semiconductor layers 23. Although the multilayer stack 25 is shown to include the second semiconductor layer 23 as the bottommost layer, in some embodiments, the bottommost layer of the multilayer stack 25 may be the first semiconductor layer 21. Although the multilayer stack 25 is shown to include the second semiconductor layer 23 as the topmost layer, in some embodiments, the uppermost layer of the multilayer stack 25 may be the first semiconductor layer 21.

[0043] Due to the high etching selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form a channel region of a nanoFET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form a channel region. The high etching selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form a channel region of a nanoFET.

[0044] exist Figure 3A and Figure 3B In the embodiment, the fin 32 is formed in the substrate 110, and the nanostructures 22, 24 are formed in the multilayer stack 25, corresponding to Fig.24 Action 1100. In some embodiments, the nanostructures 22, 24 and the fins 32 can be formed by etching grooves in the multilayer stack 25 and the substrate 110. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. The first nanostructures 22A, 22B, 22C (hereinafter also referred to as "channels 22") are formed by the first semiconductor layer 21, and the second nanostructure or "intermediary layer" 24 is formed by the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 can be about 18nm to about 100nm, but in some embodiments, a distance CD1 less than 18nm may be beneficial. To simplify the description, Figure 3A and Figure 3B A portion of the device 10 is shown in FIG. 1 , including two fins 32 . Fig.24 The process 1000 shown can be extended to any number of fins and is not limited to Figure 3A-Figure 23 Two fins 32 are shown.

[0045] The fins 32 and nanostructures 22, 24 may be patterned by any suitable method. For example, one or more photolithography processes, including double patterning or multiple patterning processes, may be used to form the fins 32 and nanostructures 22, 24. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing a pitch smaller than that obtained using a single direct photolithography process. As an example of a multiple patterning process, a sacrificial layer may be formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 32.

[0046] Figure 3A and Figure 3BThe fin 32 is shown with tapered sidewalls such that the width of each of the fin 32 and / or nanostructures 22, 24 increases continuously in a direction toward the substrate 110. In such an embodiment, each nanostructure 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the widths of the fin 32 and nanostructures 22, 24 are substantially similar, and each nanostructure 22 and 24 is rectangular in shape.

[0047] exist Figure 3A and Figure 3B In the embodiment of the present invention, an isolation region or feature 36 (which may be a shallow trench isolation (STI) region or feature) is formed adjacent to the fin 32. The isolation region 36 may be formed by depositing an insulating material on the substrate 110, the fin 32, and the nanostructures 22, 24, and between adjacent fins 32 and nanoparticles 22, 24. The insulating material may be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 110, the fin 32, and the nanostructures 22, 24. Thereafter, a core material such as those described above may be formed on the liner.

[0048] The insulating material undergoes a removal process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc., to remove excess insulating material on the nanostructures 22, 24. The top surfaces of the nanostructures 22, 24 may be exposed and flush with the insulating material after the removal process is completed.

[0049] The insulating material is then recessed to form isolation regions 36. After the recessing, the upper portions of the nanostructures 22, 24 and fins 32 may protrude from between adjacent isolation regions 36. The isolation regions 36 may have top surfaces that are flat, convex, concave, or a combination thereof as shown. In some embodiments, the isolation regions 36 are recessed by an acceptable etching process, such as using, for example, dilute hydrofluoric acid (dHF) to remove oxides, which is selective to the insulating material and leaves the fins 32 and nanostructures 22, 24 substantially unchanged.

[0050] FIG. 2A to FIG. 3B One embodiment of forming the fin 32 and nanostructures 22, 24 is shown (e.g., etched last). In some embodiments, the fin 32 and / or nanostructures 22, 24 are epitaxially grown in trenches in the dielectric layer (e.g., etched first). The epitaxial structure may include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material.

[0051] exist Figure 3A and Figure 3BIn the embodiment of the present invention, appropriate wells (not shown separately) may be formed in the fins 32, nanostructures 22, 24, and / or isolation regions 36. Using a mask, n-type impurity implantation may be performed in the p-type region of the substrate 110, and p-type impurity implantation may be performed in the n-type region of the substrate 100. Example n-type impurities may include phosphorus, arsenic, antimony, etc. Example p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implant damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fins 32 and nanostructures 22, 24 may avoid separate implantations, although in-situ doping and implantation doping may be used together.

[0052] exist Figure 4A-4C In, corresponding to Fig.24 In action 1200, a dummy or sacrificial gate structure 40 is formed on the fin 32 and / or the nanostructures 22, 24. A dummy gate layer or sacrificial gate layer 45 is formed on the fin 32 and / or the nanostructures 22, 24. The sacrificial gate layer 45 may be or include a material having a high etching selectivity relative to the isolation region 36. The sacrificial gate layer 45 may be a conductor, a semiconductor, or a non-conductor material, and may be or include amorphous silicon, polycrystalline silicon (poly), polycrystalline silicon germanium, metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. A mask layer 47 is formed on the sacrificial gate layer 45, and may include, for example, silicon nitride, silicon oxynitride, and the like. In some embodiments, a gate dielectric layer 43 is formed before the sacrificial gate layer 45 between the sacrificial gate layer 45 and the fin 32 and / or the nanostructures 22, 24. In some embodiments, mask layer 47 includes a first mask layer 47A contacting sacrificial gate layer 45, and a second mask layer 47B covering and contacting first mask layer 47A. First mask layer 47A may be or include the same or different material as second mask layer 47B.

[0053] A spacer layer 41 is formed on the sidewalls of the mask layer 47 and the sacrificial gate layer 45. According to some embodiments, the spacer layer 41 is or includes an insulating material such as SiOCN, SiOC, SiCN, etc. (or reference numerals). Figure 1A The spacer layer 41 may be formed by depositing a spacer material layer (not shown) on the mask layer 47 and the sacrificial gate layer 45. According to some embodiments, a portion of the spacer material layer between the sacrificial gate structures 40 is removed using an anisotropic etching process. In some embodiments, as shown in FIG. Figure 4B and Figure 4CAs shown in detail, the spacer layer 41 includes a first spacer layer 41A in contact with the nanostructure 22C, the gate dielectric layer 43, the sacrificial gate layer 45, and the first and second mask layers 47A, 47B. The second spacer layer 41B of the spacer layer 41 can be in contact with the first spacer layer 41A. The first spacer layer 41A can be or include the same or different material as the second spacer layer 41B.

[0054] exist Figure 5A and Figure 5B In the embodiment, the portions of the protruding fins 32 and / or the nanostructures 22, 24 not covered by the sacrificial gate structure 40 are etched by performing an etching process, thereby forming a source / drain opening 59, corresponding to Fig.24 The recess may be anisotropic such that the portion of the fin 32 directly below the sacrificial gate structure 40 and the spacer layer 41 is protected and substantially not etched. According to some embodiments, the top surface of the recessed fin 32 may be substantially coplanar with the top surface of the isolation region 36. According to some other embodiments, such as Figure 5B As shown, the top surface of the recessed fin 32 may be lower than the top surface of the isolation region 36. For simplicity, Figure 5A Three vertical stacks of nanostructures 22, 24 after the etching process are depicted. In general, the etching process may be used to form fewer or more vertical stacks of nanostructures 22, 24 on the fin 32 than shown. In some embodiments, the second mask layer 47B is exposed after the etching process, for example, due to the removal of upper portions of the spacer layers 41A, 41B during the etching process. Figure 5B Fin spacers 41F are depicted, being portions of the first and / or second spacer layers 41A, 41B, over the isolation regions 36 adjacent to respective fins 32 .

[0055] Figures 6A-7B The formation of the internal spacer 74 is shown according to various embodiments.

[0056] exist Fig. 6A , Figure 6B In the embodiment of the present invention, a selective etching process is performed to recess the ends of the nanostructures 24 exposed by the openings in the spacer layer 41 without substantially attacking the nanostructures 22. After the selective etching process, recesses are formed in the nanostructures 24 where the removed ends were once located. Then, after the recesses are formed, an inner spacer layer 74L is formed to fill (partially or completely) the recesses in the nanostructures 22 formed by the previous selective etching process. The inner spacer layer 74L may be a suitable dielectric material, such as silicon carbon nitride (SiCN), silicon oxynitride carbon nitride (SiOCN), etc., formed by a suitable deposition method such as PVD, CVD, ALD, etc.

[0057] exist Fig. 7A and Figure 7B In the embodiment, after forming the inner spacer layer 74L, an etching process, such as an anisotropic etching process, is performed to remove the portion of the inner spacer layer 74L located outside the recess, for example, to remove the portion of the inner spacer layer 74L on the sidewalls of the nanostructure 22 and the fin 32. The remaining portion of the inner spacer layer 74L (e.g., the portion disposed within the recess in the nanostructure 24) forms the inner spacer 74. The resulting structure is as shown in FIG. Fig. 7A shown.

[0058] exist Fig. 8A , Figure 8B In the embodiment of the present invention, a first material layer 110A is formed in the source / drain opening 59. The first material layer 110A may be or include an undoped semiconductor, such as undoped silicon. The deposition may include one or more operations, such as CVD, which may be ultra-high vacuum CVD (UHV-CVD), which allows for improved control of the deposition rate and purity of the first material layer 110A. The first material layer 110A may extend to the level of the upper surface of the fin 32 or slightly above the level of the upper surface of the fin 32. In some embodiments, the first material layer 110A is not formed.

[0059] Then, the source / drain 82L associated with the p-type nanostructure device can be epitaxially grown from the epitaxial material, corresponding to Fig.24 Action 1400. The source / drain 82L may be grown from the channel 22 and the undoped silicon layer 110A. The source / drain 82L is formed so that each dummy gate structure 40 is disposed between a corresponding adjacent pair of source / drain 82L. In some embodiments, the spacer layer 41 separates the source / gate 82L from the sacrificial gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the gate of a subsequently formed device. The source / drain 82L may have a surface that is raised from a corresponding surface of the fin 32 and may have facets, such as Figure 8B In some embodiments, adjacent source / drain regions 82L may be merged to form a single source / drain region 82L adjacent to two adjacent fins 32 .

[0060] exist Figure 8C According to some embodiments, before forming the source / drain 82L, the end of the nanostructure 22 may be recessed, and then the semiconductor layer 82B may be formed in the recess. In at least some embodiments, the end of the nanostructure 22 may be recessed during the source / drain formation process. The semiconductor layer 82B may be a SiB layer, which is beneficial for preventing damage to the source / drain 82L during the formation of the source / drain. In a subsequent process of replacing the source / drain 82L with a high Ge% source / drain 82P, the semiconductor layer 82B may remain in the recess, or may be removed during the replacement process.

[0061] exist Fig.9A and Fig. 9B In the embodiment, after forming the source / drain 82L, an ILD 130 covering the source / drain 82L and adjacent to the spacer layer 41 may be formed. In some embodiments, the ESL 131 is formed before forming the ILD 130. The ESL 131 may be formed by depositing a conformal thin layer of a dielectric material different from the ILD 130, such as SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO x 、HfAlO x 、HfSiO x , Al2O3 or one or more of other suitable materials. After depositing ESL 131, ILD 130 may be deposited by a suitable process, such as a blanket deposition process, including PVD, CVD, ALD, etc. The material of ILD 130 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k value) lower than the k value of silicon dioxide (about 3.9)). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon carbide (SiO x C y ), spin-on glass (SOG), or a combination thereof. The ILD 130 may be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD, or other deposition processes.

[0062] exist Fig. 10A and Fig. 10B In the embodiment of the present invention, after forming the source / drain 82L, the ESL 131 and the ILD 130, an active or replacement gate structure 200 may be formed. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed on the ILD 130 and the ESL 131. In the planarization process, a portion of the hard masks 47A, 47B and the gate spacer 41 are also removed. After the planarization process, the sacrificial gate layer 45 is exposed. The top surfaces of the ILD 130 and the ESL 131 may be coplanar with the top surfaces of the dummy gate layer 45 and the gate spacer 41.

[0063] Then, the sacrificial gate layer 45 is removed in an etching process, thereby forming an opening. In some embodiments, the sacrificial gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate layer 45 without etching the spacer layer 41. The sacrificial gate dielectric 43 (when present) may be used as an etching stop layer when etching the sacrificial gate layer 45. After removing the sacrificial gate layer 45, the sacrificial gate dielectric 43 may be removed.

[0064] Removing the nanostructure 24 to release the nanostructure 22 corresponds to Fig.24 Action 1600. After removing the nanostructures 24, the nanostructures 22 form a plurality of nanosheets extending horizontally (e.g., parallel to the main upper surface of the substrate 110). The removal of the nanostructures 24 may be performed by one or more selective etching processes using an etchant that is selective to the material of the nanostructures 24, so that the nanostructures 24 are removed without substantially attacking the nanostructures 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, a combination thereof, and the like.

[0065] In some embodiments, the nanosheet 22 is shaped (e.g., thinned) by a further etching process to improve the gate fill window. The shaping may be performed by an isotropic etching process that is selective to the nanosheet 22. After the shaping, the nanosheet 22 may have a dog-bone shape, wherein the middle portion of the nanosheet 22 along the X direction is thinner than the peripheral portion of the nanosheet 22.

[0066] exist Fig. 10A and Fig. 10B In the example, after releasing the channel 22, a replacement gate 200 is formed, corresponding to Fig.24 The replacement gate 200 may be referred to as an active gate 200 or a gate structure 200. The gate structure 200 may be formed by a series of deposition operations, such as ALD cycles, which deposit various layers of the gate structure 200 in the opening, such as Fig.23 shown.

[0067] Fig.23 is a detailed view of a portion of the gate structure 200. The gate structure 200 generally includes an interfacial layer (IL, or "first IL" described below) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interfacial layer 240 or a second work function layer 700.

[0068] refer to Fig.23 In some embodiments, the first IL 210 includes an oxide of the semiconductor material of the substrate 110, such as silicon oxide. In other embodiments, the first IL 210 may include another suitable type of dielectric material. The thickness of the first IL 210 is about to about within the range.

[0069] Still refer to Fig.23, a gate dielectric layer 600 is formed on the first IL 210. In some embodiments, the gate dielectric layer 600 is formed using an atomic layer deposition (ALD) process to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is performed using about 40 to 80 deposition cycles at a temperature range of about 200° C. to about 300° C. In some embodiments, the ALD process uses HfCl4 and / or H2O as a precursor. This ALD process can form the gate dielectric layer 600 to a thickness of about to about within the range.

[0070] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, at least one of which includes a dopant, such as lanthanum, magnesium, yttrium, etc., which can be driven by an annealing process to modify the threshold voltage of the nanostructure device 20A.

[0071] Further references Fig.23, a second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second IL 240 also provides improved thermal stability for the gate structure 200 and is used to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is achieved by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer includes one or more of the following materials: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfSrO or other suitable materials. In a specific embodiment, the high-k capping layer includes titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited by ALD using about 40 to about 100 cycles at a temperature of about 400 degrees Celsius to about 450 degrees Celsius. A thermal anneal is then performed to form the second IL 240, which in some embodiments may be or include TiSiNO. After the second IL 240 is formed by the thermal anneal, an atomic layer etch (ALE) with artificial intelligence (AI) control may be performed cyclically to remove the high-k capping layer while substantially not removing the second IL 240. Each cycle may include a first pulse of WCl5, followed by an Ar purge, followed by a second pulse of O2, and then another Ar purge. The high-k capping layer is removed to increase the gate fill window for further multi-threshold voltage tuning by metal gate patterning.

[0072] In addition, Fig.23 According to some embodiments, after forming the second IL 240 and removing the high-k capping layer, a work function barrier layer 700 is optionally formed on the gate structure 200. The work function barrier layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In a specific embodiment, the work function barrier layer 700 is TiN. The thickness of the work function barrier layer 700 can range from about 100 Å to about 200 Å. To date The inclusion of the work function barrier layer 700 provides additional threshold voltage tuning flexibility. Generally speaking, the work function barrier layer 700 increases the threshold voltage of NFET transistor devices and decreases the threshold voltage (magnitude) of PFET transistor devices.

[0073] In some embodiments, the work function metal layer 900 is formed on the work function barrier layer 700, and the work function metal layer 900 may include at least one of an N-type work function metal, an in-situ capping layer, or an oxygen barrier layer. The N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating, and / or other suitable methods, and may have a thickness of about and The in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN or another suitable material and has a thickness of about and The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer, which would result in an undesirable shift in the threshold voltage. The oxygen barrier layer is formed of a dielectric material that can prevent oxygen from penetrating into the N-type work function metal layer and can protect the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using ALD and has a thickness of about 100 nm. Peace The thickness between.

[0074] Fig.23 Metal layer 290 is further shown. In some embodiments, a glue layer (not separately shown) is formed between the oxygen barrier layer of the work function metal layer and metal layer 290. The glue layer can promote and / or enhance adhesion between metal layer 290 and work function metal layer 900. In some embodiments, the glue layer can be formed of a metal nitride such as TiN, TaN, MoN, WN, or another suitable material using ALD. In some embodiments, the thickness of the glue layer is about Peace . The metal layer 290 may be formed on the glue layer and may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. In some embodiments, the metal layer 290 may be deposited using methods such as CVD, PVD, plating, and / or other suitable processes. In some embodiments, a seam 510 (the tannin may be an air gap) is formed vertically in the metal layer 290 between the channels 22A, 22B, and 22C. In some embodiments, the metal layer 290 is conformally deposited on the work function metal layer 900. The seam 510 may be formed due to the merging of films deposited on the sidewalls during conformal deposition. In some embodiments, the seam 510 does not exist between adjacent channels 22A, 22B, and 22C.

[0075] Figures 11A-22BAn embodiment is depicted where source / drain 82L is replaced with high Ge % source / drain 82P to increase the compressive stress on channel 22 . Figures 11A-22B Depicted Fig. 10A A partial region 950 of the device 10 is shown, wherein some components are omitted for simplicity of illustration. For example, Figures 11A-22B , a single source / drain 82L is shown which is replaced by source / drain 82P, however, other source / drain 82L (such as source / drain 82P) may also be replaced by source / drains similar to source / drain 82P during and through the same process. Fig. 10A ).

[0076] exist Fig.11A and Fig. 11B In the embodiment, after forming the gate structure 200, in order to form the source / drain contact 120 in a later operation, a source / drain contact opening 120O is formed in the ILD 130 to remove the material of the ILD 130, thereby exposing the source / drain 82L. The removal of the ILD 130 can be performed by a suitable removal operation, such as wet etching or dry etching including plasma etching, atomic layer etching (ALE), etc.

[0077] Before removing the ILD 130, a second etch stop layer (ESL) 136 may be formed on the upper surface of the gate structure 200, the gate spacer 41, and the ILD 130. Then, a second ILD 135 may be formed on the etch stop layer 136. The formation of the etch stop layer 136 and the second ILD 135 may be similar in most aspects to the reference 1. Fig. 10A and Fig. 10B The formation of the etch stop layer 131 and the ILD 130 are described similarly.

[0078] When removing the ILD 130, an initial opening may be formed through the second ILD 135 and the etch stop layer 136, and then the ILD 130 covering the source / drain 82L may be removed using the second ILD 136 and the etch stop layer 136 including the initial opening as a mask. Then, removing the ILD 130 may include etching the ILD 130 through the opening, for example, by anisotropic dry etching. Fig. 11B As shown, the etching process for removing the ILD 130 may remove the exposed portion of the ILD 130 to a level below the top surface of the source / drain 82L. Then, the exposed portion of the ESL 131 may be removed from the upper surface of the source / drain 82L, thereby exposing the upper surface, as shown in FIG. Fig. 11B shown.

[0079] After removing the ILD 130, a protective (or liner) layer 132 may be formed in the opening 120O, covering the second ILD 135, the second ESL 136, the ILD 130, the ESL 131, and the source / drain 82L. The protective layer 132 may be a dielectric layer that is or includes one or more dielectric materials, such as SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, etc., and may be deposited by a suitable deposition operation, such as PVD, CVD, ALD, etc. Then, the protective layer 132 may be etched back by dry etching to remove the material of the protective layer 132 from the upper surfaces of the second ILD 135, the source / drain 82L, and the ILD 130, thereby forming a dielectric layer 132. Fig. 11B A protective layer 132 is shown.

[0080] After forming the protection layer 132, the source / drain 82L may be slightly recessed, resulting in a recessed upper surface thereof, such as Fig.11A As shown. Then, an additional sidewall spacer 133 may be formed on the upper surface of the protection layer 132 and the source / drain 82L. The sidewall spacer 133 may be a dielectric layer that is or includes one or more dielectric materials, such as SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, etc., and may be deposited by a suitable deposition operation, such as PVD, CVD, ALD, etc. Then, the sidewall spacer 133 may be etched back by dry etching to remove the material of the sidewall insulating layer 133 from the upper surface of the source / drain 82L and the ILD 130, thereby forming Fig.11A Sidewall spacers 132 are shown.

[0081] like Fig. 11B As shown, after forming the protective layer 132 and forming the recessed source / drain opening 120O including the source / drain 82L, the source / drain 82L may have an inclined upper surface that is inclined downward away from the protective layer 132 .

[0082] exist Fig. 12A and Fig. 12B In the process, an oxidation process is performed to form a porous oxide layer 82O on the sacrificial source / drain 82L with the upper surface exposed, corresponding to Fig.24 Action 1500. The thickness of the porous oxide layer 82O can be in the range of about 0.8 nm to about 2 nm, such as about 1 nm. The formation of the porous oxide layer 82O can include thermal oxidation, in which the SiGe sacrificial source / drain 82L is exposed to oxygen or water vapor at high temperature. The thermal oxidation process causes the silicon in the SiGe alloy to react with oxygen to form silicon dioxide (SiO2). Because germanium oxidizes differently than silicon, less stable germanium oxide (GeO2) may be formed, which evaporates at the oxidation temperature. x), thereby affecting the uniformity and quality of the porous oxide layer 82O. That is, there may be holes in the porous oxide layer 82O that extend completely through the porous oxide layer 82, so that the sacrificial source / drain 82L is at least partially exposed through the porous oxide layer 82O. The porous oxide layer 82O can have a porosity large enough to allow etchants and semiconductor precursor gases to pass through, and small enough that the porous oxide layer 82O has sufficient mechanical strength so that it will not break after or during the removal of the source / drain 82L. The size of the pores of the porous oxide layer 82O can be in the range of about 1 angstrom to 10 angstroms.

[0083] exist Figure 13A-13C In the embodiment, the sacrificial source / drain 82L is removed to form an opening 82H, corresponding to Fig.24 Action 1600. The sacrificial source / drain 82L may be removed by an appropriate etching operation, which may include a chlorine-based etchant, a fluorine-based etchant, etc. The etchant may be a gas, which may penetrate the pores of the porous oxide layer 82O and etch the SiGe of the sacrificial source / drain 82L, resulting in the sacrificial source / drain 82L being removed and forming an opening 82H. The opening 82H may inherit the shape of the sacrificial source / drain 82L, such as Fig.13A and Fig. 13B shown.

[0084] In some embodiments, Fig. 13C As shown, some over-etching may occur, thereby removing the end of the nanostructure 22, resulting in a recess 82H1. In some embodiments, the recess 82H1 is not formed by over-etching, but by removing the reference Figure 1A and Figure 1B That is, the first etching operation can remove the semiconductor material of the source / drain 82L, and then the second etching operation can remove the semiconductor material of the semiconductor layer 82B. Fig. 13C As shown, over-etching during the removal of the source / drain 82L may result in the removal of material in the undoped semiconductor layer 110A, thereby forming a recess 82H2.

[0085] although Figure 13A-13CAlthough not separately depicted in the figure, the device 10 may include an NFET in another region of the substrate 110, whose source / drain 82L includes a material having a different material from the source / drain 82L. For example, the source / drain 82L may be a Ge-containing layer of SiGe, GeSn, SiGeSn, and the source / drain in the NFET device region of the substrate 110 may be silicon or another semiconductor material that does not contain germanium. Therefore, the porous oxide layer 82O may be formed on the source / drain 82L in the PFET device region of the substrate 110, and a non-porous oxide layer may be formed on the source / drain in the NFET device region. Therefore, the etchant gas does not penetrate into the source / drain in the NFET device region. In some embodiments, the NFET device region includes a source / drain, which includes a Ge-containing semiconductor material (e.g., SiGe, GeSn, SiGeSn), however, in reference to Figures 12A-13C During the described operation, the NFET device region may be masked so that the etchant gas does not penetrate into the source / drain of the NFET device region.

[0086] exist Figures 14A-14D , after forming 82H, a replacement or "active" source / drain 82P is formed in opening 82H through porous oxide layer 82O, corresponding to Fig.24 Action 1700. The replacement source / drain 82P can be formed by an appropriate epitaxial growth operation that grows the material of the replacement source / drain region 82P in the opening 82H. The replacement source / drain 82P can be or include one or more semiconductor materials, which can include SiGe, Ge, GeSn, SiGeSn. In the replacement source / drain 82P, the concentration of germanium can be in the range of about 75% to 100% (i.e., pure Ge). The epitaxial growth of Ge or SiGe in the source / drain opening can be performed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), etc. In CVD, a gas containing selected elements (e.g., germanium for Ge, silane for Si, and optionally diborane, phosphine, TMGa, TEGa, AsH3 or TBA for doping) is introduced into the reaction chamber. The device 10 can be heated to a high temperature so that the gas reacts or decomposes to form an epitaxial layer. CVD is conducive to good uniformity and control of layer composition. MBE can provide the benefit of increased precision, where elements are evaporated in a high vacuum environment and then condensed on the heated device 10. MBE can provide excellent control over the thickness and composition of the epitaxial layer replacing the source / drain 82P at the atomic level, which is beneficial for nanoscale devices.

[0087] In CVD and MBE, gases (e.g., germane, silane, diborane, phosphine, etc.) may permeate the porous oxide layer 82O so that the gases may react or decompose at the nanostructure 22 in the opening 82H. That is, the exposed side surfaces of the ends of the nanostructure 22 may have semiconductor material grown thereon. During the growth process, growth may initially occur on the ends of the nanostructure 22 to form a first region. Then, as the process continues over time, growth may continue, causing the first region to expand and eventually merge to form a second region. Finally, growth continues until the second regions on both sides of the opening 82H merge with each other and are in contact with at least the nanostructure 22, the internal spacer 74, and the porous oxide layer 82O. In some embodiments, due to the growth profile of the semiconductor material in the opening 82H, one or more air gaps may be formed in the corner region of the replacement source / drain 82P. The formation of the air gaps will refer to Fig.16A and Fig. 16B Describe in more detail.

[0088] In some embodiments, as described above, dopants are introduced in situ into the replacement source / drain 82P. In some embodiments, the dopants include B, Ga, P, As, etc. During the growth process, gaseous diborane, phosphine, trimethyl gallium, triethyl gallium, arsine, tert-butyl arsine, etc. can be flowed in to dope the replacement source / drain 82P in situ. In some embodiments, the replacement source / drain 82P can be doped in subsequent operations, for example, by implanting one or more of B, Ga, P, As, etc.

[0089] exist Fig. 14C In the embodiment shown in FIG. 1 , semiconductor layer 82B is located in the recess between inner spacers 74 adjacent to channel 22 and on undoped semiconductor layer 110A. Therefore, replacement source / drain 82P may initially be grown on the exposed surface of semiconductor layer 82B before merging.

[0090] exist Fig.14D According to the reference Fig. 13C In the described embodiment, the recesses 82H1, 82H2 are located between the inner spacers 74 and on the undoped semiconductor layer 110A adjacent to the channel 22. Therefore, before merging, the replacement source / drain 82P can initially be grown on the exposed surface of the channel 22 (which is recessed from the outer side surface of the inner spacer 74) and on the upper surface of the undoped semiconductor layer 110A.

[0091] exist Fig.15A and Fig. 15B In the embodiment, after forming the replacement source / drain 82P, a source / drain contact 120 may be formed on the replacement source / drain 82P, corresponding to Fig.24Each source / drain contact 120 is located on and electrically connected to a corresponding replacement source / drain 82P. An electrical signal may be applied to the replacement source / drain 82P via the source / drain contact 120.

[0092] The source / drain contact 120 may be or include one or more conductive layers located on the replacement source / drain 82P. For example, the barrier layer or liner layer may include titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive materials. The conductive fill layer may be located on the barrier layer or liner layer and may include a conductive material such as tungsten, cobalt, ruthenium, titanium, aluminum, tantalum, or other suitable conductive materials. Other materials and configurations may be used for the source / drain contact 120 without departing from the scope of the present disclosure.

[0093] The source / drain contact 120 may include a silicide 118. The silicide 118 is formed at the interface between the replacement source / drain 82P and the source / drain contact 120. The silicide 118 may reduce the source / drain contact resistance. In some embodiments, the silicide 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi, YbSi, etc. In some embodiments, the silicide 118 is or includes NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The silicide 118 may be an alloy between the source / drain contact 120 and the replacement source / drain 82P, which may be a mixture of one or more of Ti, Ru, Mo, Ni, Co, W, etc. and at least one of Ge, SiGe, SiGeSn, GeSn, etc. The thickness of the silicide 118 may be in the range of about 1 nm to about 10 nm. A thickness below about 1 nm may result in insufficient reduction in contact resistance. A thickness greater than about 10 nm may result in an electrical short circuit with the nanostructure 22. In some embodiments, the silicide 118 is present below the capping layer 133 and in contact with the capping layer 133.

[0094] Fig.16A and Fig. 16B An optional air gap 82A that may be present in the corner region of the replacement source / drain 82P is depicted. The air gap 82A may be present near the silicide 118, the gate spacer 41, the protective layer 132, and the capping layer 133. That is, the air gap 82A may be located laterally between the capping layer 133 and the gate spacer 41, and vertically between the source / drain 82P and the protective layer 132. As previously described with reference to Figures 14A-14DAs described above, during the growth of the replacement source / drain 82P, growth may initially occur at the end of the nanostructure 22 to form a first region. Then, as the process continues over time, growth may continue, causing the first region to expand and eventually merge to form a second region. Finally, growth continues until the second regions on both sides of the opening 82H merge with each other and are in contact with at least the nanostructure 22, the internal spacer 74, and the porous oxide layer 82O.

[0095] In some embodiments, the growth of the second source / drain 82P may be terminated before its semiconductor material reaches the bottom surface of the protection layer 132 adjacent to the gate spacer 41, thereby forming an air gap 82A. The height of the air gap 82A in the Z-axis direction may be in the range of 0 nm to about 5 nm.

[0096] In reference Figure 2A-Figure 16B In the described embodiment, instead of forming Ge directly in the source / drain opening 59, a SiGe source / drain 82L is formed and then replaced with a high Ge% SiGe or pure Ge, which can achieve various benefits. For example, in the process after the high Ge concentration source / drain is formed, the diffusion of germanium into the channel 22 is prevented. The ILD 130 is also formed before the formation of the high Ge% source / drain, which causes a higher compressive stress in the channel 22 in the PFET. That is, the ILD 130 is formed after the initial source / source formation process of forming the sacrificial source / drain 82L and the NFET source / drain, and the ILD 130 is in place before replacing the sacrificial source / drain 82L with the high Ge% source / drain 82P.

[0097] In reference Figures 11A-16B In the depicted embodiment, the sacrificial source / drain 82L is replaced after the gate structure 200 is formed. In some embodiments, before the gate structure 200 is formed, the sacrificial source / drain 82L may be replaced with an active source / drain 82P having a high Ge% semiconductor material.

[0098] Figures 17A-22B A diagram depicting a process of forming active source / drain 82P by replacing sacrificial source / drain 82L before forming gate structure 200 according to various embodiments.

[0099] exist Fig.17A and Fig. 17BIn the embodiment, after forming the ILD 130 and the ESL 131 and before forming the replacement gate structure 200, the ILD 130 and the ESL 131 are recessed, resulting in the upper surface of the source / drain 82L being exposed. The recessing of the ILD 130 can be performed simultaneously (i.e., without leaving the chamber) or sequentially with the recessing of the ESL 131. For example, the ILD 130 and the etch stop layer 131 can be removed from the sacrificial source / drain 82L by a removal process, and the removal process removes the materials of the ILD 130 and the etch stop layer 131 at substantially the same rate, so that the trench in which the sacrificial source / drain 82L is located reaches a uniform depth. In this example, a physical bombardment technique, such as ion beam etching (IBE), can be performed to simultaneously remove the materials of the ILD 130 and the ESL 131. In another example, the ILD 130 can be removed to a first depth that exposes the ESL 131, and then the ESL 131 can be removed to expose the source / drain 82L. In this example, the first and second etches may be performed to remove the ILD 130 (e.g., silicon dioxide) and then remove the ESL 131 (e.g., silicon nitride). In some embodiments, the source / drain 82L is recessed by the simultaneous process or the sequential process described above. In the sequential process, after removing the ESL 131, the source / drain 82L may be recessed by the third etch. The first, second, and third etches may be wet etches or dry etches. In some embodiments, as Fig.17A As shown, after removing the ILD 130 and the ESL 131, the formation is similar in most aspects to the reference Fig.11A and Fig. 11B The cover layer 133 described above is similar to the cover layer 138 .

[0100] exist Fig.18A and Fig.18B In the embodiment of the present invention, after exposing the upper surface of the source / drain 82L by removing the ILD 130 and the ESL 131, a porous oxide layer 82O is formed on the upper surface of the exposed source / drain 82L. The porous oxide layer 82O may be similar to the reference 1 in most aspects. Fig. 12A and Fig. 12B The porous oxide layer 82O is similar to the reference Fig. 12A and Fig. 12B The porous oxide layer 82O is located on the upper surface of the source / drain 82L and includes SiO and GeO or SiGeO, which has pores therethrough to expose the source / drain 82L. The porosity of the porous oxide layer 82O can be large enough to allow the etchant and semiconductor precursor gas to pass through, and small enough to allow the porous oxide layer 82 to have sufficient mechanical strength so that it will not break during or after the removal of the source / drain 82L. In some embodiments, as Fig.18AAs shown, the porous oxide layer 82O may extend below the capping layer 138 .

[0101] exist Fig.19A and Fig.19B In the embodiment, after the porous oxide layer 82O is formed, the source / drain 82L is removed. Fig.19A and Fig.19B The removal of the source / drain 82L in most respects is similar to the reference Figure 13A-13C This removal may form an opening 82H, which may optionally include a recess in the channel 22 and / or the undoped semiconductor layer 110, as shown in FIG. Fig. 13C described.

[0102] exist Fig. 20A and Fig. 20B In the embodiment of the present invention, after the opening 82H is formed by removing the source / drain 82L, a replacement source / drain 82P can be formed in the opening 82H. The formation of the replacement source / drain 82P is similar to the reference EM in most aspects. Fig.14A and Fig. 14B In some embodiments, Fig. 20A and Fig. 20B The formation of the replacement source / drain 82P in the reference leads to Fig.16A and Fig. 16B After replacing source / drain 82L with replacement source / drain 82P, porous oxide layer 82O may be removed by a suitable removal process, such as a clean or wet etch selective to the material of porous oxide layer 82O without substantially removing the material of source / drain 82P.

[0103] exist Figure 21A-Figure 22C In the embodiment, after forming the replacement source / drain 82P, the replacement gate structure 200 and the source / source contact 120 may be formed. Fig.17A and Fig. 17B As described, ILD 130 and ESL 131 are removed to expose source / drain 82L, so source / drain 82P is initially exposed. Removing nanostructures 24 by etching prior to forming replacement gate structure 200 may damage source / drain 82P if not protected.

[0104] exist Fig.21A and Fig.21BIn the embodiment of the present invention, a top dielectric layer 137 is formed in the trench above the source / drain 82P to cover the source / drain 82P, the ILD 130 and the ESL 131. In some embodiments, before forming the top dielectric layer 137, the capping layer 138 is removed by a suitable etching operation. The top dielectric layer 137 may be or include one or more dielectric materials, such as SiN, SiON, SiCN, SiOCN, etc. The thickness or height of the top dielectric layer 137 in the Z-axis direction may be in the range of about 1 nm to about 25 nm. That is, the top dielectric layer 137 may extend from the upper surface of the source / drain 82P to be coplanar with the upper surface of the gate spacer 41. The top dielectric layer 137 may be formed by a suitable deposition operation, such as PVD, CVD, ALD, etc., and then CMP may be performed to remove excess material of the top dielectric layer 137 from above the gate spacer 41 and the sacrificial gate layer 45. Due to the CMP, upper surfaces of the dielectric layer 137 and the gate spacers 41 may be coplanar.

[0105] exist Figure 22A-22C In the embodiment, after forming the top dielectric layer 137, the gate structure 200 and the source / drain contacts 120 may be formed. The gate structure 200 may be formed in a manner similar to that of the reference Fig. 10A , Fig. 10B and Fig.23 The source / drain contacts 120 may be formed in a manner similar to that of reference Fig.15A and Fig. 15B The method described is formed.

[0106] like Fig. 22B As shown, since the top dielectric layer 137 is formed, in the profile of the YZ plane, the top dielectric layer 137 may be adjacent to the source / drain contacts 120 and separated therefrom by the protection layer 132 .

[0107] like Fig. 22C As shown, in some embodiments, the top dielectric layer 137 can extend to a depth or level D2 that is lower than the depth or level D1 of the bottom surface of the source / drain contact 120. This may be due to the fact that in reference Fig.17A and Fig. 17B In the depicted operation, the ILD 130 is etched to a level below the upper surface of the source / drain 82L.

[0108] Embodiments may provide advantages. Replacing SiGe source / drain with high Ge% source / drain, rather than forming the high Ge% source / drain directly in the source / drain opening, may prevent Ge diffusion into the channel and allow the ILD to be in place to better confine the growth of Ge, which can result in higher stress in the channel. High Ge% or pure Ge source / drain increases the lattice constant, thereby increasing channel stress and associated drive current. Source / drain contact resistance may also be reduced, which is beneficial for increased current output.

[0109] The all-around gate (GAA) transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing the creation of patterns with a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed and the remaining spacers can be used to pattern the GAA structure.

[0110] According to at least one embodiment, a method of forming a semiconductor device is provided, the method comprising: forming a nanostructure channel stack on a substrate by forming source / drain openings; forming a sacrificial source / drain in the source / drain openings; and increasing the tensile stress of the nanostructure channel stack by replacing the sacrificial source / drain with a replacement source / drain having a germanium concentration greater than that of the sacrificial source / drain.

[0111] In some embodiments, replacing the sacrificial source / drain includes replacing the silicon germanium source / drain with a substantially pure germanium source / drain having a germanium concentration exceeding about 99%.

[0112] In some embodiments, replacing the sacrificial source / drain includes replacing the silicon germanium source / drain with a high concentration germanium source / drain having a germanium concentration exceeding about 80%.

[0113] In some embodiments, replacing the sacrificial source / drain includes replacing a silicon germanium source / drain having a germanium concentration of no greater than about 40% with a silicon germanium source / drain having a germanium concentration of more than about 50%.

[0114] In some embodiments, replacing the sacrificial source / drain includes: forming a porous oxide layer on an upper surface of the sacrificial source / drain; removing the sacrificial source / drain through pores of the porous oxide layer; and growing a replacement source / drain through the pores of the porous oxide layer.

[0115] In some embodiments, the method further includes: removing the porous oxide layer; and forming source / drain contacts on the replacement source / drain.

[0116] In some embodiments, the method further includes, before replacing the sacrificial source / drain: forming an opening by removing an intervening layer of the nanostructure channel stack; and forming an active gate in the opening.

[0117] According to at least one embodiment, a method for forming a semiconductor device is provided, the method comprising: forming a nanostructure stack on a substrate by forming a source / drain opening through a multilayer lattice comprising alternating first and second semiconductor layers; forming a sacrificial gate structure on the nanostructure stack; forming a gate spacer adjacent to the sacrificial gate structure; forming a sacrificial source / drain in the source / drain opening; forming an etch stop layer on the sacrificial source / drain; forming an interlayer dielectric on the etch stop layer; exposing an upper surface of the sacrificial source / drain by removing an upper portion of the interlayer dielectric and an upper portion of the etch stop layer; replacing the sacrificial source / drain with a replacement source / drain; and, after replacing the sacrificial source / drain, forming an active gate by replacing the sacrificial gate structure and an intermediate layer of the nanostructure stack.

[0118] In some embodiments, replacing the sacrificial source / drain includes: forming a porous oxide layer on the exposed upper surface of the sacrificial source / drain; removing the sacrificial source / drain through the pores of the porous oxide layer to form an opening; and replacing the source / drain through the pore growth of the porous oxide layer.

[0119] In some embodiments, growing the replacement source / drain includes growing a semiconductor material having a germanium concentration in a range of approximately 75% to 100%.

[0120] In some embodiments, growing the replacement source / drain includes growing a semiconductor material including SiGe, Ge, GeSn, or SiGeSn.

[0121] In some embodiments, growing the semiconductor material includes growing the dopant concentration at about 1e19 / cm 3 to about 5e21 / cm 3 range of semiconductor materials.

[0122] In some embodiments, the replacement source / drain is grown not to completely fill the openings, such that the air gap is located adjacent to the gate spacer.

[0123] In some embodiments, the method further includes forming a dielectric layer covering upper surfaces of the replacement source / drain, an upper surface of the interlayer dielectric, and an upper surface of the etch stop layer before forming the active gate.

[0124] According to at least one embodiment, a semiconductor device is provided, which includes a first nanostructure channel; a second nanostructure channel located above the first nanostructure channel; an internal spacer located between the first nanostructure channel and the second nanostructure channel; a gate spacer located on the second nanostructure channel; a source / drain adjacent to the first nanostructure channel and the second nanostructure channel, the source / drain including an upper recess extending to a first depth, the drain / source having a germanium concentration greater than about 75%; a source / drain contact located on the source / drain, the source / drain contact extending into the upper recess; a capping layer located between the source / drain contact and the gate spacer, the capping layer extending into the upper recess to a second depth higher than the first depth; and a protective layer located between the gate spacer and the capping layer, the protective layer extending to a level higher than the bottom surface of the gate spacer.

[0125] In some embodiments, the semiconductor device further includes an air gap laterally located between the capping layer and the gate spacer, and vertically located between the protection layer and the source / drain.

[0126] In some embodiments, the semiconductor device further includes a silicide layer between the source / drain and the source / drain contacts.

[0127] In some embodiments, the protective layer is adjacent to the side surface of the source / drain, and the semiconductor device further includes: an interlayer dielectric adjacent to the side surface of the protective layer; and a dielectric layer located on the upper surface of the interlayer dielectric, the upper surface of the interlayer dielectric being at another level lower than the bottom surface of the source / drain contact.

[0128] In some embodiments, the dielectric layer has a thickness in a range from about 1 nanometer to about 25 nanometers.

[0129] In some embodiments, the semiconductor device further includes a semiconductor layer located between the source / drain and the first nanostructure channel, and the semiconductor layer includes SiB.

[0130] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a nanostructure channel stack over the substrate by forming source / drain openings; forming a sacrificial source / drain in the source / drain opening; as well as The tensile stress of the nanostructure channel stack is increased by replacing the sacrificial source / drain with a replacement source / drain having a germanium concentration greater than the germanium concentration of the sacrificial source / drain.

2. The method according to claim 1, wherein: Replacing the sacrificial source / drain includes replacing the silicon germanium source / drain with a substantially pure germanium source / drain having a germanium concentration exceeding 99%.

3. The method according to claim 1, wherein: Replacing the sacrificial source / drain includes replacing the silicon germanium source / drain with a high-concentration germanium source / drain having a germanium concentration exceeding 80%.

4. The method according to claim 1, wherein: Replacing the sacrificial source / drain includes replacing the silicon germanium source / drain having a germanium concentration of no more than 40% with a silicon germanium source / drain having a germanium concentration of more than 50%.

5. A method for forming a semiconductor device, comprising: forming a nanostructure stack over a substrate by forming source / drain openings through a multilayer lattice comprising alternating first and second semiconductor layers; forming a sacrificial gate structure on the nanostructure stack; forming a gate spacer adjacent to the sacrificial gate structure; forming a sacrificial source / drain in the source / drain opening; forming an etch stop layer on the sacrificial source / drain; forming an interlayer dielectric on the etch stop layer; exposing an upper surface of the sacrificial source / drain by removing an upper portion of the interlayer dielectric and an upper portion of the etch stop layer; replacing the sacrificial source / drain with a replacement source / drain; as well as After replacing the sacrificial source / drain, an active gate is formed by replacing the sacrificial gate structure and the intervening layer of the nanostructure stack.

6. The method according to claim 5, wherein: Replacing the sacrificial source / drain includes: forming a porous oxide layer on the exposed upper surface of the sacrificial source / drain; removing the sacrificial source / drain electrodes through the pores of the porous oxide layer to form openings; and The replacement source / drain electrodes are grown through the pores of the porous oxide layer.

7. The method according to claim 6, wherein: Growing the replacement source / drain includes growing a semiconductor material having a germanium concentration in a range of 75% to 100%.

8. A semiconductor device comprising: a first nanostructure channel; A second nanostructure channel, located above the first nanostructure channel; an internal spacer located between the first nanostructure channel and the second nanostructure channel; a gate spacer, located on the second nanostructure channel; A source / drain adjacent to the first nanostructure channel and the second nanostructure channel, the source / drain comprising an upper recess extending to a first depth, the drain / source having a germanium concentration exceeding 75%; A source / drain contact, located on the source / drain, the source / drain contact extending into the upper recess; a capping layer located between the source / drain contacts and the gate spacer, the capping layer extending into the upper recess to a second depth greater than the first depth; as well as A protection layer is located between the gate spacer and the capping layer, and the protection layer extends to a level higher than a bottom surface of the gate spacer. 9 . The semiconductor device of claim 8 , further comprising an air gap laterally located between the capping layer and the gate spacer and vertically located between the protection layer and the source / drain. 10 . The semiconductor device according to claim 8 , further comprising a silicide layer between the source / drain and the source / drain contacts.

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