Common-drain double-MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and preparation process thereof

Abstract

According to the preparation process of the common-drain double-MOSFET device and the common-drain double-MOSFET device, symmetrical structures are formed on the front face and the back face of the wafer, the problems existing in an existing process are solved, and the common-drain double-MOSFET wafer which is excellent in performance, smaller in area and higher in packaging performance is produced.

Description

Technical Field

[0001] The embodiments of the present application belong to the field of semiconductor technology, and in particular to a preparation process of a common-drain dual MOSFET device and a common-drain dual MOSFET device. Background Art

[0002] In the semiconductor field, MOSFET (metal-oxide semiconductor field-effect transistor) wafers are the basic components of electronic devices, and their performance and manufacturing process play a key role in the development of electronic devices. Common-drain dual MOSFET wafers have unique applications in circuits and are often used in scenarios such as input and output protection. However, there is currently no complete and efficient process flow specifically for common-drain dual MOSFET wafers.

[0003] Existing wafer manufacturing processes are usually general-purpose and cannot meet the special needs of common-drain dual MOSFET wafers. For example, in the traditional process flow, there is a lack of targeted steps and optimization for the production of MOSFETs on the front and back of the wafer, resulting in deficiencies in the performance, area, and packageability of the produced wafers. Moreover, the traditional process does not fully consider the characteristics of common-drain dual MOSFET wafers in terms of material selection, equipment use, and parameter control, making it impossible for the final product to achieve the desired effect.

[0004] These situations indicate that there is an urgent need to create a new process flow specifically for common-drain dual MOSFET wafers to improve their performance and production efficiency to meet the growing market demand. Summary of the invention

[0005] In order to overcome the shortcomings of the existing common-drain dual MOSFET wafer process flow, the embodiments of the present application provide a common-drain dual MOSFET device preparation process and a common-drain dual MOSFET device.

[0006] In a first aspect, an embodiment of the present application provides a preparation process of a common drain dual MOSFET device, comprising:

[0007] Performing photolithography on the front side of the wafer to obtain a plurality of first grooves arranged on the front side of the wafer;

[0008] Performing photolithography on the back side of the wafer to obtain a plurality of second grooves disposed on the back side of the wafer, wherein the second grooves are disposed in a one-to-one correspondence with the first grooves;

[0009] Growing a sacrificial oxide layer on the front and back sides of the wafer, and then etching away the sacrificial oxide layer;

[0010] growing a gate oxide layer in the first trench and the second trench;

[0011] depositing gate polysilicon in the first trench and the second trench;

[0012] A well region and an injection region are formed on the front and back sides of the wafer, respectively; the injection region on the front side of the wafer is arranged in the well region on the front side of the wafer, part of the first grooves only penetrates the well region on the front side of the wafer, and another part of the first grooves sequentially penetrates the injection region on the front side of the wafer and the well region on the front side of the wafer; the injection region on the back side of the wafer is arranged in the well region on the back side of the wafer, part of the second grooves only penetrates the well region on the back side of the wafer, and another part of the second grooves sequentially penetrates the injection region on the back side of the wafer and the well region on the back side of the wafer; and the well region on the front side of the wafer and the well region on the back side of the wafer are arranged in corresponding positions, and the injection region on the front side of the wafer and the injection region on the back side of the wafer are arranged in corresponding positions;

[0013] Depositing dielectric layers on the front and back sides of the wafer;

[0014] A first contact hole and a second contact hole are respectively provided in part of the first grooves on the front side of the wafer and part of the second grooves on the back side of the wafer, a third contact hole is provided between another part of the first grooves, the third contact hole penetrates the dielectric layer and the injection area on the front side of the wafer and extends to the well area on the front side of the wafer, and a fourth contact hole is provided between another part of the second grooves, the fourth contact hole penetrates the dielectric layer and the injection area on the back side of the wafer and extends to the well area on the back side of the wafer;

[0015] Filling the first contact hole, the second contact hole, the third contact hole and the fourth contact hole with conductive metal;

[0016] The first metal layer, the second metal layer, the third metal layer and the fourth metal layer are deposited on the upper surfaces of the first contact hole, the second contact hole, the third contact hole and the fourth contact hole respectively, the first metal layer and the third metal layer are arranged at intervals, and the second metal layer and the fourth metal layer are arranged at intervals.

[0017] As a preferred embodiment of the present application, the wafer includes a substrate, a first epitaxial layer arranged on a front side of the substrate, and a second epitaxial layer arranged on a back side of the substrate.

[0018] As a preferred embodiment of the present application, the substrate, the first epitaxial layer and the second epitaxial layer have the same doping type, and are all the first doping type.

[0019] As a preferred embodiment of the present application, the well region on the front side of the wafer and the well region on the back side of the wafer are both of the second doping type, and the injection region on the front side of the wafer and the injection region on the back side of the wafer are both of the first doping type.

[0020] In a second aspect, an embodiment of the present application further provides a common drain dual MOSFET device, characterized in that it is prepared by the process described in any one of the first aspects.

[0021] Compared with the prior art, the embodiments of the present application provide a preparation process for a common-drain dual MOSFET device and a common-drain dual MOSFET device, which solves the problems existing in the prior art and produces a common-drain dual MOSFET wafer with excellent performance, smaller area and stronger packageability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0023] Figure 1 It is the structural diagram obtained in step S01;

[0024] Figure 2 The structural diagram obtained in step S02;

[0025] Figure 3 The structural diagram obtained in step S04;

[0026] Figure 4 It is the structural diagram obtained in step S05;

[0027] Figure 5 The structural diagram obtained in step S06;

[0028] Figure 6 The structural diagram obtained in step S07;

[0029] Figure 7 The structural diagram obtained in step S08;

[0030] Figure 8 It is the structural diagram obtained in step S09;

[0031] Fig. 9 This is the structural diagram obtained in step S10. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0033] The present invention provides a method for preparing a common drain dual MOSFET device, comprising the following steps:

[0034] Step S01, performing photolithography on the front side of a wafer to obtain a plurality of first grooves arranged on the front side of the wafer;

[0035] like Figure 1 As shown, a plurality of first grooves spaced apart are now photolithographically formed on the front side of the wafer, the depths of the plurality of first grooves being the same, and the width of some first grooves 04 being greater than the width of other first grooves 05. The photolithography process is a process well known to those skilled in the art and will not be described in detail herein. In addition, it should be noted that the wafer includes a substrate 01 and a first epitaxial layer 02 disposed on the front side of the substrate 01 and a second epitaxial layer 03 disposed on the back side of the substrate 01. Specifically, the substrate 01, the first epitaxial layer 02 and the second epitaxial layer 03 have the same doping type, and are all the first doping type. In the embodiment of the present application, the first doping type is N-type. In order to prepare a common drain dual MOSFET device, in the embodiment of the present application, the first epitaxial layer 02 and the second epitaxial layer 03 have the same thickness.

[0036] Step S02, performing photolithography on the back side of the wafer to obtain a plurality of second grooves arranged on the back side of the wafer, and the second grooves are arranged in a one-to-one correspondence with the first grooves;

[0037] like Figure 2 As shown, the process is the same as step S01, and a plurality of second grooves spaced apart are photoetched on the back of the wafer. The depths of the plurality of second grooves are the same, and the width of some second grooves 06 is greater than the width of other second grooves 07.

[0038] Step S03, growing a sacrificial oxide layer on the front and back sides of the wafer, and then etching away the sacrificial oxide layer;

[0039] It should be noted that by producing a sacrificial oxide layer on the front and back of the wafer, the wafer surface can be made flatter.

[0040] Step S04, growing a gate oxide layer in the first trench and the second trench;

[0041] like Figure 3As shown, by precisely controlling the oxidation atmosphere, temperature and time, a gate oxide layer 08 is grown in the first trench and the second trench.

[0042] Step S05, depositing gate polysilicon in the first trench and the second trench;

[0043] like Figure 4 As shown, gate polysilicon 09 is deposited in the first trench and the second trench to serve as the gate of the entire device. The specific deposition process is well known to those skilled in the art and will not be described in detail here.

[0044] Step S06, forming a well region 10 and an injection region 11 on the front and back of the wafer respectively, the injection region 11 on the front of the wafer is arranged in the well region 10 on the front of the wafer, part of the first groove 04 only penetrates the well region 10 on the front of the wafer, and another part of the first groove 05 sequentially penetrates the injection region 11 on the front of the wafer and the well region 10 on the front of the wafer; the injection region 13 on the back of the wafer is arranged in the well region 12 on the back of the wafer, and part of the second groove 06 only penetrates the well region 10 on the front of the wafer. The well area on the back of the wafer, another part of the second groove sequentially penetrates the injection area 13 on the back of the wafer and the well area 12 on the back of the wafer; and the well area 10 on the front of the wafer and the well area 12 on the back of the wafer are arranged in a corresponding position, and the injection area 11 on the front of the wafer and the injection area 13 on the back of the wafer are arranged in a corresponding position; the well area 10 on the front of the wafer and the well area 12 on the back of the wafer are both of the second doping type, and the injection area on the front of the wafer and the injection area 13 on the back of the wafer are both of the first doping type. Specifically, the second doping type is P type, and the first doping type is N type.

[0045] like Figure 5 As shown, the source region of the entire device is prepared through step S06, by symmetrically setting the well region and the injection region on the front and back sides of the wafer. The well region and the injection region are formed by an ion implantation process. The ion implantation process is a process well known to those skilled in the art and will not be described in detail here. It should be noted that the process conditions of the ion implantation process for the well region and the injection region obtained by the ion implantation process on the front and back sides of the wafer are the same.

[0046] Step S07, depositing a dielectric layer on the front and back sides of the wafer;

[0047] like Figure 6 As shown, dielectric layers 14 and 15 are provided on the front and back sides of the wafer, and the dielectric layers play a role in protecting the wafer.

[0048] Step S08, respectively setting a first contact hole 16 and a second contact hole 18 in a portion of the first groove 04 on the front side of the wafer and a portion of the second groove 06 on the back side of the wafer, setting a third contact hole 17 between another portion of the first grooves 05, the third contact hole 17 penetrating the dielectric layer 14 and the injection region 11 on the front side of the wafer and extending to the well region 10 on the front side of the wafer, and setting a fourth contact hole 19 between another portion of the second grooves 07, the fourth contact hole 19 penetrating the dielectric layer 15 and the injection region 13 on the back side of the wafer and extending to the well region 12 on the back side of the wafer;

[0049] like Figure 7 As shown, in order to lead out the gate and source of the entire device, contact holes need to be set. Because the device prepared in this application is a common drain, the drain does not need to be led out. In this application, the first contact hole 16 and the second contact hole 18 are both for leading out the gate, and the third contact hole 17 and the fourth contact hole 19 are for leading out the source.

[0050] Step S09, filling the first contact hole 16, the second contact hole 18, the third contact hole 17 and the fourth contact hole 19 with a conductive metal;

[0051] like Figure 8 As shown, the first contact hole 16, the second contact hole 18, the third contact hole 17 and the fourth contact hole 19 need to be filled with conductive metal 20, conductive metal 21, conductive metal 22 and conductive metal 23 respectively in order to lead out the corresponding electrodes. In the present application, the conductive metal is copper.

[0052] Step S10, depositing the first metal layer 24, the second metal layer 26, the third metal layer 25 and the fourth metal layer 27 on the upper surfaces of the first contact hole 16, the second contact hole 18, the third contact hole 17 and the fourth contact hole 19 respectively, wherein the first metal layer 24 and the third metal layer 25 are spaced apart, and the second metal layer 26 and the fourth metal layer 27 are spaced apart.

[0053] like Fig. 9 As shown, the gate is led out through the first metal layer 24 and the second metal layer 26 , and the source is led out through the third metal layer 25 and the fourth metal layer 27 .

[0054] The preparation process of the common drain dual MOSFET device provided in the present application effectively avoids the increase in resistance between the source and the source due to excessively thick wafers and the risk of excessive process stress and cracking due to excessively thin wafers by precisely controlling the wafer thickness between 150um and 300um, thereby significantly improving the wafer yield and reliability.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate examples of the technical solutions provided by the embodiments of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some or all of the technical features therein can be replaced by equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A process for preparing a common drain dual MOSFET device, characterized in that: include: Performing photolithography on the front side of the wafer to obtain a plurality of first grooves arranged on the front side of the wafer; Performing photolithography on the back side of the wafer to obtain a plurality of second grooves disposed on the back side of the wafer, wherein the second grooves are disposed in a one-to-one correspondence with the first grooves; Growing a sacrificial oxide layer on the front and back sides of the wafer, and then etching away the sacrificial oxide layer; growing a gate oxide layer in the first trench and the second trench; depositing gate polysilicon in the first trench and the second trench; A well region and an injection region are formed on the front and back sides of the wafer, respectively; the injection region on the front side of the wafer is arranged in the well region on the front side of the wafer, part of the first grooves only penetrates the well region on the front side of the wafer, and another part of the first grooves sequentially penetrates the injection region on the front side of the wafer and the well region on the front side of the wafer; the injection region on the back side of the wafer is arranged in the well region on the back side of the wafer, part of the second grooves only penetrates the well region on the back side of the wafer, and another part of the second grooves sequentially penetrates the injection region on the back side of the wafer and the well region on the back side of the wafer; and the well region on the front side of the wafer and the well region on the back side of the wafer are arranged in corresponding positions, and the injection region on the front side of the wafer and the injection region on the back side of the wafer are arranged in corresponding positions; Depositing dielectric layers on the front and back sides of the wafer; A first contact hole and a second contact hole are respectively provided in part of the first grooves on the front side of the wafer and part of the second grooves on the back side of the wafer, a third contact hole is provided between another part of the first grooves, the third contact hole penetrates the dielectric layer and the injection area on the front side of the wafer and extends to the well area on the front side of the wafer, and a fourth contact hole is provided between another part of the second grooves, the fourth contact hole penetrates the dielectric layer and the injection area on the back side of the wafer and extends to the well area on the back side of the wafer; Filling the first contact hole, the second contact hole, the third contact hole and the fourth contact hole with conductive metal; The first metal layer, the second metal layer, the third metal layer and the fourth metal layer are deposited on the upper surfaces of the first contact hole, the second contact hole, the third contact hole and the fourth contact hole respectively, the first metal layer and the third metal layer are arranged at intervals, and the second metal layer and the fourth metal layer are arranged at intervals.

2. A process for preparing a common drain dual MOSFET device as claimed in claim 1, characterized in that: The wafer includes a substrate, a first epitaxial layer arranged on a front side of the substrate, and a second epitaxial layer arranged on a back side of the substrate.

3. A process for preparing a common drain dual MOSFET device as claimed in claim 2, characterized in that: The substrate, the first epitaxial layer and the second epitaxial layer have the same doping type, which is the first doping type.

4. A process for preparing a common drain dual MOSFET device as claimed in claim 1, characterized in that: The well region on the front side of the wafer and the well region on the back side of the wafer are both of the second doping type, and the injection region on the front side of the wafer and the injection region on the back side of the wafer are both of the first doping type.

5. A common drain dual MOSFET device, characterized in that: Prepared by the process according to any one of claims 1 to 4.

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