High electron mobility transistor

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to high electron mobility transistors and methods of manufacture. The structure comprises a semiconductor substrate; at least one insulator film over the semiconductor substrate, the at least one insulator film including a recess; and a field plate extending into the at least one recess and over the at least one insulator film.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to high electron mobility transistors and methods of fabrication. Background Art

[0002] A high electron mobility transistor (HEMT) is a field effect transistor that includes a junction between two materials with different band gaps as a channel, rather than a doped region (as is usually the case with MOSFETs). A common material combination is GaN and AlGaAs, although other material variants exist depending on the application of the device. HEMTs including gallium nitride, for example, offer high power performance.

[0003] HEMTs are capable of operating at higher frequencies (up to millimeter-wave frequencies) than ordinary transistors. Therefore, HEMTs are used in high-frequency products such as cellular phones, satellite receivers, voltage converters, and radar equipment. HEMTs can also be used in low-power applications such as low-power amplifiers. However, HEMTs can exhibit high gate-to-drain capacitance (Cgd), which can vary with the application of different voltages. Summary of the invention

[0004] In one aspect of the present disclosure, a structure includes: a semiconductor substrate; at least one insulator film located over the semiconductor substrate, the at least one insulator film including a recess; and a field plate extending into the at least one recess and located over the at least one insulator film.

[0005] In one aspect of the present disclosure, a structure includes a high electron mobility transistor, which includes: a semiconductor substrate; at least one insulator film located above the semiconductor substrate; and a field plate, which includes an insulator material extending into the at least one insulator film, and a metal plate located above the at least one insulator film and the insulator material.

[0006] In one aspect of the present disclosure, a method includes: forming a semiconductor substrate; forming at least one insulator film over the semiconductor substrate, the at least one insulator film including a recess exposing the semiconductor substrate; and forming a field plate extending into the at least one recess and located over the at least one insulator film. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure, with reference to the several figures mentioned.

[0008] Figure 1 A device having a field plate according to some aspects of the present disclosure, among other features, is shown.

[0009] Figure 2 A depletion mode device with a field plate is shown, among other features, in accordance with additional aspects of the present disclosure.

[0010] Figure 3 A depletion mode device with a field plate is shown, among other features, in accordance with additional aspects of the present disclosure.

[0011] Figure 4 A fabrication process for making these devices according to some aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0012] The present disclosure relates to semiconductor structures, and more particularly to high electron mobility transistors (HEMTs) and methods of fabrication. More particularly, the HEMTs include a field plate placed proximate to a surface of a channel region (e.g., AlGaN / GaN layer) of the device. Advantageously, the HEMTs described herein, for example for both enhancement mode GaN devices and depletion mode GaN devices, exhibit improved off-state leakage in addition to providing improved device switching response.

[0013] In a more specific embodiment, the HEMT can be a high voltage GaN device. The HEMT includes a field plate that is placed close to the surface of the channel region (e.g., two materials with different band gaps, such as AlGaN / GaN). A thin discrete dielectric material is deposited coincidently with the field plate metal and is located below the field plate metal to prevent or reduce leakage current. The field plate can be disposed on the opposite side of the gate metal (e.g., surrounding the gate metal contact). The field plate can be separated from the gate metal contact by a sidewall spacer, wherein the field plate also overlaps the pGaN gate device. The insulating material above the semiconductor material (AlGaN / GaN) can be recessed, which allows the metal layer to be placed close to the semiconductor substrate (e.g., the channel region). For example, the insulating layer can be AlyOx (Al 2 O 3 ).

[0014] The HEMTs of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer-scale dimensions. The methods (i.e., techniques) for manufacturing the HEMTs of the present disclosure have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned on top of the wafer by means of a photolithographic process. Specifically, the manufacture of HEMTs uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) etching the film selectively to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants from the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0015] Figure 1 A HEMT and corresponding manufacturing process according to some aspects of the present disclosure are shown. More specifically, Figure 1 The structure 10 includes a semiconductor substrate 12 and a semiconductor material 14 located on the semiconductor substrate 12. The semiconductor material 14 can be two materials with different band gaps, namely AlGaN / GaN, which can be used as a conductive channel (active region) of a HEMT device (e.g., a gate structure 19). The semiconductor substrate 12 can be made of any suitable material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. In a preferred embodiment, the semiconductor substrate 12 includes a p-type Si material with a suitable crystal orientation (e.g., (111)).

[0016] Semiconductor material 16 and conductive material 18 may be formed, e.g., deposited and patterned, on semiconductor material 14 to form gate structure 19. In an embodiment, semiconductor material 16 includes, for example, p-doped GaN, and conductive material 18 may be, for example, TiN. Semiconductor material 16 may be epitaxially grown on semiconductor material 14 by in-situ doping (e.g., p-type doping), as is known in the art. Conductive material 18 may be deposited by conventional deposition methods (e.g., chemical vapor deposition (CVD)), followed by conventional photolithography and etching processes on both materials 16, 18 to pattern gate structure 19. In an embodiment, conductive material 18 may be slightly pulled back.

[0017] Still reference Figure 1 Insulator materials (passivation layers) 20 and 22 may be formed over the gate structure 19 and the semiconductor material 14. The insulator materials 20 and 22 may be, for example, SiO 2 , AlyOx (e.g., Al 2 O3 ), SiN, or a combination thereof. Insulator materials 20, 22 may be deposited over gate structure 19 and semiconductor material 14 by conventional deposition methods. Recesses or openings 25 may be formed in insulator materials 20, 22 to expose underlying semiconductor material 14. Recesses 25 may be formed by conventional photolithography and etching processes as described herein.

[0018] Field plate 23 may be formed within recess 25 and over insulator material 22. In certain embodiments, field plate 23 may include metal layer 23a formed over insulator layer 23b (a thin discrete dielectric material deposited after recess etching and patterned coincidentally with field plate metal 23a). Figure 1 As shown, the insulator layer 23b forms a sidewall on the metal layer 23a, wherein the insulator layer 23b is in direct contact with the semiconductor material 14, such as near the surface of the channel region of the device. The metal layer 23a can be TiN; although other metal materials are also considered herein. The insulator layer 23 can be the same material as the insulator material 20, such as AlyOx (Al 2 O 3 ), although other insulator materials are also contemplated herein. The optional insulator layer 23c may be a nitride; although other insulator materials are also contemplated herein.

[0019] The field plate 23, more specifically the metal layer 23a and the insulator layer 23b within the recess 25, allow the field plate to be closer to the channel region of the gate structure 19, such as the semiconductor material 14. In an embodiment, the insulator layer 23b will reduce the corner leakage of the gate channel. The thickness of the insulator layer 23b can be less than 20nm, and preferably less than 10nm; although other sizes are also considered herein depending on the voltage technology.

[0020] The field plate 23 may be a common field plate for the gate structure 19, the source region 23, and the drain region 27. The field plate 23 may be arranged in a stepped configuration, with a portion close to the semiconductor material 14 in the source region 23 and the drain region 27. In an embodiment, the field plate 23 may physically contact (e.g., abut) the ohmic metal 29 of the source region 23 and the drain region 27. The ohmic metal 29 electrically contacts (may physically contact) the semiconductor material 14 (e.g., the conductive channel region). It will be appreciated by those skilled in the art that the ohmic metal 29 may be other shapes, such as including via contacts extending to the semiconductor material 14.

[0021] In other embodiments, the field plate 23 can surround the ohmic metal 29 of the source region 23 and the drain region 27, as well as the gate contact metal 26. In this way, the field plate 23 will reduce the peak field (e.g., field crowding) at the edge of the drain region 27. In addition, the field plate 23 can provide a uniform field distribution, reduce resistance impact, and provide improved device performance.

[0022] The field plate 23 may also be separated (e.g., electrically isolated) from the gate metal 26 by a sidewall spacer 21 formed on the sidewall of the gate contact metal 26. The gate contact metal 26 is electrically connected to (contacts) the gate structure 19, and more specifically, contacts the conductive material 18. That is, the gate contact metal 26 may be formed to physically contact the conductive material 18 (e.g., TiN) of the gate structure 19. The field plate 23 may be electrically isolated and physically separated from the gate structure 19 (more specifically, the gate contact metal 26) by the sidewall spacer 21.

[0023] The inter-level dielectric material 24 (e.g., a layer of oxide and / or nitride) may be formed below and above the field plate 23 (and partially below the field plate 23). The gate contact metal 26 may be, for example, TiAl or TiN, which is formed by patterning the inter-level dielectric material 24 to form a trench exposing the conductive material 18 (e.g., TiN), and then depositing the conductive material (e.g., TiAl or TiN). In an embodiment, the gate contact metal 26 and the ohmic metal 29 may be the same metal material formed in a similar process (e.g., a conventional CMOS process). Prior to forming the gate contact metal 26, the sidewall spacer 21 (e.g., a nitride and / or oxide material) may be blanket deposited (e.g., lined) in the trench by a conventional deposition process (e.g., CVD), followed by a conventional etching process.

[0024] Still reference Figure 1 , ohmic contacts 28a, 28c may contact (e.g., be electrically connected to) the underlying semiconductor material 14 (e.g., conductive channel) through ohmic contacts 27. Those skilled in the art will appreciate that ohmic contacts 27 may be eliminated, and ohmic contacts 28a, 28c may be directly connected to source and drain regions 23, 27 (e.g., semiconductor material 14). Ohmic contacts 28b may contact gate contact metal 26.

[0025] Additional inter-level dielectric material 24 may be formed over the inter-level dielectric material 24. Back-end process contacts (e.g., metal vias) 32 may be connected to the ohmic contacts 28a, 28c. The back-end process contacts 32 may also contact the field plate 23 through the gate contact metal 26. The ohmic contacts 28a, 28c may include, for example, TiAl or TiN. Metal wirings 34, 36 are connected to the source region 23 and the drain region 27, respectively. In an embodiment, the metal wirings 34, 36 may be electrically connected and in direct contact with the via contacts 32 for the source region 23 and the drain region 27.

[0026] Figure 2 A depletion mode device (D-mode) with a field plate is shown, among other features, in accordance with additional aspects of the present disclosure. More specifically, the depletion mode device 10a includes a field plate 23 located within the recess 25. Since this is a D-mode device, a gate structure is no longer required as the field plate 23 will act as the gate structure. As in each embodiment, the insulator material 23b will coincide with the metal material 23a and can be the same or different material as the insulator material 20. In this structure, the insulator material 23b will again be in contact with the semiconductor substrate 14. The optional insulator material 23c can also be eliminated; however, such optional insulator material can also be present. In this structure, D-mode Vpinch modulation (e.g., D-mode transistor pinch-off voltage) has been shown to be improved. The remaining structure is the same as Figure 1 The structure 10 is the same or similar.

[0027] Figure 3 A depletion mode device (D-mode) with a field plate is shown, among other features, in accordance with additional aspects of the present disclosure. More specifically, the depletion mode device 10b includes a field plate 23 located within a recess 25a formed only in the upper insulator layer 22. Since this is a D-mode device, a gate structure is no longer required as the field plate 23 will act as the gate structure. As in each embodiment, the insulator material 23b will coincide with the metal material 23a and can be the same or different material as the insulator material 20. In this structure, the insulator material 23b will be in contact with the insulator material 20. The optional insulator material 23c can also be eliminated; however, such optional insulator material can also be present. In this structure, D-mode Vpinch modulation has been shown to be improved. The remaining structure is the same as Figure 1 or Figure 2 The structure 10 is the same or similar.

[0028] Figure 4A flow diagram showing a manufacturing process for manufacturing these devices according to some aspects of the present disclosure is shown. As in the entire flow diagram description, these manufacturing processes can be used for both E-mode devices and D-mode devices. Specifically, in the E-mode device, the gate structure is patterned by conventional deposition, lithography, and etching processes known in the art; wherein, in the D-mode device, the gate structure is eliminated.

[0029] For example, at step 100, semiconductor material 16 and conductive material 18 may be deposited and patterned on semiconductor material 14 to form gate structure 19. In an embodiment, semiconductor material 16 includes, for example, p-doped GaN, and conductive material 18 may be, for example, TiN. Semiconductor material 16 may be epitaxially grown on semiconductor material 14 by in-situ doping (e.g., p-type doping) as is known in the art. Conductive material 18 may be deposited by conventional deposition methods (e.g., CVD), and then conventional photolithography and etching processes may be performed on both materials 16, 18 to pattern gate structure 19. Materials 20, 22 are deposited on gate structure 19 and over semiconductor material 14. Inter-level dielectric material may also be formed (e.g., deposited by a known CVD process) over material 22.

[0030] At steps 105 and 110, the field plate recess is patterned to expose the underlying semiconductor material 14. For example, at step 105, an oxide and nitride etch is performed to remove portions of the inter-level dielectric material 24 and material 22. The etch will stop on or slightly inside the example material 20. At step 110, an optional wet etch may be performed to remove material 20, such as Al 2 O 3 , thereby exposing the underlying semiconductor material 14.

[0031] At step 115, a dielectric material may be deposited in the recess over semiconductor material 14. For example, Al 2 O 3 The CuO2 may be deposited on the underlying semiconductor material 14 .

[0032] Thereafter, at step 120, the material of the field plate 23 may be deposited over the inter-level dielectric material 24 and within the recess 25. The field plate 23 may be used as a gate structure in a D-mode device. In any embodiment, the field plate 23 may include a metal layer 23a formed over an insulator layer 23b (e.g., a thin discrete dielectric material) that is deposited after the recess etch and patterned coincident with the field plate metal 23a. An optional insulator layer 23c may be formed over the metal layer 23a, which is also patterned coincident with the field plate metal 23a. In this article, the optional insulator layer 23c may be a nitride; although other insulator materials are also contemplated herein.

[0033] At step 125, the field plate 23 may be patterned using conventional photolithography and etching processes. The patterning may include all of the layers 23a, 23b, 23c. In an embodiment, any Al2O3 may be removed from the underlying oxide material. 2 O 3 .

[0034] At step 130, a back-end process known in the art is performed. For example, additional inter-level dielectric material 24 may be deposited over gate structure 19 and field plate 23. A trench may be formed in the dielectric material that exposes conductive material 18 of gate structure 19 in addition to semiconductor material 14 in source region 23 and drain region 27. The trench may be formed through a portion of field plate 23.

[0035] The grooves can be formed by conventional photolithography and etching methods known to those skilled in the art. For example, the resist formed above the dielectric material 24 is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemistry (e.g., reactive ion etching (RIE)) will be used to transfer the pattern into the inter-level dielectric material 24.

[0036] Ohmic contacts may also be formed in the trenches, contacting the gate structure 19 and the semiconductor material 14 in the source and drain regions 23 and 27. In an embodiment, the gate metal contact and the ohmic contact may be formed by performing the same deposition process followed by a CMP process to remove any excess conductive material on the dielectric material 24. Sidewall spacers may also be formed on the sidewalls of the gate contact to isolate the gate contact from the field plate 23.

[0037] The back-end process contact 32 and the ohmic contact can be formed using conventional photolithography, etching and deposition processes known in the art. The ohmic contact can include TiAl or TiN, for example. The metal wiring 34, 36 to the source region 23 and the drain region 27 can be formed by a back-end process metal process known in the art (e.g., a TiN liner with tungsten filling), so that no further explanation is needed to fully understand the present disclosure.

[0038] This HEMT can be utilized in system-on-chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0039] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having one or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0040] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: Semiconductor substrate; at least one insulator film located above the semiconductor substrate, the at least one insulator film comprising a recess; as well as A field plate extends into the at least one recess and is located above the at least one insulator film.

2. The structure according to claim 1, wherein: The field plate is a gate structure for a D-mode device.

3. The structure according to claim 1, wherein: The field plate includes an insulator material located in the recess and in contact with the semiconductor substrate, and a metal layer located above the insulator material.

4. The structure according to claim 3, wherein: The insulator material forms sidewalls on vertical portions of the metal layer of the field plate.

5. The structure according to claim 3, wherein: The insulator material and the at least one insulator film include the same material.

6. The structure according to claim 5, wherein: The insulator material and the at least one insulator film include AlyOx.

7. The structure according to claim 1, wherein: The field plate includes an insulator film below and above a metal layer.

8. The structure according to claim 1, wherein: The at least one insulator film includes two insulator films, and the recess extends into the two insulator films to expose the semiconductor substrate.

9. The structure according to claim 1, wherein: The at least one insulator film includes two insulator films, and the recess extends into tops of the two insulator films to expose bottoms of the two insulator films.

10. The structure of claim 1 further comprising a gate structure on the semiconductor substrate for an E-mode device.

11. The structure according to claim 10, wherein: The gate structure includes pGaN material.

12. The structure according to claim 1, wherein: The semiconductor substrate includes AlGaN / GaN material.

13. A structure comprising a high electron mobility transistor, the high electron mobility transistor comprising: Semiconductor substrate; at least one insulator film located above the semiconductor substrate; and a field plate including an insulator material extending into the at least one insulator film, and a metal plate located over the at least one insulator film and the insulator material.

14. The structure of claim 13 further comprising a gate structure comprising pGaN material, and wherein: The semiconductor substrate includes a source region and a drain region including AlGaN / GaN materials.

15. The structure according to claim 13, wherein: The field plate is a gate structure for a D-mode device.

16. The structure of claim 13, wherein: The insulator material of the field plate extends into the recess of the at least one insulator film and contacts the semiconductor substrate.

17. The structure according to claim 16, wherein: The insulator material and the at least one insulator film include AlyOx.

18. The structure of claim 16, wherein: The at least one insulator film includes two insulator films, and the recess extends into the two insulator films.

19. The structure of claim 13, wherein: The at least one insulator film includes two insulator films having recesses into top portions of the two insulator films, and the insulator material of the field plate extends into the recesses and contacts a bottom insulator film of the two insulator films.

20. A method comprising: forming at least one insulator film over a semiconductor substrate, the at least one insulator film including a recess exposing the semiconductor substrate; as well as A field plate is formed extending into the at least one recess and over the at least one insulator film.

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