Enhanced trench gate MIS-HEMT device and preparation method thereof

Abstract

The invention discloses an enhanced trench gate MIS-HEMT device and a preparation method thereof, the device comprises a substrate layer, a nucleating layer, a buffer layer, a GaN channel layer, an insertion layer and a first AlGaN barrier layer which are sequentially arranged from bottom to top, and two sides of the upper surface of the first AlGaN barrier layer respectively comprise a first isolation region and a second isolation region; the middle part of the first AlGaN barrier layer is provided with a gate region groove, and the gate region groove extends downwards from the upper surface of the first AlGaN barrier layer to the upper surface of the GaN channel layer. The inner sides of the first isolation region and the second isolation region are respectively provided with a source electrode and a drain electrode; a second AlGaN barrier layer and a high-resistance C: GaN layer are sequentially arranged in the gate region groove and on the upper surface of the first AlGaN barrier layer from bottom to top, a passivation layer covers the upper surface of the high-resistance C: GaN layer, a gate window is arranged on the passivation layer, and a gate electrode is arranged at the gate window. According to the invention, the problem of a parasitic channel of a growth interface is improved, and the stability of threshold voltage and the positive leakage characteristic of the grid are effectively improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to an enhanced trench-gate MIS-HEMT device and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN), as a wide bandgap semiconductor, has extraordinary properties such as high breakdown electric field, high thermal stability and good thermal conductivity. GaN-based high electron mobility transistors (HEMTs) show good power switching applications and cost competitiveness, and have been widely used in the fields of modern power electronics and radio frequency devices.

[0003] Enhanced-mode GaN power devices have excellent electrical properties and can provide high-efficiency and high-power density power conversion. Improving the performance of enhanced-mode GaN power devices can promote the development of GaN ICs. The methods for preparing enhanced-mode GaN devices generally include using a grooved MIS gate structure, a p-GaN gate structure, and fluoride ion treatment.

[0004] Traditional trench-gate enhanced MIS-HEMT can realize enhanced devices on depletion-mode epitaxial wafers. The device preparation method is simple and the gate withstand voltage is high. However, due to the large number of interface defects between GaN and gate dielectrics, the threshold voltage drift problem of the device is extremely serious. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides an enhanced trench-gate MIS-HEMT device and a method for manufacturing the same. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] One aspect of the present invention provides an enhanced trench-gate MIS-HEMT device, comprising a substrate layer, a nucleation layer, a buffer layer, a GaN channel layer, an insertion layer and a first AlGaN barrier layer arranged in sequence from bottom to top, wherein:

[0007] Both sides of the upper surface of the first AlGaN barrier layer include a first isolation region and a second isolation region, respectively, and the first isolation region and the second isolation region both extend downward from the upper surface of the first AlGaN barrier layer to the upper surface of the buffer layer;

[0008] A gate region groove is provided in the middle of the first AlGaN barrier layer, and the gate region groove extends downward from the upper surface of the first AlGaN barrier layer to the upper surface of the GaN channel layer; a source electrode and a drain electrode are respectively provided on the inner sides of the first isolation region and the second isolation region, and the lower surfaces of the source electrode and the drain electrode are in contact with the GaN channel layer;

[0009] A second AlGaN barrier layer and a high-resistance C:GaN layer are sequentially arranged from bottom to top inside the gate region groove and on the upper surface of the first AlGaN barrier layer. The upper surface of the high-resistance C:GaN layer is covered with a passivation layer. A gate window is arranged on the passivation layer located at the gate region groove. The gate window extends downward to the upper surface of the high-resistance C:GaN layer. A gate electrode is arranged at the gate window.

[0010] In one embodiment of the present invention, the material of the buffer layer is GaN doped with C, wherein the doping concentration of C is 10 17 ~10 20 cm -3 , the thickness of the buffer layer is 1200nm~1500nm.

[0011] In one embodiment of the present invention, the thickness of the first AlGaN barrier layer is 10 nm to 30 nm, wherein the Al component in AlGaN is 0.1 to 0.3.

[0012] In one embodiment of the present invention, the implanted ions in the first isolation region and the second isolation region are N ions with an implantation concentration of 10 18 ~10 20 cm -3 .

[0013] In one embodiment of the present invention, the thickness of the second AlGaN barrier layer is 2 nm to 10 nm, wherein the Al component in AlGaN is 0.1 to 0.3.

[0014] In one embodiment of the present invention, the thickness of the high-resistance C:GaN layer is 70nm to 90nm, wherein the doping concentration of the C element is 10 18 ~10 20 cm -3 .

[0015] In one embodiment of the present invention, an outer edge of the source electrode contacts an inner edge of the first isolation region, and an outer edge of the drain electrode contacts an inner edge of the second isolation region.

[0016] In one embodiment of the present invention, the material of the gate electrode is Ti / Al or TiN / Ti / Al / TiN; the material of the source electrode and the drain electrode is Ti, Al or a metal composite layer or alloy containing Ti / Al.

[0017] Another aspect of the present invention provides a method for preparing an enhanced trench-gate MIS-HEMT device, comprising:

[0018] Step 1: epitaxially growing a nucleation layer, a buffer layer, a GaN channel layer, an insertion layer and a first AlGaN barrier layer on the substrate layer in sequence;

[0019] Step 2: performing ion implantation on the left and right sides of the first AlGaN barrier layer to form a first isolation region and a second isolation region;

[0020] Step 3: etching the middle portion of the first AlGaN barrier layer to form a gate region groove extending downward to the upper surface of the GaN channel layer;

[0021] Step 4: growing a second AlGaN barrier layer on the upper surface of the first AlGaN barrier layer and inside the gate region groove;

[0022] Step 5: sequentially growing a high-resistance C:GaN layer and a passivation layer on the upper surface of the second AlGaN barrier layer;

[0023] Step 6: etching the passivation layer in the gate region to form a gate window, and depositing gate metal to form a gate electrode;

[0024] Step 7: Etching a source electrode window and a drain electrode window, and depositing metal in the electrode window and the drain electrode window to form a source electrode and a drain electrode respectively.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The trench-gate MIS-HEMT prepared by the conventional trench-gate technology can obtain an enhanced device, but due to the presence of a large number of defects in the interface state, the threshold voltage of the device is unstable and the threshold voltage drift is extremely serious. The enhanced trench-gate MIS-HEMT device provided by the present invention adopts a trench-gate structure to improve the threshold voltage of the device, uses a high-resistance C:GaN layer as a gate dielectric layer, effectively reduces the gate leakage current, improves the gate forward withstand voltage, suppresses the interface state trap density, and reduces the device surface current collapse.

[0027] 2. The enhanced trench-gate MIS-HEMT device of the present invention re-grows a second AlGaN barrier layer in the groove of the gate region. The second AlGaN barrier layer can effectively suppress the parasitic channel caused by the ionization of O impurities at the re-grown interface (i.e., the interface between the second AlGaN barrier layer 7 and the high-resistance C:GaN layer 8), and can effectively reduce the problem of threshold voltage drift, increase the density of the two-dimensional electron gas, and obtain a device with high current density.

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1It is a schematic structural diagram of an enhanced trench-gate MIS-HEMT device provided by an embodiment of the present invention;

[0030] Figure 2 A flow chart of a method for preparing an enhanced trench-gate MIS-HEMT device provided by an embodiment of the present invention;

[0031] Figure 3a to Figure 3g It is a schematic diagram of the preparation process of the novel enhanced trench-gate MIS-HEMT device provided in an embodiment of the present invention.

[0032] Description of reference numerals:

[0033] 1. Substrate layer; 2. Nucleation layer; 3. Buffer layer; 4. GaN channel layer; 5. Insertion layer; 6. First AlGaN barrier layer; 7. Second AlGaN barrier layer; 8. High-resistance C:GaN layer; 9. Passivation layer; 10. Gate electrode; 11. Source electrode; 12. Drain electrode; 13a. First isolation region; 13b. Second isolation region. DETAILED DESCRIPTION

[0034] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, an enhanced trench-gate MIS-HEMT device and a preparation method thereof proposed in accordance with the present invention are described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0035] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0036] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0037] Embodiment 1

[0038] See also Figure 1 , Figure 11 is a schematic diagram of the structure of an enhanced trench-gate MIS-HEMT device provided by an embodiment of the present invention. The enhanced trench-gate MIS-HEMT device comprises a substrate layer 1, a nucleation layer 2, a buffer layer 3, a GaN channel layer 4, an insertion layer 5 and a first AlGaN barrier layer 6 arranged in sequence from bottom to top, wherein the first AlGaN barrier layer 6 has a first isolation region 13a and a second isolation region 13b on both sides of its upper surface, and the first isolation region 13a and the second isolation region 13b both extend downward from the upper surface of the first AlGaN barrier layer 6 to the upper surface of the buffer layer 3; a gate region groove is provided in the middle of the first AlGaN barrier layer 6, and the gate region groove extends downward from the upper surface of the first AlGaN barrier layer 6 to the upper surface of the GaN channel layer 4; the first isolation region 13a and the second isolation region 13b extend downward from the upper surface of the first AlGaN barrier layer 6 to the upper surface of the buffer layer 3; the first isolation region 13a and the second isolation region 13b extend ... GaN channel layer 4; the first isolation region 13a and the second isolation region 13b extend downward from the upper surface of the first AlGaN barrier layer 6 to the upper surface of the GaN channel layer 4; the first isolation region 13a and the A source electrode 11 and a drain electrode 12 are respectively arranged on the inner sides of the isolation region 13a and the second isolation region 13b, and the lower surfaces of the source electrode 11 and the drain electrode 12 are in contact with the GaN channel layer 4, and the source electrode 12 and the drain electrode 13 respectively form ohmic contacts with the GaN channel layer 4; a second AlGaN barrier layer 7 and a high-resistance C:GaN layer 8 are arranged in sequence from bottom to top inside the gate region groove and on the upper surface of the first AlGaN barrier layer 6, and the upper surface of the high-resistance C:GaN layer 8 is covered with a passivation layer 9, and a gate window is arranged on the passivation layer located at the gate region groove, and the gate window extends downward to the upper surface of the high-resistance C:GaN layer 8, and a gate electrode 10 is arranged at the gate window.

[0039] In this embodiment, the substrate layer 1 can be made of sapphire, Si or SiC, with a thickness of about 1 mm. The material of the nucleation layer 2 is AlN, with a thickness of 50-500 nm; the material of the buffer layer 3 is GaN doped with C, where the doping concentration of C is 10 17 ~10 20 cm -3 , the thickness is 1200nm~1500nm, the thickness of the GaN channel layer 4 is 200nm~300nm, the material of the insertion layer 5 is preferably AlN, with a thickness of 0.5nm~2nm, the thickness of the first AlGaN barrier layer 6 is 10nm~30nm, and the Al component in AlGaN is 0.1~0.3.

[0040] Furthermore, the implanted ions in the first isolation region 13a and the second isolation region 13b are N ions with an implantation concentration of 10 18 ~10 20 cm -3 The first isolation region 13a and the second isolation region 13b are used to achieve device isolation. The thickness of the second AlGaN barrier layer 7 is 2nm to 10nm, wherein the Al component in AlGaN is 0.1 to 0.3; the high-resistance C:GaN layer 8 is used as the gate dielectric layer of the device, with a thickness of 70nm to 90nm, and the doping concentration of the C element is 10 18 ~1020 cm -3 The second AlGaN barrier layer 7 can effectively suppress the parasitic channel caused by the ionization of O (oxygen) impurities at the regrowth interface (i.e., the interface between the second AlGaN barrier layer 7 and the high-resistance C:GaN layer 8), and the high-resistance C:GaN layer 8 can effectively reduce gate leakage and increase the gate breakdown voltage.

[0041] Further, the outer edge of the source electrode 11 of the present embodiment contacts the inner edge of the first isolation region 13a, and the outer edge of the drain electrode 12 contacts the inner edge of the second isolation region 13b. The inner edge of the source electrode 11 contacts the insertion layer 5, the first AlGaN barrier layer 6, the second AlGaN barrier layer 7, the high-resistance C:GaN layer 8 and the passivation layer 9 from bottom to top, respectively, and the inner edge of the drain electrode 12 contacts the insertion layer 5, the first AlGaN barrier layer 6, the second AlGaN barrier layer 7, the high-resistance C:GaN layer 8 and the passivation layer 9 from bottom to top, respectively.

[0042] Preferably, the material of the passivation layer 10 includes one or more of SiO2, SiN, AlON or Al2O3. The material of the gate electrode 11 is Ti / Al or TiN / Ti / Al / TiN, that is, the material of the gate electrode 11 can be Ti / Al laminated metal, or TiN / Ti / Al / TiN laminated metal. The material of the source electrode 12 and the drain electrode 13 is Ti, Al or a metal composite layer or alloy containing Ti / Al. A portion of the gate electrode 11 of this embodiment extends from the inside of the gate window to the upper surface of the high-resistance C:GaN layer 8, and the outer edge of the gate electrode 11 contacts the passivation layer 10.

[0043] The enhanced trench-gate MIS-HEMT device of the present invention adopts a trench-gate structure to improve the device threshold voltage, uses a high-resistance C:GaN layer as a gate dielectric layer, effectively reduces gate leakage current, improves gate forward withstand voltage, suppresses interface state trap density, and reduces device surface current collapse.

[0044] The enhanced trench-gate MIS-HEMT device of the present invention re-grows a second AlGaN barrier layer in the groove of the gate region. The second AlGaN barrier layer can effectively suppress the parasitic channel caused by the ionization of O impurities at the re-growth interface (i.e., the interface between the second AlGaN barrier layer 7 and the high-resistance C:GaN layer 8), and can effectively reduce the problem of threshold voltage drift, increase the density of the two-dimensional electron gas, and obtain a device with high current density.

[0045] Embodiment 2

[0046] Based on the first embodiment, this embodiment provides a method for preparing an enhanced trench-gate MIS-HEMT device. Figure 2 and Figure 3a to Figure 3g, the preparation method comprises:

[0047] Step 1: epitaxially grow a nucleation layer 2, a buffer layer 3, a GaN channel layer 4, an insertion layer 5 and a first AlGaN barrier layer 6 in sequence on a substrate layer 1.

[0048] See also Figure 3a The material of the substrate layer 1 may include one of Si, SiC or sapphire, with a thickness of about 1 mm, the material of the nucleation layer 2 is AlN, with a thickness of 50 to 500 nm, and the material of the buffer layer 3 is GaN doped with C, wherein the doping concentration of C is 10 17 ~10 20 cm -3 , the thickness is 1200nm~1500nm, the thickness of the GaN channel layer 4 is 200nm~300nm, the material of the insertion layer 5 is preferably AlN, with a thickness of 0.5nm~2nm, the thickness of the first AlGaN barrier layer 6 is 10nm~30nm, and the Al component in AlGaN is 0.1~0.3.

[0049] Step 2: Perform ion implantation on the left and right sides of the first AlGaN barrier layer 6 to form a first isolation region 13 a and a second isolation region 13 b .

[0050] Specifically, see Figure 3b N ion implantation is performed on both sides of the first AlGaN barrier layer 6 to form a first isolation region 13a and a second isolation region 13b, with an implantation concentration of 10 18 ~10 20 cm -3 The first isolation region 13 a and the second isolation region 13 b both extend downward from the upper surface of the first AlGaN barrier layer 6 to the upper surface of the buffer layer 3 to achieve device isolation.

[0051] Step 3: Etch the middle portion of the first AlGaN barrier layer 6 to form a gate region groove extending downward to the upper surface of the GaN channel layer 4 .

[0052] See also Figure 3c , inductively coupled plasma (ICP) etching is performed on the upper surface of the middle portion (i.e., the gate region) of the first AlGaN barrier layer 6 using photolithography and development technology to completely etch away the first AlGaN barrier layer 6 in the gate region to form a gate region groove extending to the upper surface of the GaN channel layer 4. Since the first AlGaN barrier layer under the gate region groove is etched, the enhancement type of the device is achieved.

[0053] Step 4: growing a second AlGaN barrier layer 7 on the upper surface of the first AlGaN barrier layer 6 and inside the gate region groove.

[0054] Specifically, see Figure 3d A second AlGaN barrier layer 7 is epitaxially grown on the upper surface of the first AlGaN barrier layer 6 and inside the gate region groove using a MOCVD process. The thickness of the second AlGaN barrier layer is 2nm to 10nm, wherein the Al component in AlGaN is 0.1 to 0.3.

[0055] Step 5: A high-resistance C:GaN layer 8 and a passivation layer 9 are sequentially grown on the second AlGaN barrier layer 7 .

[0056] Specifically, see Figure 3d First, a high-resistance C:GaN layer 8 is grown on the second AlGaN barrier layer 7 by MOCVD process as the gate dielectric layer of the device. The thickness of the high-resistance C:GaN layer 8 is 70nm-90nm, and the doping concentration of the C element in the high-resistance C:GaN is 10 18 ~10 20 cm -3 The second AlGaN barrier layer 7 can effectively suppress the parasitic channel caused by the ionization of O impurities at the regrown interface (i.e., the interface between the second AlGaN barrier layer 7 and the high-resistance C:GaN layer 8). The high-resistance C:GaN layer 8 can effectively reduce gate leakage and increase gate breakdown voltage.

[0057] Next, a dielectric material is deposited on the high-resistance C:GaN layer 8 to form a passivation layer 9. For details, see Figure 3e , use Plasma Enhanced Atomic Layer Deposition (PEALD) process, atomic layer deposition (ALD) process, Plasma Enhanced Chemical Vapor Deposition (PECVD) process or Low Pressure Chemical Vapor Deposition (LPCVD) process to deposit one or more layers of dielectric material on the high resistance C:GaN layer 8, and the dielectric material includes one or more of SiO2, SiN, AlON or Al2O3.

[0058] Step 6: Etch the passivation layer 9 in the gate region to form a gate window, and deposit gate metal to form a gate electrode 10.

[0059] See also Figure 3f, all the passivation layers 9 inside the gate window are etched away, so that the gate window now extends to the upper surface of the high-resistance C:GaN layer 8, and a gate metal is deposited at the gate window by physical vapor deposition (PVD) to form a gate electrode 10, and the gate metal is Ti / Al / Ni / Au or Ti / Al. A portion of the gate electrode 11 of this embodiment extends from the inside of the gate window to the upper surface of the high-resistance C:GaN layer 8, and the outer edge of the gate electrode 11 contacts the passivation layer 10. The lower surface of the gate electrode 11 contacts the upper surface of the high-resistance C:GaN layer 8. The material of the gate electrode 11 is Ti / Al or TiN / Ti / Al / TiN, that is, the material of the gate electrode 11 can be a Ti / Al laminated metal, or a TiN / Ti / Al / TiN laminated metal.

[0060] Step 7: Etching the source electrode window and the drain electrode window, and depositing metal to form the source electrode 11 and the drain electrode 12.

[0061] Specifically, see Figure 3g The passivation layer is etched on both sides of the device using a photolithography and development process, down to the upper surface of the channel layer, to form a source-drain electrode window and a drain electrode window, and metal is deposited in the drain electrode window and the drain electrode window to form a source electrode 11 and a drain electrode 12 respectively.

[0062] In this embodiment, the outer edge of the source electrode 11 of this embodiment contacts the inner edge of the first isolation region 13a, and the outer edge of the drain electrode 12 contacts the inner edge of the second isolation region 13b. The inner edge of the source electrode 11 contacts the insertion layer 5, the first AlGaN barrier layer 6, the second AlGaN barrier layer 7, the high-resistance C:GaN layer 8 and the passivation layer 9 from bottom to top, respectively, and the inner edge of the drain electrode 12 contacts the insertion layer 5, the first AlGaN barrier layer 6, the second AlGaN barrier layer 7, the high-resistance C:GaN layer 8 and the passivation layer 9 from bottom to top.

[0063] The preparation method of the present invention obtains an enhanced device by setting a gate region groove, etching the first AlGaN barrier layer in the gate region groove, and using MOCVD to epitaxially grow a second AlGaN barrier layer, effectively suppressing the parasitic channel caused by the ionization of O impurities at the re-grown interface, and obtaining a device with a stable threshold voltage. In addition, the present invention sets a high-resistance C:GaN layer structure as a gate dielectric layer, the process steps are simple, the gate forward characteristics are enhanced, and an enhanced trench-gate MIS-HEMT with low gate leakage and high gate breakdown voltage is obtained.

[0064] In the several embodiments provided by the present invention, it should be understood that the apparatus and method disclosed by the present invention can be implemented in other ways. For example, the apparatus embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0065] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0066] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. An enhanced trench-gate MIS-HEMT device, characterized in that: The invention comprises a substrate layer (1), a nucleation layer (2), a buffer layer (3), a GaN channel layer (4), an insertion layer (5) and a first AlGaN barrier layer (6) which are arranged in sequence from bottom to top, wherein: Both sides of the upper surface of the first AlGaN barrier layer (6) respectively include a first isolation region (13a) and a second isolation region (13b), and both the first isolation region (13a) and the second isolation region (13b) extend downward from the upper surface of the first AlGaN barrier layer (6) to the upper surface of the buffer layer (3); A gate region groove is provided in the middle of the first AlGaN barrier layer (6), and the gate region groove extends downward from the upper surface of the first AlGaN barrier layer (6) to the upper surface of the GaN channel layer (4); a source electrode (11) and a drain electrode (12) are provided on the inner sides of the first isolation region (13a) and the second isolation region (13b), respectively, and the lower surfaces of the source electrode (11) and the drain electrode (12) are in contact with the GaN channel layer (4); A second AlGaN barrier layer (7) and a high-resistance C:GaN layer (8) are sequentially arranged inside the gate region groove and on the upper surface of the first AlGaN barrier layer (6) from bottom to top; the upper surface of the high-resistance C:GaN layer (8) is covered with a passivation layer (9); a gate window is arranged on the passivation layer located at the gate region groove; the gate window extends downward to the upper surface of the high-resistance C:GaN layer (8); and a gate electrode (10) is arranged at the gate window.

2. The enhancement-mode trench-gate MIS-HEMT device according to claim 1, characterized in that: The material of the buffer layer (3) is GaN doped with C, wherein the doping concentration of C is 10 17 ~10 20 cm -3 The thickness of the buffer layer (3) is 1200nm to 1500nm.

3. The enhancement-mode trench-gate MIS-HEMT device according to claim 1, characterized in that: The thickness of the first AlGaN barrier layer (6) is 10 nm to 30 nm, wherein the Al component in AlGaN is 0.1 to 0.

3.

4. The enhanced trench-gate MIS-HEMT device according to claim 1, characterized in that: The implanted ions in the first isolation region (13a) and the second isolation region (13b) are N ions with an implantation concentration of 10 18 ~10 20 cm -3 .

5. The enhancement-mode trench-gate MIS-HEMT device according to claim 1, characterized in that: The thickness of the second AlGaN barrier layer (7) is 2nm-10nm, wherein the Al component in AlGaN is 0.1-0.

3.

6. The enhanced trench-gate MIS-HEMT device according to claim 1, characterized in that The thickness of the high-resistance C:GaN layer (8) is 70 nm to 90 nm, wherein the doping concentration of the C element is 10 18 ~10 20 cm -3 .

7. The enhancement-mode trench-gate MIS-HEMT device according to claim 1, characterized in that: The outer edge of the source electrode (11) contacts the inner edge of the first isolation region (13a), and the outer edge of the drain electrode (12) contacts the inner edge of the second isolation region (13b).

8. The enhancement-mode trench-gate MIS-HEMT device according to claim 1, characterized in that: The material of the gate electrode (10) is Ti / Al or TiN / Ti / Al / TiN; the material of the source electrode (11) and the drain electrode (12) is Ti, Al or a metal composite layer or alloy containing Ti / Al.

9. A method for preparing an enhanced trench-gate MIS-HEMT device, characterized in that: include: Step 1: epitaxially growing a nucleation layer, a buffer layer, a GaN channel layer, an insertion layer and a first AlGaN barrier layer on the substrate layer in sequence; Step 2: performing ion implantation on the left and right sides of the first AlGaN barrier layer to form a first isolation region and a second isolation region; Step 3: etching the middle portion of the first AlGaN barrier layer to form a gate region groove extending downward to the upper surface of the GaN channel layer; Step 4: growing a second AlGaN barrier layer on the upper surface of the first AlGaN barrier layer and inside the gate region groove; Step 5: sequentially growing a high-resistance C:GaN layer and a passivation layer on the upper surface of the second AlGaN barrier layer; Step 6: etching the passivation layer in the gate region to form a gate window, and depositing gate metal to form a gate electrode; Step 7: Etching a source electrode window and a drain electrode window, and depositing metal in the electrode window and the drain electrode window to form a source electrode and a drain electrode respectively.

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