Structure of trench gate power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and manufacturing method of trench gate power MOSFET

Abstract

The invention discloses a structure of a trench gate power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a manufacturing method of the trench gate power MOSFET. The structure comprises a second epitaxial layer; the length direction of the strip-shaped P column is parallel to the projection direction of the crystal orientation with the most obvious channel effect on the surface of the epitaxial material; the groove gate comprises a groove, the groove is parallel to the length direction of the strip-shaped P column or perpendicular to the length direction of the strip-shaped P column, the groove is filled with filler, and therefore the groove gate is manufactured, when the length direction of the groove is parallel to the length direction of the strip-shaped P column, the groove is located over the strip-shaped P column, and the width of the groove is consistent with the width of the strip-shaped P column; when the length direction of the groove is perpendicular to the length direction of the strip-shaped P column, the width of the groove is not related to the strip-shaped P column; and a surface source region. The method has the advantages that the manufacturing steps can be reduced, and the machining process is simplified.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a structure of a trench gate power MOSFET and a method for manufacturing the trench gate power MOSFET. Background Art

[0002] Silicon carbide (SiC) MOSFET devices are currently widely used in high-voltage power electronic equipment due to their high withstand voltage, low loss, and high efficiency. At present, silicon carbide power devices are mainly positioned in scenarios with power between 1kW and 500kW and operating frequencies between 10kHz and 100MHz, especially in some applications with high requirements for energy efficiency and space size, such as electric vehicle onboard chargers and electric drive systems, charging piles, photovoltaic micro inverters, electric vehicles, etc. The use of silicon carbide MOSFET to replace silicon IGBT is an inevitable trend in the development of electric drive systems. Most of the electric vehicles launched on the market in recent years have adopted electric drive and electronic control systems based on silicon carbide power devices.

[0003] Silicon carbide (SiC) MOSFET devices are mainly divided into planar gate MOSFET device structures and trench gate MOSFET device structures in terms of structure. Among them, the planar gate structure has a simpler processing technology and higher maturity, and is the main structure of the current mass-produced SiCMOSFET devices. However, with the continuous improvement of device performance and cost requirements, the larger cell size and higher JFET area resistance of planar gate SiC MOSFET devices limit their further optimization. In comparison, trench gate SiCMOSFET devices change the flow direction of channel current by introducing a trench structure, eliminating the constraints of the JFET area on performance and cell size, and have greater development potential. The performance of the newly released new generation of trench gate SiC MOSFET devices has shown a significant improvement.

[0004] Furthermore, as SiC device technology and processing technology continue to mature, combining the trench gate structure with the charge balance concept (super junction) to form a trench gate SiC MOSFET with a super junction structure will be the ultimate goal of SiC MOSFET device development. At present, in SiC devices, the mainstream super junction implementation plans include: 1) deep trench etching combined with Al ion implantation on the trench sidewall; 2) deep trench etching combined with P-type epitaxial backfill; 3) high-energy Al ion implantation combined with multiple epitaxial growth, etc. The above solutions all have the problem of increased process difficulty and low mass production. Summary of the invention

[0005] In order to solve the above problems in the prior art, the present application provides a structure of a trench gate power MOSFET, a trench gate power MOSFET chip and a method for manufacturing a trench gate power MOSFET.

[0006] First, the present application provides a structure of a trench gate power MOSFET, including a substrate, a first epitaxial layer, a P body region, and further comprising: A second epitaxial layer, wherein the P body region is located at an upper surface of the second epitaxial layer; A strip-shaped P column, wherein the length direction of the strip-shaped P column is parallel to the projection direction of the crystal direction with the most obvious channel effect on the surface of the epitaxial material, and the depth of the strip-shaped P column penetrates the P body region and the second epitaxial layer to reach the first epitaxial layer; A trench gate, comprising a trench, wherein the trench is parallel to the length direction of the strip P column or perpendicular to the length direction of the strip P column, the depth of the trench penetrates the P body region to reach the second epitaxial layer, and a filler is filled into the trench to manufacture the trench gate; The surface source region is located at the surface layer of the P body region and further includes a surface N++ region and a surface P++ region. The surface N++ region and the surface P++ region are arranged at intervals, and their length direction is perpendicular to the length direction of the groove.

[0007] In the above structure, the second epitaxial layer is formed on the upper half of the first epitaxial layer by ion implantation, wherein the ion implantation method includes at least one high-energy ion implantation or channel implantation, and the direction of the channel implantation is the direction in which the channel effect of the epitaxial material is most obvious.

[0008] In the above structure, when the length direction of the groove is parallel to the length direction of the strip P column, the groove is located directly above the strip P column and its width is consistent with the width of the strip P column. Below the surface P++ area, there is also a P connector with a width consistent with it. One end of the P connector is electrically connected to the surface P++ area, and the other end is electrically connected to the strip P column.

[0009] In the above structure, when the length direction of the groove is perpendicular to the length direction of the strip P column, the width of the strip P column is consistent with the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P column.

[0010] In the above structure, the orthographic projection of the second epitaxial layer on the first epitaxial layer completely covers the first epitaxial layer, or only covers the area predetermined as the active area of ​​the chip.

[0011] In the above structure, the P connector is formed by at least one high energy implantation.

[0012] In the above structure, a P-type doped trench bottom protection area is also formed at the bottom of the trench gate, and the trench bottom protection area is formed after etching the trench and before filling the trench.

[0013] Secondly, the present application also provides a trench gate power MOSFET chip, which has the structure of the trench gate power MOSFET as described above.

[0014] Finally, the present application also provides a method for manufacturing a trench gate power MOSFET, which is used to manufacture the above-mentioned trench gate power MOSFET chip, comprising the following steps: Forming a second epitaxial layer, by injecting N-type ions into the first epitaxial layer having an N-type SiC epitaxial material once or multiple times by an ion implantation method, thereby forming the second epitaxial layer that is uniformly doped; Forming a strip-shaped P column, injecting P-type ions into the second epitaxial layer once or multiple times, the injection direction is the direction in which the channel effect of the epitaxial material is most obvious, and the injection depth penetrates the second epitaxial layer to reach the first epitaxial layer, thereby forming the strip-shaped P column; Forming a P body region, injecting P type ions into the surface layer of the second epitaxial layer multiple times, thereby forming the P body region in the upper layer of the second epitaxial layer; Source surface implantation, injecting high-concentration P-type ions and high-concentration N-type ions at intervals above the P body region to form alternately appearing strip-shaped surface N++ regions and surface P++ regions, wherein the length directions of the surface N++ regions and the surface P++ regions are perpendicular or parallel to the length direction of the strip-shaped P columns; Etching a gate trench in a direction parallel to or perpendicular to the length direction of the strip-shaped P column, and etching to a depth that penetrates the surface N++ region, the surface P++ region, and the P body region to reach the second epitaxial layer; A trench gate is manufactured, and a filler is filled into the trench to obtain the trench gate.

[0015] In the above manufacturing method, the ion implantation method includes at least one high-energy ion implantation or channel implantation, and the direction of the channel implantation is the direction in which the channel effect of the epitaxial material is most obvious.

[0016] In the above manufacturing method, when the length direction of the groove is parallel to the length direction of the strip P column, the groove is located directly above the strip P column and its width is consistent with the width of the strip P column. The surface P++ area also includes a P connector with a width consistent with it below the surface P++ area. One end of the P connector is electrically connected to the surface P++ area, and the other end is electrically connected to the strip P column.

[0017] In the above manufacturing method, when the length direction of the groove is perpendicular to the length direction of the strip P column, the width of the strip P column is consistent with the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P column.

[0018] In the above manufacturing method, the orthographic projection of the second epitaxial layer on the first epitaxial layer completely covers the first epitaxial layer, or only covers the area predetermined as the active area of ​​the chip.

[0019] The above manufacturing method further includes, after etching the gate trench, performing ion implantation on the bottom surface of the trench to form a trench bottom protection area.

[0020] Compared with the prior art, the present application has made improvements in both device structure and manufacturing method. Structurally, the present application proposes that the strip P-pillar structure may not be set at the bottom of the groove parallel to the groove direction, and may even intersect the groove direction at 90°, so that the strip P-pillar design and the groove design are independent of each other. In other words, the width of the strip P-pillar and the width of the groove can be independently designed according to their respective design requirements, which can maximize the potential of the super junction structure and the trench gate structure.

[0021] In terms of method, this application breaks through the existing inherent idea of ​​"injection at the bottom of the groove" and proposes a process method of first injection and then groove etching. This method makes the P-column structure design independent of the groove design and etching process. Furthermore, when ion implantation is performed at the bottom of the groove, the injected ions will inevitably be injected into the sidewalls of the groove. By adopting the process method of first injection and then groove etching, the problem of affecting the doping concentration of the body region and the threshold voltage of the device can be completely solved, thereby optimizing the device design and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 According to some embodiments of the present application, a schematic diagram of basic materials for making trench gate power SiC MOSFET is shown; Figure 2a According to some embodiments of the present application, a schematic structural diagram of a second epitaxial layer for manufacturing a trench gate power SiC MOSFET is shown; Figure 2b According to some embodiments of the present application, a schematic diagram of the structure of another second epitaxial layer for manufacturing a trench gate power SiC MOSFET is shown; Figure 3 According to some embodiments of the present application, a schematic structural diagram of a strip-shaped P column for manufacturing a trench gate power SiC MOSFET is shown; Figure 4 According to some embodiments of the present application, a schematic diagram of the structure of manufacturing a P body region of a trench gate power SiC MOSFET is shown; Figure 5 According to some embodiments of the present application, a schematic diagram of the structure of manufacturing a P connector of a trench gate power SiC MOSFET is shown; Figure 6 According to some embodiments of the present application, a schematic diagram of the structure of manufacturing a surface source region of a trench gate power SiC MOSFET is shown; Figure 7 According to some embodiments of the present application, a schematic diagram of the structure of a trench for making a trench gate power SiC MOSFET is shown; Figure 8a According to some embodiments of the present application, a schematic diagram of the structure of a trench bottom protection zone for manufacturing a trench gate power SiC MOSFET is shown; Figure 8b According to some embodiments of the present application, it is shown Figure 8a a schematic diagram of a cross section of the structure shown; Fig. 9 According to some embodiments of the present application, a schematic diagram of inner wall deposition for manufacturing a trench gate power SiC MOSFET is shown; Fig.10 According to some embodiments of the present application, a schematic diagram of changes in filling deposition for manufacturing a trench gate power SiC MOSFET is shown; Fig.11 According to some other embodiments of the present application, another schematic diagram of the structure of a trench for manufacturing a trench gate power SiC MOSFET is shown; Fig.12 According to some other embodiments of the present application, another structural schematic diagram of a strip-shaped P column for manufacturing a trench gate power SiC MOSFET is shown; Fig.13 According to some other embodiments of the present application, a schematic diagram of a structure for manufacturing a surface source region and a strip-shaped P column of a trench gate power SiC MOSFET is shown; Fig.14 According to some other embodiments of the present application, a schematic diagram of the structure of a trench and a trench bottom protection zone for manufacturing a trench gate power SiC MOSFET is shown; Fig.15 According to some embodiments of the present application, a flow chart of a method for preparing a trench gate power SiC MOSFET device is shown. DETAILED DESCRIPTION

[0023] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0024] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0025] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise clearly and specifically defined, the meaning of "plurality" is two or more.

[0026] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0027] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0028] The term "and / or" in this article is just a description of the association relationship between related objects, indicating that there can be three types of relationships: In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of types. For example, at least one of A, B, and C may mean any one or more elements selected from the set consisting of A, B, and C.

[0029] In addition, in order to better illustrate the present application, numerous specific details are provided in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0030] The following first combines Figure 1-10 as well as Fig.15A method for manufacturing a trench gate power MOSFET and structural changes of the trench gate power MOSFET after each manufacturing step are described.

[0031] like Figure 1 As shown, the epitaxial material to be processed includes a SiC substrate 1 and a first epitaxial layer 2. The first epitaxial layer 2 is a lightly doped epitaxial layer formed on the SiC substrate 1 by an epitaxial growth process. In this embodiment, the doping type of the first epitaxial layer 2 is N-type ion doping.

[0032] Step S1, forming a second epitaxial layer. In some embodiments, N-type ions, such as phosphorus (P) ions, may be implanted into the N-type SiC epitaxial material having the first epitaxial layer 2 once or multiple times, thereby forming a uniformly doped second epitaxial layer 3 in the upper half of the first epitaxial layer 2. And the thickness of the second epitaxial layer 3 is greater than that of the first epitaxial layer 2. The implantation method may be high-energy ion implantation or channel implantation (or tunnel implantation). The concentration of N-type ions in the second epitaxial layer 3 is greater than that in the first epitaxial layer 2. Generally speaking, the second epitaxial layer 3 is Figure 2a As shown, the orthographic projection of the second epitaxial layer 3 on the first epitaxial layer 2 completely covers the first epitaxial layer 2. Another more preferred embodiment is as follows: Figure 2b As shown, the orthographic projection of the second epitaxial layer 3 on the first epitaxial layer 2 can only cover part of the chip active area. In some embodiments, the depth of the second epitaxial layer 3 may be much greater than the implantation depth that can be achieved by conventional ion implantation, so the channel implantation method can be adopted, that is, the implantation direction is the direction in which the channel effect of the epitaxial material is most obvious. This direction is usually parallel to a certain crystal direction of the epitaxial material. The depth of the second epitaxial layer formed by this method can be 2-5 microns, and the doping concentration is 3E16~2E17. In a preferred embodiment, after the channel implantation, the thickness of the second epitaxial layer 3 is 3-4 microns, and the doping concentration is 6E16~8E16. The thickness of the second epitaxial layer 3 can also be understood as the implantation depth during the channel implantation, and the effect of its formation is to increase the ion concentration of the upper half of the first epitaxial layer 2. Specifically, the doping depth of the second epitaxial layer 3 is determined by the highest energy selected during the channel implantation, the doping distribution is uniformly distributed, and the doping concentration is determined by the implantation dose.

[0033] Step S2, forming a strip P column 6. The length direction of the strip P column 6 is parallel to the projection direction of the crystal orientation where the channel effect is most obvious on the surface of the second epitaxial layer 3. The strip P column 6 can be formed by injecting P-type ions into the second epitaxial layer 3 once or more. The P-type ions can be aluminum (Al) ions or boron (B) ions, and the injection direction is the direction where the channel effect is most obvious. The depth of the strip P column 6 can be close to or even exceed the thickness of the second epitaxial layer 3, and penetrate into the first epitaxial layer 2. Figure 3The figure shows an example of the strip P column 6 penetrating into the first epitaxial layer 2. The strip P column 6 formed by this method can have a depth of 2-5 microns and a doping concentration of 5E16-3E17. In a preferred embodiment, after the channel is implanted, the thickness of the strip P column 6 is 3-4 microns and the doping concentration is 1E17-2E17.

[0034] Step S3, forming a P body region. Figure 4 As shown, a P body region 4 is also formed inside the second epitaxial layer 3. The P body region 4 can be implemented by an ion implantation process, and the P body region 4 is located in the middle and upper part of the second epitaxial layer 3. The impurities doped in the P body region 4 are P-type doping, such as aluminum (Al) ions, and the specific doping concentration can be about 1E17-5E17, and the implantation depth is 0.2-1.0 microns.

[0035] After step S3, there are two different primitive cell structures. One structure is that the long strip groove is parallel to the strip P column 6 and is located above the strip P column 6, and the groove width is consistent with the width of the strip P column 6; the other structure is that the long strip groove is perpendicular to the strip P column 6, and the widths of the two are independent of each other. The bottom of the groove under both structures requires additional groove bottom injection to suppress the concentration of electric field strength at the corner of the bottom of the groove. In addition, the P-type source high doping region and the N-type source high doping region that appear at intervals on the epitaxial surface always maintain a layout perpendicular to the groove direction.

[0036] The following steps S4a-S5a illustrate the first structure, that is, the solution where the groove is parallel to the P column. The schematic diagram of the relevant structural changes can be referred to Figure 5-Figure 8b .

[0037] Step S4a, source surface implantation. The goal of this step is to implant high-concentration P-type ions and high-concentration N-type ions alternately above the P-body region 4 and the surface portion of the second epitaxial layer 3, thereby forming Figure 6 The stripe-shaped surface N++ regions 5a and surface P++ regions 5b that appear at intervals and perpendicularly intersect the stripe-shaped P columns 6 are both heavily doped.

[0038] Specifically, they include: 1) If Figure 5 As shown, high-energy ion implantation is performed at the location where the surface P++ region 5b is to be formed to form a P connector 11. The concentration of the P connector 11 is generally significantly higher than the concentration of the P body region 4, and is equivalent to the concentration of the P-type protection zone at the bottom of the trench to be made later. In addition, the depth of the P connector 11 implantation is greater than the depth of the trench to be processed later. After the trench etching is completed, the P connector 11 remains electrically connected to the P-type protection zone at the bottom of the trench. Figure 8b The relationship between the depth of the P-connector 11 and the depth of the trench will be described. Figure 8b yes Figure 8a The cross-sectional view at the point indicated by the green arrow. As shown in the figure, the depth of the P connector 11 needs to be greater than the groove 7 and connected to the groove bottom protection area 8, so that the strip P column 6 can be reliably connected to the ground through the source.

[0039] 2) Connect Figure 5 As shown, ion implantation is continued in the top region of the P connector 11, thereby forming a surface P++ region 5b with a doping concentration of P++ (indicating a concentration higher than that of the P connector 11), as shown in FIG. Figure 6 As shown. Further, N-type ions are implanted into the surface source region 5 except the surface P++ region 5b to form a surface N++ region 5a with a concentration of N++ (which means the concentration is equivalent to that of the surface P++ region 5b). The depth of the surface P++ region 5b may be slightly greater than that of the surface N++ region 5a, that is, the depth of the surface P++ region 5b may penetrate the surface source region 5 to reach the P body region 4.

[0040] After executing the above step S4a, the following is obtained: Figure 6 In the structure shown, on the upper surface of the epitaxial material, blue areas with a concentration of P++ and red areas with a concentration of N++ appear alternately to form surface N++ areas 5a and surface P++ areas 5b, wherein the high-concentration N-type ion implantation depth reaches the P body region 4, and the length directions of the surface N++ areas 5a and the surface P++ areas 5b are perpendicular to the length directions of the strip P columns 6.

[0041] Step S5a, etching the gate trench. The length direction of the gate trench is perpendicular to the length direction of the surface N++ region 5a and the surface P++ region 5b. The etching depth is to penetrate the surface N++ region 5a and the surface P++ region 5b and the P body region 4 to reach the second epitaxial layer 3, but is shallower than the depth of the P connector 11. That is, Figure 6 Based on the structure shown, the length direction of the groove 7 is parallel to the length direction of the strip P column 6, the groove 7 is located directly above the strip P column 6, and the width is consistent with the width of the strip P column 6, as shown in FIG. Figure 7 shown.

[0042] Furthermore, in this embodiment, P-type ions are implanted again at the bottom of the groove 7 to form a groove bottom protection zone 8 to alleviate the problem of electric field concentration at the corner of the groove bottom. Figure 8a and 8b The ion concentration of the groove bottom protection zone 8 is higher than the P-type ion concentration of the strip-shaped P column 6 , and the groove bottom protection zone 8 is electrically connected to the strip-shaped P column 6 .

[0043] After the etching of groove 7 is completed, the following is obtained: Figure 8a The device structure shown. Figure 8a In the structure shown, if Figure 8aTake the section at the position indicated by the green arrow, and you will get the following Figure 8b The cross-sectional view is shown. Figure 8a and 8b It can be clearly seen that the P connector 11 intersects with the strip-shaped P column 6 in the second epitaxial layer 3 .

[0044] Step S6, making a trench gate. Figure 9-10 As shown, GOX (Gate Oxide) is deposited on the inner wall of the groove 7 to form an inner wall GOX deposition layer 9, as shown in FIG. Fig. 9 Then, filler is filled into the groove 7 to form a POLY filling deposition 10 that fills the groove 7, and polysilicon is etched back in a local area by photolithography to obtain the trench gate cell structure, as shown in FIG. Fig.10 shown.

[0045] At this point, the manufacturing method of a trench gate power MOSFET is completed, and the subsequent post-processing steps can include interlayer dielectric (ILD) deposition and etching, surface metal interconnection, passivation layer deposition and etching, back thinning and laser annealing.

[0046] This embodiment adopts the channel implantation method to manufacture the second epitaxial layer 3 and the strip P column 6, which can obtain a deeper implantation depth. When the strip P column 6 is arranged directly below the trench, the width of the strip P column 6 is limited by the width of the groove 7. During the manufacturing process, the same mask can be used to manufacture the trench and the P column, thereby reducing the steps of mask manufacturing and cleaning.

[0047] In addition, in another embodiment, the groove 7 can also be etched before manufacturing the strip-shaped P column 6. Specifically, the steps include: The second epitaxial layer 3 is formed. The specific forming method is the same as step S1 and will not be described in detail here. Forming a P body region 4 and a surface source region 5 (including a surface N++ region 5a and a surface P++ region 5b) by ion implantation, for details, refer to step S3 and step S4a; Forming the P connector 11 by high energy ion implantation, for details, refer to step S4a; Groove etching is to form a groove by etching, wherein the length direction of the groove is parallel to the projection direction of the crystal direction where the channel effect of the epitaxial material is most obvious on the surface of the epitaxial material, thereby forming a Fig.11 slot 7 shown; At the bottom of the groove 7, P-type ions are implanted along the crystal direction where the channel effect of the epitaxial material is most obvious, so as to form a strip-shaped P column 6 below the groove. Fig.12 shown.

[0048] Through the above method, we can get Figure 1-Figure 7The same structure as shown in the process steps can be followed Figure 8a-Figure 10 The difference between the two routes is whether the trench is etched first and then the P column is implanted at the bottom, or the P column is implanted first and then the trench is etched.

[0049] The following steps S4b-S5b illustrate the second structure, that is, the solution in which the trench is perpendicular to the P column. In general, relative to the first structure, in the second structure, the P-type trench bottom protection area 8 at the bottom of the trench is connected to the surface P++ area 5b through the strip P column 6, thereby being directly electrically connected to the source electrode, so there is no need to make the P connector 11. The schematic diagram of the relevant structural changes can be combined with Figure 1-Figure 4 , Figure 9-10 as well as Figure 13-14 Come to understand.

[0050] Step S4b, source surface implantation. High concentration P-type ions and N-type ions are implanted alternately on the surface source region 5 to form a Fig.13 The strip-shaped surface N++ region 5a and surface P++ region 5b appear at intervals and are parallel to the strip-shaped P column 6. The implantation region of the P-type ions coincides with the strip-shaped P column 6, or is slightly larger than the width of the strip-shaped P column 6, that is, the width of the surface P++ region 5b is consistent with the width of the strip-shaped P column 6.

[0051] Step S5b, such as Fig.14 As shown, a gate groove is etched. On the basis of the surface N++ region 5a and the surface P++ region 5b formed in step S4b, the length direction of the gate groove is perpendicular to the length direction of the surface N++ region 5a and the surface P++ region 5b. The depth of etching is to penetrate the surface N++ region 5a and the surface P++ region 5b and the P body region 4 to reach the second epitaxial layer 3. In this embodiment, the length direction of the groove 7 is perpendicular to the length direction of the strip P column 6, and the width is not related to the strip P column 6. The groove width and the P column width can be designed independently to better play the performance advantages of this structure.

[0052] Similar to step S5a, P-type ions are injected into the bottom of the groove 7 again, thereby forming a groove bottom protection area 8 to suppress the electric field intensity concentration at the corner of the groove bottom.

[0053] Step S6, manufacturing a trench gate. This step has been described in detail above and will not be repeated here.

[0054] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0055] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A structure of a trench gate power MOSFET, characterized in that: The method comprises a substrate, a first epitaxial layer, a P body region, and further comprises: A second epitaxial layer, wherein the P body region is located in the middle and upper part of the second epitaxial layer; A strip-shaped P column, wherein the length direction of the strip-shaped P column is parallel to the projection direction of the crystal direction with the most obvious channel effect on the surface of the epitaxial material, and the depth of the strip-shaped P column penetrates the P body region and approaches or exceeds the second epitaxial layer; A trench gate, comprising a trench, wherein the trench is parallel to the length direction of the strip P column or perpendicular to the length direction of the strip P column, the depth of the trench penetrates the P body region to reach the second epitaxial layer, and a filler is filled into the trench to manufacture the trench gate; The surface source region is located at the surface layer of the P body region and further includes a surface N++ region and a surface P++ region. The surface N++ region and the surface P++ region are arranged at intervals, and their length direction is perpendicular to the length direction of the groove.

2. The structure of the trench gate power MOSFET according to claim 1, characterized in that: The second epitaxial layer is formed on the upper half of the first epitaxial layer by ion implantation, wherein the ion implantation method includes at least one high-energy ion implantation or channel implantation, and the direction of the channel implantation is the direction in which the channel effect of the epitaxial material is most obvious.

3. The structure of the trench gate power MOSFET according to claim 1, characterized in that: When the length direction of the groove is parallel to the length direction of the strip P column, the groove is located directly above the strip P column and its width is consistent with the width of the strip P column. The surface P++ area also includes a P connector with a width consistent with it below, and one end of the P connector is electrically connected to the surface P++ area, and the other end is electrically connected to the strip P column.

4. The structure of the trench gate power MOSFET according to claim 1, characterized in that: When the length direction of the trench is perpendicular to the length direction of the strip P column, the width of the strip P column is consistent with the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P column.

5. The structure of the trench gate power MOSFET according to claim 2, characterized in that: The orthographic projection of the second epitaxial layer on the first epitaxial layer completely covers the first epitaxial layer, or only covers a region predetermined as an active region of the chip.

6. The structure of the trench gate power MOSFET according to claim 3, characterized in that: The P linker is formed by at least one high energy implantation.

7. The structure of the trench gate power MOSFET according to claim 1, characterized in that: A P-type doped trench bottom protection zone is also formed at the bottom of the trench gate. The trench bottom protection zone is formed after the trench is etched and before the trench is filled.

8. A trench gate power MOSFET chip, characterized in that: A trench gate power MOSFET having the structure of any one of claims 1 to 7.

9. A method for manufacturing a trench gate power MOSFET chip, characterized in that: The method for manufacturing the trench gate power MOSFET chip as claimed in claim 8 comprises the following steps: Forming a second epitaxial layer, by injecting N-type ions into the first epitaxial layer having an N-type SiC epitaxial material once or multiple times by an ion implantation method, thereby forming the second epitaxial layer that is uniformly doped; Forming a strip-shaped P column, injecting P-type ions into the second epitaxial layer once or multiple times, the injection direction is the direction in which the channel effect of the epitaxial material is most obvious, and the injection depth penetrates the second epitaxial layer to reach the first epitaxial layer, thereby forming the strip-shaped P column; Forming a P body region, injecting P type ions into the surface layer of the second epitaxial layer multiple times, thereby forming the P body region in the upper layer of the second epitaxial layer; Source surface implantation, injecting high-concentration P-type ions and high-concentration N-type ions at intervals above the P body region to form alternately appearing strip-shaped surface N++ regions and surface P++ regions, wherein the length directions of the surface N++ regions and the surface P++ regions are perpendicular or parallel to the length direction of the strip-shaped P columns; Etching a gate trench in a direction parallel to or perpendicular to the length direction of the strip-shaped P column, and etching to a depth that penetrates the surface N++ region, the surface P++ region, and the P body region to reach the second epitaxial layer; A trench gate is manufactured, and a filler is filled into the trench to obtain the trench gate.

10. The manufacturing method according to claim 9, characterized in that: The ion implantation method includes at least one high-energy ion implantation or channel implantation, and the direction of the channel implantation is the direction in which the channel effect of the epitaxial material is most obvious.

11. The manufacturing method according to claim 9, characterized in that: When the length direction of the groove is parallel to the length direction of the strip P column, the groove is located directly above the strip P column and its width is consistent with the width of the strip P column. The surface P++ area also includes a P connector with a width consistent with it below, and one end of the P connector is electrically connected to the surface P++ area, and the other end is electrically connected to the strip P column.

12. The manufacturing method according to claim 9, characterized in that: When the length direction of the trench is perpendicular to the length direction of the strip P column, the width of the strip P column is consistent with the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P column.

13. The manufacturing method according to claim 9, characterized in that: The orthographic projection of the second epitaxial layer on the first epitaxial layer completely covers the first epitaxial layer, or only covers a region predetermined as an active region of the chip.

14. The manufacturing method according to claim 9, characterized in that: The method further includes, after etching the gate trench, performing ion implantation on the bottom surface of the trench to form a trench bottom protection zone.

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