Semiconductor structure and forming method thereof

Abstract

The present disclosure relates to a semiconductor structure and a method of forming the same. A structure includes a diffusion barrier structure in a source / drain epitaxial structure of an all-gate field effect transistor. The diffusion barrier structure is in contact with a nanosheet layer of the all-gate field effect transistor and extends on a side surface of the inner spacer structure adjacent to the nanosheet layer. The diffusion barrier structure separates a highly doped region of the source / drain epitaxial structure from the nanosheet layer and a region of the inner spacer structure adjacent to the nanosheet layer. The diffusion barrier structure may prevent (or mitigate) the diffusion of dopants in the highly doped region into the nanosheet layer and the inner spacer structure to maintain the integrity of the nanosheet layer as a semiconductor channel of an all-gate field effect transistor and avoid current crowding effects.

Description

Technical Field

[0001] The present disclosure provides a semiconductor structure and a method for forming the same. Background Art

[0002] A gate-all-around (GAA) field effect transistor (GAAFET), such as a nanosheet or nanowire gate-all-around field effect transistor, has a gate structure that covers the sidewalls and top surface of the semiconductor fin structure compared to other types of field effect transistors, thereby improving the gate's control over the channel region. Due to the full-gate geometry, full-gate nanosheet and nanowire field effect transistors can achieve a larger effective channel width and higher drive current. Summary of the invention

[0003] The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a nanostructured element, a gate structure, an inner spacer structure, a first epitaxial layer, and a second epitaxial layer. The nanostructured element is on the substrate. The gate structure surrounds the nanostructured element. The inner spacer structure is adjacent to the gate structure. The first epitaxial layer contacts the side surface of the nanostructured element and is located on the side surface of the inner spacer structure. The second epitaxial layer contacts the first epitaxial layer, wherein the dopant concentration of the first epitaxial layer is less than the dopant concentration of the second epitaxial layer.

[0004] The present disclosure also provides a semiconductor structure. The semiconductor structure includes a substrate, a plurality of nanosheet layers, a gate structure, an inner spacer structure, and a source / drain structure. The nanosheet layers are on the substrate. The gate structure surrounds the nanosheet layers. The inner spacer structure is inserted between these nanosheet layers. The source / drain structure is on the substrate and adjacent to the nanosheet layers, wherein the source / drain structure includes a diffusion barrier structure and an epitaxial layer. The diffusion barrier structure contacts multiple side surfaces of these nanosheet layers and the side surface of the inner spacer structure. The epitaxial layer is on the substrate and separated from the nanosheet layers by the diffusion barrier structure.

[0005] The present disclosure further provides a method for forming a semiconductor structure. The method includes the following process. A plurality of channel layers are formed on a substrate, wherein the channel layers are alternately stacked with a plurality of sacrificial layers. A portion of each of the sacrificial layers is removed to form a plurality of groove structures. A plurality of inner spacers are formed in the groove structures. A diffusion barrier structure is formed in contact with a plurality of side surfaces of the channel layers and on a plurality of side surfaces of the inner spacers. An epitaxial region is formed on a plurality of side surfaces of the diffusion barrier structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1 Various aspects of the disclosure are best understood from the following detailed description when read together.

[0007] Figure 1 is an isometric view of a semiconductor device including a nanostructure transistor according to some embodiments;

[0008] FIG. 2A to FIG. 2C is a cross-sectional view of a semiconductor element including a nanostructure transistor according to some embodiments;

[0009] FIG. 3A to FIG. 3C is a cross-sectional view of a semiconductor element including a nanostructure transistor according to some embodiments;

[0010] Figure 4 is a flow chart of a manufacturing method for forming a diffusion barrier structure in a source / drain epitaxial structure of a nanostructure transistor according to some embodiments;

[0011] Figure 5 and Figure 6 is an isometric view of an intermediate structure when fabricating a diffusion barrier structure in a source / drain epitaxial structure of a nanostructure transistor according to some embodiments;

[0012] Figures 7 to 14B is a cross-sectional view of an intermediate structure when fabricating a diffusion barrier structure in a source / drain epitaxial structure of a nanostructure transistor according to some embodiments.

[0013]

Explanation of symbols

[0014] 100:Semiconductor device

[0015] 102:Substrate

[0016] 105: Full Gate Field Effect Transistor

[0017] 110: Fin structure

[0018] 115: Gate structure

[0019] 115a:interface dielectric layer

[0020] 115b: Gate dielectric layer

[0021] 115c: Gate electrode

[0022] 120:Nanosheet

[0023] 125: Source / drain epitaxial structure

[0024] 130:Internal gap structure

[0025] 135: Gate spacer

[0026] 138: Shallow trench isolation area

[0027] 145: Isolation layer

[0028] 165: Interlayer dielectric layer

[0029] 200: Cross-sectional view

[0030] 250: Diffusion barrier structure

[0031] 255: Highly doped area

[0032] 290:Part

[0033] 300: Cross-sectional view

[0034] 350: Diffusion barrier structure

[0035] 355: Highly doped area

[0036] 390: Part

[0037] 400: Method

[0038] 405: Operation

[0039] 410: Operation

[0040] 415: Operation

[0041] 420: Operation

[0042] 425: Operation

[0043] 430: Operation

[0044] 435: Operation

[0045] 520: stack

[0046] 520a: first nanosheet layer

[0047] 520b: Second nanosheet layer

[0048] 620: Fin structure

[0049] 620a: first nanosheet layer

[0050] 620b: Second nanosheet layer

[0051] 700: Sacrificial gate structure

[0052] 700a: Sacrificial gate electrode

[0053] 705: Covering layer

[0054] 820a: first nanosheet layer

[0055] 840: Opening

[0056] 920a: first nanosheet layer

[0057] 945: Groove structure

[0058] AB:Line

[0059] BB:Line

[0060] D1: Distance

[0061] D2: Distance

[0062] D2': distance

[0063] L: Length

[0064] L1: Length

[0065] L2: Length

[0066] L2': Length

[0067] Lc: Length

[0068] T1: Thickness

[0069] T2: Thickness

[0070] W1: Width

[0071] W1': Width

[0072] W2: Width

[0073] W2': Width

[0074] W3': Width

[0075] x: direction

[0076] y: direction

[0077] z: direction

[0078] θ1: Angle

[0079] θ1': Angle

[0080] θ2: Angle

[0081] θ2': Angle DETAILED DESCRIPTION

[0082] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to limit the disclosure. For example, in the description below, forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed by direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact.

[0083] In addition, for ease of description, spatially relative terms such as "lower", "below", "below", "upper", "above", etc. may be used herein to describe the relationship of one element or feature in a figure to another element or feature in the figure. Spatially relative terms are intended to encompass different orientations of the device when in use or operation, in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or otherwise oriented), and the spatially relative terms used herein should be interpreted accordingly.

[0084] In some embodiments, the terms "about" and "substantially" can represent an amount within a 5% variation of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples and are not intended to limit the present disclosure. It should be understood that the terms "about" and "substantially" can be a percentage value understood by one of ordinary skill in the art based on the teachings herein.

[0085] By way of example and not limitation of the present disclosure, a nanostructure transistor, such as a fully gated nanosheet (NS) or nanowire (NW) field effect transistor (collectively referred to as a fully gated field effect transistor (GAAFET)) having a channel region of a nanosheet (NS) or nanowire (NW), may be formed in the following manner. A fin structure having alternating nanosheet layers or nanowire layers of silicon germanium (SiGe) and silicon (Si) is formed on a substrate (e.g., on a semiconductor substrate). A sacrificial gate structure is then formed in a middle portion of the fin structure to cover a top surface and a sidewall surface of the fin structure, such that an edge portion of the fin structure is not covered by the sacrificial gate structure. The edge portion of the fin structure not covered by the sacrificial gate structure is removed. Subsequently, an edge portion of the nanosheet layer or nanowire layer of silicon germanium is recessed relative to an edge portion of the nanosheet layer or nanowire layer of silicon, and an inner spacer structure is formed by depositing a dielectric material to fill the space formed by the etched portion of the nanosheet layer or nanowire layer of silicon germanium. Then, a source / drain (S / D) epitaxial structure is formed adjacent to (or in contact with) the edge portion of the fin structure, so that the source / drain epitaxial structure is in contact with the nanosheet layer or nanowire layer of silicon and is separated (or separated) from the nanosheet layer or nanowire layer of silicon germanium by the inner spacer structure. In the next operation, the sacrificial gate structure is removed to expose the top surface and sidewall surface of the fin structure. The nanosheet layer or nanowire layer of silicon germanium is selectively removed from the fin structure. In the selective removal process, the nanosheet layer or nanowire layer of silicon and the inner spacer structure are not removed. Subsequently, a metal gate structure is formed to surround the nanosheet layer or nanowire layer of silicon. Similar to the nanosheet layer or nanowire layer of silicon germanium before being selectively removed, the metal gate structure is separated (or separated) from the source / drain epitaxial structure by the inner spacer structure.

[0086] The structure of the full-gate field effect transistor can be patterned by any suitable method. For example, a process for patterning the structure using one or more lithography processes, including a double patterning or multiple patterning process. The double patterning or multiple patterning process can combine the lithography process with a self-alignment process to obtain a pattern with a smaller pitch than using a single and direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed along the patterned sacrificial layer by a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the full-gate transistor structure.

[0087] In the exemplary all-gate field effect transistor formed by the above process, the silicon nanosheet layer or nanowire layer as multiple channels of the all-gate field effect transistor may include intrinsic silicon (intrinsic Si) or lightly doped silicon (e.g., silicon with a dopant concentration of less than 1013cm-3) to provide effective control of channel conductivity by applying a gate bias to the metal gate structure. In addition, the nanosheet layer or nanowire layer with high purity intrinsic or lightly doped silicon can promote high mobility of charge carriers between channels to facilitate high-speed operation. On the other hand, the source / drain epitaxial structure may include a highly doped semiconductor material (e.g., a semiconductor material with a dopant concentration of about 5×10 20 cm -3 About 5×10 21 cm -3 Silicon between the electrodes) to reduce the resistance of the source / drain epitaxial structure, thereby facilitating low power consumption.

[0088] Due to the different doping methods between the silicon nanosheet layer or nanowire layer and the source / drain epitaxial structure, the doping concentration gradient near the interface between the silicon nanosheet layer or nanowire layer and the source / drain epitaxial structure causes the dopant to diffuse from the source / drain epitaxial structure to the silicon nanosheet layer or nanowire layer. The dopant diffused into the silicon nanosheet layer or nanowire layer will affect the integrity (e.g., purity) of the silicon nanosheet layer or nanowire layer, thereby reducing the mobility of charge carriers in the silicon nanosheet layer or nanowire layer. In addition, the diffusion of dopants into the silicon nanosheet layer or nanowire layer may produce paths with lower resistance, causing charge carriers to be deflected by passing through these paths. Therefore, the current is not evenly distributed over the entire cross-section of the channel, but is locally concentrated on these low-resistance paths, which is called the "current crowding effect", thereby affecting the performance of the full-gate field-effect transistor.

[0089] In order to prevent (or mitigate) the diffusion of dopants from the source / drain epitaxial structure into the nanosheet layer or nanowire layer of silicon, the source / drain epitaxial structure may include a low-doped region (e.g., a dopant concentration of about 1×10 20 cm -3 About 2×10 21 cm -3These additional low-doped regions may be referred to as "diffusion barrier structures" and may reduce the doping concentration gradient at the interface to prevent (or mitigate) dopants from diffusing directly from the highly doped regions of the source / drain epitaxial structure to the nanosheet layer or nanowire layer of silicon. However, since the diffusion barrier structure only covers the interface between the nanosheet layer or nanowire layer of silicon and the source / drain epitaxial structure, dopants in the highly doped regions of the source / drain epitaxial structure may still be deflected on the inner spacer structure and diffused through the inner spacer structure into the nanosheet layer or nanowire layer of silicon. As described above, these diffused dopants not only affect the channel, but also introduce defects in the inner spacer structure, so reducing the inner spacer structure may serve as an isolation function between the metal gate structure and the source / drain epitaxial structure.

[0090] Embodiments described herein are intended to overcome the above challenges. In some embodiments, a full-gate field effect transistor may include a nanosheet layer or a nanowire layer, an inner gap structure, and a source / drain epitaxial structure in contact with the nanosheet layer or the nanowire layer. The source / drain epitaxial structure may include a low-doped region as a diffusion barrier structure, and the diffusion barrier structure not only covers the interface between the nanosheet layer or the nanowire layer and the source / drain epitaxial structure, but also covers the side surface of the inner gap structure. In some embodiments, the source / drain epitaxial structure may be formed by epitaxially growing a low-doped region on a nanosheet layer or a nanowire layer until the low-doped region extends to the side surface of the inner gap structure and epitaxially growing a high-doped region on the low-doped region.

[0091] According to some embodiments, reference Figure 1 , a semiconductor device 100 having a plurality of full-gate field-effect transistors 105 is formed on a substrate 102 . Figure 1 An isometric view of a semiconductor device 100 according to some embodiments is shown. The semiconductor device 100 may be included in a microprocessor, a memory cell, or other integrated circuit (IC). In addition, according to some embodiments, Figure 1 Each of the illustrated full-gate field effect transistors 105 may be a full-gate field effect transistor.

[0092] Reference Figure 1, the substrate 102 may be a semiconductor material, such as silicon. In some embodiments, the substrate 102 may include a crystallized silicon substrate (e.g., a wafer). In some embodiments, the substrate 102 may include (i) an elemental semiconductor, such as silicon (Si) or germanium (Ge); (ii) a compound semiconductor, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), gallium indium phosphide (InGaP), gallium indium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), aluminum indium arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) a combination of the foregoing. In addition, the substrate 102 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or with an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, the crystal orientation of the substrate 102 may be (100), (110), or (111).

[0093] The full-gate field effect transistor 105 may include a fin structure 110 extending along a direction x, a gate structure 115 passing through the fin structure 110 along a direction y, and a source / drain epitaxial structure 125 formed on multiple portions of the fin structure 110. Figure 1 A fin structure 110 with two full-gate field effect transistors 105 is shown, but any number of full-gate field effect transistors 105 may be disposed along the fin structure 110. In some embodiments, the full-gate field effect transistor 105 may include a plurality of fin structures 110 extending along a first horizontal direction (e.g., in direction x) and a gate structure 115 crossing the plurality of fin structures 110 along a second horizontal direction (e.g., in direction y). In some embodiments, the crystal orientation of the fin structure 110 may be the same as the crystal orientation of the substrate 102.

[0094] One or more nanosheet (NS) layers 120 may be disposed on the fin structure 110. Each nanosheet layer 120 may be wrapped by a gate structure 115 to serve as a channel of the full-gate field effect transistor 105. For example, the top surface, side surface, and bottom surface of each nanosheet layer 120 may be surrounded by the gate structure 115 and physically contact the gate structure 115. The fin structure 110 and the nanosheet layer 120 may be made of a material similar to the substrate 102 (e.g., within a lattice mismatch of about 5%). In some embodiments, the crystal orientation of the nanosheet layer 120 may be the same as that of the fin structure 110. In some embodiments, each of the fin structure 110 and the nanosheet layer 120 may be made of silicon or silicon germanium. Each of the fin structure 110 and the nanosheet layer 120 may be undoped, doped with a p-type dopant, doped with an n-type dopant, or doped with an intrinsic dopant. In some embodiments, the fin structure 110 and the nanosheet layer 120 may be doped with a p-type dopant together or with an n-type dopant together. Figure 1 Each gate-all-around field effect transistor 105 is shown to include four nanosheet layers 120 , but each gate-all-around field effect transistor 105 may include any number of nanosheet layers 120 .

[0095] The gate structure 115 may be a multi-layer structure and wrapped around each nanosheet layer 120 to form a full-gate field effect transistor 105. The gate structure 115 may have a length Lc used to represent the channel length of the full-gate field effect transistor 105. The length Lc may have a dimension at any suitable level (e.g., in the direction x), such as from about 3 nm to about 200 nm. By way of example and not limitation, each gate structure 115 may include a dielectric stack formed by an interfacial dielectric layer 115a and a gate dielectric layer 115b. In addition, each gate structure 115 includes a gate electrode 115c and has a gate electrode 115c that is not shown for simplicity. Figure 1Multiple capping layers, one or more work function metal layers, and metal fillers are shown separately. The gate dielectric layer 115b may include any suitable dielectric material and have any suitable thickness to provide regulation of the channel of the full gate field effect transistor 105. In some embodiments, the gate dielectric layer 115b may be made of silicon oxide or a high-k dielectric material (such as hafnium oxide or aluminum oxide). In some embodiments, the thickness of the gate dielectric layer 115b may range from about 1nm to about 5nm. Based on what is disclosed herein, other materials and thicknesses for the gate dielectric layer 115b are also within the scope and spirit of the present disclosure. The gate electrode 115c may be used as the gate terminal of the full gate field effect transistor 105. The gate electrode 115c may include any suitable conductive material to provide a suitable work function to operate the full gate field effect transistor 105. In some embodiments, the gate electrode 115c may be made of titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel. Based on the disclosure herein, other materials for the gate electrode 115 c are also within the scope and spirit of the present disclosure.

[0096] Source / drain epitaxial structures 125 may be disposed on opposite sides (e.g., along direction x) of each nanosheet layer 120 to serve as source and drain terminals of the full-gate field effect transistor 105. The source / drain epitaxial structures 125 may be disposed on the fin structure 110. In some embodiments, the source / drain epitaxial structures 125 may be disposed on an isolation layer 145 on the fin structure 110 so that the source / drain epitaxial structures 125 and the fin structure 110 are electrically isolated. The source / drain epitaxial structures 125 may be made of an epitaxially grown semiconductor material similar to the nanosheet layer 120 (e.g., with a lattice mismatch within about 5%). In some embodiments, the source / drain epitaxial structures 125 may be made of silicon, germanium, silicon germanium, indium gallium arsenide, or gallium arsenide. The source / drain epitaxial structures 125 may be doped with p-type dopants, n-type dopants, or intrinsic dopants. In some embodiments, the source / drain epitaxial structure 125 may have a different dopant type than the nanosheet layer 120. In some embodiments, the n-type dopant in the source / drain epitaxial structure 125 may include phosphorus, arsenic, antimony, and / or a combination thereof. In some embodiments, the crystal orientation of the source / drain epitaxial structure 125 may be the same as that of the nanosheet layer 120.

[0097] The semiconductor device 100 may further include a gate spacer 135 formed between the gate structure 115 and the source / drain epitaxial structure 125 to provide structural support when forming the gate structure 115. In addition, the gate spacer 135 provides electrical isolation and protection for the gate structure 115 during the source / drain contact formation process, but is not shown in the figure. Figure 1The gate spacer 135 can be made of any suitable dielectric material. In some embodiments, the gate spacer 135 can be made of silicon oxide, silicon nitride, or a low-k material having a dielectric constant of less than about 3.9. In some embodiments, the gate spacer 135 can have any suitable thickness, such as from about 5 nm to about 15 nm. Based on what is disclosed herein, other materials and thicknesses for the gate spacer 135 are also within the scope and spirit of the present disclosure.

[0098] The semiconductor device 100 may also include a shallow trench isolation (STI) region 138 configured to provide electrical isolation between the fin structures 110. In addition, the shallow trench isolation region 138 may provide electrical isolation between the full-gate field effect transistor 105 and adjacent active and passive components integrated with or deposited on the substrate 102. The shallow trench isolation region 138 may include one or more layers of dielectric material, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride layer. In some embodiments, the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, and / or other suitable insulating materials. Based on what is disclosed herein, other dielectric materials for the shallow trench isolation region 138 are also within the scope and spirit of the present disclosure.

[0099] The semiconductor device 100 may further include an interlayer dielectric (ILD) layer 165 to provide electrical isolation to the structural elements surrounding or covered by it, such as providing electrical isolation to the gate structure 115 and the source / drain epitaxial structure 125. In some embodiments, a gate spacer 135 may be formed between the gate structure 115 and the interlayer dielectric layer 165. The interlayer dielectric layer 165 may include any suitable dielectric material to provide electrical insulation, such as silicon oxide, silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon oxy-carbon nitride, and silicon carbonitride. The interlayer dielectric layer 165 may have any suitable thickness, such as from about 50 nm to about 200 nm, to provide electrical insulation. Based on the disclosure herein, other insulating materials and thicknesses of the interlayer dielectric layer 165 are also within the scope and spirit of the present disclosure.

[0100] The semiconductor device 100 may further include an inner spacer structure 130 adjacent to (or in contact with) a side surface of the gate structure 115. The inner spacer structure 130 may separate the gate structure 115 from the source / drain epitaxial structure 125. For example, the inner spacer structure 130 may be formed on opposite sides of the gate structure 115 along a channel direction (e.g., along direction x) of the full gate field effect transistor 105 to separate the gate structure 115 from the source / drain epitaxial structure 125. In some embodiments, the inner spacer structure 130 may be formed between two vertically (e.g., in direction z) adjacent nanosheet layers 120. In some embodiments, the inner spacer structure 130 may be formed between the fin structure 110 and the nanosheet layer 120. In some embodiments, the inner spacer structure 130 may include a silicon-based dielectric, such as silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), or silicon oxynitride (SiON). In some embodiments, the inter-spacer structure 130 can include low-k materials, such as porous materials and carbon-rich silicon oxide-based dielectrics.

[0101] According to some embodiments, Figure 2A and Figure 3A The semiconductor device 100 is shown along Figure 1 The cross-sectional view 200 and the cross-sectional view 300 are taken along line BB. Figure 2B and Figure 3B Enlarge Figure 2A and Figure 3A Portions 290 and 390 in cross-sectional views 200 and 300 . Figure 2C and Figure 3C An embodiment of an n-type nanosheet transistor with a diffusion barrier structure in a source / drain epitaxial structure is shown. Figure 1 The discussion of components with the same symbols also applies to FIG. 2A to FIG. 2C and FIG. 3A to FIG. 3C middle.

[0102] Figure 2A An embodiment of a source / drain epitaxial structure including a diffusion barrier structure is shown. Figure 2A, each source / drain epitaxial structure 125 may include a low-doped region (or diffusion barrier structure 250) and a high-doped region 255. The high-doped region 255 is separated (or separated) from the nanosheet layer 120 by the low-doped region (or diffusion barrier structure 250). The dopant concentration of the low-doped region (or diffusion barrier structure 250) may be lower than the doping concentration of the high-doped region 255. The low-doped region (or diffusion barrier structure 250) may cover multiple side surfaces of the nanosheet layer 120 to prevent (or reduce) the dopant in the high-doped region 255 from diffusing into the nanosheet layer 120. The low-doped region may also be referred to as a "diffusion barrier structure 250". In some embodiments, the high-doped region 255 and the low-doped region (or diffusion barrier structure 250) may include the same semiconductor material (e.g., silicon). In some embodiments, the high-doped region 255 and the low-doped region (or diffusion barrier structure 250) may be doped with the same type of dopant (e.g., n-type). In some embodiments, the dopant in the highly doped region 255 may be doped with phosphorus and the dopant concentration may be about 5×10 20 cm -3 About 5×10 21 cm -3 In some embodiments, the dopant in the low-doped region (or diffusion barrier structure 250) may be doped with phosphorus, arsenic, antimony, and / or a combination thereof and may have a value of about 1×10 20 cm -3 About 2×10 21 cm -3 between the dopant concentrations.

[0103] Figure 2B Zoomed in Figure 2A In some embodiments, the diffusion barrier structure 250 may extend vertically (eg, along direction z) beyond the edge of the interface between the diffusion barrier structure 250 and the nanosheet layer 120. In some embodiments, as Figure 2B As shown, the vertical length L of the diffusion barrier structure 250 may be greater than the thickness T1 of the nanosheet layer 120. In some embodiments, the side surface of the diffusion barrier structure 250 may extend onto the inner spacer structure 130 adjacent to the nanosheet layer 120. In some embodiments, the diffusion barrier structure 250 may be in direct contact with the inner spacer structure 130. For example, Figure 2B As shown, the interface between the diffusion barrier structure 250 and the inner spacer structure 130 may have a length L1 along the direction z. In some embodiments, the length L1 may be less than about 4 nm. For example, the length L1 may be about 0.5 nm, about 1 nm, about 2 nm, or about 3 nm.

[0104] In some embodiments, the diffusion barrier structure 250 in contact with the topmost nanosheet layer 120 may extend vertically onto the gate spacer 135 on the topmost nanosheet layer 120. In some embodiments, the diffusion barrier structure 250 may directly contact the side surface of the gate spacer 135. For example, Figure 2B As shown, the interface between the diffusion barrier structure 250 and the gate spacer 135 may have a length L2 along the direction z. In some embodiments, the length L2 may be less than about 4 nm. For example, the length L2 may be about 0.5 nm, about 1 nm, about 2 nm, or about 3 nm. In some embodiments, the highly doped region 255 may contact the gate spacer 135, and the interface between the highly doped region 255 and the gate spacer 135 is located above the interface between the diffusion barrier structure 250 and the gate spacer 135.

[0105] In some embodiments, the high doping region 255 may be in contact with the inner spacer structure 130. In some embodiments, the side surface of the inner spacer structure 130 may be in contact with the side surfaces of two adjacent diffusion barrier structures 250 and the side surface of the high doping region 255. In some embodiments, the vertical distance D1 between two adjacent diffusion barrier structures 250 may be less than the vertical thickness T2 of the inner spacer structure 130. In some embodiments, the vertical distance D1 may be between about 1 nm and about 4 nm. For example, the vertical distance D1 may be about 1 nm, about 2 nm, about 3 nm, or about 4 nm. The diffusion barrier structure 250 covering the inner spacer structure 130 may prevent (or reduce) the dopant in the high doping region 255 from diffusing into the nanosheet layer 120 through the inner spacer structure 130.

[0106] In some embodiments, a vertical distance D2 between the bottommost diffusion barrier structure 250 and the fin structure 110 may be less than the vertical thickness T2. In some embodiments, the vertical distance D2 may be between about 1 nm and about 4 nm. For example, the vertical distance D2 may be about 1 nm, about 2 nm, about 3 nm, or about 4 nm.

[0107] In some embodiments, each diffusion barrier structure 250 may have a non-uniform width along a horizontal direction (eg, along direction x). Figure 2BAs shown, the diffusion barrier structure 250 may have a width W1 and a width W2, wherein the width W1 is measured at a midpoint of the interface between the diffusion barrier structure 250 and the nanosheet layer 120, and the width W2 is measured at an edge of the interface between the diffusion barrier structure 250 and the nanosheet layer 120. In some embodiments, the width W1 may be greater than the width W2. In some embodiments, the width W1 may be between about 1 nm and about 8 nm. For example, the width W1 may be about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, about 7 nm, or about 8 nm. In some embodiments, the width W2 may be between about 1 nm and about 5 nm. For example, the width W2 may be about 1 nm, about 2 nm, about 3 nm, about 4 nm, or about 5 nm.

[0108] In some embodiments, each diffusion barrier structure 250 may include an inclined surface. Figure 2B As shown, the angle θ1 between the horizontal plane (e.g., the xy plane) and the surface connected to the topmost point of the diffusion barrier structure 250 may be between about 0° and about 90°. For example, the angle θ1 may be about 45°, about 60°, about 70°, about 80°, or about 85°. Figure 2B As shown, the angle θ2 between the horizontal plane and the surface connected to the lowest point of the diffusion barrier structure 250 may be between about 0° and about 90°. For example, the angle θ2 may be about 45°, about 60°, about 70°, about 80°, or about 85°. In some embodiments, the angle θ1 and the angle θ2 may be less than arctan(thickness T1*(width W1-width W2) / 2).

[0109] Figure 2C An embodiment of an n-type nanosheet transistor with a diffusion barrier structure on an inner spacer is shown. Figure 2C Each source / drain epitaxial structure 125 may include a low-doped region (or diffusion barrier structure 250) and a high-doped region 255. The high-doped region 255 may be highly doped (n+) with an n-type dopant, such as phosphorus. For example, the dopant concentration of the high-doped region 255 may be about 5×10 20 cm -3 About 5×10 21 cm -3 The low-doped region (or diffusion barrier structure 250) may have a doping concentration less than that of the high-doped region 255, and may be a diffusion barrier structure to prevent (or mitigate) the diffusion of dopants in the high-doped region 255 into the nanosheet layer 120. For example, the dopant concentration of the low-doped region (or diffusion barrier structure 250) may be about 1×10 20 cm -3 About 2×10 21 cm -3The dopant in the low-doped region (or diffusion barrier structure 250 ) may be phosphorus, arsenic, antimony, or a combination thereof. In some embodiments, the side surface of the low-doped region (or diffusion barrier structure 250 ) may extend onto the inner spacer structure 130 adjacent to the nanosheet layer 120 .

[0110] Figure 3A Another embodiment of a source / drain epitaxial structure having a diffusion barrier structure is shown. Figure 3A Each source / drain epitaxial structure 125 may include a low-doped region (or diffusion barrier structure 350) and a high-doped region 355. The high-doped region 355 is separated from the nanosheet layer 120 by the low-doped region (or diffusion barrier structure 350). Figure 2A The discussion of components in Figure 3A Unless otherwise specified, Figure 2A The discussion of the low-doped region (or diffusion barrier structure 250) and the high-doped region 255 in FIG. 1 also applies to the low-doped region (or diffusion barrier structure 350) and the high-doped region 355, respectively. The low-doped region may also be referred to as "diffusion barrier structure 350". In some embodiments, the portion of the low-doped region (or diffusion barrier structure 350) that contacts the adjacent nanosheet layer may extend onto the interspacer structure 130 and merge with each other, such as Figure 3A shown.

[0111] Figure 3B Zoomed in Figure 3A In some embodiments, the diffusion barrier structure 350 may extend to span the side surface of the inner spacer structure 130. In some embodiments, the entire surface of the inner spacer structure 130 may be in direct contact with the diffusion barrier structure 350. In some embodiments, the diffusion barrier structure 350 may extend vertically to span multiple nanosheet layers 120 and / or multiple inner spacer structures 130. In some embodiments, the diffusion barrier structure 350 may extend vertically on the gate spacer 135. In some embodiments, the diffusion barrier structure 350 may be in direct contact with the side surface of the gate spacer 135. For example, Figure 3BAs shown, the interface between the diffusion barrier structure 350 and the gate spacer 135 may have a length L2' along the direction z. In some embodiments, the length L2' may be less than about 4nm. For example, the length L2' may be about 0.5nm, about 1nm, about 2nm, or about 3nm. In some embodiments, the vertical distance D2' between the diffusion barrier structure 350 and the fin structure 110 may be less than the vertical thickness T2. In some embodiments, the vertical distance D2' may be between about 1nm and about 4nm. For example, the vertical distance D2' may be about 1nm, about 2nm, about 3nm, or about 4nm. The diffusion barrier structure 350 covering the inner spacer structure 130 may prevent (or reduce) the dopant in the highly doped region 355 from diffusing into the nanosheet layer 120 through the inner spacer structure 130.

[0112] In some embodiments, the diffusion barrier structure 350 may have a non-uniform width along a horizontal direction (e.g., along a direction x). In some embodiments, the diffusion barrier structure 350 may have a width W1', a width W2', and a width W3', wherein the width W1' is measured at a midpoint of the interface between the diffusion barrier structure 350 and the nanosheet layer 120, the width W2' is measured at an edge of the interface between the diffusion barrier structure 350 and the nanosheet layer 120, and the width W3' is measured at a midpoint of the interface between the diffusion barrier structure 350 and the inner spacer structure 130. In some embodiments, the width W1' may be greater than the width W2', and the width W2' may be greater than the width W3'. In some embodiments, the width W1' may be between about 1 nm and about 8 nm. For example, the width W1' may be about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, about 7 nm, or about 8 nm. In some embodiments, the width W2' may be between about 1 nm and about 5 nm. For example, width W2' may be about 1 nm, about 2 nm, about 3 nm, about 4 nm, or about 5 nm. In some embodiments, width W3' may be between about 1 nm and about 3 nm. For example, width W3' may be about 1 nm, about 2 nm, or about 3 nm.

[0113] In some embodiments, the diffusion barrier structure 350 may include an inclined surface. Figure 3B As shown, the angle θ1′ between the horizontal plane (e.g., the xy plane) and the surface connected to the topmost point of the diffusion barrier structure 350 may be between about 0° and about 90°. For example, the angle θ1′ may be about 45°, about 60°, about 70°, about 80°, or about 85°. Figure 3BAs shown, the angle θ2′ between the horizontal plane and the surface connected to the narrowest portion of the diffusion barrier structure 250 may be between about 0° and about 90°. For example, the angle θ2′ may be about 45°, about 60°, about 70°, about 80°, or about 85°. In some embodiments, the angle θ1′ and the angle θ2′ may be less than arctan(thickness T1*(width W1′-width W2′) / 2).

[0114] Figure 3C An embodiment of an n-type nanosheet transistor with a diffusion barrier structure on an inner spacer is shown. Figure 3C Each source / drain epitaxial structure 125 may include a low-doped region (or diffusion barrier structure 350) and a high-doped region 355. The high-doped region 355 may be highly doped (n+) with an n-type dopant, such as phosphorus. For example, the dopant concentration of the high-doped region 355 may be about 5×10 20 cm -3 About 5×10 21 cm -3 The low-doped region (or diffusion barrier structure 350) may have a doping concentration less than that of the high-doped region 355, and may be a diffusion barrier structure to prevent (or mitigate) the diffusion of dopants in the high-doped region 355 into the nanosheet layer 120. For example, the dopant concentration of the low-doped region (or diffusion barrier structure 350) may be between about 1×10 20 cm -3 About 2×10 21 cm -3 The dopant in the low-doped region (or diffusion barrier structure 350 ) may be phosphorus, arsenic, antimony, or a combination thereof. In some embodiments, the side surface of the low-doped region (or diffusion barrier structure 350 ) may cover the inner spacer structure 130 adjacent to the nanosheet layer 120 .

[0115] although Figures 2A to 3C The two embodiments of the diffusion barrier structure proposed in the embodiment are different, but a person skilled in the art will understand that the different features of these embodiments can be included in a single embodiment. For example, the source / drain epitaxial structure can include the diffusion barrier structure 250 and the diffusion barrier structure 350.

[0116] According to some embodiments, Figure 4 A flow chart of a method 400 for forming a full gate field effect transistor 105 is shown. Figures 1 to 3B The present disclosure is not limited to these operational descriptions, and other operations may be performed. Other manufacturing operations may be performed between various operations of method 400 and are omitted for clarity. Furthermore, not all operations may be required to perform the present disclosure. Furthermore, certain operations may be performed simultaneously or in parallel. Figure 4 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described. For illustrative purposes, method 400 refers to Figures 5 to 14B The structure shown is described.

[0117] In reference Figure 4 When the method 400 is performed, the method 400 starts with a process of forming a stack having alternating first nanosheet layers and second nanosheet layers on a substrate (eg, the substrate 102 ) at operation 405 . Figure 5 4 is an isometric view of the substrate 102 after operation 405 and after forming a stack 520 having alternating first nanosheet layers 520a and second nanosheet layers 520b. In some embodiments, the first nanosheet layers 520a and second nanosheet layers 520b are formed on the exposed top surface of the substrate 102. In some embodiments, the first nanosheet layers 520a are sacrificial nanosheet layers and will be removed later, and the second nanosheet layers 520b correspond to Figure 1 Nanosheet layer 120 is shown. In some embodiments, the material of the first nanosheet layer 520a in the stack 520 is selected so that the first nanosheet layer 520a can be selectively removed from the stack 520 by etching without removing the second nanosheet layer 520b. For example, the second nanosheet layer 520b can be a nanosheet layer of silicon, and the first nanosheet layer 520a can be a nanosheet layer of silicon germanium.

[0118] The first nanosheet layer 520a and the second nanosheet layer 520b may be grown by any suitable method. For example, the first nanosheet layer 520a and the second nanosheet layer 520b may be grown by a chemical vapor deposition process using a precursor gas, such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), germane (GeH4), digermane (Ge2H6), other suitable gases or combinations thereof. In some embodiments, the first nanosheet layer 520a may include germanium at a concentration between about 20% and about 30%, while the second nanosheet layer 520b is substantially free of germanium, for example having a germanium concentration of less than about 1%. In some embodiments, corresponding to Figure 1 The second nanosheet layer 520b of the nanosheet layer 120 in the embodiment of the present invention forms the channel region of the gate-all-around field effect transistor 105 and can be lightly doped or intrinsic (e.g., undoped). If lightly doped, the doping level of the second nanosheet layer 520b is less than about 10 13 Atom / cm 3The first nanosheet layer 520a and the second nanosheet layer 520b may be deposited sequentially without interrupting the vacuum (e.g., in-situ) to avoid the formation of any intermediate layers. In some embodiments, the first nanosheet layer 520a may be doped to increase the etch selectivity compared to the second nanosheet layer 520b in a subsequent etch.

[0119] In some embodiments, the thickness of the first nanosheet layer 520a controls the spacing between the second nanosheet layers 520b in the stack 520. The thickness of the first nanosheet layer 520a and the second nanosheet layer 520b may range, for example, from about 3 nm to about 15 nm. Since the first nanosheet layer 520a and the second nanosheet layer 520b are grown separately, the thickness of each nanosheet layer may be independently adjusted according to the deposition time, etc. In some embodiments, an additional or less number of first nanosheet layers 520a and second nanosheet layers 520b may be formed in the stack 520. In some embodiments, the total number of nanosheet layers may be 2n, where n is the number of first nanosheet layers 520a or second nanosheet layers 520b in the stack 520.

[0120] In reference Figure 4 , method 400 continues to operation 410 and a process of patterning the stack 520 to form a fin structure. In some embodiments, the stack 520 is patterned to form a fin structure having a width along a direction y and a length along a direction x. The formation of the fin structure can be patterned using any suitable method. For example, the fin structure can be patterned using one or more lithography processes, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes can combine lithography and self-alignment processes to obtain patterns with smaller spacing than using a single and direct lithography process. For example, in some embodiments, a sacrificial layer is formed on the stack 520 and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Then, after removing the sacrificial layer, the remaining spacers can be used as a mask structure to pattern the fin structure.

[0121] By way of example and not limitation, Figure 6is an isometric view of a fin structure 620 formed by a stack 520 having the above-described patterning process. In some embodiments, the fin structure 620 may be formed by etching a first nanosheet layer 520a and a second nanosheet layer 520b into a first nanosheet layer 620a and a second nanosheet layer 620b. In some embodiments, the aforementioned patterning process does not stop on the top surface of the substrate 102, but continues to etch the top of the substrate 102 to form a fin structure 110 from the substrate 102 below the fin structure 620. Since the fin structure 620 and the fin structure 110 are formed by the same patterning process, the fin structure 620 and the fin structure 110 are substantially aligned with each other. For example, the sidewall surfaces of the fin structure 620 in the xz plane and in the yz plane are each substantially aligned with the sidewall surfaces of the fin structure 110, such as Figure 6 shown.

[0122] Additional fin structures, such as fin structure 620, may be formed on substrate 102 and may be formed in the same or different regions of substrate 102. Figure 6 These additional fin structures are not shown in FIG. By way of example and not limitation, each fin structure 620 has a width along direction y between about 15 nm and about 150 nm.

[0123] In some embodiments, when the width of the first nanosheet layer 620a and the second nanosheet layer 620b along the direction y is substantially different from the height along the direction z, for example, when their width is greater than or less than their height, they are referred to as "nanosheets". In some embodiments, when the width of the first nanosheet layer 620a and the second nanosheet layer 620b along the direction y is equal to the height along the direction z, they may also be referred to as "nanowires". In some embodiments, the first nanosheet layer 620a and the second nanosheet layer 620b are deposited as nanosheets and then patterned to form nanowires with the same height and width. As an example and not a limitation, the first nanosheet layer 620a and the second nanosheet layer 620b are described herein as nanosheet (NS) layers. Based on what is disclosed herein, nanowires (NW) also belong to the spirit and scope of the present disclosure. In addition, for the purpose of example and not to limit the scope of the present disclosure, the first nanosheet layer 620a and the second nanosheet layer 620b in the method 400 are described herein as silicon germanium nanosheet layers and silicon nanosheet layers, respectively.

[0124] In some embodiments, after forming the fin structure 620, a shallow trench isolation region 138 may be formed on the etched or recessed portion of the substrate 102 to cover the sidewall surface of the fin structure 110. In some embodiments, the shallow trench isolation region 138 may electrically isolate the fin structure 110 and include one or more silicon oxide-based dielectrics. By way of example and not limitation, the shallow trench isolation region 138 may be formed by the following operations. An isolation structure material (e.g., a silicon oxide-based dielectric) is blanket deposited on the fin structure 620 and the substrate 102. The thus deposited isolation structure material is then planarized (e.g., by a chemical mechanical polishing (CMP) process) so that the top surface of the isolation structure material is substantially coplanar with the top surface of the fin structure 620. The planarized isolation structure material is then etched back so that the resulting shallow trench isolation region 138 has a substantially similar height to the fin structure 110, such as Figure 6 In some embodiments, the fin structure 620 protrudes from the shallow trench isolation region 138 so that the shallow trench isolation region 138 does not cover the sidewall portion of the fin structure 620, such as Figure 6 This is intentional, to help create Figure 1 A full gate field effect transistor 105 is shown.

[0125] The method 400 continues with operation 415 and a process of removing a portion of the fin structure to form an opening in the fin structure, including (i) forming a sacrificial gate structure 700, referring to Figure 7 and (ii) removing the portion of the fin structure 620 exposed by the sacrificial gate structure 700, referring to Figure 8 shown.

[0126] In some embodiments, the sacrificial gate structure 700 is formed to have a length along the direction y (eg, perpendicular to Figure 6 The fin structure 620 shown in the isometric view has a width along the direction x. By way of example and not limitation, Figure 7 yes Figure 6 Cross-sectional view taken along line AB. Figure 7 The sacrificial gate structure 700 is shown formed on a portion of the fin structure 620. Figure 7 is a cross-sectional view, not an isometric view, and therefore the portion of the sacrificial gate structure 700 covering the sidewall portion of the fin structure 620 is not shown. Figure 7 In the cross-sectional view of Figure 6 In some embodiments, a portion of the sacrificial gate structure 700 is formed between the fin structure 620 and the shallow trench isolation region 138, such as Figure 6 shown.

[0127] In some embodiments, the sacrificial gate structure 700 covers the top and sidewall portions of the fin structure 620. In some embodiments, the sacrificial gate structure 700 is subsequently Figure 1 The sacrificial gate structure 700 may include a sacrificial gate electrode 700a formed on a sacrificial gate dielectric, but for simplicity, Figure 7 Not shown. The sacrificial gate structure 700 may further include a capping layer 705 formed on a top surface of the sacrificial gate structure 700. In some embodiments, the capping layer 705 may protect the sacrificial gate electrode 700a from subsequent etching operations. During the manufacturing stage, a gate spacer 135 may be formed on the side surface of the sacrificial gate structure 700. As described above, the gate spacer 135 is not removed during the gate replacement process; rather, the gate spacer 135 facilitates the formation of the gate structure 115.

[0128] By way of example and not limitation, the sacrificial gate structure 700 may be formed by depositing and patterning a sacrificial gate electrode 700a on the fin structure 620. In some embodiments, the sacrificial gate structure 700 is formed on a plurality of fin structures 620. Figure 7 As shown, a portion of the fin structure 620 is not covered by the sacrificial gate structure 700 because the width of the sacrificial gate structure 700 along the direction x is narrower than the length of the fin structure 620. In some embodiments, the sacrificial gate structure 700 is used as a mask structure in a subsequent etching operation to define the fin structure 620 as shown in FIG. Figure 1 The channel region of the gate-all-around field effect transistor 105 is shown. Therefore, the lateral dimensions (eg, width and length) of the sacrificial gate structure 700 and the gate structure 115 are substantially similar.

[0129] Reference Figure 8, the portion of the fin structure 620 not covered by the sacrificial gate structure 700 may be removed. In some embodiments, the removal process involves a dry etching process, a wet etching process, or a combination thereof. The removal process is selective to the first nanosheet layer 620a and the second nanosheet layer 620b to shape them into the first nanosheet layer 820a and the nanosheet layer 120, respectively. In some embodiments, the dry etching process includes an etchant having an oxygen-containing gas; a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and / or hexafluoroethane (C2F6)); a chlorine-containing gas (e.g., chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), and / or boron trichloride (BCl3)); a bromine-containing gas (e.g., hydrogen bromide (HBr) and / or bromoform (CHBr3)); an iodine-containing gas; other suitable etching gases and / or plasmas; or a combination thereof. The wet etch chemistry may include diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; aqueous ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ), acetic acid (CH 3 COOH); or a combination thereof.

[0130] In some embodiments, the etchant of the aforementioned etching process does not substantially etch the sacrificial gate structure 700 (which is protected by the capping layer 705 and the gate spacer 135) and Figure 6 The shallow trench isolation region 138 shown. This is because the capping layer 705, the gate spacer 135, and the shallow trench isolation region 138 include materials with low etching selectivity, such as silicon nitride-based materials (e.g., silicon nitride, silicon carbonitride, and silicon carbonitride oxide) or silicon oxide-based materials. In some embodiments, Figure 6 The shallow trench isolation region 138 shown serves as an etch stop layer in the etching process described above.

[0131] As a result of operation 415, an opening 840 is formed in each fin structure 620, such as Figure 8 As shown. The opening 840 divides each fin structure 620 into separate portions, and each portion is covered by the sacrificial gate structure 700. In some embodiments, the removal process in operation 415 may also include removing portions of the fin structure 110 that are not covered by the remaining portions of the fin structure 620. Removing the portions of the fin structure 110 may include etching the portions of the fin structure 110, and the manner may be similar to etching the portions of the fin structure 620 that are not covered by the sacrificial gate structure 700. In some embodiments, an isolation layer 145 may be deposited on the bottom surface of the opening 840 to fill the space left by removing the portions of the fin structure 110.

[0132] Reference Figure 4, the method 400 continues to operation 420 and a process of forming an inner spacer. The process of forming the inner spacer may include (i) selectively etching an edge portion of the first nanosheet layer 820a to form a groove structure 945, as shown in FIG. Fig. 9 and (ii) depositing a dielectric material to fill the recessed structure, as shown in FIG. Fig.10 According to some embodiments, Fig. 9 Show Figure 8 The exposed edge of the first nanosheet layer 820a of the structure is laterally etched (e.g., recessed) along the direction x to become the structure after the first nanosheet layer 920a. According to some embodiments, the exposed edge of the first nanosheet layer 820a is recessed (e.g., partially etched) by an amount of about 3nm to about 10nm along the direction x to form a structure as shown in FIG. Fig. 9 A groove structure 945 is shown.

[0133] In some embodiments, selectively etching the first nanosheet layer 820a can be achieved by a dry etching process that is selective to silicon germanium. For example, halogen-based chemicals exhibit high etching selectivity to germanium, but low etching selectivity to silicon. Therefore, the halogen gas etches the germanium-containing layer such as the first nanosheet layer 820a at a higher etching rate than etching the substantially germanium-free layer such as the nanosheet layer 120. In some embodiments, the halogen-based chemicals include fluorine-based and / or chlorine-based gases. Alternatively, a wet etching chemistry that is highly selective to silicon germanium can be used. As an example but not limiting, the wet etching chemistry may include a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (or SPM), or a mixture of ammonium hydroxide, H2O2 and water (or APM). The desired amount of silicon germanium can be removed by timing the execution time of the above etching process.

[0134] In some embodiments, the first nanosheet layer 820a having a higher germanium atomic concentration has a higher etching rate than the nanosheet layer 120 having a lower or zero germanium atomic concentration. Therefore, the etching rate of the above etching process can be adjusted by adjusting the germanium atomic concentration (e.g., germanium content) in the first nanosheet layer 820a. As described above, the germanium content in the first nanosheet layer 820a can be between about 20% and about 30%. The etching rate of the silicon germanium nanosheet layer having a germanium content of about 20% can be slower than the etching rate of the silicon germanium nanosheet layer having a germanium content of about 30%. Therefore, the germanium concentration can be adjusted accordingly to achieve the desired etching rate and selectivity between the first nanosheet layer 820a and the nanosheet layer 120.

[0135] Reference Fig.10 , the inner spacer structure 130 may be formed in the recess structure 945. In some embodiments, forming the inner spacer structure 130 may include (i) Fig. 9(ii) removing a portion of the dielectric layer outside the recess structure 945, such as Fig. 9 As shown, the inner spacer structure 130 is left to fill the groove structure 945 .

[0136] Reference Figure 4 The method 400 continues with operation 425 and a process of forming a diffusion barrier structure at the opening. Fig.11A and Fig. 11B As described respectively, the diffusion barrier structure 250 and the diffusion barrier structure 350 may be epitaxially grown on the exposed side surfaces of the nanosheet layer 120 .

[0137] In some embodiments, as described in reference Fig.11A As shown, the diffusion barrier structure 250 may be epitaxially grown using a chemical vapor deposition (CVD) process similar to that used in operation 405 to form a first nanosheet layer 520a and a second nanosheet layer 520b, as shown in FIG. Figure 5As shown. In some embodiments, the diffusion barrier structure 250 can be epitaxially grown using a plasma-enhanced CVD (PECVD) process. In some embodiments, a precursor gas (e.g., SiH4, SiH2Cl2, SiHCl3 and / or a combination thereof) can be used to epitaxially grow a semiconductor material (e.g., silicon) having a crystalline structure on the side surface of the nanosheet layer 120. In some embodiments, the flow rate of the precursor gas can be controlled. For example, the flow rate of the SiH4 precursor gas can be between about 10 sccm and about 150 sccm, the flow rate of the SiH2Cl2 precursor gas can be between about 200 sccm and about 900 sccm, and the flow rate of the SiHCl3 precursor gas can be between about 200 sccm and about 900 sccm. In some embodiments, an etching gas (e.g., hydrogen chloride (HCl)) can be used to selectively remove a semiconductor material of an amorphous structure formed on a dielectric surface (e.g., the side surface of the inner spacer structure 130 or the gate spacer 135). In some embodiments, the flow rate of the etching gas can be controlled. For example, the flow rate of the HCl etching gas may be between about 0 sccm and about 600 sccm. Removing the semiconductor material having an amorphous structure ensures that the diffusion barrier structure 250 has a crystalline structure. In some embodiments, a dopant precursor gas, such as phosphine (PH3), arsenic (AsH3), antimonide (SbH3) and / or a combination thereof may be used to dope the diffusion barrier structure 250 in a CVD process or a PECVD process. In some embodiments, the flow rate of the dopant precursor gas may be controlled. For example, the flow rate of the PH3 dopant precursor may be between about 0 sccm and about 200 sccm, the flow rate of the AsH3 dopant precursor may be between about 0 sccm and about 450 sccm, and the flow rate of the SbH3 dopant precursor may be between about 0 sccm and about 450 sccm. In some embodiments, in the CVD process or the PECVD process for forming the diffusion barrier structure 250, the pressure may be controlled at about 5 torr to about 300 torr, and the temperature may be controlled at about 650°C to about 680°C.

[0138] In some embodiments, in the process of forming the diffusion barrier structure 250, the semiconductor material having a crystalline structure is initially epitaxially grown along a horizontal direction (e.g., along a direction x) on the side surface of the nanosheet layer 120. Subsequently, after a certain amount of semiconductor material is formed on the side surface of the nanosheet layer 120, the semiconductor material may also be epitaxially grown along a vertical direction (e.g., along a direction z) and cross the edge of the side surface of the nanosheet layer 120 to further extend to the side surface of the inner spacer structure 130. The process may continue so that a portion of the semiconductor material on the side surface of the inner spacer structure 130 may be further epitaxially grown along a horizontal direction and in a direction toward the inner spacer structure 130 so that the diffusion barrier structure 250 contacts the inner spacer structure 130. In operation 425, the time for which the diffusion barrier structure 250 is epitaxially grown may be controlled to ensure that the diffusion barrier structure 250 extends to or contacts the side surface of the inner spacer structure 130.

[0139] In some embodiments, as described in reference Fig. 11B As described, the diffusion barrier structure 350 may be formed on the exposed side surfaces of the nanosheet layer 120. Unless otherwise specified, the description of the process for forming the diffusion barrier structure 250 is applicable to the process for forming the diffusion barrier structure 350. In some embodiments, the diffusion barrier structure 350 may be epitaxially grown from the side surfaces of the nanosheet layer 120 and then covered on the inner spacer structure 130. In some embodiments, the process for forming the diffusion barrier structure 350 may continue so that portions of the diffusion barrier structure 350 initially grown from adjacent nanosheet layers 120 may merge with each other on the side surfaces of the inner spacer structure 130. In some embodiments, the time for epitaxially growing the diffusion barrier structure 350 may be controlled to be longer than the time for epitaxially growing the diffusion barrier structure 250 to ensure that the diffusion barrier structure 350 merges on the side surfaces of the inner spacer structure 130. In some embodiments, since the diffusion barrier structure 350 grows from the side surface of the nanosheet layer 120 , the portion of the diffusion barrier structure 350 surrounding the horizontal portion of the nanosheet layer 120 may protrude more into the opening 840 than the portion of the diffusion barrier structure 350 surrounding the horizontal portion of the inner-spacer structure 130 .

[0140] In order to make the side surface of the diffusion barrier structure 350 exposed in the opening 840 flatter, in some embodiments, the etching process can be combined with the epitaxial growth process to trim the side surface of the diffusion barrier structure 350. For example, the flow rate of the etching gas can be increased at the end of the process of forming the diffusion barrier structure 350 to trim the side surface of the diffusion barrier structure 350. Preventing the diffusion barrier structure 350 from protruding too much into the opening 840 can provide more space for the subsequently formed high-doped region 355 and reduce the overall resistivity of the subsequently formed source / drain epitaxial structure 125, such as Fig. 12B shown.

[0141] Reference Figure 4 , the method 400 continues to operation 430 and a process of forming a highly doped region of the source / drain epitaxial structure in the opening. As an example and not limitation, the highly doped region 255 and the highly doped region 355 can be formed by epitaxially growing a semiconductor material on the exposed surface of the diffusion barrier structure 250 and the diffusion barrier structure 350, respectively, as shown in FIG. Fig. 12A and Fig. 12B As shown, the process of the source / drain epitaxial structure 125 is completed.

[0142] In some embodiments, as described in reference Fig. 12AAs described, the highly doped region 255 can be epitaxially grown to the diffusion barrier structure 250 using a CVD process or a PECVD process similar to that used in operation 425, unless otherwise specified. In some embodiments, the diffusion barrier structure 250 and the highly doped region 255 can be formed sequentially without interrupting the vacuum (e.g., in-situ) to avoid any layer formation that may interfere. In some embodiments, a precursor gas (e.g., SiH4, SiH2Cl2, SiHCl3 and / or a combination thereof) can be used to epitaxially grow a semiconductor material (e.g., silicon) on the exposed surface of the diffusion barrier structure 250. In some embodiments, the flow rate of the precursor gas can be controlled. For example, the flow rate of the SiH4 precursor gas can be between about 20 sccm and about 150 sccm, the flow rate of the SiH2Cl2 precursor gas can be between about 300 sccm and about 900 sccm, and the flow rate of the SiHCl3 precursor gas can be between about 300 sccm and about 900 sccm. In some embodiments, an etching gas (e.g., hydrogen chloride (HCl)) may be used to selectively remove semiconductor materials of an amorphous structure formed on a dielectric surface (e.g., a side surface of an inner spacer structure 130 or a gate spacer 135). In some embodiments, the flow rate of the etching gas may be controlled. For example, the flow rate of the HCl etching gas may be between about 0 sccm and about 600 sccm. Removing semiconductor materials with an amorphous structure may ensure that the highly doped region 255 is a crystalline structure with crystallization. In some embodiments, a dopant precursor gas, such as phosphine (PH3), arsenic (AsH3), antimonide (SbH3) and / or a combination thereof may be used in a CVD process or a PECVD process to dope the diffusion barrier structure 250. In some embodiments, the flow rate of the dopant precursor gas may be controlled. For example, the flow rate of the PH3 dopant precursor may be between about 30 sccm and about 450 sccm, the flow rate of the AsH3 dopant precursor may be between about 0 sccm and about 270 sccm, and the flow rate of the SbH3 dopant precursor may be between about 0 sccm and about 270 sccm. In some embodiments, the dopant concentration of the doped high-doped region 255 may be higher than the dopant concentration of the doped diffusion barrier structure 250 by controlling the flow rates of the precursor gas and the dopant precursor gas. In some embodiments, the ratio of the flow rate of the dopant precursor gas to the flow rate of the precursor gas used for epitaxial growth of the high-doped region 255 may be greater than the ratio of the flow rate of the dopant precursor gas to the flow rate of the precursor gas used for epitaxial growth of the diffusion barrier structure 250 by about 2 times to about 50 times. In some embodiments, in the CVD process or the PECVD process for forming the high-doped region 255, the pressure may be controlled at about 100 torr to about 300 torr, and the temperature may be controlled at about 650° C. to about 700° C.

[0143] As reference Fig. 12A As described, in some embodiments, the epitaxial growth time of the highly doped region 255 can be controlled to ensure that different portions of the highly doped region 255 grown on different surfaces of the diffusion barrier structure 250 merge with each other. In some embodiments, the epitaxial growth time of the highly doped region 255 can be controlled to ensure that the highly doped region 255 contacts the side surface of the inner spacer structure 130. In some embodiments, the epitaxial growth time of the highly doped region 255 can be controlled to ensure that the highly doped region 255 contacts the isolation layer 145 on the bottom surface of the opening 840. In some embodiments, the epitaxial growth time of the highly doped region 255 can be controlled to ensure that the highly doped region 255 is formed above the topmost point of the diffusion barrier structure 250. In some embodiments, the epitaxial growth time of the highly doped region 255 can be controlled to ensure that the highly doped region 255 contacts the gate spacer 135 at the interface above the interface between the diffusion barrier structure 250 and the gate spacer 135.

[0144] In some embodiments, as described in reference Fig. 12B As described, the highly doped region 355 may be epitaxially grown using a CVD process or a PECVD process similar to that used in operation 425 to form the diffusion barrier structure 350, unless otherwise noted. Fig. 12A The description of forming the highly doped region 255 is applicable to forming the highly doped region 355. Fig. 12B As described, in some embodiments, since the diffusion barrier structure 350 may not completely cover some side surfaces of the inner-spacer structure 130 , the highly doped region 355 may not contact these side surfaces of the inner-spacer structure 130 .

[0145] Reference Figure 4 , the method 400 continues to operation 435 and a process of forming a metal gate structure. The process of forming a metal gate structure may include (i) removing the sacrificial gate structure 700 and the first nanosheet layer 920a, as shown in FIG. Fig.13A and Fig. 13B and (ii) forming a metal gate structure 115 to surround the nanosheet layer 120, as shown in FIG. Fig.14A and Fig. 14B shown.

[0146] In some embodiments, removing the sacrificial gate structure 700 may include removing the capping layer 705 to expose the sacrificial gate electrode 700a; and subsequently, removing the sacrificial gate electrode 700a to expose the fin structure 620 between the source / drain epitaxial structures 125. In some embodiments, removing the first nanosheet layer 920a may include selectively etching the first nanosheet layer 920a without removing the nanosheet layer 120, as shown in FIG. Fig.13A and Fig. 13B shown.

[0147] In some embodiments, forming the metal gate structure 115 may include (i) forming an interfacial dielectric layer 115a on the exposed surface of the nanosheet layer 120; (ii) forming a gate dielectric layer 115b on the interfacial dielectric layer 115a; and (iii) forming a gate electrode 115c on the gate dielectric layer 115b, referring to Fig.14A and Fig. 14B As described above, the metal gate structure 115 is electrically isolated from the source / drain epitaxial structure 125 by the inner spacer structure 130 and the gate spacer 135. In some embodiments, after forming the metal gate structure 115, an interlayer dielectric layer 165 may be formed to fill the space above the source / drain epitaxial structure 125.

[0148] The embodiments described in the present disclosure are directed to structures of full-gate field effect transistors and methods for forming the structures. In some embodiments, the structure includes a diffusion barrier structure in the source / drain epitaxial structure of the full-gate field effect transistor. The diffusion barrier structure contacts the nanosheet layer of the full-gate field effect transistor and extends to the inner gap structure adjacent to the nanosheet layer. The diffusion barrier structure separates the highly doped region of the source / drain epitaxial structure from the nanosheet layer and the highly doped region of the source / drain epitaxial structure from the region of the inner gap structure near the nanosheet layer to prevent (or reduce) the diffusion of dopants in the highly doped region into the nanosheet layer and the inner gap structure, thereby maintaining the integrity of the nanosheet layer as a semiconductor channel of the full-gate field effect transistor, thereby avoiding the current crowding effect.

[0149] In some embodiments, the semiconductor structure includes a substrate, a nanostructure element, a gate structure, an inner spacer structure, a first epitaxial layer and a second epitaxial layer. The nanostructure element is on the substrate. The gate structure surrounds the nanostructure element. The inner spacer structure is adjacent to the gate structure. The first epitaxial layer contacts the side surface of the nanostructure element and is located on the side surface of the inner spacer structure. The second epitaxial layer contacts the first epitaxial layer, wherein the dopant concentration of the first epitaxial layer is less than the dopant concentration of the second epitaxial layer. In some embodiments, the semiconductor structure also includes a gate spacer on the nanostructure element, wherein the first epitaxial layer is on the side surface of the gate spacer. In some embodiments, the interface between the gate spacer and the second epitaxial layer is located above another interface between the gate spacer and the first epitaxial layer. In some embodiments, the vertical length of the first epitaxial layer is greater than the thickness of the nanostructure element. In some embodiments, the first epitaxial layer is located on the edge of the interface between the nanostructure element and the gate structure. In some embodiments, the side surface of the inner spacer structure contacts a portion of the side surface of the first epitaxial layer and the side surface of the second epitaxial layer. In some embodiments, the first epitaxial layer extends from a top edge of a side surface of the inner-spacer structure to a bottom edge of a side surface of the inner-spacer structure.

[0150] In some embodiments, a semiconductor structure includes a substrate, a plurality of nanosheet layers, a gate structure, an inner spacer structure, and a source / drain structure. The nanosheet layers are on the substrate. The gate structure surrounds the nanosheet layers. The inner spacer structure is inserted between the nanosheet layers. The source / drain structure is on the substrate and adjacent to the nanosheet layers, wherein the source / drain structure includes a diffusion barrier structure and an epitaxial layer. The diffusion barrier structure contacts multiple side surfaces of the nanosheet layers and the side surface of the inner spacer structure. The epitaxial layer is on the substrate and separated from the nanosheet layers by the diffusion barrier structure. In some embodiments, the dopant concentration of the epitaxial layer is greater than the dopant concentration of the diffusion barrier structure. In some embodiments, the dopant concentration of the diffusion barrier structure is about 1×10 20 cm -3 About 2×10 21 cm -3 In some embodiments, the dopant concentration of the epitaxial layer is between about 5×10 20 cm -3 About 5×10 21 cm -3In some embodiments, the diffusion barrier structure includes phosphorus, arsenic, antimony, or a combination thereof. In some embodiments, the diffusion barrier structure extends from a top edge of a side surface of the inner spacer structure to a bottom edge of a side surface of the inner spacer structure. In some embodiments, a side surface of the inner spacer structure contacts a first side surface and a second side surface of the diffusion barrier structure, a side surface of the inner spacer structure contacts a side surface of the epitaxial layer, and a side surface of the epitaxial layer contacts a first side surface and a second side surface of the diffusion barrier structure.

[0151] In some embodiments, a method for forming a semiconductor structure includes the following operations. A plurality of channel layers are formed on a substrate, and the channel layers are alternately stacked with a plurality of sacrificial layers. A portion of each of the sacrificial layers is removed to form a plurality of groove structures. A plurality of inner spacers are formed in the groove structures. A diffusion barrier structure is formed in contact with a plurality of side surfaces of the channel layers and on a plurality of side surfaces of the inner spacers. An epitaxial region is formed on a plurality of side surfaces of the diffusion barrier structure. In some embodiments, the method further includes forming a gate spacer on the channel layer, wherein forming the diffusion barrier structure includes epitaxially growing the diffusion barrier structure on the side surface of the gate spacer. In some embodiments, forming the epitaxial region includes growing the epitaxial region on the side surface of the gate spacer and the diffusion barrier structure. In some embodiments, forming the diffusion barrier structure includes epitaxially growing semiconductor material to cover a plurality of interfaces between the channel layers and the inner spacers. In some embodiments, forming the diffusion barrier structure includes: growing a first portion of the diffusion barrier structure on the side surface of the first channel layer of the channel layers; growing a second portion of the diffusion barrier structure on the side surface of the second channel layer of the channel layers; and merging the first portion and the second portion of the diffusion barrier structure on the side surface of the inner spacer between the first channel layer and the second channel layer. In some embodiments, forming the diffusion barrier structure includes doping the diffusion barrier structure with a first dopant concentration, and forming the epitaxial region includes doping the epitaxial region with a second dopant concentration greater than the first dopant concentration.

[0152] It should be understood that the "Implementation" section, rather than the "Abstract" section, is intended to be used to interpret the scope of the patent application. The Abstract section may list one or more implementations of the present disclosure, but not all implementations, and is therefore not intended to limit the scope of the patent application in any way.

[0153] The features of some embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A nanostructured element is on a substrate; A gate structure surrounds the nanostructure element; An inner spacer structure is adjacent to the gate structure; A first epitaxial layer contacts a side surface of the nanostructure element and is located on a side surface of the inner spacer structure; as well as A second epitaxial layer contacts the first epitaxial layer, wherein a dopant concentration of the first epitaxial layer is less than a dopant concentration of the second epitaxial layer.

2. The semiconductor structure according to claim 1, wherein: A gate spacer is also included on the nanostructure element, wherein the first epitaxial layer is on a side surface of the gate spacer.

3. The semiconductor structure according to claim 1, wherein: A vertical length of the first epitaxial layer is greater than a thickness of the nanostructure element.

4. The semiconductor structure according to claim 1, wherein: The first epitaxial layer is located on an edge of an interface between the nanostructure element and the gate structure.

5. A semiconductor structure, characterized in that: include: A plurality of nanosheet layers are on a substrate; a gate structure surrounding the plurality of nanosheet layers; An interstitial structure is inserted between the plurality of nanosheet layers; as well as A source / drain structure is on the substrate and adjacent to the plurality of nanosheet layers, wherein the source / drain structure comprises: a diffusion barrier structure in contact with a plurality of side surfaces of the plurality of nanosheet layers and a side surface of the interspacer structure; as well as An epitaxial layer is on the substrate and separated from the plurality of nanosheet layers by the diffusion barrier structure.

6. The semiconductor structure according to claim 5, characterized in that A dopant concentration of the epitaxial layer is greater than a dopant concentration of the diffusion barrier structure.

7. The semiconductor structure according to claim 5, characterized in that The diffusion barrier structure extends from a top edge of the side surface of the inner spacer structure to a bottom edge of the side surface of the inner spacer structure.

8. The semiconductor structure according to claim 5, wherein: in The side surface of the inner spacer structure is in contact with a first side surface and a second side surface of the diffusion barrier structure; The side surface of the inner spacer structure is in contact with a side surface of the epitaxial layer; as well as The side surface of the epitaxial layer contacts the first side surface and the second side surface of the diffusion barrier structure.

9. A method for forming a semiconductor structure, characterized in that: include: Forming a plurality of channel layers on a substrate, wherein the plurality of channel layers and a plurality of sacrificial layers are alternately stacked; removing a portion of each of the plurality of sacrificial layers to form a plurality of recess structures; forming a plurality of inner gaps in the plurality of groove structures; forming a diffusion barrier structure in contact with the plurality of side surfaces of the plurality of channel layers and on the plurality of side surfaces of the plurality of inner spacers; as well as An epitaxial region is formed on a plurality of side surfaces of the diffusion barrier structure.

10. The method according to claim 9, characterized in that in: Forming the diffusion barrier structure includes doping the diffusion barrier structure with a first dopant concentration; and Forming the epitaxial region includes doping the epitaxial region with a second dopant concentration greater than the first dopant concentration.

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