Metal oxide semiconductor field effect transistor and preparation method thereof

Abstract

The invention discloses a metal oxide semiconductor field effect transistor and a preparation method thereof. The metal oxide semiconductor field effect transistor comprises a drain metal layer, a substrate, an epitaxial layer, a gate oxide layer, a gate layer, a dielectric layer and a source metal layer which are stacked in sequence, the upper surface of the epitaxial layer comprises ion implantation regions arranged at intervals and inverted trapezoidal grooves arranged between two adjacent ion implantation regions; the lower oxidation layer of the gate oxidation layer is laminated on the upper surface of the inverted trapezoidal groove, and the upper surface of the gate oxidation layer is flush with the upper surface of the ion implantation region; an upper oxide layer of the gate oxide layer is laminated on the upper surface of the lower oxide layer, and two ends of the upper oxide layer extend and cover a first region on the upper surface of the ion implantation region; the width of the gate layer is the same as that of the upper oxide layer; the dielectric layer is stacked on the upper surface of the gate layer and the second region on the upper surface of the ion implantation region. According to the embodiment of the invention, the switching loss of the metal oxide semiconductor field effect transistor is reduced, and the reliability of the metal oxide semiconductor field effect transistor is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a metal oxide semiconductor field effect transistor and a preparation method thereof. Background Art

[0002] Silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) can realize the miniaturization of passive devices and heat dissipation components due to its high operating frequency, low switching loss, and high power density. In addition, SiC MOSFET has a small chip area and does not require an anti-parallel freewheeling diode, which is conducive to the realization of a small package; however, in the inverter high-frequency circuit, the switching loss of SiC MOSFET is still high.

[0003] The related technology reduces the switching loss of the SiC MOSFET device by setting a split gate structure in the SiC MOSFET and utilizing the split gate structure to reduce the overlapping area between the gate and the drain.

[0004] Although the switching loss of SiC MOSFET devices can be reduced to a certain extent by setting a split gate structure in the SiC MOSFET to reduce the switching loss of the device, the split gate structure will cause serious electric field concentration problems at the gate oxide corners in the device, thereby reducing the reliability of the device. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a metal oxide semiconductor field effect transistor and a method for preparing the same, which can solve the problem in the related art that silicon carbide metal oxide semiconductor field effect transistors cannot reduce switching losses while taking into account device reliability.

[0006] In a first aspect, an embodiment of the present application provides a metal oxide semiconductor field effect transistor, wherein the metal oxide semiconductor field effect transistor comprises a drain metal layer, a substrate, an epitaxial layer, a gate oxide layer, a gate layer, a dielectric layer and a source metal layer stacked in sequence;

[0007] The upper surface of the epitaxial layer includes at least two ion implantation regions arranged at intervals, and an inverted trapezoidal groove arranged between two adjacent ion implantation regions; the ion implantation region extends from the upper surface of the epitaxial layer to the inside of the epitaxial layer along the direction of the thickness of the metal oxide semiconductor field effect transistor;

[0008] The gate oxide layer comprises an upper oxide layer and a lower oxide layer connected to each other; the lower oxide layer is stacked on the upper surface of the inverted trapezoidal groove and the upper surface of the lower oxide layer is flush with the upper surface of the ion implantation region; the upper oxide layer is stacked on the upper surface of the lower oxide layer and the two ends of the upper oxide layer extend and cover the first area of ​​the upper surface of the ion implantation region respectively;

[0009] The width of the gate layer is the same as that of the upper oxide layer; the width of the dielectric layer is greater than that of the gate layer, and the dielectric layer is stacked on the upper surface of the gate layer and the second area on the upper surface of the ion implantation area; the first area and the second area are adjacent.

[0010] Optionally, in the metal oxide semiconductor field effect transistor, a minimum value of an angle between a side wall of the inverted trapezoidal groove and a bottom surface of the inverted trapezoidal groove is 30° to 60°.

[0011] Optionally, in the metal oxide semiconductor field effect transistor, the width of the bottom surface of the inverted trapezoidal groove is 0.1 μm to 0.6 μm.

[0012] Optionally, in the metal oxide semiconductor field effect transistor, the depth of the inverted trapezoidal groove is 0.1 μm to 0.4 μm.

[0013] Optionally, in the metal oxide semiconductor field effect transistor, the thickness of the upper oxide layer is 50 nm to 200 nm.

[0014] Optionally, in the metal oxide semiconductor field effect transistor, the source metal layer includes an ohmic metal layer and a front metal layer; the ohmic metal layer is stacked on the upper surface of the ion implantation region, and the front metal layer is stacked on the upper surfaces of the ohmic metal layer and the dielectric layer;

[0015] The thickness of the ohmic metal layer is less than the first target thickness of the dielectric layer; the first target thickness is the thickness between the upper surface of the dielectric layer and the upper surface of the ion implantation region.

[0016] Optionally, in the metal oxide semiconductor field effect transistor, the thickness of the ohmic metal layer is 10nm to 500nm; the second target thickness of the source metal layer is 2μm to 5μm; the second target thickness is the thickness between the upper surface of the source metal layer and the upper surface of the ion implantation area.

[0017] Optionally, in the metal oxide semiconductor field effect transistor, the ion implantation region includes an ion implantation base region and a heavily doped ion implantation region; the width of the heavily doped ion implantation region is smaller than the width of the ion implantation base region, and the heavily doped ion implantation region extends from the upper surface of the epitaxial layer along the direction of the thickness of the metal oxide semiconductor field effect transistor to the interior of the ion implantation base region;

[0018] Wherein, the heavily doped ion implantation region includes a P-type heavily doped ion implantation region and an N-type heavily doped ion implantation region; in the heavily doped ion implantation region, both ends of the P-type heavily doped ion implantation region are respectively connected to the N-type heavily doped ion implantation region;

[0019] The first region and the second region are regions in the upper surface of the N-type heavily doped ion implantation region; the upper surface of the N-type heavily doped ion implantation region also includes a third region, and the source metal layer is stacked on the third region.

[0020] Optionally, in the metal oxide semiconductor field effect transistor, the thickness of the P-type heavily doped ion implantation region is greater than or equal to the thickness of the N-type heavily doped ion implantation region.

[0021] Optionally, in the metal oxide semiconductor field effect transistor, the difference between the thickness of the P-type heavily doped ion implantation region and the thickness of the N-type heavily doped ion implantation region is 0 to 0.2 μm.

[0022] Optionally, in the metal oxide semiconductor field effect transistor, the width of the ion implantation region is 1.2 μm to 3 μm.

[0023] Optionally, in the metal oxide semiconductor field effect transistor, a width of the first region is 0.1 μm to 0.3 μm.

[0024] In a second aspect, an embodiment of the present application provides a method for preparing a metal oxide semiconductor field effect transistor, the method comprising:

[0025] forming an initial epitaxial layer on the upper surface of the substrate;

[0026] forming ion implantation regions at at least two first target regions spaced apart from each other on the upper surface of the initial epitaxial layer; the ion implantation regions extending from the upper surface of the initial epitaxial layer to the interior of the initial epitaxial layer along the direction of the substrate thickness;

[0027] Forming an inverted trapezoidal groove in a second target area between two adjacent ion implantation areas on the upper surface of the initial epitaxial layer, so as to obtain an epitaxial layer having an upper surface including at least two ion implantation areas spaced apart and an inverted trapezoidal groove disposed between the two adjacent ion implantation areas;

[0028] Depositing a first oxide layer on the upper surface of the inverted trapezoidal groove until the upper surface of the first oxide layer is flush with the upper surface of the ion implantation region to obtain a lower oxide layer;

[0029] An upper oxide layer is prepared on the upper surface of the lower oxide layer, the first region of the upper surface of the ion implantation region, and a fourth region between the upper surface of the lower oxide layer and the first region; the upper oxide layer and the lower oxide layer constitute a gate oxide layer;

[0030] A gate layer is prepared on the upper surface of the gate oxide layer; the width of the gate layer is the same as the width of the upper oxide layer;

[0031] A dielectric layer is prepared on the upper surface of the gate layer and the second region on the upper surface of the ion implantation region; the first region and the second region are adjacent to each other;

[0032] Prepare a source metal layer in the area other than the first area and the second area on the upper surface of the ion implantation region and on the upper surface of the dielectric layer;

[0033] A drain metal layer is prepared on the lower surface of the substrate to obtain the metal oxide semiconductor field effect transistor as described in any one of the above items.

[0034] The metal oxide semiconductor field effect transistor provided by the embodiment of the present application is provided with at least two ion implantation regions on the upper surface of the epitaxial layer, and an inverted trapezoidal groove is provided between adjacent ion implantation regions, the inverted trapezoidal groove is filled with the lower oxide layer in the gate oxide layer stacked on the upper surface of the epitaxial layer, and the upper oxide layer in the gate oxide layer is used to form a connection relationship between the gate oxide layer and the first area on the upper surface of the ion implantation region; in the metal oxide semiconductor field effect transistor, the gate oxide layer including the upper oxide layer and the lower oxide layer is used as a buried oxide layer between the epitaxial layer and the gate oxide layer, which can reduce the amount of charge between the gate and the drain in the metal oxide semiconductor field effect transistor, thereby reducing the switching loss of the metal oxide semiconductor field effect transistor; further, the embodiment of the present application uses the inverted trapezoidal groove structure to form an inclined and slowly changing structure at the corners of the gate oxide layer in contact with the epitaxial layer, which can reduce or even avoid the electric field concentration problem at the gate oxide corners in the metal oxide semiconductor field effect transistor, and improve the reliability of the metal oxide semiconductor field effect transistor.

[0035] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 1 ;

[0037] Figure 2 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 2 ;

[0038] Figure 3 It is a flow chart of the steps of a method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present application;

[0039] Figure 4 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 3 ;

[0040] Figure 5 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 4 ;

[0041] Figure 6 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 5 ;

[0042] Figure 7 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 6 ;

[0043] Figure 8 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 7 ;

[0044] Fig. 9 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 8 ;

[0045] Fig.10 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 9 ;

[0046] Fig.11 The cross-sectional structure of a metal oxide semiconductor field effect transistor provided in the embodiment of the present application is shown in FIG. Figure 10 .

[0047] Description of reference numerals:

[0048] 11-drain metal layer; 12-substrate; 13-epitaxial layer; 131-ion implantation area; 1311-heavily doped ion implantation area; 1312-ion implantation base area; 132-inverted trapezoidal trench; 14-gate oxide layer; 141-upper oxide layer; 142-lower oxide layer; 15-gate layer; 16-dielectric layer; 17-source metal layer; 171-ohmic metal layer; 172-front metal layer; 01-first area; 02-second area. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0050] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0051] Product Examples

[0052] The silicon carbide diode provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0053] Reference Figure 1 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 1 It should be noted that the cross-sectional structure diagram of the metal oxide semiconductor field effect transistor is a cross-sectional structure diagram along the thickness direction of the metal oxide semiconductor field effect transistor.

[0054] like Figure 1 As shown, the metal oxide semiconductor field effect transistor includes a drain metal layer 11, a substrate 12, an epitaxial layer 13, a gate oxide layer 14, a gate layer 15, a dielectric layer 16 and a source metal layer 17 which are stacked in sequence.

[0055] Specifically, the upper surface of the drain metal layer 11 is stacked with the lower surface of the epitaxial layer 13 , and the upper surface of the epitaxial layer 13 is sequentially stacked with the gate oxide layer 14 , the gate layer 15 , the dielectric layer 16 and the source metal layer 17 .

[0056] The epitaxial layer 13 includes at least two spaced ion implantation regions 131 and an inverted trapezoidal trench 132 disposed between two adjacent ion implantation regions 131. The ion implantation region 131 extends from the upper surface of the epitaxial layer 13 to the inside of the epitaxial layer 13 along the thickness direction of the MOSFET.

[0057] The gate oxide layer 14 includes an upper oxide layer 141 and a lower oxide layer 142 which are connected to each other. The lower oxide layer 142 is stacked on the upper surface of the inverted trapezoidal groove 132 and the upper surface of the lower oxide layer 142 is flush with the upper surface of the ion implantation area 131; the upper oxide layer 141 is stacked on the upper surface of the lower oxide layer 142, and the two ends of the upper oxide layer 141 extend and are stacked on the first area 01 on the upper surface of the ion implantation area 131 respectively.

[0058] The width of the gate layer 15 is the same as the width of the upper oxide layer 141 of the gate oxide layer 14, the width of the dielectric layer 16 is greater than the width of the gate layer 15, and the dielectric layer 16 is stacked on the upper surface of the gate layer 15 and the second region 02 on the upper surface of the ion implantation region 131; in the upper surface of the ion implantation region 131, the first region 01 and the second region 02 are adjacent.

[0059] Specifically, the drain metal layer 11 may include any one of nickel (Ni), titanium (Ti) and titanium-nickel alloy and copper (Cu) aluminum (Al) alloy. In some embodiments, the thickness of the drain metal layer 11 may be 0.5 μm to 1.5 μm. In the embodiment of the present application, the drain metal layer 11 serves as a back metal electrode layer connected to the substrate 12, providing good electrical contact for the metal oxide semiconductor field effect transistor, ensuring that the current can smoothly pass through the metal oxide semiconductor field effect transistor.

[0060] The substrate 12 is an N-type heavily doped (N+) silicon carbide substrate. Specifically, the substrate 12 can be any one of a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate, and a 3C-SiC single crystal substrate. As the bottom material of the entire metal oxide semiconductor field effect transistor, the substrate 12 provides physical support for the metal oxide semiconductor field effect transistor and ensures the structural integrity of the metal oxide semiconductor field effect transistor. In addition, the silicon carbide substrate has excellent thermal and electrical conductivity, so that the substrate 12 can effectively remove the heat generated inside the metal oxide semiconductor field effect transistor and improve the uniformity of the current distribution in the metal oxide semiconductor field effect transistor. The thickness of the substrate 12 can be determined according to the design requirements of the metal oxide semiconductor field effect transistor. For example, the thickness of the substrate 12 is 100 μm to 150 μm.

[0061] In addition, in the embodiment of the present application, the resistivity of the substrate 12 is 0.01 Ωcm to 0.03 Ωcm.

[0062] The epitaxial layer 13 is an N-type lightly doped (N-) silicon carbide epitaxial layer. The thickness of the epitaxial layer 13 is 5 μm to 100 μm. In some embodiments, the thickness of the epitaxial layer 13 can be in the range of one or any two of 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm and 10 μm. The ion doping concentration of the epitaxial layer 13 is 1×10 14 cm -3 Up to 5×10 16 cm -3 ; The ion doping concentration of the epitaxial layer 13 refers to the doping concentration of the nitrogen (N) element inside the epitaxial layer 13.

[0063] The upper surface of the epitaxial layer 13 refers to the surface of the epitaxial layer 13 away from the substrate 12; the upper surface of the epitaxial layer 13 includes at least two ion implantation regions 131 arranged at intervals, and an inverted trapezoidal groove 132 arranged between two adjacent ion implantation regions 131. The ion implantation region 131 extends from the upper surface of the epitaxial layer 13 to the inside of the epitaxial layer 13 along the direction of the thickness of the metal oxide semiconductor field effect transistor; the spacing between adjacent ion implantation regions 131 is equal.

[0064] In the embodiment of the present application, the spacing between adjacent ion implantation regions 131 can be determined according to the width of the inverted trapezoidal groove 132 disposed between two adjacent ion implantation regions 131, and the spacing between adjacent ion implantation regions 131 is greater than or equal to the maximum width of the inverted trapezoidal groove 132. It can be understood that the spacing between adjacent ion implantation regions 131 is greater than or equal to the width of the upper surface of the lower oxide layer 142 filled in the inverted trapezoidal groove 132.

[0065] It should be noted that two adjacent ion implantation regions 131 and the epitaxial layer 13 between the two adjacent ion implantation regions 131 constitute a junction field effect transistor (JFET) region; an inverted trapezoidal trench 132 is set between the two adjacent ion implantation regions 131, which can provide a specific stacking position for the gate oxide layer 14, so as to form a gate oxide layer 14 as a buried oxide layer between the epitaxial layer 13 and the gate oxide layer 14 of the metal oxide semiconductor field effect transistor, thereby achieving the purpose of reducing the switching loss of the metal oxide semiconductor field effect transistor and improving the reliability of the device.

[0066] In the embodiment of the present application, the longitudinal center line of the inverted trapezoidal groove 132 may coincide with the longitudinal center line of the epitaxial layer 13 between two adjacent ion implantation regions 131 ; the longitudinal center line refers to the center line along the direction of the thickness of the metal oxide semiconductor field effect transistor.

[0067] The depth of the inverse trapezoidal trench 132 is smaller than the depth of the ion implantation region 131 .

[0068] like Figure 1 As shown, the gate oxide layer 14 stacked on the upper surface of the epitaxial layer 13 includes an upper oxide layer 141 and a lower oxide layer 142 connected to each other.

[0069] Among them, the lower oxide layer 142 is stacked on the upper surface of the area where the inverted trapezoidal groove 132 is located in the epitaxial layer 13, that is, the lower oxide layer 142 is stacked on the upper surface of the inverted trapezoidal groove 132, and the lower oxide layer 142 is completely filled in the bottom of the cavity of the inverted trapezoidal groove 132, so that the upper surface of the lower oxide layer 142 is flush with the upper surface of the ion implantation area 131.

[0070] The upper oxide layer 141 is stacked on the upper surface of the lower oxide layer 142 , and both ends of the upper oxide layer 141 extend to and cover the first region 01 on the upper surface of the ion implantation region 131 .

[0071] It should be noted that if Figure 1 As shown, the upper oxide layer 141 simultaneously covers the upper surface of the lower oxide layer 142 , the first region 01 on the upper surface of the implantation region 131 , and the region between the upper surface of the lower oxide layer 142 and the first region 01 on the upper surface of the epitaxial layer 13 .

[0072] The ion implantation regions 131 respectively extended and covered by the two ends of the upper oxide layer 141 are the ion implantation regions 131 located on both sides of the inverted trapezoidal trench 132 .

[0073] In the embodiment of the present application, the lower oxide layer 142 in the gate oxide layer 14 is filled in the bottom of the cavity of the inverted trapezoidal groove 132, so that a sloped and gradually changing structure can be formed at the lower surface of the gate oxide layer 14 that is in direct contact with the epitaxial layer 13. The sloped and gradually changing structure can reduce or even avoid the problem of electric field concentration at the gate oxide corners in the metal oxide semiconductor field effect transistor, thereby improving the reliability of the metal oxide semiconductor field effect transistor.

[0074] like Figure 1 As shown, the gate layer 15 is stacked on the upper surface of the gate oxide layer 14 , and the upper surface of the gate oxide layer 14 is the upper surface of the upper oxide layer 141 ; in the embodiment of the present application, the width of the gate layer 15 is the same as the width of the upper oxide layer 141 .

[0075] The width of the dielectric layer 16 stacked on the upper surface of the gate layer 15 is greater than the width of the gate layer 15 , so that the dielectric layer 16 is stacked on the upper surface of the gate layer 15 and the second region 02 in the upper surface of the ion implantation region 131 at the same time.

[0076] The longitudinal center line of the dielectric layer 16 coincides with the longitudinal center line of the gate layer 15. The first region 01 and the second region 02 on the upper surface of the ion implantation region 131 are two adjacent regions on the upper surface of the ion implantation region 131. It can be understood that the first region 01 is a region on the upper surface of the ion implantation region 131 close to the inverted trapezoidal groove 132.

[0077] In the embodiment of the present application, the gate oxide layer 14 may include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), at least one of borophosphosilicate glass (BPSG), borosilicate glass (BSG), and phosphosilicate glass (PSG), and the material forming the upper oxide layer 141 is the same as the material forming the lower oxide layer 142.

[0078] The gate layer 15 includes polysilicon; the thickness of the gate layer 15 is 200nm to 2000nm; in some embodiments, the thickness of the gate layer 15 is in the range of one or any two of 200nm, 400nm, 600nm, 800nm, 1000nm, 1200nm, 1400nm, 1600nm, 1800nm ​​and 2000nm. It is understood that the thickness of the gate layer 15 refers to the thickness between the upper surface of the gate layer 15 and the upper surface of the gate oxide layer 14.

[0079] The dielectric layer 16 may include at least one of silicon dioxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, borosilicate glass, and phosphosilicate glass. The dielectric layer 16 may have a thickness of 0.5 μm to 2 μm; in some embodiments, the dielectric layer 16 may have a thickness of 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, and 2 μm, or any two of the range values.

[0080] The thickness of the dielectric layer 16 refers to the thickness between the upper surface of the dielectric layer 16 and the upper surface of the ion implantation region 131 .

[0081] The source metal layer 17 is stacked on the upper surface of the dielectric layer 16 and the upper surface of the ion implantation area 131 ; it can be understood that the upper surface of the ion implantation area 131 stacked with the source metal layer 17 refers to the area of ​​the upper surface of the epitaxial layer 13 excluding the area covered by the dielectric layer 16 .

[0082] In the embodiment of the present application, the source metal layer 17 includes any one of titanium-aluminum alloy, nickel-aluminum alloy and titanium-nickel-aluminum alloy.

[0083] The thickness of the source metal layer 17 is 2 μm to 5 μm. In some embodiments, the thickness of the source metal layer 17 may be in the range of one or any two of 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm and 5 μm. The thickness of the source metal layer 17 refers to the thickness between the upper surface of the source metal layer 17 and the upper surface of the ion implantation region 131.

[0084] In order to reduce the switching loss of the metal oxide semiconductor field effect transistor in the related art, a split gate structure is usually provided in the metal oxide semiconductor field effect transistor, and the overlapping area between the gate and the drain is reduced by using the split gate structure to reduce the switching loss of the metal oxide semiconductor field effect transistor. However, the split gate structure will cause a serious problem of electric field concentration at the corners of the gate oxide in the device, thereby reducing the reliability of the device. In the embodiment of the present application, at least two ion implantation regions 131 are provided on the upper surface of the epitaxial layer 13, and an inverted trapezoidal groove 132 is provided between adjacent ion implantation regions 131, and the lower oxide layer 142 in the gate oxide layer 14 stacked on the upper surface of the epitaxial layer 13 is used to fill the inverted trapezoidal groove 132, and the upper oxide layer 141 in the gate oxide layer 14 is used to form The connection relationship between the gate oxide layer 14 and the first area 01 on the upper surface of the ion implantation area 131; in the metal oxide semiconductor field effect transistor, the gate oxide layer 14 including the upper oxide layer 141 and the lower oxide layer 142 is used as a buried oxide layer between the epitaxial layer 13 and the gate oxide layer 14, which can reduce the amount of charge between the gate and the drain in the metal oxide semiconductor field effect transistor, thereby reducing the switching loss of the metal oxide semiconductor field effect transistor; further, the embodiment of the present application uses an inverted trapezoidal groove structure to form an inclined and slowly changing structure at the corners of the gate oxide layer 14 that contact the epitaxial layer 13, which can reduce or even avoid the electric field concentration problem at the gate oxide corners in the metal oxide semiconductor field effect transistor, and improve the reliability of the metal oxide semiconductor field effect transistor.

[0085] Optionally, the minimum angle between the sidewall of the inverted trapezoidal groove 132 and the bottom surface of the inverted trapezoidal groove 132 is 30° to 60°. In some embodiments, the minimum angle between the sidewall of the inverted trapezoidal groove 132 and the bottom surface of the inverted trapezoidal groove 132 can be a range of one or any two of 30°, 35°, 40°, 45°, 50°, 55° and 60°.

[0086] The bottom surface of the inverted trapezoidal groove 132 refers to the area formed between the lower ends of the two side walls of the inverted trapezoidal groove 132 .

[0087] The metal oxide semiconductor field effect transistor provided in the embodiment of the present application controls the minimum value of the angle between the side wall of the inverted trapezoidal groove 132 arranged on the upper surface of the epitaxial layer 13 and the bottom surface of the inverted trapezoidal groove 132 within the range of 30° to 60°, which can control the inclination degree of the inclined gradually changing structure formed at the corners in contact with the epitaxial layer 13 in the gate oxide layer 14, reduce the electric field concentration at the gate oxide corners in the metal oxide semiconductor field effect transistor, and thus improve the reliability of the metal oxide semiconductor field effect transistor.

[0088] Alternatively, if Figure 1 As shown, the bottom width w of the inverted trapezoidal trench 132 is 0.1 μm to 0.6 μm. In some embodiments, the bottom width w of the inverted trapezoidal trench 132 may be in the range of one or any two of 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm and 0.6 μm.

[0089] The metal oxide semiconductor field effect transistor provided in the embodiment of the present application controls the width of the bottom surface of the inverted trapezoidal groove 132 within the range of 0.1μm to 0.6μm, and can control the inverted trapezoidal groove 132 to be located between two adjacent ion implantation areas 131 without occupying the area where the ion implantation area 131 is located, which is beneficial to the realization of the function of the gate oxide layer 14 stacked on the upper surface of the inverted trapezoidal groove 132 and the realization of the function of the ion implantation area 131, and is beneficial to improving the overall performance of the metal oxide semiconductor field effect transistor while ensuring low switching loss and high reliability of the metal oxide semiconductor field effect transistor.

[0090] Optionally, refer to Figure 1 , the depth h of the inverse trapezoidal groove 132 is 0.1 μm to 0.4 μm. In some embodiments, the depth h of the inverse trapezoidal groove 132 may be in the range of one or any two of 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm and 0.4 μm.

[0091] Among them, the depth of the inverted trapezoidal groove 132 refers to the distance between the bottom surface and the top surface of the inverted trapezoidal groove 132; the top surface of the inverted trapezoidal groove 132 refers to the area formed between the upper ends of the two side walls of the inverted trapezoidal groove 132. It can be understood that the top surface of the inverted trapezoidal groove 132 coincides with the upper surface of the lower oxide layer 142.

[0092] The metal oxide semiconductor field effect transistor provided in the embodiment of the present application controls the depth of the bottom surface of the inverted trapezoidal groove 132 within the range of 0.1μm to 0.4μm, and can control the depth of the inverted trapezoidal groove 132 to be less than the depth of the ion implantation area 131, and without causing a significant increase in the thickness of the metal oxide semiconductor field effect transistor, ensure that the gate oxide layer 14 stacked on the upper surface of the inverted trapezoidal groove 132 has a sufficient thickness, which is conducive to the full realization of the function of the gate oxide layer 14 in reducing the amount of charge between the gate and the drain and the switching loss in the metal oxide semiconductor field effect transistor.

[0093] It can be understood that the thickness of the lower oxide layer 142 in the gate oxide layer 14 is equal to the depth of the inverted trapezoidal trench 132 .

[0094] Optionally, the thickness of the upper oxide layer 141 is 50 nm to 200 nm. In some embodiments, the thickness of the upper oxide layer 141 can be in the range of one or any two of 50 nm, 65 nm, 80 nm, 95 nm, 110 nm, 125 nm, 140 nm, 155 nm, 170 nm, 185 nm and 200 nm.

[0095] The thickness of the upper oxide layer 141 refers to the thickness between the upper surface of the upper oxide layer 141 and the upper surface of the ion implantation region 131. It can be understood that the minimum thickness of the gate oxide layer 14 is equal to the thickness of the upper oxide layer 141; the maximum thickness of the gate oxide layer 14 is equal to the sum of the thickness of the upper oxide layer 141 and the thickness of the lower oxide layer 142.

[0096] The metal oxide semiconductor field effect transistor provided in the embodiment of the present application controls the thickness of the upper oxide layer 141 within the range of 50 nm to 200 nm. While utilizing the upper oxide layer 141 in the gate oxide layer 14 to form a connection relationship between the gate oxide layer 14 and the first region 01 on the upper surface of the ion implantation region 131, the thickness of the metal oxide semiconductor field effect transistor is not significantly increased, thereby ensuring that the gate oxide layer 14 stacked on the upper surface of the inverted trapezoidal trench 132 has a sufficient thickness, which is conducive to fully realizing the function of the gate oxide layer 14 in reducing the amount of charge between the gate and the drain and the switching loss in the metal oxide semiconductor field effect transistor.

[0097] Optionally, refer to Figure 2 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 2 ,like Figure 2As shown, the source metal layer 17 includes an ohmic metal layer 171 and a front metal layer 172 ; the ohmic metal layer 171 is stacked on the upper surface of the ion implantation region 131 , and the front metal layer 172 is stacked on the upper surfaces of the ohmic metal layer 171 and the dielectric layer 16 .

[0098] The thickness of the ohmic metal layer 171 is less than the first target thickness of the dielectric layer 16 ; the first target thickness is the thickness between the upper surface of the dielectric layer 16 and the upper surface of the ion implantation region 131 .

[0099] The ohmic metal layer 171 is a P-type heavily doped (P+) ohmic metal layer, and the ohmic metal layer 171 may include, but is not limited to, titanium-aluminum alloy, nickel-aluminum alloy, titanium-nickel-aluminum alloy, etc. The front metal layer 172 may include, but is not limited to, aluminum, titanium-aluminum alloy, nickel-aluminum alloy, titanium-nickel-aluminum alloy, etc.

[0100] In the embodiment of the present application, the ohmic metal layer 171 stacked on the upper surface of the ion implantation area 131 means that: the ohmic metal layer 171 is stacked on the area of ​​the upper surface of the ion implantation area 131 that is not covered by the dielectric layer 16; the front metal layer 172 is stacked on the upper surface of the ohmic metal layer 171 and the upper surface of the dielectric layer 16.

[0101] Optionally, in some embodiments, the thickness of the ohmic metal layer 171 is 10nm to 500nm; specifically, the thickness of the ohmic metal layer 171 can be a range of one or any two of 10nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm and 500nm.

[0102] Optionally, in some embodiments, the second target thickness of the source metal layer 17 is 2 μm to 5 μm; specifically, the second target thickness of the source metal layer 17 is in the range of one or any two of 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm and 5 μm.

[0103] The second target thickness is the thickness between the upper surface of the source metal layer 17 and the upper surface of the ion implantation region 131 . The thickness of the front metal layer 172 is the difference between the second target thickness and the thickness of the ohmic metal layer 171 .

[0104] The metal oxide semiconductor field effect transistor provided in the embodiment of the present application, the source metal layer 17 includes an ohmic metal layer 171 and a front metal layer 172. The contact resistance between the silicon carbide semiconductor and the source metal layer 17 in the metal oxide semiconductor field effect transistor can be reduced by the ohmic metal layer 171, allowing the current to flow between the source metal layer 17 and the silicon carbide semiconductor with less hindrance; the current is drawn out from the source region by the front metal layer 172 and connected to the external circuit, so that the current can flow smoothly from the metal oxide semiconductor field effect transistor to the external circuit, thereby improving the electrical performance of the metal oxide semiconductor field effect transistor. In addition, the front metal layer 172 has high conductivity and good mechanical properties to ensure that the current can be efficiently transmitted to the external circuit and withstand the mechanical stress that the device may be subjected to during operation, thereby improving the reliability and service life of the metal oxide semiconductor field effect transistor.

[0105] Optionally, refer to Figure 1 and Figure 2 The ion implantation region 131 includes an ion implantation base region 1312 and a heavily doped ion implantation region 1311; the width of the heavily doped ion implantation region 1311 is smaller than the width of the ion implantation base region 1312, and the heavily doped ion implantation region 1311 extends from the upper surface of the epitaxial layer 13 along the direction of the thickness of the metal oxide semiconductor field effect transistor to the interior of the ion implantation base region 1312.

[0106] Among them, the heavily doped ion implantation area 1311 includes a P-type heavily doped ion implantation area and an N-type heavily doped ion implantation area; in the heavily doped ion implantation area 1311, both ends of the P-type heavily doped ion implantation area are respectively connected to the N-type heavily doped ion implantation area.

[0107] The first region 01 and the second region 02 are regions in the upper surface of the N-type heavily doped ion implantation region; the upper surface of the N-type heavily doped ion implantation region also includes a third region, on which a source metal layer 17 is stacked.

[0108] In the embodiment of the present application, the ion implantation base region 1312 is a P-type lightly doped (P-) region; the heavily doped ion implantation region 1311 is obtained after an ion implantation operation is performed on the basis of the ion implantation base region 1312; specifically, an ion implantation operation of aluminum elements is performed on the basis of the ion implantation base region 1312 to obtain a P-type heavily doped ion implantation region, and an ion implantation operation of nitrogen elements is performed on the basis of the ion implantation base region 1312 to obtain an N-type heavily doped ion implantation region.

[0109] It should be noted that the longitudinal center line of the ion implantation base region 1312 coincides with the longitudinal center line of the heavily doped ion implantation region 1311 , and the width of the heavily doped ion implantation region 1311 is smaller than the width of the ion implantation base region 1312 .

[0110] In the embodiment of the present application, the first region 01 and the second region 02 on the upper surface of the ion implantation region 131 are regions on the upper surface of the N-type heavily doped ion implantation region; in addition, the upper surface of the N-type heavily doped ion implantation region also includes a third region, on which a source metal layer 17 is stacked.

[0111] The third region is adjacent to the second region 02 , and the first region 01 , the second region 02 and the third region 03 together constitute the upper surface of the N-type heavily doped ion implantation region.

[0112] It can be understood that the upper surface of the N-type heavily doped ion implantation area is simultaneously covered with the upper oxide layer 141 in the gate oxide layer 14, the dielectric layer 16 and the source metal layer 17; in some embodiments, the upper surface of the N-type heavily doped ion implantation area is simultaneously covered with the upper oxide layer 141 in the gate oxide layer 14, the dielectric layer 16 and the ohmic metal layer 171 in the source metal layer 17.

[0113] The upper surface of the P-type lightly doped region is covered with a source metal layer 17 ; in some embodiments, the upper surface of the P-type lightly doped region is covered with an ohmic metal layer 171 in the source metal layer 17 .

[0114] Optionally, in some embodiments, the depth of the inverted trapezoidal trench 132 is less than the thickness of the N-type heavily doped ion implantation region.

[0115] Optionally, in some embodiments, the thickness of the P-type heavily doped ion implantation region is greater than or equal to the thickness of the N-type heavily doped ion implantation region.

[0116] In the embodiments of the present application, taking into account the different diffusion depths of different doping elements in silicon carbide semiconductors, the diffusion depth of the P-type doping element (aluminum) in the semiconductor material is slightly greater than that of the N-type doping element (nitrogen). In order to keep the ion doping concentration of the P-type heavily doped ion implantation region and the ion doping concentration of the N-type heavily doped ion implantation region at the same level, the thickness of the P-type heavily doped ion implantation region can be controlled to be greater than or equal to the thickness of the N-type heavily doped ion implantation region, so as to improve the electrical balance between the P-type heavily doped ion implantation region and the N-type heavily doped ion implantation region, thereby improving the electrical performance of the metal oxide semiconductor field effect transistor.

[0117] Optionally, in some embodiments, the difference between the thickness of the P-type heavily doped ion implantation region and the thickness of the N-type heavily doped ion implantation region is 0 to 0.2 μm. Specifically, the difference between the thickness of the P-type heavily doped ion implantation region and the thickness of the N-type heavily doped ion implantation region can be 0, 0.02 μm, 0.04 μm, 0.06 μm, 0.08 μm, 0.1 μm, 0.12 μm, 0.14 μm, 0.16 μm, 0.18 μm and 0.2 μm, or any two of the range values.

[0118] Optionally, in some embodiments, in each ion implantation region 131 , the sum of the widths of the N-type heavily doped ion implantation regions connected to both ends of the P-type heavily doped ion implantation region is greater than or equal to the width of the P-type heavily doped ion implantation region.

[0119] Among them, in the metal oxide semiconductor field effect transistor, the N-type heavily doped ion injection region serves as the electron injection region, and the P-type heavily doped ion injection region serves as the hole injection region. Since the mobility of electrons is usually higher than the mobility of holes, the N-type heavily doped ion injection region will be subjected to a higher current density during the operation of the metal oxide semiconductor field effect transistor; the present application controls the sum of the widths of the N-type heavily doped ion injection regions connected to the two ends of the P-type heavily doped ion injection region to be greater than or equal to the width of the P-type heavily doped ion injection region, which can provide the metal oxide semiconductor field effect transistor with a larger current channel and heat dissipation area, reduce the resistance and heat generation of the N-type heavily doped ion injection region, and thereby improve the electrical performance of the metal oxide semiconductor field effect transistor.

[0120] Optionally, in some embodiments, the width of the ion implantation region 131 is 1.2 μm to 3 μm. Specifically, the width of the ion implantation region 131 may be in the range of one or any two of 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm and 3 μm.

[0121] The width of the ion implantation region 131 refers to the width of the overlapping region between the ion implantation region 131 and the upper surface of the epitaxial layer 13 ; the width of the ion implantation region 131 is equal to the width of the ion implantation base region 1312 in the ion implantation region 131 .

[0122] In the embodiment of the present application, the width of the ion implantation region 131 is controlled within the range of 1.2 μm to 3 μm, so that the depletion region of the metal oxide semiconductor field effect transistor can be controlled within a suitable width range to prevent the punch-through effect in high voltage and high current application scenarios; in addition, the width of the ion implantation region 131 is controlled within the range of 1.2 μm to 3 μm, so that the threshold voltage of the metal oxide semiconductor field effect transistor can be controlled within a preset range, which is beneficial to improving the stability and consistency of the threshold voltage of the metal oxide semiconductor field effect transistor, thereby improving the performance and reliability of the metal oxide semiconductor field effect transistor.

[0123] Optionally, the width of the first region 01 is 0.1 μm to 0.3 μm. Specifically, the width of the first region 01 may be in the range of one or any two of 0.1 μm, 0.12 μm, 0.14 μm, 0.16 μm, 0.18 μm, 0.2 μm, 0.22 μm, 0.24 μm, 0.26 μm, 0.28 μm and 0.3 μm.

[0124] It can be understood that the width of the first region 01 is equal to the overlapping width between the gate oxide layer 14 and the N-type heavily doped ion implantation region in the ion implantation region 131; the embodiment of the present application controls the width of the first region 01 within the range of 0.1μm to 0.3μm, which is beneficial to improving the performance stability and reliability of the metal oxide semiconductor field effect transistor.

[0125] In summary, the metal oxide semiconductor field effect transistor provided in the embodiment of the present application is provided with at least two ion implantation regions 131 on the upper surface of the epitaxial layer 13, and an inverted trapezoidal groove 132 is provided between adjacent ion implantation regions 131, and the inverted trapezoidal groove 132 is filled with the lower oxide layer 142 in the gate oxide layer 14 stacked on the upper surface of the epitaxial layer 13, and the upper oxide layer 141 in the gate oxide layer 14 is used to form a connection relationship between the gate oxide layer 14 and the first region 01 on the upper surface of the ion implantation region 131; in the metal oxide semiconductor field effect transistor, the upper oxide layer 142 is provided to fill the inverted trapezoidal groove 132, and the upper oxide layer 141 in the gate oxide layer 14 ... The gate oxide layer 14 of the lower oxide layer 142 serves as a buried oxide layer between the epitaxial layer 13 and the gate oxide layer 14, which can reduce the amount of charge between the gate and the drain in the metal oxide semiconductor field effect transistor, thereby reducing the switching loss of the metal oxide semiconductor field effect transistor; further, the embodiment of the present application uses an inverted trapezoidal groove structure to form an inclined and slowly changing structure at the corners of the gate oxide layer 14 that contacts the epitaxial layer 13, which can reduce or even avoid the electric field concentration problem at the gate oxide corners in the metal oxide semiconductor field effect transistor, and improve the reliability of the metal oxide semiconductor field effect transistor.

[0126] Method Embodiment

[0127] Reference Figure 3 , shows a flowchart of a method for preparing a metal oxide semiconductor field effect transistor provided in an embodiment of the present application, the method comprising steps S101 to S109:

[0128] Step S101 : forming an initial epitaxial layer on the upper surface of a substrate.

[0129] Specifically, refer to Figure 4 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 3, epitaxial growth is performed on the upper surface of the substrate 12 to obtain an initial epitaxial layer 13 ′ stacked on the upper surface of the substrate 12 .

[0130] Among them, the substrate 12 is an N-type heavily doped silicon carbide substrate, specifically, the substrate 12 can be any one of a 4H-SiC single crystal substrate, a 6H-SiC single crystal substrate and a 3C-SiC single crystal substrate; in steps S101 to S108, the thickness of the substrate 12 is 320μm to 380μm; the resistivity of the substrate 12 is 0.01Ωcm to 0.03Ωcm.

[0131] The initial epitaxial layer 13' is an N-type lightly doped silicon carbide epitaxial layer, and the thickness of the initial epitaxial layer 13' is 5 μm to 100 μm; the ion doping concentration of the initial epitaxial layer 13' is 1×10 14 cm -3 Up to 5×10 16 cm -3 The ion doping concentration of the initial epitaxial layer 13' refers to the doping concentration of the nitrogen element inside the initial epitaxial layer 13'.

[0132] Step S102 , forming ion implantation regions at at least two first target regions spaced apart from each other on the upper surface of the initial epitaxial layer.

[0133] The ion implantation region extends from the upper surface of the initial epitaxial layer to the interior of the initial epitaxial layer along the direction of the substrate thickness. The first target region is the region where the ion implantation region is located.

[0134] Specifically, refer to Figure 5 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 4 First, the upper surface of the initial epitaxial layer 13' is cleaned, and an ion implantation mask layer (PETEOS layer) is deposited on the upper surface of the initial epitaxial layer 13'; wherein the thickness of the PETEOS layer is 1 μm to 5 μm, and the PETEOS layer includes at least one of silicon oxide and polysilicon.

[0135] Then, photoresist is spin-coated on the upper surface of the PETEOS layer, and an ion implantation window corresponding to the first target area is formed through photolithography and etching processes.

[0136] Then, the photoresist is removed, and the PETEOS layer is used as a mask to perform the first ion implantation operation, and the PETEOS layer is removed to form an original ion implantation area extending from the upper surface of the initial epitaxial layer 13' to the inside of the initial epitaxial layer 13'; wherein the first ion implantation operation is an aluminum ion implantation operation, and the original ion implantation area is a P-type lightly doped ion implantation area; the width of the original ion implantation area on the upper surface of the initial epitaxial layer 13' is 1.2μm to 3μm.

[0137] Then, a PETEOS layer is deposited on the upper surface of the initial epitaxial layer 13', and photoresist is spin-coated on the upper surface of the PETEOS layer, and an ion implantation window corresponding to the P-type heavily doped ion implantation area in the heavily doped ion implantation area 1311 is formed by photolithography and etching processes; wherein the thickness of the PETEOS layer is 1 μm to 5 μm, and the PETEOS layer includes at least one of silicon oxide and polycrystalline silicon.

[0138] Then, the photoresist is removed, and the PETEOS layer is used as a mask to perform a second ion implantation operation, and the PETEOS layer is removed to form a P-type heavily doped ion implantation area in the heavily doped ion implantation area 1311; the second ion implantation operation is an aluminum ion implantation operation.

[0139] Then, a PETEOS layer is deposited on the upper surface of the initial epitaxial layer 13', and photoresist is spin-coated on the upper surface of the PETEOS layer, and an ion implantation window corresponding to the N-type heavily doped ion implantation area in the heavily doped ion implantation area 1311 is formed by photolithography and etching processes; wherein the thickness of the PETEOS layer is 1 μm to 5 μm, and the PETEOS layer includes at least one of silicon oxide and polycrystalline silicon.

[0140] Then, the photoresist is removed, and the PETEOS layer is used as a mask to perform a third ion implantation operation, and the PETEOS layer is removed to form an N-type heavily doped ion implantation area in the heavily doped ion implantation area 1311, thereby obtaining a heavily doped ion implantation area 1311 composed of a P-type heavily doped ion implantation area and an N-type heavily doped ion implantation area; wherein the third ion implantation operation is a nitrogen ion implantation operation.

[0141] Finally, a carbon film is prepared on the upper surface of the initial epitaxial layer 13' as a high-temperature activation protective layer; the impurity ions injected by the first ion implantation operation, the second ion implantation operation and the third ion implantation operation are activated at high temperature, and the carbon film is removed after activation to obtain an ion implantation area 131 including an ion implantation base area 1312 and a heavily doped ion implantation area 1311; wherein the carbon film is prepared by photoresist carbonization or radio frequency sputtering, the carbon film thickness is 0.05μm to 2μm, and the temperature of high-temperature activation is 1500℃ to 1900℃.

[0142] It should be noted that the upper part of the original ion implantation area is formed into a heavily doped ion implantation area 1311 including two N-type heavily doped ion implantation areas and one P-type heavily doped ion implantation area through the second ion implantation operation and the third ion implantation operation, and the part of the original ion implantation area outside the heavily doped ion implantation area 1311 is the ion implantation base area 1312; the thickness of the original ion implantation area is equal to the sum of the thicknesses of the heavily doped ion implantation area 1311 and the ion implantation base area 1312.

[0143] In each heavily doped ion implantation region 1311, two ends of the P-type heavily doped ion implantation region are respectively connected to the N-type heavily doped ion implantation region, the width of the heavily doped ion implantation region 1311 is smaller than the width of the ion implantation base region 1312, and the upper surface of the initial epitaxial layer 13' of the heavily doped ion implantation region 1311 extends to the interior of the ion implantation base region 1312 along the direction of the thickness of the metal oxide semiconductor field effect transistor.

[0144] In some embodiments, the thickness of the P-type heavily doped ion implantation region is greater than or equal to the thickness of the N-type heavily doped ion implantation region.

[0145] In some embodiments, the difference between the thickness of the P-type heavily doped ion implantation region and the thickness of the N-type heavily doped ion implantation region is 0 to 0.2 μm.

[0146] The intervals between adjacent ion implantation regions 131 in the upper surface of the initial epitaxial layer 13 ′ are equal.

[0147] In addition, the doping concentrations of the ion implantation base region 1312 and the heavily doped ion implantation region 1311 in the ion implantation region 131 may be determined according to actual requirements, and the embodiments of the present application do not limit this.

[0148] Step S103, forming an inverted trapezoidal groove in a second target area between two adjacent ion implantation areas in the upper surface of the initial epitaxial layer, to obtain an epitaxial layer having an upper surface including at least two spaced ion implantation areas and an inverted trapezoidal groove between the two adjacent ion implantation areas.

[0149] The second target region is the region where the upper surface of the initial epitaxial layer 13' is located between two adjacent ion implantation regions 131. The maximum value of the width of the inverted trapezoidal groove 132 formed in the second target region is less than or equal to the width of the second target region; the maximum value of the width of the inverted trapezoidal groove 132 is equal to the width of the top surface of the inverted trapezoidal groove 132.

[0150] Specifically, in the case where at least two ion implantation regions 131 are spaced apart on the upper surface of the initial epitaxial layer 13' through step S102, etching can be performed at the second target region along the longitudinal center line of the second target region between the two adjacent ion implantation regions 131 by etching processes such as growth mask medium, photolithography, dry etching, surface oxidation, and selective etching to obtain an inverted trapezoidal groove 132 disposed between the two adjacent ion implantation regions 131, thereby obtaining an epitaxial layer 13 having an upper surface including at least two spaced apart ion implantation regions 131 and an inverted trapezoidal groove 132 disposed between the two adjacent ion implantation regions 131, with reference to Figure 6, showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 5 .

[0151] In the embodiment of the present application, the longitudinal center line of the second target area coincides with the longitudinal center line of the inverted trapezoidal groove 132 .

[0152] In some embodiments, the minimum value of the angle between the sidewall of the inverted trapezoidal trench 132 and the bottom surface of the inverted trapezoidal trench 132 is 30° to 60°.

[0153] In some embodiments, the width of the bottom surface of the inverted trapezoidal trench 132 is 0.1 μm to 0.6 μm.

[0154] In some embodiments, the depth of the inverse trapezoidal trench 132 is 0.1 μm to 0.4 μm.

[0155] Step S104 , depositing a first oxide layer on the upper surface of the inverted trapezoidal trench until the upper surface of the first oxide layer is flush with the upper surface of the ion implantation region, thereby obtaining a lower oxide layer.

[0156] Specifically, first, a sacrificial oxide layer of good quality is formed on the upper surface of the epitaxial layer 13 after step S103 by using a dry oxygen thermal oxidation method, and the interface damage caused by ion implantation and dry etching is removed by wet etching of the sacrificial oxide layer; then, after the sacrificial oxide layer is removed, Figure 7 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 6 A first oxide layer is deposited on the upper surface of the inverted trapezoidal groove 132 by combining dry oxygen thermal oxidation, deposition and annealing until the upper surface of the first oxide layer is flush with the upper surface of the ion implantation area 131 to obtain a lower oxide layer 142, wherein the temperature of the dry oxygen thermal oxidation is 1000° C. to 1500° C.

[0157] The thickness of the lower oxide layer 142 is equal to the depth of the inverted trapezoidal trench 132 .

[0158] Step S105, preparing an upper oxide layer on the upper surface of the lower oxide layer, a first region on the upper surface of the ion implantation region, and a fourth region between the upper surface of the lower oxide layer and the first region; the upper oxide layer and the lower oxide layer constitute a gate oxide layer.

[0159] Specifically, first, a second oxide layer is deposited on the upper surface of the epitaxial layer 13 processed in step S104 by a method combining dry oxygen thermal oxidation, deposition and annealing; then, the upper surface of the lower oxide layer 142 in the upper surface of the epitaxial layer 13, the first region 01 on the upper surface of the ion implantation region 131, and the second oxide layer on the region other than the fourth region between the upper surface of the lower oxide layer 142 and the first region 01 are etched away to obtain an upper oxide layer 141 which is stacked on the upper surface of the lower oxide layer 142 and whose two ends extend respectively and cover the first region 01 on the upper surface of the ion implantation region 131; refer to Figure 8 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 7 .

[0160] The temperature of dry oxygen thermal oxidation is 1000°C to 1500°C.

[0161] The upper oxide layer 141 and the lower oxide layer 142 constitute the gate oxide layer 14 .

[0162] In some embodiments, the thickness of the upper oxide layer 141 is 50 nm to 200 nm.

[0163] In some embodiments, the width of the first region 01 is 0.1 μm to 0.3 μm.

[0164] The gate oxide layer 14 may include silicon dioxide, silicon nitride, silicon oxynitride (SiO x N y ), at least one of borophosphosilicate glass, borosilicate glass, and phosphosilicate glass, and the material forming the upper oxide layer 141 is the same as the material forming the lower oxide layer 142.

[0165] Step S106, preparing a gate layer on the upper surface of the gate oxide layer; the width of the gate layer is the same as the width of the upper oxide layer.

[0166] Specifically, first, polysilicon is deposited on the upper surface of the gate oxide layer 14 and the upper surface of the epitaxial layer 13 processed in step S105 by a low pressure chemical vapor deposition (LPCVD) process; then, the polysilicon on the upper surface of the epitaxial layer 13 processed in step S105 is etched to obtain a gate layer 15 stacked on the upper surface of the gate oxide layer 14; Fig. 9 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 8 .

[0167] The gate layer 15 includes polysilicon; the thickness of the gate layer 15 is 200 nm to 2000 nm, and the thickness of the gate layer 15 refers to the thickness between the upper surface of the gate layer 15 and the upper surface of the gate oxide layer 14 .

[0168] Step S107 , preparing a dielectric layer on the upper surface of the gate layer and a second region on the upper surface of the ion implantation region; the first region and the second region are adjacent to each other.

[0169] Specifically, first, an original dielectric layer is deposited on the upper surface of the gate layer 15 and the upper surface of the epitaxial layer 13 processed in step S106 by a deposition process; then, the original dielectric layer on the upper surface of the epitaxial layer 13 outside the second region 02 is etched to obtain a dielectric layer 16; Fig.10 , showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 9 The width of the dielectric layer 16 is greater than the width of the gate layer 15 , and the dielectric layer 16 is stacked on the upper surface of the gate layer 15 and the second region 02 on the upper surface of the ion implantation region 131 .

[0170] The dielectric layer 16 may include at least one of silicon dioxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, borosilicate glass, and phosphosilicate glass. The dielectric layer 16 may have a thickness of 0.5 μm to 2 μm, and the thickness of the dielectric layer 16 refers to the thickness between the upper surface of the dielectric layer 16 and the upper surface of the ion implantation region 131.

[0171] The longitudinal center line of the dielectric layer 16 coincides with the longitudinal center line of the gate layer 15. The first region 01 and the second region 02 on the upper surface of the ion implantation region 131 are two adjacent regions on the upper surface of the ion implantation region 131. It can be understood that the first region 01 is a region on the upper surface of the ion implantation region 131 close to the inverted trapezoidal groove 132.

[0172] In some embodiments, the first region 01 and the second region 02 are regions in the upper surface of the N-type heavily doped ion implantation region.

[0173] Step S108 , preparing a source metal layer on the upper surface of the ion implantation region except the first region and the second region and on the upper surface of the dielectric layer.

[0174] Specifically, first, an ohmic metal layer 171 is prepared on the upper surface of the ion implantation region 131 except the first region 01 and the second region 02 by sputtering; then, a front metal layer 172 is prepared on the upper surface of the ohmic metal layer 171 and the upper surface of the dielectric layer 16 by sputtering, so as to obtain a source metal layer 17 including the ohmic metal layer 171 and the front metal layer 172; Fig.11, showing a schematic cross-sectional structure of a metal oxide semiconductor field effect transistor provided in an embodiment of the present application Figure 10 The ohmic metal layer 171 is stacked on the upper surface of the ion implantation region 131 , and the front metal layer 172 is stacked on the upper surfaces of the ohmic metal layer 171 and the dielectric layer 16 .

[0175] Among them, the source metal layer 17 is stacked on the upper surface of the dielectric layer 16 and the upper surface of the ion implantation area 131; it can be understood that the upper surface of the ion implantation area 131 stacked with the source metal layer 17 refers to the area of ​​the upper surface of the epitaxial layer 13 except the area covered by the dielectric layer 16.

[0176] In the embodiment of the present application, the source metal layer 17 includes any one of titanium-aluminum alloy, nickel-aluminum alloy and titanium-nickel-aluminum alloy.

[0177] The thickness of the source metal layer 17 is 2 μm to 5 μm, and the thickness of the source metal layer 17 refers to the thickness between the upper surface of the source metal layer 17 and the upper surface of the ion implantation region 131 .

[0178] In some embodiments, the thickness of the ohmic metal layer 171 is 10 nm to 500 nm.

[0179] In some embodiments, the upper surface of the N-type heavily doped ion implantation region further includes a third region, on which the source metal layer 17 is stacked. In some embodiments, the upper surface of the N-type heavily doped ion implantation region further includes a third region, on which the ohmic metal layer 171 in the source metal layer 17 is stacked.

[0180] The thickness of the ohmic metal layer 171 is less than the first target thickness of the dielectric layer 16 ; the first target thickness is the thickness between the upper surface of the dielectric layer 16 and the upper surface of the ion implantation region 131 .

[0181] The ohmic metal layer 171 is a P-type heavily doped ohmic metal layer, and the ohmic metal layer 171 may include but is not limited to: titanium aluminum alloy, nickel aluminum alloy, titanium nickel aluminum alloy, etc. The front metal layer 172 may include but is not limited to: aluminum, titanium aluminum alloy, nickel aluminum alloy, titanium nickel aluminum alloy, etc.

[0182] In the embodiment of the present application, the ohmic metal layer 171 stacked on the upper surface of the ion implantation area 131 means that: the ohmic metal layer 171 is stacked on the area of ​​the upper surface of the ion implantation area 131 that is not covered by the dielectric layer 16; the front metal layer 172 is stacked on the upper surface of the ohmic metal layer 171 and the upper surface of the dielectric layer 16.

[0183] Step S109: preparing a drain metal layer on the lower surface of the substrate to obtain a metal oxide semiconductor field effect transistor.

[0184] Specifically, the lower surface of the substrate 12 is thinned by at least one of mechanical grinding, chemical etching, and inductively coupled plasma etching (ICP) technology to reduce the thickness of the substrate 12 to 100 μm to 150 μm, and a drain metal layer 11 is formed on the lower surface of the substrate 12 by a sputtering process, referring to Figure 1 and Figure 2 .

[0185] The drain metal layer 11 may include any one of nickel, titanium, a titanium-nickel alloy, and a copper-aluminum alloy. In some embodiments, the drain metal layer 11 may have a thickness of 0.5 μm to 1.5 μm.

[0186] It is understandable that the method for preparing the metal oxide semiconductor field effect transistor provided in the embodiment of the present application can be used to prepare the metal oxide semiconductor field effect transistor as described in any of the above items, and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0187] It should be noted that, in this article, the term "comprises", "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0188] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A metal oxide semiconductor field effect transistor, characterized in that: The metal oxide semiconductor field effect transistor comprises a drain metal layer, a substrate, an epitaxial layer, a gate oxide layer, a gate layer, a dielectric layer and a source metal layer which are stacked in sequence; The upper surface of the epitaxial layer includes at least two ion implantation regions arranged at intervals, and an inverted trapezoidal groove arranged between two adjacent ion implantation regions; the ion implantation region extends from the upper surface of the epitaxial layer to the inside of the epitaxial layer along the direction of the thickness of the metal oxide semiconductor field effect transistor; The gate oxide layer comprises an upper oxide layer and a lower oxide layer connected to each other; the lower oxide layer is stacked on the upper surface of the inverted trapezoidal groove and the upper surface of the lower oxide layer is flush with the upper surface of the ion implantation region; the upper oxide layer is stacked on the upper surface of the lower oxide layer and the two ends of the upper oxide layer extend and cover the first area of ​​the upper surface of the ion implantation region respectively; The width of the gate layer is the same as that of the upper oxide layer; the width of the dielectric layer is greater than that of the gate layer, and the dielectric layer is stacked on the upper surface of the gate layer and the second area on the upper surface of the ion implantation area; the first area and the second area are adjacent.

2. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The minimum value of the angle between the side wall of the inverted trapezoidal groove and the bottom surface of the inverted trapezoidal groove is 30° to 60°.

3. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The width of the bottom surface of the inverted trapezoidal groove is 0.1 μm to 0.6 μm.

4. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The depth of the inverted trapezoidal groove is 0.1 μm to 0.4 μm.

5. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The thickness of the upper oxide layer is 50nm to 200nm.

6. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The source metal layer includes an ohmic metal layer and a front metal layer; the ohmic metal layer is stacked on the upper surface of the ion implantation region, and the front metal layer is stacked on the upper surfaces of the ohmic metal layer and the dielectric layer; The thickness of the ohmic metal layer is less than the first target thickness of the dielectric layer; the first target thickness is the thickness between the upper surface of the dielectric layer and the upper surface of the ion implantation region.

7. The metal oxide semiconductor field effect transistor according to claim 6, characterized in that: The thickness of the ohmic metal layer is 10 nm to 500 nm; the second target thickness of the source metal layer is 2 μm to 5 μm; the second target thickness is the thickness between the upper surface of the source metal layer and the upper surface of the ion implantation region.

8. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The ion implantation region includes an ion implantation base region and a heavily doped ion implantation region; the width of the heavily doped ion implantation region is smaller than the width of the ion implantation base region, and the heavily doped ion implantation region extends from the upper surface of the epitaxial layer along the direction of the thickness of the metal oxide semiconductor field effect transistor to the interior of the ion implantation base region; Wherein, the heavily doped ion implantation region includes a P-type heavily doped ion implantation region and an N-type heavily doped ion implantation region; in the heavily doped ion implantation region, both ends of the P-type heavily doped ion implantation region are respectively connected to the N-type heavily doped ion implantation region; The first region and the second region are regions in the upper surface of the N-type heavily doped ion implantation region; the upper surface of the N-type heavily doped ion implantation region also includes a third region, and the source metal layer is stacked on the third region.

9. The metal oxide semiconductor field effect transistor according to claim 8, characterized in that: The thickness of the P-type heavily doped ion implantation region is greater than or equal to the thickness of the N-type heavily doped ion implantation region.

10. The metal oxide semiconductor field effect transistor according to claim 9, characterized in that: A difference between a thickness of the P-type heavily doped ion implantation region and a thickness of the N-type heavily doped ion implantation region is 0 to 0.2 μm.

11. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The width of the ion implantation region is 1.2 μm to 3 μm.

12. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The width of the first region is 0.1 μm to 0.3 μm.

13. A method for preparing a metal oxide semiconductor field effect transistor, characterized in that: The method comprises: forming an initial epitaxial layer on the upper surface of the substrate; forming ion implantation regions at at least two first target regions spaced apart from each other on the upper surface of the initial epitaxial layer; the ion implantation regions extending from the upper surface of the initial epitaxial layer to the interior of the initial epitaxial layer along the direction of the substrate thickness; Forming an inverted trapezoidal groove in a second target area between two adjacent ion implantation areas on the upper surface of the initial epitaxial layer, so as to obtain an epitaxial layer having an upper surface including at least two ion implantation areas spaced apart and an inverted trapezoidal groove disposed between the two adjacent ion implantation areas; Depositing a first oxide layer on the upper surface of the inverted trapezoidal groove until the upper surface of the first oxide layer is flush with the upper surface of the ion implantation region to obtain a lower oxide layer; An upper oxide layer is prepared on the upper surface of the lower oxide layer, the first region of the upper surface of the ion implantation region, and a fourth region between the upper surface of the lower oxide layer and the first region; the upper oxide layer and the lower oxide layer constitute a gate oxide layer; A gate layer is prepared on the upper surface of the gate oxide layer; the width of the gate layer is the same as the width of the upper oxide layer; A dielectric layer is prepared on the upper surface of the gate layer and the second region on the upper surface of the ion implantation region; the first region and the second region are adjacent to each other; Prepare a source metal layer in the area other than the first area and the second area on the upper surface of the ion implantation region and on the upper surface of the dielectric layer; A drain metal layer is prepared on the lower surface of the substrate to obtain the metal oxide semiconductor field effect transistor as claimed in any one of claims 1 to 12.

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