Semiconductor structure and manufacturing method thereof
By designing a gate structure with an inverted trapezoidal profile and obtuse angle and forming an oxide layer thereon, the oxide layer collapse and leakage current problems of traditional trench metal oxide semiconductor field effect transistors when applying voltage is solved, and the stability of the structure is improved.
Patent Information
- Application Number
- CN202311367965.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-04
- Filing Date
- 2023-10-20
- Publication Date
- 2025-04-11
AI Technical Summary
When a traditional trench metal oxide semiconductor field effect transistor applies a gate-source voltage, it is easy to cause the gate oxide layer to collapse and leakage current, thereby causing the component to fail.
A semiconductor structure is designed, the bottom surface width of the gate structure is smaller than the top surface width, the cross-sectional profile is inverted trapezoid, and obtuse angles are sandwiched between the side walls of the trench and the bottom surface, thereby enhancing the stability of the structure by forming the first and second oxide layers.
By reducing the electric field concentration when the gate voltage is applied, the collapse of the gate oxide layer and leakage current are avoided, and the stability of the semiconductor structure is improved. It is suitable for the application of trench metal oxide semiconductor field-effect transistors.
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Figure CN119815880A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art
[0002] Among various types of power metal-oxide-semiconductor field-effect transistors (power MOSFET), trench MOS structure can realize a vertical channel to avoid the formation of an equivalent junction gate field-effect transistor (JFET), thereby reducing on-state resistance. Therefore, trench MOS is one of the focuses of research and development.
[0003] However, when a gate-source voltage is applied to a conventional trench MOSFET, the right angle of the gate causes the electric field to concentrate, which can easily lead to gate oxide breakdown and leakage current, causing device failure. Summary of the invention
[0004] A technical aspect of the present invention is a semiconductor structure.
[0005] According to some embodiments of the present invention, a semiconductor structure includes a substrate, a gate structure, a first oxide layer and a second oxide layer. The substrate has a groove. An obtuse angle is formed between the inclined surface and the bottom surface of the groove. The gate structure is located in the groove. The width of the bottom surface of the gate structure is less than the width of the top surface of the gate structure. The cross-sectional profile of the gate structure is an inverted trapezoid. The first oxide layer is located between the gate structure and the substrate. The second oxide layer is located on the top surface of the gate structure.
[0006] In some embodiments of the present invention, the gate structure has a sidewall adjacent to the top surface and the bottom surface, and an obtuse angle is formed between the bottom surface and the sidewall of the gate structure.
[0007] In some embodiments of the present invention, an obtuse angle between a bottom surface and a sidewall of the gate structure is in a range of 108 degrees to 118 degrees.
[0008] Another technical aspect of the present invention is a method for manufacturing a semiconductor structure.
[0009] According to some embodiments of the present invention, a method for manufacturing a semiconductor structure includes forming a hard mask structure on a substrate, wherein the hard mask structure has an opening, and the side wall of the hard mask structure facing the opening is stepped; etching the substrate from the opening through the hard mask structure to form a groove, wherein the groove has a side wall and a bottom surface, and the side wall is stepped; flattening the side wall of the groove so that it and the bottom surface are oxidized so that an obtuse angle is formed between the side wall and the bottom surface; forming a first oxide layer on the side wall and the bottom surface of the groove; forming a gate structure on the first oxide layer in the groove, wherein the width of the bottom surface of the gate structure is less than the width of the top surface of the gate structure, and the cross-sectional profile of the gate structure is an inverted trapezoid; and forming a second oxide layer on the gate structure.
[0010] In some embodiments of the present invention, forming a hard mask structure on a substrate includes the following steps: (a) using a photomask to form a photoresist layer on a film stack structure, wherein the film stack structure has a plurality of first hard mask layers and a plurality of second hard mask layers stacked in sequence, and a first portion of the uppermost second hard mask layer is exposed from the photoresist layer; (b) removing the first portion of the uppermost second hard mask layer and a first portion of one of the lower first hard mask layers; (c) removing the photoresist layer; (d) moving the photomask displacement in a horizontal direction and forming a photoresist layer on the film stack structure again, so that the second hard mask layer (e) removing the second portion of the second hard mask layer and the second portion of one of the first hard mask layers thereunder and simultaneously removing the first portion of the other of the second hard mask layer and the first portion of one of the first hard mask layers thereunder; (f) removing the photoresist layer again; (g) repeating steps (d) to (f) until the first portion of the lowermost second hard mask layer is exposed from the photoresist layer; and (h) removing the first portion of the lowermost second hard mask layer, so that the film stack structure defines a hard mask structure.
[0011] In some embodiments of the present invention, the displacement is in the range of 0.2 microns to 0.63 microns.
[0012] In some embodiments of the present invention, the thickness of the photoresist layer is greater than the thickness of the film stack structure plus 1 micron.
[0013] In some embodiments of the present invention, the hard mask structure further has another sidewall opposite to the sidewall and facing away from the opening, and a distance between the sidewall and the other sidewall is in a range of 0.5 micrometers to 5.5 micrometers.
[0014] In some embodiments of the present invention, forming a hard mask structure on a semiconductor substrate includes forming a plurality of first hard mask layers and a plurality of second hard mask layers stacked in sequence, and the number of the first hard mask layers and the number of the second hard mask layers are the same and are a positive integer less than or equal to 5.
[0015] In some embodiments of the present invention, the sum of the thickness of any one of the first hard mask layers and the thickness of any one of the second hard mask layers is in a range between 0.05 micrometers and 5.05 micrometers.
[0016] In the above-mentioned embodiment of the present invention, since the semiconductor structure has a gate structure with a trapezoidal cross-sectional profile, and the width of the bottom surface of the gate structure is smaller than the width of the top surface of the gate structure, the electric field concentrated at the bottom corner of the gate structure when the gate voltage is applied to the semiconductor structure can be weakened, thereby avoiding gate oxide breakdown and the leakage current caused by it. The semiconductor structure can be applied to a trench metal-oxide-semiconductor field-effect transistor (trench MOSFET) to improve its stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A cross-sectional view of a semiconductor structure according to an embodiment of the present invention is shown.
[0018] Figures 2 to 11 Draw Figure 1 A cross-sectional view of a semiconductor structure at an intermediate stage in a method of manufacturing the semiconductor structure. DETAILED DESCRIPTION
[0019] The following disclosed embodiments provide many different embodiments, or examples, for implementing the different features of the provided objectives. Specific examples of components and arrangements are described below to simplify the present case. Of course, these examples are only examples and are not intended to be limiting.
[0020] Spatially relative terms such as “below,” “beneath,” “lower,” “above,” “upper,” and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings.
[0021] Figure 1A cross-sectional view of a semiconductor structure 100 according to an embodiment of the present invention is shown. As shown in the figure, the semiconductor structure 100 includes a substrate 110, a gate structure 120, a first oxide layer 130 and a second oxide layer 140. The substrate 110 has a groove 111, which includes an inclined surface 112 and a bottom surface 113, and an obtuse angle A1 is formed between the inclined surface 112 and the bottom surface 113. The gate structure 120 is located in the groove 111 of the substrate 110. The width of the bottom surface 122 of the gate structure 120 is less than the width of the top surface 124 of the gate structure 120. The cross-sectional profile of the gate structure 120 is an inverted trapezoid. The first oxide layer 130 is located between the gate structure 120 and the substrate 110. The second oxide layer 140 is located on the top surface 124 of the gate structure 120. In some embodiments, the substrate 110 can be used as a base of a metal-oxide-semiconductor field-effect transistor (MOSFET), the gate structure 120 can be used as a gate, and the first oxide layer 130 and the second oxide layer 140 can be used as gate oxide layers (gateoxide), so that the semiconductor structure 100 can be used as a trench metal-oxide semiconductor (trench MOS) structure for application in a power metal-oxide semiconductor field-effect transistor (power MOSFET).
[0022] In addition, since the cross-sectional profile of the gate structure 120 is an inverted trapezoid and the width of the bottom surface 122 of the gate structure 120 is smaller than the width of the top surface 124 of the gate structure 120, the electric field concentrated at the bottom corner of the gate structure 120 when a gate voltage is applied to the semiconductor structure 100 can be weakened to protect the first oxide layer 130, thereby avoiding gate oxide breakdown and the resulting leakage current.
[0023] In addition, the gate structure 120 may have a sidewall 126 adjacent to the top surface 124 and the bottom surface 122, and an obtuse angle A2 is formed between the bottom surface 122 and the sidewall 126 of the gate structure 120. In some embodiments, the obtuse angle A2 formed between the bottom surface 122 and the sidewall 126 of the gate structure 120 may be in a range of 108 to 118 degrees. The obtuse angle A1 formed between the inclined surface 112 and the bottom surface 113 of the substrate 110 may be the same as the obtuse angle A2 formed between the bottom surface 122 and the sidewall 126 of the gate structure 120. In other words, the obtuse angle A1 formed between the inclined surface 112 and the bottom surface 113 of the substrate 110 may be in a range of 108 to 118 degrees. In such a configuration, the bottom angle of the gate structure 120 is an obtuse angle A2 rather than a right angle or an acute angle, so that the bottom of the gate structure 120 can have a larger surface radius of curvature to reduce the electric field intensity adjacent to the bottom angle of the gate structure 120 .
[0024] In some embodiments, the gate structure 120 is covered by a first oxide layer 130 and a second oxide layer 140, and the thickness of the first oxide layer 130 is the same as the thickness of the second oxide layer 140. In this embodiment, the thickness of the first oxide layer 130 and the thickness of the second oxide layer 140 can both be about 40 nanometers. In addition, the material of the first oxide layer 130 and the material of the second oxide layer 140 can be the same and can include silicon dioxide or hafnium oxide (HfO x ).
[0025] In addition, the material of the gate structure 120 may include polysilicon, tantalum, tungsten, tantalum nitride or titanium nitride, and the material of the substrate 110 may include silicon or silicon carbide.
[0026] In some embodiments, the substrate 110 may further include an epitaxial region 114, a well 115 located on the epitaxial region 114, and a first doped region 116 and a second doped region 117 located in the well 115. The well 115 extends to the first oxide layer 130. The first doped region 116 is adjacent to the second doped region 117, and the cross-sectional profile of the first doped region 116 is L-shaped. In this way, the first doped region 116 and the second doped region 117 can be used as a source contact region, and the bottom of the substrate 110 can be used as a drain contact region, so that the semiconductor structure 100 can be used as a power metal oxide semiconductor field effect transistor (power MOSFET). In some embodiments, the substrate 110 can be an N-type substrate, the well 115 can be a P-type well, the first doped region 116 can include an N-type dopant (such as phosphorus or arsenic or nitrogen), and the second doped region 117 can include a P-type dopant (such as aluminum or boron), so that the semiconductor structure 100 can be used as an N-type power MOSFET. In addition, the semiconductor structure 100 may further include a first conductive layer 152 located on the first doped region 116 and the second doped region 117 of the substrate 110 and a second conductive layer 154 located under the substrate 110. The first conductive layer 152 may serve as a source of the power MOSFET, and the second conductive layer 154 may serve as a drain of the power MOSFET.
[0027] See also Figure 2 The manufacturing method of the semiconductor structure 100 includes forming a patterned film stack structure 160 on a substrate 110, wherein the film stack structure 160 has a plurality of first hard mask layers 161 and a plurality of second hard mask layers 162 that are stacked alternately in sequence, and the number of the first hard mask layers 161 and the number of the second hard mask layers 162 are the same and are a positive integer N less than or equal to 5. In the present embodiment, the positive integer N is 3. In addition, the material of the first hard mask layer 161 and the material of the second hard mask layer 162 may be different, so that the first hard mask layer 161 and the second hard mask layer 162 may serve as each other's etch stop layers. In some embodiments, the materials of the first hard mask layer 161 and the second hard mask layer 162 include silicon dioxide, silicon nitride, or polysilicon, for example, the material of the first hard mask layer 161 is silicon dioxide, and the material of the second hard mask layer 162 is silicon nitride. In addition, the thickness of any one of the first hard mask layers 161 and the thickness of any one of the second hard mask layers 162 may be the same, and the sum thereof is within a range between 0.05 micrometers and 5.05 micrometers.
[0028] Next, a photoresist layer may be formed on the film stack structure 160, and the thickness of the photoresist layer is greater than the thickness of the film stack structure 160 plus 1 micron. Then, a portion of the photoresist layer is removed by exposure and development using a photomask 180 to expose a portion of the film stack structure 160. In some embodiments, the width of the photomask 180 may be 5 microns.
[0029] Next, reactive-ion etching may be used to remove the film stack structure 160 exposed from the photoresist layer, so that the film stack structure 160 has an opening 163 and a sidewall 164 facing the opening 163. In some embodiments, the width of the opening 163 of the film stack structure 160 may be 1 micron. Then, the photoresist layer may be removed.
[0030] See also Figure 3 , a photoresist layer 170 is formed again on the film stack structure 160, so that the uppermost first portion 166a of the second hard mask layer 162 of the film stack structure 160 is exposed from the photoresist layer 170. In addition, the photoresist layer 170 extends to and covers the sidewall 165 of the film stack structure 160 that is opposite to the opening 163 and the sidewall 164. In some embodiments, the width of the uppermost first portion 166a of the second hard mask layer 162 is in the range of 0.2 micrometers to 0.63 micrometers.
[0031] Next, see also Figure 3 and Figure 4 , the uppermost first portion 166a of the second hard mask layer 162 not covered by the photoresist layer 170 can be removed, so that the first portion 167a of the first hard mask layer 161 thereunder is exposed. In this step, a reactive ion etching having a selectivity between the first hard mask layer 161 and the second hard mask layer 162 can be used to remove the second hard mask layer 162, so that the first hard mask layer 161 can be used as an etching stop layer for this step. Then, the exposed first portion 167a of the first hard mask layer 161 can be removed, so that the first portion 166b of the other second hard mask layer 162 is exposed. In this step, a reactive ion etching having a selectivity between the first hard mask layer 161 and the second hard mask layer 162 can be used to remove the first hard mask layer 161, so that the second hard mask layer 162 can be used as an etching stop layer for this step. Next, the first hard mask layer 161 can be removed. Figure 4 The photoresist layer 170 is formed on the surface of the substrate.
[0032] See also Figure 5 , a photoresist layer 170 is formed again on the film stack structure 160 to expose the uppermost second portion 168a of the second hard mask layer 162 and the first portion 166b of the other second hard mask layer 162. In addition, the photoresist layer 170 extends to and covers the sidewall 165 of the film stack structure 160 facing away from the opening 163.
[0033] See also Figure 5 and Figure 6Then, the first hard mask layer 161 can be used as an etching stop layer again to remove the uppermost second portion 168a of the second hard mask layer 162 and simultaneously remove the first portion 166b of the other second hard mask layer 162, so that the uppermost second portion 169a of the first hard mask layer 161 and the first portion 167b of the other first hard mask layer 161 are exposed. Then, the second hard mask layer 162 can be used as an etching stop layer again to remove the uppermost second portion 169a of the first hard mask layer 161 and the first portion 167b of the other first hard mask layer 161, so that the lowermost first portion 166c of the second hard mask layer 162 and the second portion 168b of the other second hard mask layer 162 are exposed from the photoresist layer 170. Then, the second hard mask layer 162 can be removed. Figure 6 The photoresist layer 170 is formed by a plurality of layers of a plurality of optical fibers.
[0034] See also Figure 7 , a photoresist layer 170 is formed again on the film stack structure 160 to expose the uppermost third portion T of the second hard mask layer 162, the second portion 168b of another second hard mask layer 162, and the lowermost first portion 166c of the second hard mask layer 162.
[0035] In some embodiments, the number of first hard mask layers 161 and the number of second hard mask layers 162 may be a positive integer N less than or equal to 5 and not equal to 3 (in the present embodiment, the positive integer N is 3), and thus the above steps may be deleted or repeated until the first portion 166 c of the lowermost second hard mask layer 162 and a portion of the uppermost second hard mask layer 162 are exposed from the photoresist layer 170.
[0036] See also Figure 7 and Figure 8 Then, the first hard mask layer 161 can be used as an etching stop layer again to remove the third portion T of the uppermost second hard mask layer 162, the second portion 168b of another second hard mask layer 162, and the first portion 166c of the lowermost second hard mask layer 162, so that the first portion 167c of the lowermost first hard mask layer 161 is exposed, and the sidewall 164 of the film stack structure 160 can be stepped. Then, the Figure 8 The photoresist layer 170 is formed by removing the second hard mask layer 162 , so that the uppermost portion of the second hard mask layer 162 is exposed.
[0037] See also Fig. 9 After removing the photoresist layer 170 of FIG. 13 , the sidewall 165 of the film stack structure 160 facing away from the opening 163 and opposite to the sidewall 164 can be stepped according to the above method, and the film stack structure 160 can define a hard mask structure 160a. In some embodiments, the distance between the sidewall 164 and the sidewall 165 of the film stack structure 160 along the horizontal direction H1 is in the range of 0.5 micrometers to 5.5 micrometers.
[0038] Next, the substrate 110 located below the hard mask structure 160a and exposed from the opening 163 can be etched to form a trench 111, which includes a sidewall 112a and a bottom surface 113. Since the hard mask structure 160a is stepped, the sidewall 112a of the trench 111 is stepped after the etching step of the substrate 110 in the opening 163. In addition, the width of the bottom surface 113 of the substrate 110 is substantially the same as the width of the bottom of the opening 163 of the hard mask structure 160a. Next, the hard mask structure 160a can be removed.
[0039] See also Fig.10 , the sidewalls 112a and the bottom surface 113 of the substrate 110 may be planarized. In some embodiments, the sidewalls 112a and the bottom surface 113 are oxidized to form a surface oxide layer, and the thickness of the surface oxide layer is in the range of 10 nanometers to 50 nanometers.
[0040] Thereafter, the surface oxide layer may be removed, so that the sidewall 112 a of the substrate 110 forms an inclined surface 112 , and an obtuse angle A1 is formed between the inclined surface 112 and the bottom surface 113 . The obtuse angle A1 is in a range of 108 degrees to 118 degrees.
[0041] See also Fig.11 Then, a first oxide layer 130, a gate structure 120, and a second oxide layer 140 may be sequentially formed on the substrate 110, so that the first oxide layer 130 covers the substrate 110 and is located between the substrate 110 and the gate structure 120. In addition, the first oxide layer 130 and the gate structure 120 may fill the trench 111 of the substrate 110. In some embodiments, the thickness of the first oxide layer 130 is about 40 nanometers.
[0042] After the first oxide layer 130 and the gate structure 120 are sequentially formed on the substrate 110, an etchant having a selectivity ratio between the gate structure 120 and the first oxide layer 130 may be used to remove a portion of the gate structure 120, so that the cross-sectional profile of the remaining gate structure 120 is an inverted trapezoid, and the top surface 132 of the first oxide layer 130 is exposed. In addition, the top surface 124 of the gate structure 120 may be lower than the top surface 132 of the first oxide layer 130, so that the top surface 124 of the gate structure 120 may be substantially coplanar with the top surface 118 of the substrate 110. In some embodiments, the top surface 124 of the gate structure 120 may be about 40 nanometers lower than the top surface 132 of the first oxide layer 130, the width of the bottom surface 122 of the gate structure 120 may be 1 micrometer, the width of the top surface 124 of the gate structure 120 may be 3 micrometers, and the thickness of the gate structure 120 may be in the range of 2 to 3 micrometers.
[0043] Next, a second oxide layer 140 may be formed on the top surface 124 of the gate structure 120 and the top surface 132 of the first oxide layer 130, so that the gate structure 120 is covered by the first oxide layer 130 and the second oxide layer 140. In addition, the material and thickness of the second oxide layer 140 may be respectively the same as the material and thickness of the first oxide layer 130. For example, the thickness of the first oxide layer 130 and the thickness of the second oxide layer 140 may both be approximately 40 nanometers.
[0044] See also Figure 1 Then, an ion implantation method may be used to form a well 115, a first doping region 116, and a second doping region 117 in the substrate 110, wherein the first doping region 116 and the second doping region 117 may include different dopants. In some embodiments, the first oxide layer 130 and the second oxide layer 140 located on the top surface 118 of the substrate 110 may be removed, and a first conductive layer 152 and a second conductive layer 154 may be formed on the top surface 118 and the bottom surface 119 of the substrate 110, respectively, to obtain the semiconductor structure 100. The first conductive layer 152 is located on the first doping region 116 and the second doping region 117. With such a configuration, the first doping region 116 and the second doping region 117 may be used as source contact regions, the bottom of the substrate 110 may be used as a drain contact region, the first conductive layer 152 may be used as a source, and the second conductive layer 154 may be used as a drain, so that the semiconductor structure 100 may be applied to a power MOSFET.
[0045]
Explanation of symbols
[0046] 100:Semiconductor structure
[0047] 110:Substrate
[0048] 111: Groove
[0049] 112: Inclined surface
[0050] 112a: Side wall
[0051] 113: Bottom surface
[0052] 114: Epitaxial area
[0053] 115: Trap
[0054] 116: first doping region
[0055] 117: second doping region
[0056] 118: Top
[0057] 119: Bottom surface
[0058] 120: Gate structure
[0059] 122: Bottom surface
[0060] 124: Top
[0061] 126: Side wall
[0062] 130: First oxide layer
[0063] 132: Top
[0064] 140: Second oxide layer
[0065] 152: first conductive layer
[0066] 154: second conductive layer
[0067] 160: Membrane stack structure
[0068] 160a: Hard mask structure
[0069] 161: First hard mask layer
[0070] 162: Second hard mask layer
[0071] 163: Opening
[0072] 164: Side wall
[0073] 165: Side wall
[0074] 166a, 166b, 166c: Part I
[0075] 167a, 167b, 167c: Part I
[0076] 168a,168b:Part 2
[0077] 169a: Part 2
[0078] 170: Photoresist layer
[0079] 180: Photomask
[0080] A1, A2: Obtuse angle
[0081] H1: Horizontal direction
[0082] T: Part 3.
Claims
1. A semiconductor structure, characterized in that: include: A substrate having a groove, wherein an inclined surface of the groove and a bottom surface thereof form an obtuse angle; A gate structure is located in the trench, wherein the width of the bottom surface of the gate structure is smaller than the width of the top surface of the gate structure, and the cross-sectional profile of the gate structure is an inverted trapezoid; A first oxide layer is located between the gate structure and the substrate; and The second oxide layer is located on the top surface of the gate structure.
2. The semiconductor structure according to claim 1, wherein: The gate structure has a side wall adjacent to the top surface and the bottom surface, and an obtuse angle is formed between the bottom surface and the side wall of the gate structure.
3. The semiconductor structure according to claim 2, wherein: The obtuse angle between the bottom surface and the sidewall of the gate structure is in a range of 108 degrees to 118 degrees.
4. A method for manufacturing a semiconductor structure, characterized in that: include: forming a hard mask structure on the substrate, wherein the hard mask structure has an opening, and a side wall of the hard mask structure facing the opening is stepped; Etching the substrate from the opening through the hard mask structure to form a trench, wherein the trench has a sidewall and a bottom surface, and the sidewall is stepped; The sidewall of the trench is flattened to form an obtuse angle with the bottom surface. forming a first oxide layer on the sidewall and the bottom surface of the trench; Forming a gate structure on the first oxide layer in the trench, wherein the width of the bottom surface of the gate structure is smaller than the width of the top surface of the gate structure, and the cross-sectional profile of the gate structure is an inverted trapezoid; as well as A second oxide layer is formed on the gate structure.
5. The method for manufacturing a semiconductor structure according to claim 4, wherein: Forming the hard mask structure on the substrate includes the following steps: (a) forming a photoresist layer on a film stack structure using a photomask, wherein the film stack structure has a plurality of first hard mask layers and a plurality of second hard mask layers stacked alternately in sequence, and a first portion of an uppermost one of the plurality of second hard mask layers is exposed from the photoresist layer; (b) removing the first portion of the uppermost one of the plurality of second hard mask layers and a first portion of one of the plurality of first hard mask layers thereunder; (c) removing the photoresist layer; (d) moving the mask displacement amount in a horizontal direction and forming the photoresist layer on the film stack structure again, so that the second portion of the uppermost one of the plurality of second hard mask layers and the first portion of another one of the plurality of second hard mask layers are exposed; (e) removing the second portion of the uppermost one of the plurality of second hard mask layers and the second portion of one of the plurality of first hard mask layers thereunder and simultaneously removing the first portion of the other one of the plurality of second hard mask layers and the first portion of one of the plurality of first hard mask layers thereunder; (f) removing the photoresist layer again; (g) repeating steps (d) to (f) until a first portion of a lowermost one of the plurality of second hard mask layers is exposed from the photoresist layer; as well as (h) removing the first portion of the lowest one of the plurality of second hard mask layers so that the film stack structure defines the hard mask structure.
6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The displacement is in the range of 0.2 micrometers to 0.63 micrometers.
7. The method for manufacturing a semiconductor structure according to claim 5 or 6, characterized in that: The thickness of the photoresist layer is greater than the thickness of the film stack structure plus 1 micron.
8. The method for manufacturing a semiconductor structure according to any one of claims 4 to 6, characterized in that: The hard mask structure also has another sidewall opposite to the sidewall and facing away from the opening, and a distance between the sidewall and the other sidewall is in a range of 0.5 micrometers to 5.5 micrometers.
9. The method for manufacturing a semiconductor structure according to claim 4, wherein: Forming the hard mask structure on the semiconductor substrate includes forming a plurality of first hard mask layers and a plurality of second hard mask layers that are sequentially staggered and stacked, and the number of the plurality of first hard mask layers and the plurality of second hard mask layers is the same and is a positive integer less than or equal to 5.
10. The method for manufacturing a semiconductor structure according to claim 9, wherein: A sum of a thickness of any one of the plurality of first hard mask layers and a thickness of any one of the plurality of second hard mask layers is in a range between 0.05 micrometers and 5.05 micrometers.