Groove type field effect transistor and manufacturing method thereof

Abstract

The invention discloses a groove type field effect transistor and a manufacturing method thereof, and the groove type field effect transistor comprises an epitaxial layer, a main body layer and a gate structure layer, and the main body layer and the gate structure layer extend into the epitaxial layer from a first surface of the epitaxial layer. The main body layer comprises a terminal structure region, a first conductive structure region, a well region and a Schottky contact structure, the terminal structure region is opened towards the first surface and forms a conductive main body region, and the first conductive structure region, the well region and part of the epitaxial layer are stacked in the conductive main body region; the Schottky contact structures extend into the conductive main body region from the first surface and form Schottky contact with the first conductive structure region and the well region, at least one gate structure layer is arranged in the conductive main body region and is in contact with the well region, and the Schottky contact structures are arranged on the two sides of any gate structure layer. The reverse conduction voltage drop of the groove type field effect transistor is low, and the groove type field effect transistor has high working efficiency so as to meet actual use requirements.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a trench field effect transistor and a manufacturing method thereof. Background Art

[0002] SiC MOSFET devices are power devices commonly used in various current electronic devices, with faster switching speeds and lower power losses.

[0003] With the development of power devices, the requirements for the working efficiency of MOSFET devices have also increased. In order to ensure high working efficiency, an ohmic contact layer or a Schottky contact layer is usually set between the electrode layer and the epitaxial layer of the MOSFET device. However, in a trench MOSFET device, the gate is in the trench of the epitaxial layer. The structure of the above-mentioned planar MOSFET device has poor effect and cannot reduce the reverse conduction voltage drop of the trench MOSFET device, resulting in low working efficiency of the trench MOSFET device. Summary of the invention

[0004] The present application provides a trench field effect transistor and a method for manufacturing the same. The trench field effect transistor has a low reverse conduction voltage drop and high working efficiency to match actual use requirements.

[0005] The present application provides a trench field effect transistor, which includes an epitaxial layer, a main layer and a gate structure layer, wherein the main layer and the gate structure layer both extend from the first surface of the epitaxial layer into the epitaxial layer, the main layer includes a terminal structure region, a first conductive structure region, a well region and a Schottky contact structure, the terminal structure region opens toward the first surface and forms a conductive main region, the first conductive structure region, the well region and part of the epitaxial layer are stacked in the conductive main region, the Schottky contact structure extends from the first surface into the conductive main region and forms Schottky contact with the first conductive structure region and the well region, at least one gate structure layer is arranged in the conductive main region and in contact with the well region, and Schottky contact structures are provided on both sides of any gate structure layer; wherein the epitaxial layer and the first conductive structure region have a first conductivity type, and the well region has a second conductivity type.

[0006] As above, the trench field effect transistor, wherein the terminal structure region includes a second conductive structure region and a conductive channel, at least one conductive channel is arranged in a one-to-one correspondence with at least one gate structure layer, the gate structure layer is in contact with the first conductive structure region, the well region and the epitaxial layer stacked in the conductive main region, and each gate structure layer is spaced apart from the corresponding conductive channel by the epitaxial layer; wherein the second conductive structure region has a second conductive type, and the conductive channel has a first conductive type.

[0007] As above, the trench field effect transistor, wherein the epitaxial layer includes a first epitaxial layer and a second epitaxial layer which are stacked, the first surface is arranged on the second epitaxial layer, the second conductive structure area includes a terminal body area and a terminal connection area which are connected to each other, the terminal body area is arranged in the second epitaxial layer, and the terminal body area extends from the first surface to the surface of the first epitaxial layer, a plurality of terminal connection areas are arranged at intervals in the first epitaxial layer, and a conductive channel is arranged between adjacent terminal connection areas.

[0008] In the trench field effect transistor as above, the main layer has a plurality of Schottky contact structures, the plurality of Schottky contact structures are arranged one by one corresponding to the plurality of terminal connection regions, and the Schottky contact structures extend from the first surface to the first epitaxial layer to connect with the corresponding terminal connection regions.

[0009] In the trench field effect transistor as above, the first conductive structure region extends from the first surface to the inside of the epitaxial layer, an ohmic contact structure is provided on the first surface, and the ohmic contact structure is connected to the first conductive structure region to form an ohmic contact.

[0010] As above, the trench field effect transistor, wherein the Schottky contact structure includes a first contact portion and a second contact portion, the first contact portion extends along the stacking direction of the first conductive structure region and the well region, the second contact portion is parallel to the ohmic contact structure and connected to the side of the ohmic contact structure away from the first surface, and the second contact portion covers a portion of the surface of the ohmic contact structure.

[0011] As in the trench field effect transistor above, the second conductive structure region includes two terminal main regions, the two terminal main regions are respectively arranged on both sides of the conductive main region, and extension regions are also arranged on both sides of the two terminal main regions, the extension regions have the second conductive type, and the doping concentration of the extension regions is less than the doping concentration of the terminal main regions.

[0012] As above, the trench field effect transistor further includes a substrate layer, a first electrode layer and a second electrode layer, the substrate layer and the second electrode layer are stacked on the second surface of the epitaxial layer, and the substrate layer is connected to the second surface, the first electrode layer is arranged on the first surface of the epitaxial layer, and the first electrode layer is conductively connected to the Schottky contact structure.

[0013] On the other hand, the present application also provides a method for manufacturing a trench field effect transistor, which comprises:

[0014] Performing epitaxial growth on one side of the substrate layer to form an epitaxial layer having a first conductivity type;

[0015] Performing implantation of the first conductivity type and the second conductivity type on the first surface of the epitaxial layer to form a terminal structure region of the main layer and a first conductive structure region and a well region stacked in a conductive main region of the terminal structure region;

[0016] Performing trench etching in the conductive body region to form a plurality of receiving trenches;

[0017] Disposing a gate structure layer in the receiving groove;

[0018] Disposing a first electrode layer on a first surface of the epitaxial layer;

[0019] Performing trench etching in a region of the first electrode layer corresponding to the first conductive structure region to form a first contact hole penetrating the first electrode layer;

[0020] forming an ohmic contact structure in the first contact hole;

[0021] Performing trench etching from the ohmic contact structure toward the epitaxial layer to form a second contact hole penetrating the conductive body region;

[0022] A Schottky contact structure is formed in the second contact hole.

[0023] The manufacturing method of the trench field effect transistor as above, wherein the step of performing epitaxial growth on one side of the substrate layer specifically includes: performing epitaxial growth on one side of the substrate layer to form a first epitaxial layer; performing injection of the first conductivity type and the second conductivity type on the surface of the first epitaxial layer to form a terminal connection area and a conductive channel in the terminal structure area; performing epitaxial growth on the surface of the first epitaxial layer to form a second epitaxial layer.

[0024] The manufacturing method of the trench field effect transistor as mentioned above, wherein the step of performing the injection of the first conductivity type and the second conductivity type on the first surface of the epitaxial layer specifically includes: performing the injection of the second conductivity type on the first surface of the epitaxial layer to form a well region; performing the injection of the first conductivity type in the well region to form a first conductive structure region; performing the injection of the second conductivity type on both sides of the well region to form a terminal body region connected to the terminal connection region.

[0025] The manufacturing method of the trench field effect transistor as described above, wherein, after the step of performing the second conductivity type implantation on both sides of the well region, further comprises: performing the second conductivity type implantation on both sides of the two terminal body regions away from each other to form two extension regions.

[0026] The main body layer and gate structure layer of the trench field effect transistor of the present application are extended from the first surface of the epitaxial layer to the epitaxial layer, so that the gate structure layer is a trench gate structure, and the gate structure layer is formed in the main body layer. In the main body layer, the first conductive structure area, the well area and part of the epitaxial layer are stacked in the conductive main body area of ​​the terminal structure area, wherein the first conductive structure area and the well area are respectively the first conductive type area and the second conductive type area, and the two can form a PN junction, and the Schottky contact structure extends from the first surface to the conductive main body area and can form a Schottky contact with the first conductive structure area and the well area, so that the contact area between the conductive main body area, the first conductive structure area and the well area forms a JBS structure, and because the JBS structure is formed inside the main layer and is arranged close to both sides of the gate structure layer, it can play a role in the working state of the trench field effect transistor, reduce the reverse conduction voltage drop of the trench field effect transistor, and improve the overall working efficiency of the device, so as to match the actual use requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 It is a schematic diagram of the overall structure of the trench field effect transistor according to an embodiment of the present application;

[0029] Figure 2 It is an isometric view of a part of the structure of a trench field effect transistor according to an embodiment of the present application;

[0030] Figure 3 It is a schematic diagram of a trench field effect transistor after the terminal connection region is formed according to an embodiment of the present application;

[0031] Figure 4 A schematic diagram of a trench field effect transistor after a conductive channel is formed according to an embodiment of the present application;

[0032] Figure 5 It is a schematic diagram of a trench field effect transistor after the second epitaxial layer is formed according to an embodiment of the present application;

[0033] Figure 6 It is a schematic diagram of a trench field effect transistor after the well region is formed according to an embodiment of the present application;

[0034] Figure 7 It is a schematic diagram of a trench field effect transistor after the first conductive structure region is formed according to an embodiment of the present application;

[0035] Figure 8It is a schematic diagram of a terminal body region of a trench field effect transistor according to an embodiment of the present application after being formed;

[0036] Fig. 9 It is a schematic diagram of a trench field effect transistor after the extension region is formed according to an embodiment of the present application;

[0037] Fig.10 It is a schematic diagram of a trench field effect transistor after the receiving trench is formed according to an embodiment of the present application;

[0038] Fig.11 It is a schematic diagram of a trench field effect transistor after a gate oxide layer is formed according to an embodiment of the present application;

[0039] Fig.12 It is a schematic diagram of a trench field effect transistor after a dielectric layer is formed according to an embodiment of the present application;

[0040] Fig.13 It is a schematic diagram of the ohmic contact structure of the trench field effect transistor of the embodiment of the present application after being formed;

[0041] Fig.14 This is a schematic diagram of a trench field effect transistor after a second contact hole is formed according to an embodiment of the present application;

[0042] Fig.15 A schematic diagram of a trench field effect transistor after the Schottky contact structure is formed in an embodiment of the present application;

[0043] Fig.16 Flow chart of a method for manufacturing a trench field effect transistor according to an embodiment of the present application.

[0044] Description of Figure Numbers:

[0045] 10. epitaxial layer; 11. first epitaxial layer; 12. second epitaxial layer; 20. main layer; 30. gate structure layer; 31. gate oxide layer; 32. dielectric layer; 40. terminal structure region; 41. conductive main region; 42. second conductive structure region; 421. terminal main region; 422. terminal connection region; 43. conductive channel; 44. accommodating groove; 45. second contact hole; 50. first conductive structure region; 60. well region; 70. Schottky contact structure; 71. first contact portion; 72. second contact portion; 80. ohmic contact structure; 90. extension region; 100. first electrode layer; 101. first contact hole; 110. substrate layer. DETAILED DESCRIPTION

[0046] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0047] like Figures 1 to 15 As shown, an embodiment of the present application provides a trench field effect transistor, which includes an epitaxial layer 10, a main layer 20 and a gate structure layer 30, wherein the main layer 20 and the gate structure layer 30 both extend from the first surface of the epitaxial layer 10 into the epitaxial layer 10, the main layer 20 includes a terminal structure region 40, a first conductive structure region 50, a well region 60 and a Schottky contact structure 70, the terminal structure region 40 opens toward the first surface and forms a conductive main region 41, the first conductive structure region 50, the well region 60 and a portion of the epitaxial layer 10 are stacked in the conductive main region 41, the Schottky contact structure 70 extends from the first surface into the conductive main region 41 and forms Schottky contacts with the first conductive structure region 50 and the well region 60, at least one gate structure layer 30 is arranged in the conductive main region 41 and contacts the well region 60, and Schottky contact structures 70 are provided on both sides of any gate structure layer 30; wherein the epitaxial layer 10 and the first conductive structure region 50 have a first conductivity type, and the well region 60 has a second conductivity type.

[0048] In the embodiment of the present application, the trench field effect transistor is one of SiC MOSFET (SiC Metal Oxide Semiconductor Field Effect Transistor). In the semiconductor device, the first conductivity type is N-type, that is, the layer structure or region with the first conductivity type is formed by N-type semiconductor material, and the second conductivity type is P-type, that is, the layer structure or region with the second conductivity type is formed by P-type semiconductor material. It should be noted that the first conductivity type can also be set to P-type and the second conductivity type can be set to N-type.

[0049] In specific implementation, the main layer 20 and the gate structure layer 30 of the trench field effect transistor of the embodiment of the present application are extended from the first surface of the epitaxial layer 10 to the inside of the epitaxial layer 10 so that the gate structure layer 30 presents a trench gate structure, and the gate structure layer 30 is formed in the main layer 20. In the main body layer 20, the first conductive structure region 50, the well region 60 and part of the epitaxial layer 10 are stacked in the conductive main body region 41 of the terminal structure region 40, wherein the first conductive structure region 50 and the well region 60 are respectively the first conductive type region and the second conductive type region, and the two can form a PN junction, and the Schottky contact structure 70 extends from the first surface to the conductive main body region 41 and can form a Schottky contact with the first conductive structure region 50 and the well region 60, so that the PN junction can be integrated in the Schottky contact structure 70, so that the contact area between the conductive main body region 41, the first conductive structure region 50 and the well region 60 can form a JBS (Junction Barrier Schottky) structure. Since the JBS structure is formed inside the main layer 20 and is arranged close to both sides of the gate structure layer 30, it can play a role in the working state of the trench field effect transistor, reduce the reverse conduction voltage drop of the trench field effect transistor, and improve the overall working efficiency of the device, so that the trench field effect transistor of the present application is suitable for high voltage and high power applications, thereby matching actual use requirements.

[0050] Specifically, the trench field effect transistor further includes a substrate layer 110, a first electrode layer 100 and a second electrode layer, wherein the substrate layer 110 and the second electrode layer are stacked on the second surface of the epitaxial layer 10, and the substrate layer 110 is connected to the second surface, the first electrode layer 100 is arranged on the first surface of the epitaxial layer 10, and the first electrode layer 100 is conductively connected to the Schottky contact structure 70. After a forward voltage is applied to the gate structure layer 30, a current can be formed from the second electrode layer to the first electrode layer 100, and the current path is the second electrode layer, the substrate layer 110, the epitaxial layer 10, the various structural regions of the main layer 20, the Schottky contact structure 70 of the main layer 20 to the first electrode layer 100. Among them, the first electrode layer 100 is a source structure layer, and the second electrode layer is a drain structure layer, both of which are made of metal materials.

[0051] Specifically, the gate structure layer 30 includes a gate oxide layer 31 and a dielectric layer 32. The gate oxide layer 31 is arranged in the accommodating groove 44 of the conductive main region 41, and is in contact with the first conductive structure region 50, the well region 60 and a portion of the epitaxial layer 10 in the conductive main region 41. The dielectric layer 32 is connected to the surface of the gate oxide layer 31 facing the first electrode layer 100, thereby forming the overall structure of the gate structure layer 30.

[0052] like Figure 1 and Figure 2As shown, a trench field effect transistor in an embodiment of the present application, wherein the terminal structure region 40 includes a second conductive structure region 42 and a conductive channel 43, at least one conductive channel 43 is arranged in a one-to-one correspondence with at least one gate structure layer 30, the gate structure layer 30 is in contact with the first conductive structure region 50, the well region 60 and the epitaxial layer 10 stacked in the conductive main region 41, and each gate structure layer 30 is arranged at intervals with the corresponding conductive channel 43 through the epitaxial layer 10; wherein the second conductive structure region 42 has a second conductivity type, and the conductive channel 43 has a first conductivity type.

[0053] The doping concentrations of the first conductive structure region 50 and the second conductive structure region 42 are greater than the doping concentration of the well region 60, the doping concentration of the well region 60 is greater than the doping concentration of the epitaxial layer 10, and the doping concentrations between the well region 60 and the epitaxial layer 10 are set so that the two together with the Schottky contact structure 70 form a JBS structure. Specifically, the first conductive structure region 50 and the second conductive structure region 42 are heavily doped N+ and P+ regions, respectively, the well region 60 is a P-well region, and the epitaxial layer 10 is an N- region.

[0054] In specific implementation, when a forward voltage is applied to the gate structure layer 30, a conduction channel from the first conductive structure region 50 to the epitaxial layer 10 is formed in the well region 60, and the electrons in the first conductive structure region 50 can be transferred from the conduction channel to the epitaxial layer 10 in the conductive main region 41, and transferred from the conductive channel 43 connected to this part of the epitaxial layer 10 to the external epitaxial layer 10, thereby forming an electron transfer path, and the current path is opposite to it. The transferred electrons formed on both sides of each gate structure layer 30 all flow out from the corresponding conductive channel 43. By setting the same number of conductive channels 43 as the gate structure layer 30 and corresponding to each other, it can be adapted to the setting of the gate structure layer 30 in actual work, thereby matching the actual use requirements and ensuring the working efficiency of the device.

[0055] like Figure 1 and Figure 2 As shown, a trench field effect transistor in an embodiment of the present application, wherein the epitaxial layer 10 includes a first epitaxial layer 11 and a second epitaxial layer 12 which are stacked, the first surface is arranged on the second epitaxial layer 12, the second conductive structure region 42 includes a terminal body region 421 and a terminal connection region 422 which are connected to each other, the terminal body region 421 is arranged in the second epitaxial layer 12, and the terminal body region 421 extends from the first surface to the surface of the first epitaxial layer 11, a plurality of terminal connection regions 422 are arranged at intervals in the first epitaxial layer 11, and a conductive channel 43 is arranged between adjacent terminal connection regions 422.

[0056] Multiple terminal connection areas 422 are arranged in sequence and spaced apart in the first epitaxial layer 11, and conductive channels 43 are provided between adjacent terminal connection areas 422, so that multiple conductive channels 43 corresponding to multiple gate structure layers 30 can be formed in the first epitaxial layer 11, thereby improving the overall working efficiency of the device.

[0057] The main body layer 20 has a plurality of Schottky contact structures 70. Since both sides of each conductive channel 43 are provided with a terminal connection region 422, and both sides of the gate structure layer 30 are also provided with a Schottky contact structure 70, the plurality of Schottky contact structures 70 can be arranged one by one with the plurality of terminal connection regions 422, and the Schottky contact structure 70 extends from the first surface to the first epitaxial layer 11 to connect with the corresponding terminal connection region 422. Since the terminal connection region 422 is of the second conductivity type, it can form a PN junction with a portion of the epitaxial layer 10 adjacently arranged in the conductive main body region 41, and the Schottky contact structure 70 extends to connect with the terminal connection region 422, so that the PN junction can form a JBS structure with the Schottky contact structure 70. Therefore, the terminal connection region 422 can be combined with the conductive main body region 41, the first conductive structure region 50 and the well region 60, so as to increase the overall volume of the JBS structure, further reduce the reverse conduction voltage drop of the device, and further improve the overall working efficiency of the device.

[0058] Multiple terminal connection areas 422 and multiple conductive channels 43 are interconnected, thereby forming an overall structure extending in the horizontal direction in the first epitaxial layer 11. The two terminal main areas 421 are connected to the two terminal connection areas 422 on both sides, and extend from the first surface to the surface of the first epitaxial layer 11. The extension length is the same as the thickness of the second epitaxial layer 12, thereby achieving the encirclement of the conductive main area 41, so that the layer structure or area inside the conductive main area 41 can serve as the main conductive area of ​​the trench field effect transistor, thereby realizing different switching functions.

[0059] like Figure 1 and Figure 2 As shown, a trench field effect transistor in an embodiment of the present application, wherein the second conductive structure region 42 includes two terminal main body regions 421, and the two terminal main body regions 421 are respectively arranged on both sides of the conductive main body region 41, and an extension region 90 is also arranged on both sides of the two terminal main body regions 421, and the extension region 90 has a second conductive type, and the doping concentration of the extension region 90 is less than the doping concentration of the terminal main body region 421.

[0060] In a specific implementation, the two extension regions 90 are respectively arranged on both sides of the two terminal main regions 421, that is, arranged on the outside of the terminal structure region 40, so as to form a JTE (Junction Termination Extension) structure. The doping concentration of the extension region 90 is relatively small, and a lightly doped P-region can be formed, which can increase the overall breakdown voltage of the device, thereby improving the device performance.

[0061] In the trench field effect transistor of the embodiment of the present application, the first conductive structure region 50 extends from the first surface to the inside of the epitaxial layer 10, and an ohmic contact structure 80 is provided on the first surface, which is connected to the first conductive structure region 50 to form an ohmic contact.

[0062] In specific implementation, the ohmic contact structure 80 is a metal layer structure provided on the first surface, which can form a metal semiconductor contact with the surface of the heavily doped first conductive structure region 50, thereby realizing ohmic contact. Therefore, the contact resistance between the ohmic contact structure 80 and the first conductive structure region 50 is small, and a good current path can be formed between the two. Moreover, since the ohmic contact structure 80 is conductively connected to the first electrode layer 100, a good current path can be formed between the second electrode layer and the first electrode layer 100, thereby improving the switching speed, and thus improving the overall working efficiency of the device.

[0063] like Figure 1 and Figure 2 As shown, a trench field effect transistor of an embodiment of the present application, wherein the Schottky contact structure 70 includes a first contact portion 71 and a second contact portion 72, the first contact portion 71 extends along the stacking direction of the first conductive structure region 50 and the well region 60, the second contact portion 72 is parallel to the ohmic contact structure 80 and connected to a side of the ohmic contact structure 80 away from the first surface, and the second contact portion 72 covers a portion of the surface of the ohmic contact structure 80.

[0064] In specific implementation, the first contact portion 71 of the Schottky contact structure 70 extends along the stacking direction of the first conductive structure area 50 and the well area 60, and the overall structure is a rod-shaped structure. Its side surface can contact both the well area 60 and the epitaxial layer 10, and the bottom extends to contact the corresponding terminal connection area 422, thereby forming a Schottky contact, and the contact part of the Schottky contact structure 70 with the well area 60, the epitaxial layer 10 and the terminal connection area 422 forms a JBS structure with a larger area, further reducing the reverse conduction voltage drop of the device.

[0065] like Fig.16 As shown, the embodiment of the present application also provides a method for manufacturing a trench field effect transistor, which includes:

[0066] S110, such as Figure 3As shown, epitaxial growth is performed on one side of the substrate layer 110 to form an epitaxial layer 10 having a first conductivity type;

[0067] S120, such as Figure 6 and Figure 7 As shown, the first conductive type and the second conductive type are implanted on the first surface of the epitaxial layer 10 to form the terminal structure region 40 of the main layer 20 and the first conductive structure region 50 and the well region 60 stacked in the conductive main region 41 of the terminal structure region 40;

[0068] Wherein, the first conductivity type and the second conductivity type are implanted separately to form regions of different conductivity types, and regions of different doping concentrations can be formed, and the doping concentration of the first conductive structure region 50 is greater than the doping concentration of the well region 60;

[0069] S130, such as Fig.10 As shown, trench etching is performed in the conductive body region 41 to form a plurality of receiving trenches 44;

[0070] S140, such as Fig.11 and Fig.12 As shown, a gate structure layer 30 is disposed in the receiving groove 44;

[0071] The accommodating groove 44 is recessed from the first surface of the epitaxial layer 10 to the inside, and the accommodating groove 44 penetrates the first conductive structure region 50 and the well region 60, and forms a partially recessed structure on the epitaxial layer 10 in the conductive body region 41, so that the gate structure layer 30 disposed in the accommodating groove 44 can contact the first conductive structure region 50, the well region 60 and the epitaxial layer 10;

[0072] S150, such as Fig.13 As shown, a first electrode layer 100 is provided on a first surface of the epitaxial layer 10;

[0073] The first electrode layer 100 is a source structure layer, which can be in contact with and electrically connected to the conductive main region 41 of the epitaxial layer 10 after being disposed on the first surface;

[0074] S160, such as Fig.13 As shown, trench etching is performed in the area of ​​the first electrode layer 100 corresponding to the first conductive structure area 50 to form a first contact hole 101 penetrating the first electrode layer 100;

[0075] S170, such as Fig.13 As shown, an ohmic contact structure 80 is formed in the first contact hole 101;

[0076] S180, such as Fig.14As shown, trench etching is performed from the ohmic contact structure 80 toward the epitaxial layer 10 to form a second contact hole 45 penetrating the conductive body region 41;

[0077] S190, such as Fig.15 As shown, a Schottky contact structure 70 is formed in the second contact hole 45;

[0078] Among them, the second contact hole 45 extends downward from the ohmic contact structure 80 to the terminal connection area 422 of the terminal structure area 40, so that the Schottky contact structure 70 arranged inside the second contact hole 45 is in contact with the first conductive structure area 50, the well area 60, the epitaxial layer 10 and the terminal connection area 422, thereby forming a JBS structure.

[0079] In specific implementation, the manufacturing method of the trench field effect transistor in the embodiment of the present application is adopted for manufacturing. The formed trench field effect transistor has a trench gate structure layer 30, and the first contact hole 101 and the second contact hole 45 are etched on at least one side of the gate structure layer 30, and an ohmic contact structure 80 and a Schottky contact structure 70 are formed respectively. The ohmic contact structure 80 arranged on the first surface can reduce the contact resistance of the entire device and form a good current path. The Schottky contact structure 70 arranged in the second contact hole 45 can contact the first conductive structure area 50, the well area 60, the epitaxial layer 10 and the terminal connection area 422 to form a JBS structure. Since the JBS structure is formed inside the main layer 20 and is arranged close to both sides of the gate structure layer 30, it can play a role in the working state of the trench field effect transistor, reduce the reverse conduction voltage drop of the trench field effect transistor, and improve the overall working efficiency of the device, so that the trench field effect transistor of the present application is suitable for high voltage and high power applications, thereby matching actual use requirements.

[0080] like Fig.11 and Fig.12 As shown, in the step of setting the gate structure layer 30 in the accommodating groove 44, specifically, firstly, a gate oxide layer 31 is set in the accommodating groove 44, so that the gate oxide layer 31 is in contact with the first conductive structure region 50, the well region 60 and a part of the epitaxial layer 10 in the conductive main region 41, and then a dielectric layer 32 is set on the surface of the gate oxide layer 31 facing the first electrode layer 100 to form the overall structure of the gate structure layer 30.

[0081] The method for manufacturing a trench field effect transistor in an embodiment of the present application, wherein the step of performing epitaxial growth on one side of the substrate layer 110 specifically includes:

[0082] like Figure 3 As shown, epitaxial growth is performed on one side of the substrate layer 110 to form a first epitaxial layer 11;

[0083] like Figure 3 and Figure 4 As shown, the first conductivity type and the second conductivity type are implanted on the surface of the first epitaxial layer 11 to form the terminal connection area 422 and the conductive channel 43 of the terminal structure area 40;

[0084] like Figure 5 As shown, epitaxial growth is performed on the surface of the first epitaxial layer 11 to form the second epitaxial layer 12 .

[0085] When performing the first conductivity type and the second conductivity type injection, the first conductivity type conductive channel 43 needs to be disposed between the second conductivity type terminal connection regions 422 so that current can pass through the conductive channel 43 .

[0086] In a specific implementation, after forming the first epitaxial layer 11 on one side of the substrate layer 110, the terminal connection area 422 and the conductive channel 43 are formed by performing the first conductive type and the second conductive type implantation on the surface of the first epitaxial layer 11, and the terminal connection area 422 and the conductive channel 43 can be buried in the first epitaxial layer 11 to form a buried layer. By sequentially forming the first epitaxial layer 11 and the second epitaxial layer 12, and forming the terminal connection area 422 and the conductive channel 43 in the first epitaxial layer 11 before forming the second epitaxial layer 12, it is convenient to form the conductive body area 41 in the second epitaxial layer 12, avoiding affecting the doping concentration of the conductive body area 41 during the implantation process, facilitating the manufacture of the overall device, and ensuring the switching function of the overall device.

[0087] like Figures 6 to 8 As shown, the manufacturing method of the trench field effect transistor of the embodiment of the present application, wherein the step of performing the first conductivity type and the second conductivity type injection on the first surface of the epitaxial layer 10 specifically includes: performing the second conductivity type injection on the first surface of the epitaxial layer 10 to form a well region 60; performing the first conductivity type injection in the well region 60 to form a first conductive structure region 50; performing the second conductivity type injection on both sides of the well region 60 to form a terminal body region 421 connected to the terminal connection region 422.

[0088] In a specific implementation, the well region 60 is arranged on one side of the terminal connection region 422 and the conductive channel 43 close to the first surface, and is spaced apart from the terminal connection region 422 and the conductive channel 43, with a portion of the second epitaxial layer 12 between the two, and the first conductive structure region 50 is buried in the well region 60; the second conductive type is injected on both sides of the well region 60 to form a terminal main body region 421 connected to the terminal connection region 422, and the terminal main body region 421, the terminal connection region 422 and the conductive channel 43 are jointly enclosed to form the conductive main body region 41, so that the well region 60 and the first conductive structure region 50 are both arranged in the conductive main body region 41, thereby forming the main conductive area of ​​the device.

[0089] like Fig. 9 As shown, the manufacturing method of the trench field effect transistor of the embodiment of the present application further includes: after the step of performing the second conductivity type injection on both sides of the well region 60, performing the second conductivity type injection on both sides of the two terminal main regions 421 away from each other to form two extension regions 90.

[0090] In a specific implementation, the two extension regions 90 are both lightly doped regions, which are disposed on two sides away from each other of the two terminal main regions 421 , and can increase the overall breakdown voltage of the device, thereby improving the device performance.

[0091] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0092] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A trench field effect transistor, characterized in that: The invention comprises an epitaxial layer (10), a main layer (20) and a gate structure layer (30), wherein the main layer (20) and the gate structure layer (30) both extend from a first surface of the epitaxial layer (10) into the epitaxial layer (10), the main layer (20) comprises a terminal structure region (40), a first conductive structure region (50), a well region (60) and a Schottky contact structure (70), the terminal structure region (40) is open toward the first surface and forms a conductive main region (41), the first conductive structure region (50), the well region (60) and the Schottky contact structure (70) The well region (60) and part of the epitaxial layer (10) are stacked in the conductive body region (41), the Schottky contact structure (70) extends from the first surface into the conductive body region (41) and forms Schottky contact with both the first conductive structure region (50) and the well region (60), at least one gate structure layer (30) is arranged in the conductive body region (41) and in contact with the well region (60), and the Schottky contact structure (70) is provided on both sides of any gate structure layer (30); The epitaxial layer (10) and the first conductive structure region (50) have a first conductive type, and the well region (60) has a second conductive type.

2. The trench field effect transistor according to claim 1, characterized in that: The terminal structure region (40) comprises a second conductive structure region (42) and a conductive channel (43), at least one of the conductive channels (43) is arranged in one-to-one correspondence with at least one of the gate structure layers (30), the gate structure layer (30) is in contact with the first conductive structure region (50), the well region (60) and the epitaxial layer (10) stacked in the conductive body region (41), and each of the gate structure layers (30) is arranged at intervals with the corresponding conductive channel (43) through the epitaxial layer (10); The second conductive structure region (42) has a second conductive type, and the conductive channel (43) has a first conductive type.

3. The trench field effect transistor according to claim 2, characterized in that: The epitaxial layer (10) comprises a first epitaxial layer (11) and a second epitaxial layer (12) which are stacked, the first surface being arranged on the second epitaxial layer (12), the second conductive structure region (42) comprising a terminal body region (421) and a terminal connection region (422) which are connected to each other, the terminal body region (421) being arranged in the second epitaxial layer (12), and the terminal body region (421) extending from the first surface to the surface of the first epitaxial layer (11), a plurality of the terminal connection regions (422) being arranged at intervals in the first epitaxial layer (11), and the conductive channel (43) being arranged between adjacent terminal connection regions (422).

4. The trench field effect transistor according to claim 3, characterized in that: The main body layer (20) has a plurality of Schottky contact structures (70), the plurality of Schottky contact structures (70) are arranged in one-to-one correspondence with the plurality of terminal connection areas (422), and the Schottky contact structures (70) extend from the first surface to the first epitaxial layer (11) to connect with the corresponding terminal connection area (422).

5. The trench field effect transistor according to claim 1, characterized in that: The first conductive structure region (50) extends from the first surface to the inside of the epitaxial layer (10), and an ohmic contact structure (80) is provided on the first surface. The ohmic contact structure (80) is connected to the first conductive structure region (50) to form an ohmic contact.

6. The trench field effect transistor according to claim 5, characterized in that: The Schottky contact structure (70) comprises a first contact portion (71) and a second contact portion (72), wherein the first contact portion (71) extends along the stacking direction of the first conductive structure region (50) and the well region (60), and the second contact portion (72) is parallel to the ohmic contact structure (80) and connected to a side of the ohmic contact structure (80) away from the first surface, and the second contact portion (72) covers a portion of the surface of the ohmic contact structure (80).

7. The trench field effect transistor according to claim 3, characterized in that: The second conductive structure area (42) includes two terminal body areas (421), and the two terminal body areas (421) are respectively arranged on both sides of the conductive body area (41). An extension area (90) is also arranged on both sides of the two terminal body areas (421), and the extension area (90) has a second conductive type, and the doping concentration of the extension area (90) is less than the doping concentration of the terminal body area (421).

8. The trench field effect transistor according to claim 1, characterized in that: The trench field effect transistor further comprises a substrate layer (110), a first electrode layer (100) and a second electrode layer, wherein the substrate layer (110) and the second electrode layer are stacked on the second surface of the epitaxial layer (10), and the substrate layer (110) is connected to the second surface, the first electrode layer (100) is arranged on the first surface of the epitaxial layer (10), and the first electrode layer (100) is conductively connected to the Schottky contact structure (70).

9. A method for manufacturing a trench field effect transistor, characterized in that: include: Performing epitaxial growth on one side of the substrate layer (110) to form an epitaxial layer (10) having a first conductivity type; Performing implantation of a first conductivity type and a second conductivity type on the first surface of the epitaxial layer (10) to form a terminal structure region (40) of the main layer (20) and a first conductive structure region (50) and a well region (60) stacked in a conductive main region (41) of the terminal structure region (40); Performing trench etching in the conductive main region (41) to form a plurality of accommodating trenches (44); A gate structure layer (30) is arranged in the accommodating groove (44); Providing a first electrode layer (100) on a first surface of the epitaxial layer (10); Performing trench etching in a region of the first electrode layer (100) corresponding to the first conductive structure region (50) to form a first contact hole (101) penetrating the first electrode layer (100); forming an ohmic contact structure (80) in the first contact hole (101); Performing trench etching from the ohmic contact structure (80) toward the epitaxial layer (10) to form a second contact hole (45) penetrating the conductive main region (41); A Schottky contact structure (70) is formed in the second contact hole (45).

10. The method for manufacturing a trench field effect transistor according to claim 9, characterized in that: The step of performing epitaxial growth on one side of the substrate layer (110) specifically includes: Performing epitaxial growth on one side of the substrate layer (110) to form a first epitaxial layer (11); Performing implantation of a first conductivity type and a second conductivity type on the surface of the first epitaxial layer (11) to form a terminal connection region (422) and a conductive channel (43) of the terminal structure region (40); Epitaxial growth is performed on the surface of the first epitaxial layer (11) to form a second epitaxial layer (12).

11. The method for manufacturing a trench field effect transistor according to claim 10, characterized in that: The step of implanting the first conductivity type and the second conductivity type into the first surface of the epitaxial layer (10) specifically includes: Performing implantation of a second conductivity type on the first surface of the epitaxial layer (10) to form the well region (60); Performing implantation of a first conductivity type in the well region (60) to form the first conductive structure region (50); Implantation of a second conductivity type is performed on both sides of the well region (60) to form a terminal body region (421) connected to the terminal connection region (422).

12. The method for manufacturing a trench field effect transistor according to claim 11, characterized in that: After the step of performing the second conductivity type implantation on both sides of the well region (60), the method further comprises: Implantation of the second conductivity type is performed on two sides of the two terminal main body regions (421) that are away from each other, respectively, to form two extension regions (90).

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