SiC MOSFET device based on asymmetric P + shielding layer and preparation method thereof

Abstract

The invention discloses a SiC MOSFET device based on an asymmetric P + shielding layer and a preparation method of the SiC MOSFET device, and belongs to the technical field of semiconductors. The device comprises an N + substrate and an N-epitaxial layer located on the N + substrate, a P well region is arranged in the N-epitaxial layer along the first direction; the P well region is located on one side, away from the N + substrate, of the N-epitaxial layer, and a certain space is formed between the P well region and the bottom of the N-epitaxial layer to form a drift region of the device; wherein the P well region comprises a first P well region and a second P well region, and the first P well region and the second P well region are arranged at an interval; the first direction is a direction perpendicular to the thickness of the N-epitaxial layer; p + shielding layers are arranged on two sides of the bottom of the second P well region; and the P + shielding layer is connected with the second P well region and extends upwards to the interior of the N-epitaxial layer from the horizontal position where the lower edge of the second P well region is located, so that a three-dimensional asymmetric deep P well structure is formed. According to the structural design, the leakage current caused by a short channel is reduced, and the short-circuit endurance capability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a SiC MOSFET device based on an asymmetric P+ shielding layer and a preparation method thereof. Background Art

[0002] Semiconductor technology has played a decisive role in the development of the power electronics industry. Among them, power semiconductor devices have always been considered a key component of power electronic equipment. With the widespread application of power electronics technology in industries such as industry, medical care, transportation, and consumption, power semiconductor devices directly affect the cost and efficiency of these power electronic equipment.

[0003] In recent years, the rapid development of SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) technology has attracted widespread attention to this new generation of power devices.

[0004] At present, the research direction of SiC MOSFET is mainly focused on reducing on-resistance by improving channel mobility. Although the current methods such as NO (nitric oxide) gas environment have greatly improved channel mobility, the channel resistance still accounts for a high proportion of the total on-resistance. In order to reduce the on-resistance, engineers usually adopt a short channel solution.

[0005] However, in the blocking state, a shorter channel will have a relatively large drain leakage current; and a short channel will increase the saturation current of the device, which makes the short-circuit tolerance of the device decrease as the channel length becomes shorter. In practical applications, the requirements for leakage current and short-circuit tolerance are more stringent, so the performance of the device needs to be further improved. Summary of the invention

[0006] In order to solve the problems of high leakage current and poor short-circuit tolerance in the blocking state of SiC MOSFET devices due to short channels in the prior art, the present invention provides a SiC MOSFET device based on an asymmetric P+ shielding layer and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0007] In a first aspect, the present invention provides a SiC MOSFET device based on an asymmetric P+ shielding layer, comprising: an N+ substrate and an N- epitaxial layer located on the N+ substrate;

[0008] A P-well region is arranged in the N-epitaxial layer along the first direction; the P-well region is located on the side of the N-epitaxial layer away from the N+ substrate and has a certain space from the bottom of the N-epitaxial layer to form a drift region of the device; wherein the P-well region includes a first P-well region and a second P-well region, and the two are arranged alternately; the first direction is a direction perpendicular to the thickness of the N-epitaxial layer;

[0009] A P+ shielding layer is provided on both sides of the bottom of the second P-well region; the P+ shielding layer is connected to the second P-well region and extends upward from the horizontal position where the lower edge of the second P-well region is located to the inside of the N-epitaxial layer to form a three-dimensional asymmetric deep P-well structure;

[0010] A JFET shallow injection region is arranged directly above the P+ shielding layer; the JFET shallow injection region extends downward from the upper surface of the N- epitaxial layer and has a certain distance from the P+ shielding layer;

[0011] A JFET deep injection region is provided on one side of the JFET shallow injection region close to the first P-well region; the JFET deep injection region includes a first deep injection region and a second deep injection region; the first deep injection region is arranged adjacent to the JFET shallow injection region, and extends downward from the upper surface of the N-epitaxial layer to the same depth as the JFET shallow injection region; the second deep injection region extends downward from the lower edge of the first deep injection region to the same depth as the P+ shielding layer, and is connected to the P+ shielding layer.

[0012] In a second aspect, the present invention proposes a method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer, comprising the following steps:

[0013] Step 1: growing an N- epitaxial layer on an N+ substrate;

[0014] Step 2: using an ion implantation process and a first mask, a P-well region is formed in the N-epitaxial layer along a first direction; at the same time, a P-type base region is formed on the surface of the P-well region;

[0015] The P-well region is located on the side of the N-epitaxial layer away from the N+ substrate, and has a certain distance from the bottom of the N-epitaxial layer to form a drift region of the device; the P-well region includes a first P-well region and a second P-well region, and the two are arranged alternately; the first direction is a direction perpendicular to the thickness of the N-epitaxial layer;

[0016] Step 3: Using an ion implantation process and a second mask, an N+ source region is formed in the P-type base region;

[0017] Step 4: Using an ion implantation process and a third mask, a P+ region is formed in the N+ source region;

[0018] Step 5: Using an ion implantation process and a fourth mask, a P+ shielding layer is formed on both sides of the bottom of the second P well region;

[0019] The P+ shielding layer is connected to the second P-well region and extends upward from the horizontal position where the lower edge of the second P-well region is located to the inside of the N- epitaxial layer;

[0020] Step 6: Using the ion implantation process and the fifth mask, a JFET shallow implantation region is formed above the P+ shielding layer;

[0021] Step 7: Using an ion implantation process and a sixth mask, a first deep implantation region and a second deep implantation region are sequentially formed on a side of the JFET shallow implantation region close to the first P-well region;

[0022] The first deep injection region is arranged adjacent to the JFET shallow injection region and extends downward from the upper surface of the N-epitaxial layer to the same depth as the JFET shallow injection region; the second deep injection region extends downward from the lower edge of the first deep injection region to the same depth as the P+ shielding layer and is connected to the P+ shielding layer;

[0023] Step 8: Using thermal oxidation process and photolithography process to make a gate structure on the surface of N-epitaxial layer;

[0024] Step 9: Deposit metal on the top and bottom of the entire device to form the source and drain of the device.

[0025] Beneficial effects of the present invention:

[0026] The SiC MOSFET device based on an asymmetric P+ shielding layer provided by the present invention comprises an N+ substrate and an N-epitaxial layer located on the N+ substrate; a P-well region is arranged in the N-epitaxial layer along a first direction; the P-well region is located on a side of the N-epitaxial layer away from the N+ substrate, and has a certain space from the bottom of the N-epitaxial layer to form a drift region of the device; wherein the P-well region comprises a first P-well region and a second P-well region arranged at intervals; a P+ shielding layer is arranged on both sides of the bottom of the second P-well region; the P+ shielding layer is connected to the second P-well region, and extends upward from the horizontal position where the lower edge of the second P-well region is located to the inside of the N-epitaxial layer to form a three-dimensional asymmetric deep P-well structure. This device structure adds an asymmetric P+ shielding layer on the basis of the deep P-well structure, which allows the device to pinch off and enter the saturation region more quickly in the blocking state, thereby further reducing the leakage current. In addition, since the saturation current is reduced, the short-circuit capability is also improved. The asymmetric P+ shielding structure retains the JFET deep injection region on one side, minimizing the impact on the device's on-resistance and the device's current outflow capability, thereby improving the device performance.

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1Schematic diagram of the structure of a SiC MOSFET device based on an asymmetric P+ shielding layer provided in an embodiment of the present invention;

[0029] Figure 2 It is a schematic flow chart of a method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer provided in an embodiment of the present invention;

[0030] Figures 3a-3k It is a schematic diagram of a process for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer provided in an embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of a mask corresponding to the square cell structure provided in an embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of a mask corresponding to the stripe cell structure provided in an embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of a three-dimensional P+ shielding layer provided by an embodiment of the present invention;

[0034] Description of reference numerals:

[0035] 1-N+ substrate, 2-N-epitaxial layer, 3-P well region, 3a-first P well region, 3b-second P well region, 4-P+ shielding layer, 5-JFET shallow injection region, 6-JFET deep injection region, 6a-first deep injection region, 6b-second deep injection region, 7-P-type base region, 8-N+ source region, 9-P+ region, 10-gate structure, 10a-gate dielectric layer, 10b-polysilicon gate, 10c-interlayer dielectric ILD, 11-source, 12-drain;

[0036] A-JFET deep injection window, BP well injection window, C-P+ shielding layer injection window / JFET shallow injection window. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] The first aspect of the present invention provides a SiC MOSFET device based on an asymmetric P+ shielding layer. Figure 1 , Figure 11 is a schematic structural diagram of a SiC MOSFET device based on an asymmetric P+ shielding layer provided in an embodiment of the present invention, wherein the device comprises: an N+ substrate 1 and an N- epitaxial layer 2 located on the N+ substrate 1;

[0039] A P-well region 3 is provided in the N-epitaxial layer 2 along a first direction; the P-well region 3 is located on a side of the N-epitaxial layer 2 away from the N+ substrate 1, and has a certain space from the bottom of the N-epitaxial layer 2 to form a drift region of the device; wherein the P-well region 3 includes a first P-well region 3a and a second P-well region 3b, and the two are arranged alternately; the first direction is a direction perpendicular to the thickness of the N-epitaxial layer 2;

[0040] P+ shielding layers 4 are provided on both sides of the bottom of the second P-well region 3b; the P+ shielding layer 4 is connected to the second P-well region 3b, and extends upward from the horizontal position where the lower edge of the second P-well region 3b is located to the inside of the N-epitaxial layer 2 to form a three-dimensional asymmetric deep P-well structure;

[0041] A JFET shallow injection region 5 is provided directly above the P+ shielding layer 4; the JFET shallow injection region 5 extends downward from the upper surface of the N-epitaxial layer 2 and has a certain distance from the P+ shielding layer 4;

[0042] A JFET deep injection region 6 is provided on one side of the JFET shallow injection region 5 close to the first P-well region 3a; the JFET deep injection region 6 includes a first deep injection region 6a and a second deep injection region 6b; the first deep injection region 6a is arranged adjacent to the JFET shallow injection region 5, and extends downward from the upper surface of the N-epitaxial layer 2 to the same depth as the JFET shallow injection region 5; the second deep injection region 6b extends downward from the lower edge of the first deep injection region 6a to the same depth as the P+ shielding layer 4, and is connected to the P+ shielding layer 4.

[0043] Specifically, if Figure 1 As shown, in this embodiment, three P-well regions are designed in the N-epitaxial layer 2, wherein the first P-well region 3a is located in the middle, and the second P-well regions 3b are located on both sides; the bottom of the second P-well region 3b in the middle is provided with a P+ shielding layer 4 on both sides, and the bottom edge of the P+ shielding layer 4 is flush with the bottom edge of the second P-well region 3b. The area below the P-well region is the drift region of the device.

[0044] Understandably, Figure 1 The positional relationship between the various structures of the device is only schematically shown and does not represent its actual size.

[0045] In this embodiment, the implantation concentration of the P+ shielding layer 4 is greater than the implantation concentration of the P well region 3 .

[0046] Furthermore, the implantation concentration of the JFET shallow implantation region 5 is the same as the implantation concentration of the first deep implantation region 6 a ; and the implantation concentration of the second deep implantation region 6 b is greater than the implantation concentration of the first deep implantation region 6 a .

[0047] Optionally, as an implementation method, the implantation concentration of each implantation region in this embodiment is designed as follows: the implantation concentration of the P-well region 3 is 8×10 15 ~1×10 18 ; The injection concentration of P+ shielding layer 4 is 8×10 16 ~1×10 18 ;

[0048] The implantation concentration of the JFET shallow implantation region 5 and the first deep implantation region 6a in the JFET deep implantation region 6 is 1×10 16 ~2×10 17 The second deep implantation region 6b has an implantation concentration of 5×10 16 ~2×10 18 .

[0049] The present invention designs the injection concentration of the P+ shielding layer 4 to be greater than the injection concentration of the P well region 3, which can achieve rapid pinch-off of the device; at the same time, a higher injection concentration is used for the JFET shallow injection region 5, which can reduce the on-resistance and improve the outflow capacity.

[0050] In this way, by adding an asymmetric P+ shielding layer on the basis of the P-well structure, the leakage current can be further reduced by pinching off the saturation region more quickly in the blocking state; since the saturation current is reduced, the short-circuit capability is also improved. In addition, the asymmetric P+ shielding structure retains the JFET deep injection region on one side, which minimizes the impact on the device's on-resistance and the device's outflow capability.

[0051] For further information, please see Figure 1 , wherein the surface layer of the second P-well region 3b on one side of the JFET shallow injection region 5 and the surface layer of the first P-well region 3a on one side of the JFET deep injection region 6 are also symmetrically provided with a P-type base region 7, an N+ source region 8 and a P+ region 9; and the edge of the P-type base region 7 is aligned with the edge of the second P-well region 3b or the first P-well region 3a.

[0052] Specifically, if Figure 1As shown, on the surface layer of the first P-well region 3a on the far left, a P-type base region 7, an N+ source region 8 and a P+ region 9 are sequentially designed from right to left; on the surface layer of the second P-well region 3b in the middle, a P-type base region 7, an N+ source region 8 and a P+ region 9 are sequentially designed from left to right on its left half, so as to form a symmetrical structure with respect to the JFET deep injection region 6 and the JFET shallow injection region 5 with the surface layer of the first P-well region 3a on the left. On the right half of the surface layer of the second P-well region 3b in the middle, a P-type base region 7, an N+ source region 8 and a P+ region 9 are sequentially designed from right to left, and on the surface layer of the first P-well region 3a on the far right, a P-type base region 7, an N+ source region 8 and a P+ region 9 are sequentially designed from left to right, so as to form a symmetrical structure with respect to the JFET deep injection region 6 and the JFET shallow injection region 5 with the right half of the surface layer of the second P-well region 3b in the middle.

[0053] It is understandable that the device provided in this embodiment further includes a gate structure 10, which is arranged on the surface of the N-epitaxial layer 2 above the JFET shallow injection region 5 and the JFET deep injection region 6; wherein the gate structure 10 can be a planar gate structure or a non-trench separated gate structure.

[0054] Optionally, as an implementation method, this embodiment adopts Figure 1 In the planar gate structure shown, it can be seen that the gate structure 10 specifically includes a gate dielectric layer 10a, a polysilicon gate 10b and an interlayer dielectric ILD 10c; wherein the gate dielectric layer 10a is arranged on the upper surface of the N-epitaxial layer 2, and its projection in the thickness direction of the N-epitaxial layer 2 covers the JFET shallow implantation region 5, and extends to both sides to partially cover the N+ source region 8;

[0055] The polysilicon gate 10b is located on the upper surface of the gate dielectric layer 10a;

[0056] The interlayer dielectric ILD 10c covers the gate dielectric layer 10a and the gate dielectric layer 10a and both sides of the gate dielectric layer 10a.

[0057] It should be noted that Figure 1 The positional relationship and thickness of the gate dielectric layer 10 a , the polysilicon gate 10 b and the interlayer dielectric ILD 10 c are only schematically shown, and do not represent their actual sizes.

[0058] For further information, please see Figure 1 , the device also includes a source electrode 11 and a drain electrode 12;

[0059] The source electrode 11 is arranged at the top of the entire device and is in contact with the N+ source region 8, the P+ region 9 and the interlayer dielectric ILD 10c;

[0060] The drain 12 is arranged at the bottom of the entire device and contacts the lower surface of the N+ substrate 1 .

[0061] It is understandable that the source 11 and the drain 12 can be implemented by using source and drain metals commonly used in the art.

[0062] The device provided by the present invention adds an asymmetric P+ shielding layer on the basis of the deep P-well structure, so that the device can be cut off and enter the saturation region more quickly in the blocking state, thereby further reducing the leakage current; in addition, since the saturation current is reduced, the short-circuit capability is also improved; and the asymmetric P+ shielding structure retains the JFET deep injection region on one side, which minimizes the impact on the on-resistance and the outflow capacity of the device, thereby improving the device performance.

[0063] Based on the same inventive concept, the second aspect of the present invention also provides a method for preparing a SiCMOSFET device based on an asymmetric P+ shielding layer. Figure 2 The schematic diagram of the preparation method shown and Figures 3a-3k The schematic diagram of the preparation process shown in the figure describes in detail the preparation method of the SiC MOSFET device based on the asymmetric P+ shielding layer provided in this embodiment.

[0064] The method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer provided in this embodiment mainly comprises the following steps:

[0065] Step 1: Grow an N- epitaxial layer 2 on an N+ substrate 1.

[0066] Specifically, the N+ substrate 1 is a heavily doped Si substrate or SiC substrate, and a lightly doped SiC is epitaxially grown on the SiC substrate by an epitaxial process to form an N- epitaxial layer 2, such as Figure 3a shown.

[0067] Step 2: Using an ion implantation process and a first mask, a P-well region 3 is formed in the N-epitaxial layer 2 along a first direction; at the same time, a P-type base region 7 is formed on the surface of the P-well region 3 .

[0068] Specifically, a photoresist is used as a first mask, and Al ions are implanted on the side of the N-epitaxial layer 2 away from the N+ substrate 1 to form a plurality of P-well regions 3 in a direction perpendicular to the thickness of the N-epitaxial layer 2, that is, in a horizontal direction; wherein the P-well region 3 has a certain distance from the bottom of the N-epitaxial layer 2 to form a drift region of the device; and the P-well region includes a first P-well region 3a and a second P-well region 3b, and the two are arranged alternately; at the same time, a P-type base region 7 is formed on the top of the first P-well region 3a and the second P-well region 3b, as shown in FIG. Figure 3b shown.

[0069] Step 3: Using an ion implantation process and a second mask, an N+ source region 8 is formed in the P-type base region 7 .

[0070] Specifically, a photoresist is used as a second mask to implant N ions into the P-type base region 7 to form an N+ source region 8, such as Figure 3c shown.

[0071] Step 4: Using an ion implantation process and a third mask, a P+ region 9 is formed in the N+ source region 8 .

[0072] Specifically, a photoresist is used as the third mask, and Al ions are implanted into the N+ source region 8 to form the P+ region 9, as shown in FIG. Figure 3d shown.

[0073] Step 5: using an ion implantation process and a fourth mask, a P+ shielding layer 4 is formed on both sides of the bottom of the second P well region 3b;

[0074] The P+ shielding layer 4 is connected to the second P-well region 3 b and extends upward from the horizontal position where the lower edge of the second P-well region 3 b is located to the inside of the N- epitaxial layer 2 .

[0075] Specifically, a photoresist is used as a fourth mask, and Al ions are implanted at both sides of the bottom of the second P well region 3b to form a P+ shielding layer 4, such as Figure 3e shown.

[0076] Optionally, as an implementation method, on the fourth mask provided in this embodiment, a JFET deep injection window A, a P well injection window B, and a P+ shielding layer injection window C are set, and the P+ shielding layer injection window C is shared with the JFET shallow injection window.

[0077] It can be understood that in the mask corresponding to the square cell structure, the P well injection window B is arranged in an array in the JFET deep injection window A according to the square cell arrangement; the P+ shielding layer injection window C is distributed at intervals around the P well injection window B to form an asymmetric P+ shielding layer structure with the surrounding four cells, such as Figure 4 shown.

[0078] Correspondingly, in the mask corresponding to the stripe cell structure, the P well injection window B is distributed in the JFET deep injection window A according to the stripe cell arrangement; the P+ shielding layer injection window C is distributed at intervals on both sides of the P well injection window B, as shown in FIG. Figure 5 shown.

[0079] The layout design of the fourth mask effectively increases the utilization area of ​​the source region. The three-dimensional structure of the P+ shielding layer formed by step 5 is as follows: Figure 6 shown.

[0080] Step 6: Using an ion implantation process and a fifth mask, a JFET shallow implantation region 5 is formed above the P+ shielding layer 4 .

[0081] It can be understood that, since the JFET shallow implantation region 5 is located directly above the P+ shielding layer 4 in the vertical direction, the same mask can be used for both, that is, the fifth mask here can be replaced by the fourth mask in step 5 .

[0082] Using the fourth mask, N ion implantation is performed in the N-epitaxial layer 2 above the P+ shielding layer 4 to implant the JFET shallow implantation region 5, such as Figure 3f shown.

[0083] Step 7: Using an ion implantation process and a sixth mask, a first deep implantation region 6a and a second deep implantation region 6b are sequentially formed on a side of the JFET shallow implantation region 5 close to the first P-well region 3a.

[0084] Specifically, a photoresist is used as the sixth mask, and N ions with corresponding energies and doses are sequentially injected into the JFET shallow injection region 5 near the first P well region 3a to sequentially form a first deep injection region 6a and a second deep injection region 6b. Figure 3g shown.

[0085] Among them, the first deep injection region 6a is arranged adjacent to the JFET shallow injection region 5, and extends downward from the upper surface of the N-epitaxial layer 2 to the same depth as the JFET shallow injection region 5; the second deep injection region 6b extends downward from the lower edge of the first deep injection region 6a to the same depth as the P+ shielding layer 4, and is connected to the P+ shielding layer 4.

[0086] Step 8: A gate structure 10 is fabricated on the surface of the N-epitaxial layer 2 by using a thermal oxidation process and a photolithography process.

[0087] First, on the surface of the N-epitaxial layer 2, an oxide is grown by a thermal oxidation process, and a gate dielectric layer 10a is obtained by a mask etching process, such as Figure 3h shown.

[0088] The gate dielectric layer 10 a is located on the upper surface of the N-epitaxial layer 2 , and its projection in the thickness direction of the N-epitaxial layer 2 covers the JFET shallow implantation region 5 , and extends to both sides to partially cover the N+ source region 8 .

[0089] Then, a deposition process is used to deposit polysilicon on the gate dielectric layer 10a, and an etching process is used to form a polysilicon gate 10b. Figure 3i shown.

[0090] Finally, an interlayer dielectric ILD 10c is deposited on and on both sides of the polysilicon gate 10b through a deposition process to form a complete gate structure 10, and a source contact hole is formed through an etching process, such as Figure 3j shown.

[0091] Step 9: Deposit metal on the top and bottom of the entire device to form the source 11 and drain 12 of the device.

[0092] Specifically, after the ohmic contact process and the deposition process, metal is deposited on the N+ source region 8, the P+ region 9, and the interlayer dielectric ILD10c to form the source 11, and metal is deposited on the bottom of the device to form the drain 12, as shown in FIG. Figure 3k shown.

[0093] At this point, the preparation of SiC MOSFET devices based on asymmetric P+ shielding layer has been completed.

[0094] Optionally, as an implementation method, the depth, width, and implantation concentration or doping concentration of each device structure involved in the above-mentioned preparation process can be set according to the parameter range of Table 1 below.

[0095] Table 1 Reference parameters for each region

[0096]

[0097] In addition, it should be noted that the epitaxial growth process, ion implantation process, photolithography process, deposition process, etc. used in the process of preparing the SiC MOSFET device based on the asymmetric P+ shielding layer in this embodiment are all existing mature processes, and the relevant parameter settings can also be implemented by referring to the existing related technologies.

[0098] The preparation method provided in the second aspect of the present invention can be used to prepare the SiC MOSFET device based on the asymmetric P+ shielding layer provided in the first aspect, and therefore has similar beneficial effects as the device embodiment of the first aspect. For technical details not disclosed in the preparation method embodiment of the present invention, they can be understood by referring to the description of the device embodiment.

[0099] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0100] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0101] In the description of the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0102] In the description of the present invention, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0103] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A SiC MOSFET device based on an asymmetric P+ shielding layer, characterized in that: include: An N+ substrate (1) and an N- epitaxial layer (2) located on the N+ substrate (1); A P-well region (3) is arranged in the N-epitaxial layer (2) along a first direction; the P-well region (3) is located on a side of the N-epitaxial layer (2) away from the N+ substrate (1), and has a certain distance from the bottom of the N-epitaxial layer (2) to form a drift region of the device; wherein the P-well region (3) includes a first P-well region (3a) and a second P-well region (3b), and the two are arranged at intervals; the first direction is a direction perpendicular to the thickness of the N-epitaxial layer (2); P+ shielding layers (4) are provided on both sides of the bottom of the second P-well region (3b); the P+ shielding layer (4) is connected to the second P-well region (3b) and extends upward from the horizontal position where the lower edge of the second P-well region (3b) is located to the inside of the N-epitaxial layer (2) to form a three-dimensional asymmetric deep P-well structure; A JFET shallow injection region (5) is arranged directly above the P+ shielding layer (4); the JFET shallow injection region (5) extends downward from the upper surface of the N-epitaxial layer (2) and has a certain distance from the P+ shielding layer (4); A JFET deep injection region (6) is provided on one side of the JFET shallow injection region (5) close to the first P well region (3a); the JFET deep injection region (6) comprises a first deep injection region (6a) and a second deep injection region (6b); the first deep injection region (6a) is arranged adjacent to the JFET shallow injection region (5), and extends downward from the upper surface of the N-epitaxial layer (2) to the same depth as the JFET shallow injection region (5); the second deep injection region (6b) extends downward from the lower edge of the first deep injection region (6a) to the same depth as the P+ shielding layer (4), and is connected to the P+ shielding layer (4).

2. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 1, characterized in that: The injection concentration of the P+ shielding layer (4) is greater than the injection concentration of the P well region (3).

3. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 1, characterized in that: The injection concentration of the JFET shallow injection region (5) is the same as the injection concentration of the first deep injection region (6a); and the injection concentration of the second deep injection region (6b) is greater than the injection concentration of the first deep injection region (6a).

4. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 1, characterized in that: The implantation concentration of the P well region (3) is 8×10 15 ~1×10 18 The implantation concentration of the P+ shielding layer (4) is 8×10 16 ~1×10 18 ; The injection concentration of the JFET shallow injection region (5) and the first deep injection region (6a) in the JFET deep injection region (6) is 1×10 16 ~2×10 17 The implantation concentration of the second deep implantation region (6b) is 5×10 16 ~2×10 18 .

5. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 1, characterized in that: The surface layer of the second P-well region (3b) on one side of the JFET shallow injection region (5) and the surface layer of the first P-well region (3a) on one side of the JFET deep injection region (6) are also symmetrically provided with a P-type base region (7), an N+ source region (8) and a P+ region (9); and the edge of the P-type base region (7) is aligned with the edge of the second P-well region (3b) or the edge of the first P-well region (3a).

6. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 5, characterized in that: It also includes a gate structure (10); the gate structure (10) is arranged on the surface of the N-epitaxial layer (2) above the JFET shallow injection region (5) and the JFET deep injection region (6); wherein the gate structure (10) is a planar gate structure or a non-trench separated gate structure.

7. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 6, characterized in that: The gate structure (10) comprises a gate dielectric layer (10a), a polysilicon gate (10b) and an interlayer dielectric ILD (10c); wherein the gate dielectric layer (10a) is arranged on the upper surface of the N-epitaxial layer (2), and its projection in the thickness direction of the N-epitaxial layer (2) covers the JFET shallow injection region (5), and extends to both sides to partially cover the N+ source region (8); The polysilicon gate (10b) is located on the upper surface of the gate dielectric layer (10a); The interlayer dielectric ILD (10c) covers the gate dielectric layer (10a) as well as the gate dielectric layer (10a) and both sides of the gate dielectric layer (10a).

8. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 7, characterized in that: Also includes a source electrode (11) and a drain electrode (12); The source electrode (11) is arranged at the top of the entire device and is in contact with the N+ source region (8), the P+ region (9) and the interlayer dielectric ILD (10c); The drain electrode (12) is arranged at the bottom of the entire device and is in contact with the lower surface of the N+ substrate (1).

9. A method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer, characterized in that: The following steps are involved: Step 1: growing an N- epitaxial layer on an N+ substrate; Step 2: using an ion implantation process and a first mask to form a P-well region along a first direction in the N-epitaxial layer; and at the same time, forming a P-type base region on the surface of the P-well region; The P-well region is located on a side of the N-epitaxial layer away from the N+ substrate, and has a certain distance from the bottom of the N-epitaxial layer to form a drift region of the device; the P-well region includes a first P-well region and a second P-well region, and the two are arranged alternately; the first direction is a direction perpendicular to the thickness of the N-epitaxial layer; Step 3: using an ion implantation process and a second mask to form an N+ source region in the P-type base region; Step 4: using an ion implantation process and a third mask to form a P+ region in the N+ source region; Step 5: using an ion implantation process and a fourth mask to form a P+ shielding layer on both sides of the bottom of the second P well region; Wherein, the P+ shielding layer is connected to the second P-well region, and extends upward from the horizontal position where the lower edge of the second P-well region is located to the inside of the N- epitaxial layer; Step 6: Using an ion implantation process and a fifth mask, a JFET shallow implantation region is formed above the P+ shielding layer; Step 7: using an ion implantation process and a sixth mask, sequentially forming a first deep implantation region and a second deep implantation region on a side of the JFET shallow implantation region close to the first P-well region; The first deep injection region is arranged adjacent to the JFET shallow injection region and extends downward from the upper surface of the N-epitaxial layer to the same depth as the JFET shallow injection region; the second deep injection region extends downward from the lower edge of the first deep injection region to the same depth as the P+ shielding layer and is connected to the P+ shielding layer; Step 8: fabricating a gate structure on the surface of the N-epitaxial layer by using a thermal oxidation process and a photolithography process; Step 9: Electrode metal is applied to the top and bottom of the entire device to form the source and drain of the device.

10. The method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 9, characterized in that: The fourth mask in step 5 is the same as the fifth mask in step 6, both of which include a JFET deep injection window, a P well injection window, and a P+ shielding layer injection window, and the P+ shielding layer injection window is shared with the JFET shallow injection window; In the mask corresponding to the square cell structure, the P well injection windows are arranged in an array in the JFET deep injection window according to the square cell arrangement; the P+ shielding layer injection windows are distributed at intervals around the P well injection window to form an asymmetric P+ shielding layer structure with the surrounding four cells; In the mask corresponding to the stripe cell structure, the P-well injection windows are distributed in the JFET deep injection window in a stripe cell arrangement; and the P+ shielding layer injection windows are distributed at intervals on both sides of the P-well injection window.

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