SiC MOSFET device based on asymmetric P+ shielding layer and preparation method thereof

Abstract

The present invention discloses a SiC MOSFET device based on an asymmetric P+ shielding layer and a preparation method thereof, belonging to the field of semiconductor technology. The device comprises: an N+ substrate and an N-epitaxial layer located on the N+ substrate; a P-well region is arranged in the N-epitaxial layer along a first direction; the P-well region is located on the side of the N-epitaxial layer away from the N+ substrate and has a certain distance from the bottom of the N-epitaxial layer to form a drift region of the device; wherein the P-well region comprises a first P-well region and a second P-well region, and the two are arranged at intervals; the first direction is a direction perpendicular to the thickness of the N-epitaxial layer; a P+ shielding layer is provided on both sides of the bottom of the second P-well region; the P+ shielding layer is connected to the second P-well region and extends upward from the horizontal position of the lower edge of the second P-well region to the inside of the N-epitaxial layer to form a three-dimensional asymmetric deep P-well structure. This structural design reduces the leakage current caused by the short channel and improves the short-circuit tolerance of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a SiC MOSFET device based on an asymmetric P+ shielding layer and a preparation method thereof. Background Art

[0002] Semiconductor technology has played a decisive role in the development of the power electronics industry. Power semiconductor devices, in particular, have long been considered a key component of power electronics. With the widespread application of power electronics in industries such as industry, healthcare, transportation, and consumer electronics, power semiconductors have a direct impact on the cost and efficiency of these devices.

[0003] In recent years, the rapid development of SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) technology has attracted widespread attention to this new generation of power devices.

[0004] Currently, SiC MOSFET research focuses on reducing on-resistance by increasing channel mobility. While current methods, such as using a NO (nitric oxide) gas environment, have significantly increased channel mobility, channel resistance still accounts for a significant portion of the total on-resistance. To reduce on-resistance, engineers typically employ short-channel solutions.

[0005] However, in the blocking state, a shorter channel results in a higher drain leakage current; a shorter channel also increases the device's saturation current, which causes the device's short-circuit withstand capability to decrease as the channel length shortens. In practical applications, the requirements for leakage current and short-circuit withstand are even more stringent, necessitating further improvements in device performance. Summary of the Invention

[0006] In order to solve the problems of high leakage current and poor short-circuit withstand capability in the blocking state caused by short channel in the existing SiC MOSFET devices, the present invention provides a SiC MOSFET device based on an asymmetric P+ shielding layer and a preparation method thereof. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a SiC MOSFET device based on an asymmetric P+ shielding layer, comprising: an N+ substrate and an N- epitaxial layer located on the N+ substrate;

[0008] A P-well region is provided in the N-epitaxial layer along a first direction. The P-well region is located on a side of the N-epitaxial layer facing away from the N+ substrate and has a certain distance from the bottom of the N-epitaxial layer to form a drift region of the device. The P-well region includes a first P-well region and a second P-well region, and the two are arranged alternately. The first direction is a direction perpendicular to the thickness of the N-epitaxial layer.

[0009] P+ shielding layers are provided on both sides of the bottom of the second P-well region; the P+ shielding layer is connected to the second P-well region and extends upward from the horizontal position of the lower edge of the second P-well region to the inside of the N-epitaxial layer to form a three-dimensional asymmetric deep P-well structure;

[0010] A JFET shallow injection region is provided directly above the P+ shielding layer; the JFET shallow injection region extends downward from the upper surface of the N- epitaxial layer and has a certain distance between it and the P+ shielding layer;

[0011] A JFET deep injection region is provided on one side of the JFET shallow injection region close to the first P-well region; the JFET deep injection region includes a first deep injection region and a second deep injection region; the first deep injection region is arranged adjacent to the JFET shallow injection region, and extends downward from the upper surface of the N-epitaxial layer to the same depth as the JFET shallow injection region; the second deep injection region extends downward from the lower edge of the first deep injection region to the same depth as the P+ shielding layer, and is connected to the P+ shielding layer.

[0012] In a second aspect, the present invention provides a method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer, comprising the following steps:

[0013] Step 1: growing an N- epitaxial layer on an N+ substrate;

[0014] Step 2: Using an ion implantation process and a first mask, a P-well region is formed along a first direction in the N-epitaxial layer; at the same time, a P-type base region is formed on the surface of the P-well region;

[0015] The P-well region is located on the side of the N-epitaxial layer facing away from the N+ substrate, and has a certain distance from the bottom of the N-epitaxial layer to form a drift region of the device; the P-well region includes a first P-well region and a second P-well region, and the two are arranged alternately; the first direction is perpendicular to the thickness of the N-epitaxial layer;

[0016] Step 3: Use ion implantation and a second mask to form an N+ source region in the P-type base region;

[0017] Step 4: Use the ion implantation process and the third mask to form a P+ region in the N+ source region;

[0018] Step 5: Using an ion implantation process and a fourth mask, a P+ shielding layer is formed on both sides of the bottom of the second P-well region;

[0019] The P+ shielding layer is connected to the second P-well region and extends upward from the horizontal position of the lower edge of the second P-well region to the inside of the N- epitaxial layer;

[0020] Step 6: Using the ion implantation process and the fifth mask, a JFET shallow implantation region is formed above the P+ shielding layer;

[0021] Step 7: Using an ion implantation process and a sixth mask, a first deep implantation region and a second deep implantation region are sequentially formed on a side of the JFET shallow implantation region close to the first P-well region;

[0022] The first deep injection region is arranged adjacent to the JFET shallow injection region and extends downward from the upper surface of the N-epitaxial layer to the same depth as the JFET shallow injection region; the second deep injection region extends downward from the lower edge of the first deep injection region to the same depth as the P+ shielding layer and is connected to the P+ shielding layer;

[0023] Step 8: Using thermal oxidation process and photolithography process to make gate structure on the surface of N-epitaxial layer;

[0024] Step 9: Deposit metal on the top and bottom of the entire device to form the source and drain of the device.

[0025] Beneficial effects of the present invention:

[0026] The SiC MOSFET device based on an asymmetric P+ shielding layer provided by the present invention includes an N+ substrate and an N-epitaxial layer located on the N+ substrate; a P-well region is arranged in a first direction within the N-epitaxial layer; the P-well region is located on a side of the N-epitaxial layer away from the N+ substrate and has a certain distance from the bottom of the N-epitaxial layer to form a drift region of the device; wherein the P-well region includes a first P-well region and a second P-well region arranged at intervals; a P+ shielding layer is provided on both sides of the bottom of the second P-well region; the P+ shielding layer is connected to the second P-well region and extends upward from the horizontal position of the lower edge of the second P-well region to the interior of the N-epitaxial layer to form a three-dimensional asymmetric deep P-well structure. This device structure adds an asymmetric P+ shielding layer to the deep P-well structure, allowing the device to pinch off and enter the saturation region more quickly in the blocking state, further reducing leakage current. In addition, since the saturation current is reduced, the short-circuit capability is also improved. The asymmetric P+ shielding structure retains the JFET deep injection region on one side, minimizing the impact on the device's on-resistance and current outflow capability, thereby improving device performance.

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1Schematic diagram of the structure of a SiC MOSFET device based on an asymmetric P+ shielding layer provided by an embodiment of the present invention;

[0029] Figure 2 1 is a flow chart of a method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer provided by an embodiment of the present invention;

[0030] Figures 3a-3k Schematic diagram of the process for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer according to an embodiment of the present invention;

[0031] Figure 4 Schematic diagram of a mask corresponding to the square cell structure provided by an embodiment of the present invention;

[0032] Figure 5 Schematic diagram of a mask corresponding to the stripe cell structure provided by an embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of a three-dimensional P+ shielding layer provided by an embodiment of the present invention;

[0034] Description of reference numerals:

[0035] 1-N+ substrate, 2-N-epitaxial layer, 3-P well region, 3a-first P well region, 3b-second P well region, 4-P+ shielding layer, 5-JFET shallow injection region, 6-JFET deep injection region, 6a-first deep injection region, 6b-second deep injection region, 7-P-type base region, 8-N+ source region, 9-P+ region, 10-gate structure, 10a-gate dielectric layer, 10b-polysilicon gate, 10c-interlayer dielectric ILD, 11-source, 12-drain;

[0036] A-JFET deep injection window, BP well injection window, C-P+ shielding layer injection window / JFET shallow injection window. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0038] The first aspect of the present invention provides a SiC MOSFET device based on an asymmetric P+ shielding layer. Figure 1 , Figure 1Schematic diagram of the structure of a SiC MOSFET device based on an asymmetric P+ shielding layer provided by an embodiment of the present invention, the device includes: an N+ substrate 1 and an N- epitaxial layer 2 located on the N+ substrate 1;

[0039] A P-well region 3 is provided in the N-epitaxial layer 2 along a first direction. The P-well region 3 is located on the side of the N-epitaxial layer 2 facing away from the N+ substrate 1 and has a certain distance from the bottom of the N-epitaxial layer 2 to form a drift region of the device. The P-well region 3 includes a first P-well region 3a and a second P-well region 3b, which are arranged alternately. The first direction is perpendicular to the thickness of the N-epitaxial layer 2.

[0040] P+ shielding layers 4 are provided on both sides of the bottom of the second P-well region 3b. The P+ shielding layers 4 are connected to the second P-well region 3b and extend upward from the horizontal position of the lower edge of the second P-well region 3b to the interior of the N-epitaxial layer 2 to form a three-dimensional asymmetric deep P-well structure.

[0041] A JFET shallow injection region 5 is provided directly above the P+ shielding layer 4; the JFET shallow injection region 5 extends downward from the upper surface of the N- epitaxial layer 2 and has a certain distance between it and the P+ shielding layer 4;

[0042] A JFET deep injection region 6 is provided on one side of the JFET shallow injection region 5 close to the first P-well region 3a; the JFET deep injection region 6 includes a first deep injection region 6a and a second deep injection region 6b; the first deep injection region 6a is arranged adjacent to the JFET shallow injection region 5, and extends downward from the upper surface of the N-epitaxial layer 2 to the same depth as the JFET shallow injection region 5; the second deep injection region 6b extends downward from the lower edge of the first deep injection region 6a to the same depth as the P+ shielding layer 4, and is connected to the P+ shielding layer 4.

[0043] Specifically, if Figure 1 As shown, this embodiment designs three P-well regions within the N-epitaxial layer 2. The center region is the first P-well region 3a, and the two flanking regions are the second P-well regions 3b. P+ shielding layers 4 are located on both sides of the bottom of the second P-well region 3b, with the bottom edges of the P+ shielding layers 4 flush with the bottom edges of the second P-well region 3b. The area below the P-well regions serves as the device's drift region.

[0044] It is understandable that Figure 1 The positional relationship between the various structures of the device is only schematically shown and does not represent its actual size.

[0045] In this embodiment, the implantation concentration of the P+ shielding layer 4 is greater than the implantation concentration of the P-well region 3 .

[0046] Furthermore, the implantation concentration of the JFET shallow implantation region 5 is the same as the implantation concentration of the first deep implantation region 6 a ; and the implantation concentration of the second deep implantation region 6 b is greater than the implantation concentration of the first deep implantation region 6 a .

[0047] Optionally, as an implementation method, the implantation concentration of each implantation region is designed as follows in this embodiment: the implantation concentration of the P-well region 3 is 8×10 15 ~1×10 18 ; The injection concentration of the P+ shielding layer 4 is 8×10 16 ~1×10 18 ;

[0048] The implantation concentration of the JFET shallow implantation region 5 and the first deep implantation region 6a in the JFET deep implantation region 6 is 1×10 16 ~2×10 17 The second deep implantation region 6b has an implantation concentration of 5×10 16 ~2×10 18 .

[0049] The present invention designs the injection concentration of the P+ shielding layer 4 to be greater than the injection concentration of the P well region 3, which can achieve rapid device pinch-off; at the same time, the JFET shallow injection region 5 is matched with a higher injection concentration, which can reduce the on-resistance and improve the outflow capacity.

[0050] By adding an asymmetric P+ shield layer to the P-well structure, the device can enter the saturation region more quickly in the blocking state, further reducing leakage current. This reduced saturation current also improves short-circuit capability. Furthermore, the asymmetric P+ shield structure preserves the deep JFET implant region on one side, minimizing the impact on the device's on-resistance and current capability.

[0051] For further information, please see Figure 1 , wherein the surface layer of the second P-well region 3b on the side of the JFET shallow injection region 5 and the surface layer of the first P-well region 3a on the side of the JFET deep injection region 6 are also symmetrically provided with a P-type base region 7, an N+ source region 8 and a P+ region 9; and the edge of the P-type base region 7 is aligned with the edge of the second P-well region 3b or the first P-well region 3a.

[0052] Specifically, if Figure 1As shown, on the surface layer of the first P-well region 3a on the far left, a P-type base region 7, an N+ source region 8, and a P+ region 9 are sequentially designed from right to left; on the surface layer of the second P-well region 3b in the middle, a P-type base region 7, an N+ source region 8, and a P+ region 9 are sequentially designed from left to right, so as to form a symmetrical structure with the surface layer of the first P-well region 3a on the left relative to the JFET deep injection region 6 and the JFET shallow injection region 5. On the right half of the surface layer of the second P-well region 3b in the middle, a P-type base region 7, an N+ source region 8, and a P+ region 9 are sequentially designed from right to left; on the surface layer of the first P-well region 3a on the far right, a P-type base region 7, an N+ source region 8, and a P+ region 9 are sequentially designed from left to right, so as to form a symmetrical structure with the right half of the surface layer of the second P-well region 3b in the middle relative to the JFET deep injection region 6 and the JFET shallow injection region 5.

[0053] It is understandable that the device provided in this embodiment further includes a gate structure 10, which is arranged on the surface of the N-epitaxial layer 2 above the JFET shallow injection region 5 and the JFET deep injection region 6; wherein the gate structure 10 can be a planar gate structure or a non-trench separated gate structure.

[0054] Optionally, as an implementation method, this embodiment adopts Figure 1 In the planar gate structure shown, it can be seen that the gate structure 10 specifically includes a gate dielectric layer 10a, a polysilicon gate 10b, and an interlayer dielectric ILD 10c. The gate dielectric layer 10a is disposed on the upper surface of the N-epitaxial layer 2, and its projection in the thickness direction of the N-epitaxial layer 2 covers the JFET shallow implant region 5 and extends to both sides to partially cover the N+ source region 8.

[0055] The polysilicon gate 10b is located on the upper surface of the gate dielectric layer 10a;

[0056] The interlayer dielectric ILD 10 c covers the gate dielectric layer 10 a and the gate dielectric layer 10 a and both sides of the gate dielectric layer 10 a.

[0057] It should be noted that Figure 1 The positional relationship and thickness of the gate dielectric layer 10 a , the polysilicon gate 10 b and the interlayer dielectric ILD 10 c are only schematically shown, and do not represent their actual sizes.

[0058] For further information, please see Figure 1 , the device further includes a source electrode 11 and a drain electrode 12;

[0059] The source electrode 11 is arranged at the top of the entire device and contacts the N+ source region 8, the P+ region 9 and the interlayer dielectric ILD 10c;

[0060] The drain 12 is arranged at the bottom of the entire device and contacts the lower surface of the N+ substrate 1 .

[0061] It is understandable that the source 11 and the drain 12 can be implemented using source and drain metals commonly used in the art.

[0062] The device provided by the present invention adds an asymmetric P+ shielding layer on the basis of the deep P-well structure, so that the device can be cut off and enter the saturation region more quickly in the blocking state, which can further reduce the leakage current; in addition, since the saturation current is reduced, the short-circuit capability is also improved; and the asymmetric P+ shielding structure retains the JFET deep injection region on one side, which minimizes the impact on the device's on-resistance and the device's outflow capacity, thereby improving the device performance.

[0063] Based on the same inventive concept, the second aspect of the present invention also provides a method for preparing a SiCMOSFET device based on an asymmetric P+ shielding layer. Figure 2 The schematic diagram of the preparation method shown and Figures 3a-3k The schematic diagram of the manufacturing process shown in the figure provides a detailed description of the manufacturing method of the SiC MOSFET device based on the asymmetric P+ shielding layer provided in this embodiment.

[0064] The method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer provided in this embodiment mainly includes the following steps:

[0065] Step 1: Grow an N- epitaxial layer 2 on an N+ substrate 1.

[0066] Specifically, the N+ substrate 1 is a heavily doped Si substrate or SiC substrate, and a lightly doped SiC is epitaxially grown on the SiC substrate through an epitaxial process to form an N- epitaxial layer 2, as shown in FIG. Figure 3a shown.

[0067] Step 2: Using an ion implantation process and a first mask, a P-well region 3 is formed along a first direction in the N-epitaxial layer 2 ; at the same time, a P-type base region 7 is formed on the surface of the P-well region 3 .

[0068] Specifically, a photoresist is used as a first mask, and Al ions are implanted on the side of the N-epitaxial layer 2 facing away from the N+ substrate 1 to form multiple P-well regions 3 in a direction perpendicular to the thickness of the N-epitaxial layer 2, that is, in the horizontal direction; wherein the P-well region 3 has a certain distance from the bottom of the N-epitaxial layer 2 to form a drift region of the device; and the P-well region includes a first P-well region 3a and a second P-well region 3b, and the two are arranged at intervals; at the same time, a P-type base region 7 is formed on the top of the first P-well region 3a and the second P-well region 3b, as shown in FIG. Figure 3b shown.

[0069] Step 3: Using an ion implantation process and a second mask, an N+ source region 8 is formed in the P-type base region 7 .

[0070] Specifically, a photoresist is used as a second mask to implant N ions into the P-type base region 7 to form an N+ source region 8, as shown in FIG. Figure 3c shown.

[0071] Step 4: Using an ion implantation process and a third mask, a P+ region 9 is formed in the N+ source region 8 .

[0072] Specifically, photoresist is used as the third mask, Al ions are implanted into the N+ source region 8 to form the P+ region 9, as shown in FIG. Figure 3d shown.

[0073] Step 5: Using an ion implantation process and a fourth mask, a P+ shielding layer 4 is formed on both sides of the bottom of the second P-well region 3b;

[0074] The P+ shielding layer 4 is connected to the second P-well region 3 b and extends upward from the horizontal position of the lower edge of the second P-well region 3 b to the inside of the N- epitaxial layer 2 .

[0075] Specifically, a photoresist is used as the fourth mask, and Al ions are implanted at both sides of the bottom of the second P well region 3b to form a P+ shielding layer 4, as shown in FIG. Figure 3e shown.

[0076] Optionally, as an implementation method, a JFET deep injection window A, a P well injection window B, and a P+ shielding layer injection window C are set on the fourth mask provided in this embodiment, and the P+ shielding layer injection window C is shared with the JFET shallow injection window.

[0077] It can be understood that in the mask corresponding to the square cell structure, the P-well injection window B is arrayed in the JFET deep injection window A according to the square cell arrangement; the P+ shielding layer injection window C is spaced apart and distributed around the P-well injection window B to form an asymmetric P+ shielding layer structure with the surrounding four cells, as shown in FIG. Figure 4 shown.

[0078] Correspondingly, in the mask corresponding to the stripe cell structure, the P-well injection window B is distributed in the JFET deep injection window A according to the stripe cell arrangement; the P+ shielding layer injection window C is distributed on both sides of the P-well injection window B at intervals, as shown in FIG. Figure 5 shown.

[0079] The layout design of the fourth mask effectively increases the utilization area of ​​the source region. The three-dimensional structure of the P+ shielding layer formed in step 5 is as follows: Figure 6 shown.

[0080] Step 6: Using an ion implantation process and a fifth mask, a JFET shallow implantation region 5 is formed above the P+ shielding layer 4 .

[0081] It is understandable that, since the JFET shallow injection region 5 is located directly above the P+ shielding layer 4 in the vertical direction, the same mask can be used for both, that is, the fifth mask here can be replaced by the fourth mask in step 5 .

[0082] Using the fourth mask, N ions are implanted into the N-epitaxial layer 2 above the P+ shielding layer 4 to form a JFET shallow implantation region 5, as shown in FIG. Figure 3f shown.

[0083] Step 7: Using an ion implantation process and a sixth mask, a first deep implantation region 6 a and a second deep implantation region 6 b are sequentially formed on a side of the JFET shallow implantation region 5 close to the first P-well region 3 a .

[0084] Specifically, using photoresist as the sixth mask, N ions with corresponding energy and dose are sequentially injected into the JFET shallow injection region 5 near the first P well region 3a to form the first deep injection region 6a and the second deep injection region 6b. Figure 3g shown.

[0085] Among them, the first deep injection region 6a is arranged adjacent to the JFET shallow injection region 5, and extends downward from the upper surface of the N-epitaxial layer 2 to the same depth as the JFET shallow injection region 5; the second deep injection region 6b extends downward from the lower edge of the first deep injection region 6a to the same depth as the P+ shielding layer 4, and is connected to the P+ shielding layer 4.

[0086] Step 8: A gate structure 10 is fabricated on the surface of the N-epitaxial layer 2 using a thermal oxidation process and a photolithography process.

[0087] First, on the surface of the N-epitaxial layer 2, an oxide is grown by a thermal oxidation process, and a mask etching process is performed to obtain a gate dielectric layer 10a, such as Figure 3h shown.

[0088] The gate dielectric layer 10 a is located on the upper surface of the N-epitaxial layer 2 , and its projection in the thickness direction of the N-epitaxial layer 2 covers the JFET shallow injection region 5 and extends to both sides to partially cover the N+ source region 8 .

[0089] Then, a deposition process is used to deposit polysilicon on the gate dielectric layer 10a, and an etching process is used to form a polysilicon gate 10b. Figure 3i shown.

[0090] Finally, an interlayer dielectric ILD 10c is deposited on and on both sides of the polysilicon gate 10b through a deposition process to form a complete gate structure 10, and a source contact hole is formed through an etching process, as shown in FIG. Figure 3j shown.

[0091] Step 9: Deposit metal on the top and bottom of the entire device to form the source 11 and drain 12 of the device.

[0092] Specifically, after the ohmic contact process and the deposition process, metal is deposited on the N+ source region 8, the P+ region 9, and the interlayer dielectric ILD10c to form the source 11, and metal is deposited on the bottom of the device to form the drain 12. Figure 3k shown.

[0093] At this point, the preparation of SiC MOSFET devices based on asymmetric P+ shielding layer has been completed.

[0094] Optionally, as an implementation method, the depth, width, and implantation concentration or doping concentration of each device structure involved in the above-mentioned preparation process can be set according to the parameter ranges in Table 1 below.

[0095] Table 1 Reference parameters for each region

[0096]

[0097] In addition, it should be noted that the epitaxial growth process, ion implantation process, photolithography process, deposition process, etc. used in the process of preparing the SiC MOSFET device based on the asymmetric P+ shielding layer in this embodiment are all existing mature processes, and the relevant parameter settings can also be implemented by referring to existing related technologies.

[0098] The preparation method provided in the second aspect of the present invention can be used to prepare the SiC MOSFET device based on the asymmetric P+ shielding layer provided in the first aspect, and thus has similar beneficial effects as the device embodiment of the first aspect. Technical details not disclosed in the preparation method embodiments of the present invention can be understood by referring to the description of the device embodiment.

[0099] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0100] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0101] In the description of the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0102] In the description of the present invention, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0103] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A SiC MOSFET device based on an asymmetric P+ shielding layer, characterized in that: include: An N+ substrate (1) and an N- epitaxial layer (2) located on the N+ substrate (1); A P-well region (3) is provided in the N-epitaxial layer (2) along a first direction; the P-well region (3) is located on a side of the N-epitaxial layer (2) facing away from the N+ substrate (1), and has a certain distance from the bottom of the N-epitaxial layer (2) to form a drift region of the device; wherein the P-well region (3) includes a first P-well region (3a) and a second P-well region (3b), and the two are arranged at intervals; the first direction is a direction perpendicular to the thickness of the N-epitaxial layer (2); P+ shielding layers (4) are provided on both sides of the bottom of the second P-well region (3b); the P+ shielding layer (4) is connected to the second P-well region (3b) and extends upward from the horizontal position of the lower edge of the second P-well region (3b) to the inside of the N-epitaxial layer (2) to form a three-dimensional asymmetric deep P-well structure; A JFET shallow injection region (5) is provided directly above the P+ shielding layer (4); the JFET shallow injection region (5) extends downward from the upper surface of the N-epitaxial layer (2) and has a certain distance between it and the P+ shielding layer (4); A JFET deep injection region (6) is provided on one side of the JFET shallow injection region (5) close to the first P-well region (3a); the JFET deep injection region (6) comprises a first deep injection region (6a) and a second deep injection region (6b); the first deep injection region (6a) is arranged adjacent to the JFET shallow injection region (5) and extends downward from the upper surface of the N-epitaxial layer (2) to the same depth as the JFET shallow injection region (5); the second deep injection region (6b) extends downward from the lower edge of the first deep injection region (6a) to the same depth as the P+ shielding layer (4), and is connected to the P+ shielding layer (4).

2. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 1, characterized in that: The injection concentration of the P+ shielding layer (4) is greater than the injection concentration of the P well region (3).

3. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 1, characterized in that: The injection concentration of the JFET shallow injection region (5) is the same as the injection concentration of the first deep injection region (6a); and the injection concentration of the second deep injection region (6b) is greater than the injection concentration of the first deep injection region (6a).

4. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 1, characterized in that: The implantation concentration of the P-well region (3) is 8×10 15 ~1×10 18 The injection concentration of the P+ shielding layer (4) is 8×10 16 ~1×10 18 ; The injection concentration of the JFET shallow injection region (5) and the first deep injection region (6a) in the JFET deep injection region (6) is 1×10 16 ~2×10 17 The second deep injection region (6b) has an injection concentration of 5×10 16 ~2×10 18 .

5. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 1, characterized in that: The surface layer of the second P-well region (3b) on one side of the JFET shallow injection region (5) and the surface layer of the first P-well region (3a) on one side of the JFET deep injection region (6) are also symmetrically provided with a P-type base region (7), an N+ source region (8) and a P+ region (9); and the edge of the P-type base region (7) is aligned with the edge of the second P-well region (3b) or the edge of the first P-well region (3a).

6. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 5, characterized in that: It also includes a gate structure (10); the gate structure (10) is arranged on the surface of the N-epitaxial layer (2) above the JFET shallow injection region (5) and the JFET deep injection region (6); wherein the gate structure (10) is a planar gate structure or a non-trench separated gate structure.

7. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 6, characterized in that: The gate structure (10) comprises a gate dielectric layer (10a), a polysilicon gate (10b) and an interlayer dielectric ILD (10c); wherein the gate dielectric layer (10a) is arranged on the upper surface of the N-epitaxial layer (2), and its projection in the thickness direction of the N-epitaxial layer (2) covers the JFET shallow injection region (5), and extends to both sides to partially cover the N+ source region (8); The polysilicon gate (10b) is located on the upper surface of the gate dielectric layer (10a); The interlayer dielectric ILD (10c) covers the gate dielectric layer (10a) and the gate dielectric layer (10a) and both sides of the gate dielectric layer (10a).

8. The SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 7, characterized in that: Also includes a source electrode (11) and a drain electrode (12); The source electrode (11) is arranged at the top of the entire device and is in contact with the N+ source region (8), the P+ region (9) and the interlayer dielectric ILD (10c); The drain (12) is arranged at the bottom of the entire device and is in contact with the lower surface of the N+ substrate (1).

9. A method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer, characterized in that: The following steps are involved: Step 1: growing an N- epitaxial layer on an N+ substrate; Step 2: using an ion implantation process and a first mask to form a P-well region along a first direction in the N-epitaxial layer; and simultaneously forming a P-type base region on a surface layer of the P-well region; The P-well region is located on a side of the N-epitaxial layer facing away from the N+ substrate, and has a certain distance from the bottom of the N-epitaxial layer to form a drift region of the device; the P-well region includes a first P-well region and a second P-well region, and the two are arranged alternately; the first direction is a direction perpendicular to the thickness of the N-epitaxial layer; Step 3: using an ion implantation process and a second mask to form an N+ source region in the P-type base region; Step 4: using an ion implantation process and a third mask to form a P+ region in the N+ source region; Step 5: Using an ion implantation process and a fourth mask, a P+ shielding layer is formed on both sides of the bottom of the second P-well region; The P+ shielding layer is connected to the second P-well region and extends upward from the horizontal position of the lower edge of the second P-well region to the inside of the N- epitaxial layer; Step 6: Using an ion implantation process and a fifth mask, a JFET shallow implantation region is formed above the P+ shielding layer; Step 7: Using an ion implantation process and a sixth mask, a first deep implantation region and a second deep implantation region are sequentially formed on a side of the JFET shallow implantation region close to the first P-well region; The first deep injection region is arranged adjacent to the JFET shallow injection region and extends downward from the upper surface of the N-epitaxial layer to the same depth as the JFET shallow injection region; the second deep injection region extends downward from the lower edge of the first deep injection region to the same depth as the P+ shielding layer and is connected to the P+ shielding layer; Step 8: fabricating a gate structure on the surface of the N-epitaxial layer using a thermal oxidation process and a photolithography process; Step 9: Electrode metal is applied at the top and bottom of the entire device to form the source and drain of the device.

10. The method for preparing a SiC MOSFET device based on an asymmetric P+ shielding layer according to claim 9, characterized in that: The fourth mask in step 5 is the same as the fifth mask in step 6, both including a JFET deep injection window, a P well injection window, and a P+ shielding layer injection window, and the P+ shielding layer injection window is shared with the JFET shallow injection window; In the mask corresponding to the square cell structure, the P-well injection windows are arranged in an array within the JFET deep injection window in a square cell arrangement; the P+ shielding layer injection windows are spaced apart and distributed around the P-well injection window to form an asymmetric P+ shielding layer structure with the four surrounding cells; In the mask corresponding to the stripe cell structure, the P-well injection windows are distributed in the JFET deep injection window in a stripe cell arrangement manner; and the P+ shielding layer injection windows are distributed at intervals on both sides of the P-well injection window.

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