SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) cellular structure with built-in junction barrier Schottky structure and preparation method of SiC MOSFET cellular structure

Abstract

The invention discloses a SiC MOSFET cellular structure with a built-in junction barrier Schottky structure and a preparation method thereof.The cellular structure comprises a substrate, an epitaxial layer, a JFET region, P-well regions, a gate oxide layer and a gate poly layer, the epitaxial layer is arranged on the upper surface of the substrate, the JFET region is arranged in the middle of the upper surface of the epitaxial layer, the P-well regions are arranged on the left side and the right side of the JFET region, the gate oxide layer is arranged on the P-well regions, and the gate poly layer is arranged on the P-well regions. Each P-well region comprises an N + region and a P + region, the JFET region is composed of a low-doped N-high-resistance region and two high-doped N + low-resistance regions, the N-high-resistance region is located in the middle of the JFET region, and the two N + low-resistance regions are located on the two sides of the N-high-resistance region respectively. A doped region similar to a sandwich is adopted in the JFET region of the cellular structure provided by the invention. According to the structure, the specific on-resistance of the device can be reduced, and meanwhile, the short-circuit performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a SiC MOSFET cell structure with a built-in junction barrier Schottky structure and a preparation method thereof. Background Art

[0002] With the update of SiC MOSFET products, in order to reduce conduction loss and save costs, manufacturers have made the conduction capacity of devices larger and the chip area smaller. At the same time, with the advancement of technology, the quality of the gate oxide layer has improved, the resistance of the channel region has decreased, the threshold voltage has decreased, and the forward capability of the device has become stronger, so the short-circuit tolerance of the device has become smaller and smaller. How to solve the above problems is the direction that technicians in this field are committed to researching. Summary of the invention

[0003] The object of the present invention is to provide a SiC MOSFET cell structure with a built-in junction barrier Schottky structure, which can greatly improve the short-circuit tolerance of the device while reducing the device's specific on-resistance.

[0004] To achieve this purpose, the present invention adopts the following technical scheme: a SiCMOSFET cell structure with a built-in junction barrier Schottky structure, the cell structure includes a substrate, an epitaxial layer, a JFET region, a P-well region, a gate oxide layer, and a gate poly layer, the epitaxial layer is arranged on the upper surface of the substrate, the JFET region is arranged in the middle of the upper surface of the epitaxial layer, and P-well regions are arranged on the left and right sides of the JFET region, each P-well region includes an N+ region and a P+ region, and the JFET region is composed of a low-doped N-high resistance region and two high-doped N+ low resistance regions, wherein the N-high resistance region is located in the middle of the JFET region, and the two N+ low resistance regions are respectively located on both sides of the N-high resistance region.

[0005] As a specific implementation, the N-high resistance region is doped with phosphorus, and the phosphorus ion implantation energy is 100-120keV and the dosage is 1-3 E12 cm -3 ; The N+ low resistance region is doped with phosphorus, and the phosphorus ion injection energy is 100-120keV and the dose is 3~5 E15 cm -3 .

[0006] As a specific implementation, the thickness of the N-high resistance region is greater than that of the N+ low resistance region, the thickness of the N-high resistance region is 0.5-1 μm; the thickness of the N+ low resistance region is 0.2-0.5 μm.

[0007] As a specific implementation manner, the substrate uses a silicon substrate doped with phosphorus, and the resistivity is 0.2-0.5Ω·cm.

[0008] As a specific implementation manner, the epitaxial layer is an N-epi epitaxial layer, the thickness of which is 10-15 μm, the epitaxial layer is doped with arsenic, and the resistivity of the epitaxial layer is 0.002-0.004 Ω·cm.

[0009] As a specific implementation, the P-well region is implanted with boron ions, with an implantation energy of 50-80 keV and a dose of 1-3E15 cm -3 , the thickness of the P-well region is 1~1.5μm.

[0010] As a specific implementation manner, the thickness of the gate oxide layer is 800-1200 Å; the thickness of the gate poly layer is 6000-8000 Å.

[0011] Another object of the present invention is to provide a method for preparing the SiC MOSFET cell structure with a built-in junction barrier Schottky structure, comprising the following steps: 1) growing an epitaxial layer on the substrate; 2) The JFET region is exposed through the mask of the reticle, and two highly doped N+ low resistance regions are added to the left and right areas of the JFET region respectively, and a low doped N- high resistance region is added in the middle of the two N+ low resistance regions; 3) Remove the mask, perform high-energy ion implantation of boron on both sides of the JFET region, and form the P-well region through high-temperature annealing; 4) forming a gate oxide layer on the upper surface of the JFET region by dry-wet-dry oxidation at 1000° C., wherein the gate oxide layer extends to both sides above the P-well region, and the gate oxide layer partially covers the P-well region. A layer of polysilicon is deposited above the gate oxide layer, and a gate is formed by photolithography etching using a mask; 5) Using a self-aligned process, high-energy ions are implanted into the P-well region with phosphorus and boron, respectively, and high-temperature annealing is performed to form the N+ region and the P+ region.

[0012] As a specific implementation, in step 3), the boron ion implantation energy is 50-80 keV, and the dose is 1-3E15 cm -3 , the high temperature annealing temperature is 1150℃, and the annealing time is 100-180min.

[0013] As a specific implementation, in step 5), the phosphorus ion implantation energy is 100-120 keV and the dose is 3-5 E15 cm -3 The boron ion implantation energy is 50~80keV and the dose is 1~5E15 cm -3 The high temperature annealing temperature is 1150℃ and the annealing time is 60-90min.

[0014] Compared with the prior art, the technical solution of the present invention has the following advantages: the SiC MOSFET cell structure with built-in junction barrier Schottky structure proposed by the present invention adds a sandwich-like doping area in the JFET area, which reduces the device's specific on-resistance while improving the short-circuit performance of the device. The reason is that the device using this structure works in the linear region when normally turned on, and works in the saturation region when short-circuited. The depletion layer extension width of the JFET region in the two states is different, so the current paths in the two states are different. Based on the above principle, the SD (junction barrier Schottky) structure is added. In normal operation, the N+ region can reduce the device's specific on-resistance and reduce the device's conduction loss; in the case of a short circuit, the N+ region can reduce the device's short-circuit saturation current, slow down the device's heat accumulation, and improve the short-circuit tolerance of the SiC MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic structural diagram of a SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to the present invention; Figure 2 This is a process flow chart for preparing the SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to the present invention; Among them: 1. Substrate; 2. Epitaxial layer; 3. JFET region; 4. N- high resistance region; 5. N+ low resistance region; 6. P-well region; 7. Gate oxide layer; 8. Gate poly layer; 9. N+ region; 10. P+ region. DETAILED DESCRIPTION

[0016] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific embodiments.

[0017] The present invention provides a SiC MOSFET cell structure with a built-in junction barrier Schottky structure, comprising a substrate, an epitaxial layer, a JFET region, a P-well region, a gate oxide layer, and a gate poly layer.

[0018] The epitaxial layer is arranged on the upper surface of the substrate, the JFET region is arranged in the middle of the upper surface of the epitaxial layer, P-well regions are arranged on the left and right sides of the JFET region, each P-well region contains an N+ region and a P+ region, and the JFET region is composed of a low-doped N-high resistance region and two highly-doped N+ low resistance regions, wherein the N-high resistance region is located in the middle of the JFET region, and the two N+ low resistance regions are respectively located on both sides of the N-high resistance region, and the thickness of the N-high resistance region is greater than the thickness of the N+ low resistance region.

[0019] The method for preparing the SiC MOSFET cell structure with a built-in junction barrier Schottky structure comprises the following steps: 1) 1~2E15cm -3 A 10-15 μm N-epi epitaxial layer is grown on a high-concentration N+sub substrate, and the resistivity of the epitaxial layer is 0.002-0.004 Ω·cm. Here, the resistivity of the N+sub substrate is 0.2-0.5 Ω·cm. 2) The JFET region is exposed through the mask. Two highly doped N+ low resistance regions are added to the left and right sides of the JFET region, and a low doped N- high resistance region is added in the middle of the two N+ low resistance regions. The doping concentration of the N+ low resistance region is 1E16cm -3 , the doping concentration of the N-high resistance region is 1E15cm -3 , the thickness of the N- high resistance region is 1μm; the thickness of the N+ low resistance region is 0.3μm; 3) Remove the mask and perform high-energy ion implantation of boron on both sides of the JFET region with an implantation energy of 50-80keV and a dose of 1-3E15 cm -3 , and anneal at 1150℃ for 100-180min to form a P-well region with a thickness of 1μm; 4) A gate oxide layer with a thickness of 800-1200 Å is formed on the upper surface of the JFET region by a 1000°C dry-wet-dry oxidation method, wherein the gate oxide layer extends to both sides above the P-well region, and the gate oxide layer partially covers the upper surface of the P-well region. A layer of polysilicon with a thickness of 6000-8000 Å is deposited above the gate oxide layer, and a gate is formed by photolithography etching using a mask; 5) Using a self-aligned process, phosphorus is implanted in the P-well region by high-energy ion implantation with an implantation energy of 100-120keV and a dose of 3-5 E15 cm -3 and high-energy ion implantation of boron, with an implantation energy of 50-80 keV and a dose of 1-5E15 cm -3 , and annealed at 1150℃ for 60-90min to form N+ region and P+ region respectively.

[0020] The JFET region uses a sandwich-like doping region with a middle N- high resistance region and two N+ low resistance regions on both sides. This structure can reduce the device's specific on-resistance while improving the device's short-circuit performance.

[0021] The above contents are only preferred embodiments of the present invention. For ordinary technicians in this field, according to the concept of the present invention, there will be changes in the specific implementation methods and application scopes. The content of this specification should not be understood as limiting the present invention.

Claims

1. A SiC MOSFET cell structure with a built-in junction barrier Schottky structure, characterized in that: The cell structure includes a substrate, an epitaxial layer, a JFET region, a P-well region, a gate oxide layer, and a gate poly layer. The epitaxial layer is arranged on the upper surface of the substrate, the JFET region is arranged in the middle of the upper surface of the epitaxial layer, and P-well regions are arranged on the left and right sides of the JFET region. Each P-well region contains an N+ region and a P+ region. The JFET region is composed of a low-doped N-high resistance region and two high-doped N+ low resistance regions, wherein the N-high resistance region is located in the middle of the JFET region, and the two N+ low resistance regions are respectively located on both sides of the N-high resistance region.

2. The SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to claim 1, characterized in that: The N-high resistance region is doped with phosphorus, and the phosphorus ion implantation energy is 100-120keV and the dosage is 1-3 E12 cm -3 ; The N+ low resistance region is doped with phosphorus, and the phosphorus ion injection energy is 100-120keV and the dose is 3~5 E15 cm -3 .

3. The SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to claim 1, characterized in that: The thickness of the N-high resistance region is greater than that of the N+ low resistance region, the thickness of the N-high resistance region is 0.5-1 μm; the thickness of the N+ low resistance region is 0.2-0.5 μm.

4. The SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to claim 1, characterized in that: The substrate is a silicon substrate doped with phosphorus, and has a resistivity of 0.2-0.5Ω·cm.

5. The SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to claim 1, characterized in that: The epitaxial layer is an N-epi epitaxial layer, the thickness of which is 10-15 μm, the epitaxial layer is doped with arsenic, and the resistivity of the epitaxial layer is 0.002-0.004 Ω·cm.

6. The SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to claim 1, characterized in that: The P-well region is implanted with boron ions, with an implantation energy of 50-80 keV and a dose of 1-3E15 cm -3 , the thickness of the P-well region is 1~1.5μm.

7. The SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to claim 1, characterized in that: The thickness of the gate oxide layer is 800-1200 Å; the thickness of the gate poly layer is 6000-8000 Å.

8. A method for preparing a SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: 1) growing an epitaxial layer on the substrate; 2) The JFET region is exposed through the mask, and two highly doped N+ low resistance regions are added to the left and right sides of the JFET region, and a low doped N- high resistance region is added between the two N+ low resistance regions; 3) Remove the mask, perform high-energy ion implantation of boron on both sides of the JFET region, and form the P-well region through high-temperature annealing; 4) forming a gate oxide layer on the upper surface of the JFET region by a 1000° C. dry-wet-dry oxidation method, wherein the gate oxide layer extends to both sides above the P-well region, and the gate oxide layer partially covers the P-well region, and depositing a layer of polysilicon above the gate oxide layer, and forming a gate by photolithography etching through a mask; 5) Using a self-aligned process, high-energy ions are implanted into the P-well region with phosphorus and boron, respectively, and high-temperature annealing is performed to form the N+ region and the P+ region.

9. The method for preparing a SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to claim 8, characterized in that: In step 3), the boron ion implantation energy is 50-80keV and the dose is 1-3E15 cm -3 , the high temperature annealing temperature is 1150℃, and the annealing time is 100-180min.

10. The method for preparing a SiC MOSFET cell structure with a built-in junction barrier Schottky structure according to claim 8, characterized in that: In step 5), the phosphorus ion implantation energy is 100-120keV and the dose is 3-5 E15 cm -3 The boron ion implantation energy is 50~80keV and the dose is 1~5E15 cm -3 The high temperature annealing temperature is 1150℃ and the annealing time is 60-90min.

Images