A super junction MOS device and its preparation method

Abstract

The present invention provides a super junction MOS device and a preparation method thereof. A groove is opened on a substrate, and an N-type epitaxial layer is embedded in the groove. Since the doping concentration of the N-type epitaxial layer in the groove is lower than the doping concentration of the substrate, it will act as a barrier or buffer in the subsequent heating process, effectively preventing the high-concentration ions of the substrate from diffusing into the effective area of ​​the super junction withstand voltage, effectively alleviating the problems of non-depletion and charge imbalance caused by the increase of the epitaxial layer concentration in the bottom area of ​​the groove. The depletion line is flat at the bottom of the groove, which increases the process window and improves the withstand voltage. In addition, when the super junction MOS device is turned on, the electrons reaching the bottom of the groove will be dispersed in the substrate, and the area below the P-type epitaxial layer is still a high-concentration area, so the on-resistance is smaller than the traditional method of increasing the thickness of the epitaxial layer as a whole.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a super junction MOS device and a preparation method thereof. Background Art

[0002] Superjunction technology forms a unique charge balance mechanism by introducing alternating P-type and N-type semiconductor layers in the drift region of the device. This structure can effectively reduce the on-resistance while ensuring a high blocking voltage, greatly improving the performance of power devices and making power semiconductor devices a key step forward in the development of high voltage, high current and high frequency.

[0003] There are two common super junction processes: multiple epitaxy and trench etching. The multiple epitaxial process forms a super junction P region by multiple epitaxy of a certain concentration of N-type region, and then only uses P-type injection compensation to form a super junction P region. The process is relatively easy to control, but the process has many procedures and high cost. The trench process etches a groove with a certain depth-to-width ratio in the super junction voltage-withstand layer, fills the groove with P-type silicon epitaxially, and then uses chemical mechanical polishing to flatten the super junction voltage-withstand layer. The cost is low, but the process is difficult.

[0004] In the trench process, since the substrate concentration is much higher than that of the epitaxial layer, the thermal process in the superjunction process will cause the substrate ions to diffuse upward, resulting in an increase in the concentration of the bottom area of ​​the epitaxial layer, which makes the bottom area incompletely depleted. In addition, process deviations such as the tilt of the trench angle make depletion more difficult, and the charge balance is destroyed, which will lead to a significant drop in BV (Breakdown Voltage). The current practice is to increase the thickness of the overall epitaxial layer above the substrate to keep the bottom of the trench away from the high-concentration substrate, but thickening the low-concentration epitaxial layer will greatly increase the on-resistance. Summary of the invention

[0005] Based on this, the purpose of the present invention is to provide a super junction MOS device and a preparation method thereof, aiming to improve the breakdown voltage of the super junction MOS and increase the process window without significantly increasing the on-resistance.

[0006] A super junction MOS device according to an embodiment of the present invention, when the super junction MOS device is an NMOS transistor, comprises a substrate having a groove, an N-type epitaxial layer partially embedded in the groove, a P-type epitaxial layer disposed on the substrate and located on both sides of the N-type epitaxial layer, and an oxide layer and a gate polysilicon layer sequentially disposed on the N-type epitaxial layer, wherein the doping concentration of the N-type epitaxial layer is lower than the doping concentration of the substrate;

[0007] Wherein, a well region is provided in the N-type epitaxial layer and the P-type epitaxial layer away from the substrate, a source region is provided in the well region, and a part of the well region and a part of the source region are in contact with the oxide layer;

[0008] When the super junction MOS device is a PMOS transistor, it is obtained by inverting all doping in the NMOS transistor.

[0009] Furthermore, the depth of the groove is 1 μm to 4 μm.

[0010] Furthermore, the doping concentration range of the N-type epitaxial layer and the P-type epitaxial layer is 1E15cm -3 ~9E16cm -3 .

[0011] Furthermore, the doping concentrations of the N-type epitaxial layer and the P-type epitaxial layer are the same.

[0012] Furthermore, the doping impurity of the well region is B element, the temperature is 700℃~1000℃, and the doping concentration is 1E12cm -3 ~9E14cm -3 .

[0013] Furthermore, the thickness of the oxide layer is 500Å~1500Å.

[0014] Furthermore, the growth temperature of the oxide layer is 800°C to 1100°C.

[0015] Furthermore, the doping impurity of the source region is P element, the temperature is 800°C~1100°C, and the doping concentration is 1E14cm -3 ~9E16cm -3 .

[0016] A method for preparing a super junction MOS device according to an embodiment of the present invention is used to prepare the above-mentioned super junction MOS device, and the method includes:

[0017] When the super junction MOS device is an NMOS transistor, an N-type substrate is provided, and a trench mask is first used to perform exposure using a negative photoresist to etch the trench;

[0018] epitaxially growing an N-type epitaxial layer on a substrate with a groove, and then grinding it flat, wherein the doping concentration of the N-type epitaxial layer is lower than the doping concentration of the N-type substrate;

[0019] Etching both sides of the N-type epitaxial layer until the N-type substrate is exposed, then epitaxially growing a P-type epitaxial layer on the exposed N-type substrate, and then grinding it flat;

[0020] Doping a well region in an N-type epitaxial layer and a P-type epitaxial layer away from the substrate;

[0021] Epitaxially growing an oxide layer and a gate polysilicon layer on the N-type epitaxial layer;

[0022] Doping the source in the well region, wherein a portion of the well region and a portion of the source region are in contact with the oxide layer;

[0023] When the super junction MOS device is a PMOS transistor, it is obtained by inverting all doping in the NMOS transistor.

[0024] The beneficial effects of the present invention are:

[0025] A groove is formed on the substrate and an N-type epitaxial layer is embedded in the groove. Since the doping concentration of the N-type epitaxial layer in the groove is lower than that of the substrate, it acts as a barrier or buffer during the subsequent heating process, effectively preventing the high-concentration ions of the substrate from diffusing into the effective area of ​​the superjunction withstand voltage, and effectively alleviating the problems of non-depletion and charge imbalance caused by the increase in the concentration of the epitaxial layer in the bottom area of ​​the groove. The depletion line is flattened at the bottom of the groove, which increases the process window and improves the withstand voltage. In addition, when the superjunction MOS device is turned on, electrons reaching the bottom of the groove will be dispersed in the substrate, and the area below the P-type epitaxial layer is still a high-concentration area, which has a smaller on-resistance than the traditional method of increasing the thickness of the epitaxial layer as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of a super junction MOS device provided by an embodiment of the present invention;

[0027] Figure 2 A flowchart of a method for preparing a super junction MOS device provided in an embodiment of the present invention;

[0028] Figure 3 A schematic diagram of a process flow for preparing a super junction MOS device provided by an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the structure of a super junction MOS device proposed in Comparative Example 2.

[0030] Description of main component symbols:

[0031]

[0032] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0033] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0034] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0036] The present invention provides a super junction MOS device. Figure 1 , is a schematic diagram of the structure of a super junction MOS device provided by an embodiment of the present invention. When the super junction MOS device is an NMOS transistor, it includes a substrate 1 with a groove, an N-type epitaxial layer partially embedded in the groove, a P-type epitaxial layer arranged on the substrate and located on both sides of the N-type epitaxial layer, and an oxide layer 4 and a gate polysilicon layer 5 sequentially arranged on the N-type epitaxial layer. The doping concentration of the N-type epitaxial layer is lower than the doping concentration of the substrate 1 with the groove. In this embodiment, the substrate 1 with the groove is an N-type substrate, and the doping concentration of the N-type substrate is 1E17cm -3 ~9E19cm -3 The oxide layer 4 is a high-quality gate oxide layer grown by thermal oxidation, and the thickness of the oxide layer 4 is 500Å~1500Å. Exemplarily, the thickness of the oxide layer 4 is 500Å, 800Å, 1000Å, 1200Å or 1500Å, but not limited thereto. The growth temperature of the oxide layer 4 is 800°C~1100°C;

[0037] In order to form a well of the superjunction MOS device under the gate, a well region 6 is provided in the N-type epitaxial layer and the P-type epitaxial layer away from the substrate 1 with the trench, which is also the body region. The doping impurity of the well region 6 is B (boron) element, the temperature is 700℃~1000℃, and the doping concentration is 1E12cm -3 ~9E14cm -3 The well region 6 is provided with a source region 7 to form the source of the super junction MOS device. The doping impurity of the source region is P (phosphorus) element, the temperature is 800℃~1100℃, and the doping concentration is 1E14cm -3 ~9E16cm -3Part of the well region 6 and part of the source region 7 are in contact with the oxide layer 4. According to the above arrangement, the N column 2 and the P column 3 of the super junction MOS device in the embodiment of the present invention are formed.

[0038] It should be noted that before the epitaxial layer grows, a groove mask is first used to expose negative photoresist (the normal process uses positive photoresist, and the exposure etching forms the groove area of ​​the P column 3), and a shallow groove is etched at the bottom of the N column 2 of the super junction MOS device, that is, a groove is etched below the N-type epitaxial layer. The depth of the groove is 1μm~4μm. Exemplarily, the depth of the groove is 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm or 4μm, but is not limited to this.

[0039] Then, a 30 μm to 60 μm N-type epitaxial layer is grown on the substrate and then polished. The doping concentration of the N-type epitaxial layer ranges from 1E15 cm -3 ~9E16cm -3 , which is in the same doping concentration range as the P-type epitaxial layer, and the doping concentrations of the N-type epitaxial layer and the P-type epitaxial layer are the same.

[0040] In addition, when the super junction MOS device is a PMOS transistor, it is obtained by inverting all the doping in the above NMOS transistor. It can be understood that when the super junction MOS device is a PMOS transistor, it includes a substrate with a groove, a P-type epitaxial layer partially embedded in the groove, an N-type epitaxial layer arranged on the substrate and located on both sides of the P-type epitaxial layer, and an oxide layer and a gate polysilicon layer sequentially arranged on the P-type epitaxial layer. The doping concentration of the P-type epitaxial layer is lower than the doping concentration of the substrate with the groove. In this embodiment, the substrate with the groove is a P-type substrate, and the doping concentration of the P-type substrate is 1E17cm -3 ~9E19cm -3 The oxide layer is a high-quality gate oxide layer grown by thermal oxidation, the thickness of the oxide layer is 500Å~1500Å, and the growth temperature of the oxide layer is 800℃~1100℃;

[0041] In order to form a well of the superjunction MOS device under the gate, a well region is set in the P-type epitaxial layer and the N-type epitaxial layer away from the substrate with the trench, which is also the body region. The doping impurity of the well region is As (arsenic), the temperature is 800℃~1100℃, and the doping concentration is 1E14cm -3 ~9E16cm -3 The source region is set in the well region to form the source of the super junction MOS device. The doping impurity of the source region is B (boron) element, the temperature is 700℃~1000℃, and the doping concentration is 1E12cm -3 ~9E14cm -3, part of the well region and part of the source region are in contact with the oxide layer. According to the above arrangement, the P column and N column of the super junction MOS device in the embodiment of the present invention are formed.

[0042] It should be noted that before the epitaxial layer grows, a trench mask is used to expose the layer using positive photoresist, and a shallow trench is etched at the bottom of the P column of the superjunction MOS device, that is, a trench is etched below the P-type epitaxial layer, and the depth of the trench is 1μm~4μm.

[0043] Then, a 30μm~60μm P-type epitaxial layer is grown on the substrate and then polished. The doping concentration of the P-type epitaxial layer ranges from 1E15cm -3 ~9E16cm -3 , which is in the same range as the doping concentration of the N-type epitaxial layer, and the doping concentrations of the N-type epitaxial layer and the P-type epitaxial layer are the same.

[0044] In order to prepare the above-mentioned super junction MOS device, the embodiment of the present invention provides a method for preparing a super junction MOS device, please refer to Figure 2 and Figure 3 , Figure 2 A flowchart of a method for preparing a super junction MOS device provided by an embodiment of the present invention is provided. Figure 3 A schematic diagram of a manufacturing process flow of a super junction MOS device provided in an embodiment of the present invention. When the super junction MOS device is an NMOS transistor, the method specifically includes the following steps:

[0045] S100: providing an N-type substrate, first using a trench mask and negative photoresist for exposure, and etching a trench.

[0046] Specifically, using the mask of the P column 3 groove and negative photoresist, a shallow groove with a depth of 1μm~4μm is etched in the N column 2 area, and finally a substrate 1 with a groove is obtained. In this step, no additional mask is added, which has the advantage of low manufacturing cost.

[0047] S200: epitaxially growing an N-type epitaxial layer on a substrate with grooves, and then grinding it flat, wherein the doping concentration of the N-type epitaxial layer is lower than the doping concentration of the N-type substrate.

[0048] The N-type epitaxial layer 21 with a thickness of 30 μm to 60 μm is epitaxially grown on the substrate 1 with the grooves, and then ground flat. The thickness of the ground N-type epitaxial layer 21 is 2 μm to 6 μm less than the thickness of the epitaxial growth. The doping concentration range of the N-type epitaxial layer 21 is 1E15 cm -3 ~9E16cm -3 .

[0049] S300: etching both sides of the N-type epitaxial layer until the N-type substrate is exposed, then epitaxially growing a P-type epitaxial layer on the exposed N-type substrate, and then grinding it flat.

[0050] It can be understood that a deep groove is etched on the N-type epitaxial layer 21 to obtain the etched N-type epitaxial layer 22, and then a P-type epitaxial layer 31 is epitaxially grown to fill the deep groove and then polished. The doping concentration of the P-type epitaxial layer 31 is the same as the doping concentration of the N-type epitaxial layer 21.

[0051] S400: doping a well region in an N-type epitaxial layer and a P-type epitaxial layer away from the substrate.

[0052] In this embodiment, the doping impurity of the well region 6 is B (boron) element, the temperature is 700°C~1000°C, and the doping concentration is 1E12cm -3 ~9E14cm -3 .

[0053] S500: epitaxially growing an oxide layer and a gate polysilicon layer on the N-type epitaxial layer.

[0054] Specifically, a high-quality oxide layer 4 with a thickness of 500Å to 1500Å is grown by thermal oxidation (oxygen is introduced at a high temperature of 800°C to 1100°C) to form a gate oxide layer, and then a gate polysilicon layer 5 is deposited to form a gate.

[0055] S600: performing source doping in the well region, wherein a portion of the well region and a portion of the source region are in contact with the oxide layer.

[0056] Specifically, the doping impurity of the source region 7 is P (phosphorus) element, the temperature is 800°C~1100°C, and the doping concentration is 1E14cm -3 ~9E16cm -3 .

[0057] Furthermore, a dielectric layer (not shown) is deposited as a whole, and the dielectric layer is also obtained by thermal oxidation, and then CT (through hole) etching is performed, and finally metal aluminum is deposited to form an electrode of the super junction MOS device.

[0058] In some other embodiments of the present invention, when the super junction MOS device is a PMOS transistor, it can be obtained by inverting all doping in the above-mentioned NMOS transistor.

[0059] The present invention will be further described below with specific embodiments:

[0060] Example 1

[0061] Embodiment 1 of the present invention provides a super junction MOS device. When the super junction MOS device is an NMOS transistor, it includes a substrate with a trench depth of 1 μm, an N-type epitaxial layer partially embedded in the trench, a P-type epitaxial layer disposed on the substrate and located on both sides of the N-type epitaxial layer, and an oxide layer with a thickness of 800 Å and a gate polysilicon layer with a thickness of 2000 Å sequentially disposed on the N-type epitaxial layer. The doping concentration of the N-type epitaxial layer is lower than the doping concentration of the substrate. Specifically, the thickness of the N-type epitaxial layer is 41 μm, the thickness of the P-type epitaxial layer is 40 μm, and the doping concentration of the N-type epitaxial layer is 1E15 cm -3 , the doping concentration of the substrate is 1E17cm -3 ;

[0062] Wherein, a well region is arranged in the N-type epitaxial layer and the P-type epitaxial layer far away from the substrate, a source region is arranged in the well region, and a part of the well region and a part of the source region are in contact with the oxide layer;

[0063] Specifically, the doping impurity in the well region is element B, the temperature is 800°C, and the doping concentration is 1E12cm -3 The doping impurity in the source region is P element, the temperature is 900℃, and the doping concentration is 1E15cm -3 .

[0064] Example 2

[0065] Embodiment 2 of the present invention also provides a super junction MOS device, which differs from Embodiment 1 in that the depth of the trench is 2 μm.

[0066] Example 3

[0067] Embodiment 3 of the present invention also provides a super junction MOS device, which differs from Embodiment 1 in that the depth of the trench is 4 μm.

[0068] Comparative Example 1

[0069] Comparative Example 1 also provides a super junction MOS device, which differs from Example 1 in that no groove is opened in the substrate, that is, there is no N-type epitaxial layer embedded in the substrate. It can be understood that the thickness of the N-type epitaxial layer and the thickness of the P-type epitaxial layer are both 40μm.

[0070] Comparative Example 2

[0071] Comparative Example 2 also provides a super junction MOS device, see Figure 4, is a structural schematic diagram of a super junction MOS device proposed in Comparative Example 2. The difference from Comparative Example 1 is that, based on the current N-type epitaxial layer 21, an N-type epitaxial portion 23 is extended toward the grooveless substrate 11. It can be understood that the P-type epitaxial layer 31 is located on both sides of the N-type epitaxial layer 21 and is placed on the N-type epitaxial portion 23, that is, the N-type epitaxial portion 23 separates the P-type epitaxial layer 31 from the grooveless substrate 11. Specifically, the thickness of the N-type epitaxial portion 23 is 1 μm, so the thickness of the new N-type epitaxial layer composed of the N-type epitaxial layer 21 and the N-type epitaxial portion 23 is 41 μm.

[0072] Comparative Example 3

[0073] Comparative Example 3 also provides a super junction MOS device, which differs from Comparative Example 2 in that the thickness of the N-type epitaxial portion is 2 μm.

[0074] The super junction MOS devices in Examples 1 to 3 and Comparative Examples 1 to 3 were tested under the same conditions, and the specific results are as follows:

[0075]

[0076] It can be seen from the table that the superjunction MOS device in the embodiment of the present invention performs significantly better than the comparative example in terms of the on-resistance increase rate. In addition, the superjunction MOS device in the embodiment of the present invention can significantly improve the breakdown voltage when the on-resistance increase rate is small. In particular, the superjunction MOS device in Example 1 of the present invention has a breakdown voltage of 655V and an on-resistance increase rate of 2% compared with that of Comparative Example 1.

[0077] In summary, the super junction MOS device and its preparation method in the embodiments of the present invention, by opening a groove on the substrate, and embedding the N-type epitaxial layer in the groove, since the doping concentration of the N-type epitaxial layer in the groove is lower than the doping concentration of the substrate, it will act as a barrier or buffer in the subsequent heating process, effectively preventing the high-concentration ions of the substrate from diffusing into the effective area of ​​the super junction withstand voltage, and effectively alleviating the problem of non-depletion and charge imbalance caused by the increase in the concentration of the epitaxial layer in the bottom area of ​​the trench. The depletion line is flat at the bottom of the trench, which increases the process window and improves the withstand voltage. In addition, when the super junction MOS device is turned on, the electrons reaching the bottom of the trench will be dispersed in the substrate, and the area below the P-type epitaxial layer is still a high-concentration area, and the on-resistance is smaller than the traditional method of increasing the thickness of the epitaxial layer as a whole.

[0078] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A super junction MOS device, characterized in that: When the super junction MOS device is an NMOS transistor, it includes a substrate with a groove, an N-type epitaxial layer partially embedded in the groove, a P-type epitaxial layer disposed on the substrate and located on both sides of the N-type epitaxial layer, and an oxide layer and a gate polysilicon layer sequentially disposed on the N-type epitaxial layer, wherein the doping concentration of the N-type epitaxial layer is lower than the doping concentration of the substrate; Wherein, a well region is provided in the N-type epitaxial layer and the P-type epitaxial layer away from the substrate, a source region is provided in the well region, and a part of the well region and a part of the source region are in contact with the oxide layer; When the super junction MOS device is a PMOS transistor, it is obtained by inverting all doping in the NMOS transistor; The depth of the groove is 1 μm to 4 μm, and the doping concentration range of the N-type epitaxial layer and the P-type epitaxial layer is 1E15 cm -3 ~9E16cm -3 , the doping concentration of the N-type epitaxial layer and the P-type epitaxial layer is the same.

2. The super junction MOS device according to claim 1, characterized in that: The doping impurity of the well region is B element, the temperature is 700℃~1000℃, and the doping concentration is 1E12cm -3 ~9E14cm -3 .

3. The super junction MOS device according to claim 1, characterized in that: The thickness of the oxide layer is 500Å~1500Å.

4. The super junction MOS device according to claim 3, characterized in that: The growth temperature of the oxide layer is 800°C to 1100°C.

5. The super junction MOS device according to claim 1, characterized in that: The doping impurity of the source region is P element, the temperature is 800℃~1100℃, and the doping concentration is 1E14cm -3 ~9E16cm -3 .

6. A method for preparing a super junction MOS device, characterized in that: For preparing the super junction MOS device according to any one of claims 1 to 5, the method comprises: When the super junction MOS device is an NMOS transistor, an N-type substrate is provided, and a trench mask is first used to perform exposure using a negative photoresist to etch the trench; epitaxially growing an N-type epitaxial layer on a substrate with a groove, and then grinding it flat, wherein the doping concentration of the N-type epitaxial layer is lower than the doping concentration of the N-type substrate; Etching both sides of the N-type epitaxial layer until the N-type substrate is exposed, then epitaxially growing a P-type epitaxial layer on the exposed N-type substrate, and then grinding it flat; Doping a well region in an N-type epitaxial layer and a P-type epitaxial layer away from the substrate; Epitaxially growing an oxide layer and a gate polysilicon layer on the N-type epitaxial layer; Doping the source in the well region, wherein a portion of the well region and a portion of the source region are in contact with the oxide layer; When the super junction MOS device is a PMOS transistor, it is obtained by inverting all doping in the NMOS transistor.

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