Wafer substrate for improving warpage generated in epitaxial layer growth process and application thereof

Abstract

The invention relates to a wafer substrate for improving warping generated in the growth process of an epitaxial layer and application of the wafer substrate, belongs to the field of semiconductors, and aims to improve the warping problem generated in the growth process of the epitaxial layer. The first stress release areas are arranged on the outer ring of the wafer and are symmetrically distributed around the center of the wafer; the first stress release area is an axial symmetry graph, the symmetry axis points to the circle center, and the first stress release area is gradually widened in the direction away from the circle center along the symmetry axis; the method has the advantages that damage of stress to the wafer in the epitaxial layer growth process is reduced, generation of poor warping is reduced, particularly, production limitation on large-size wafers can be reduced, and the yield and reliability of devices can be improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductors, and in particular to a wafer substrate for improving warping generated during the growth of an epitaxial layer and a use thereof. Background Art

[0002] Nitride semiconductor materials, such as gallium nitride, aluminum gallium nitride, aluminum nitride, etc., have advantages such as high electron mobility and high breakdown voltage in the manufacture of power devices compared to traditional silicon material devices.

[0003] In the manufacturing process of power devices made of nitride semiconductor materials, nitride semiconductor materials are usually formed by epitaxial growth on a heterogeneous material substrate. For example, in the manufacturing process of a high electron mobility transistor made of gallium nitride material, an epitaxial layer of gallium nitride material needs to be epitaxially grown on a substrate of silicon, silicon carbide or aluminum nitride material.

[0004] However, due to the large lattice mismatch and large difference in thermal expansion coefficient between the substrate material (silicon, silicon carbide or aluminum nitride, etc.) and the epitaxially grown nitride semiconductor material, wafer warpage is likely to occur during the high-temperature epitaxial growth process and the cooling process to room temperature after the growth process. Moreover, under thermal stress, the grown crystal may have more defects. Compared with the heating process, warpage during the cooling process needs to be avoided more. Material deformation during the cooling process may cause microcracks in the epitaxial layer crystals and even cause more crystal defects.

[0005] The above-mentioned wafer warping will affect subsequent processing and affect the final product production yield and reliability. In addition, as the wafer size increases, especially in the manufacturing process of 8-inch or larger wafers, the problem will become more serious, thus limiting the increase in wafer size and further reduction in production costs. Summary of the invention

[0006] The present invention provides a patterned heterogeneous substrate structure for epitaxial growth of nitride semiconductor materials. The present invention provides a method for preparing a power device wafer of nitride semiconductor materials, which is beneficial to improving the wafer warping caused by epitaxial growth of nitride semiconductor materials and the crystal defect problem caused by stress deformation.

[0007] The technical solution provided by the present invention is: a wafer substrate for improving the warping during the growth of an epitaxial layer, the wafer substrate for growing an epitaxial layer includes a substrate and more than four first stress release areas arranged on the substrate, the first stress release areas are arranged on the outer ring of the wafer and are symmetrically distributed with respect to the center of the wafer; the first stress release areas are axisymmetric figures, the axis of symmetry points to the center of the circle, and the first stress release areas gradually widen along the axis of symmetry away from the center of the circle; the number of the first stress release areas can be 4, 6, 8, etc., and they are centrally symmetrical with respect to the center of the circle of the wafer as the center of symmetry; the first stress release area itself is also an axisymmetric figure, and the axis of symmetry is the radius of the wafer. For wafers of small size, the first stress release area located on the outer ring is sufficient.

[0008] Furthermore, a second stress release area with an area smaller than the first stress release area is provided above the substrate and in the middle of the adjacent first stress release area. The second stress release area is provided in the inner circle of the wafer and is symmetrically distributed with the center of the wafer as the center. The second stress release area is an axisymmetric figure, with its axis of symmetry pointing to the center of the circle, and the second stress release area gradually widens away from the center of the circle along the axis of symmetry. For large-sized wafers, in addition to providing the first stress release area in the outer circle, a second stress release area in the inner circle can also be provided.

[0009] Further, the first stress release region includes a first platform region and a first slope region that uniformly transitions from the plane of the first platform region to the plane of the substrate, and the angle between the slope surface of the first slope region and the substrate plane is 2-45°; or the second stress release region includes a second platform region and a second slope region that uniformly transitions from the plane of the second platform region to the plane of the substrate, and the angle between the slope surface of the second slope region and the substrate plane is 2-45°.

[0010] Furthermore, the first stress release region or the second stress release region is in the shape of a triangular pyramid. Since the slope region is the main area for stress consumption, the triangular pyramid setting can increase the area of ​​the slope region and reduce the angle between the slope region and the substrate, which is beneficial to avoid cracks at the bottom of the slope due to stress.

[0011] Furthermore, the first stress release area or the second stress release area is an isosceles triangle, and the acute angle pointing to the center of the wafer is 2-30°; or the first stress release area or the second stress release area is an isosceles trapezoid, and the ratio of the base and height of the isosceles trapezoid is 0.05-0.5.

[0012] Furthermore, the upper base and / or lower base of the isosceles trapezoid is an arc-shaped edge, wherein the lower base is close to the edge of the wafer or coincides with the edge of the wafer.

[0013] Furthermore, the height of the first stress release area or the second stress release area gradually increases along the symmetry axis in a direction away from the center of the circle.

[0014] The present invention also provides a use of a wafer substrate that is not warped during the growth of an epitaxial layer. The wafer substrate is used to manufacture power devices made of nitride semiconductor materials. The manufacturing method is as follows: first, in a high-temperature environment, a nitride semiconductor epitaxial layer is formed on the wafer substrate by an epitaxial method, and then cooled to room temperature for further manufacture of nitride semiconductor power devices.

[0015] The manufacturing method also includes: secondly, in the wafer spot measurement and sorting process, the area adjacent to the slope area with a thickness of 100-3000 um is set as a defective area for elimination.

[0016] The beneficial effect of the present invention is that by reducing the damage of stress to the wafer during the growth of the epitaxial layer, the occurrence of warping defects can be reduced, especially the production restrictions on large-size wafers can be reduced, and the yield and reliability of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram showing the distribution of stress release areas on a wafer substrate; Figure 2 It is a top view of the release area with different shapes; Figure 3 Another embodiment of the present invention; Figure 4 for Figure 3 Schematic diagram of the section along the midline A-A', B-B'; Figure 5 for Figure 3 Stress analysis diagram of Figure 6 It is another embodiment of the present invention; Figure 7 for Figure 6 Schematic diagram of the section along the midline A-A', B-B'; Figure 8-9 Schematic diagram of the formation of stress release area; Fig.10 It is another embodiment of the present invention; Fig.11 It is an area that can be used to remove defective products during wafer spot measurement and sorting processes. DETAILED DESCRIPTION

[0018] The relevant technical background is explained below. It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. In the specific implementation, there is no restriction on the fixed direction. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions, grooves, and material layers in the drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0019] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0020] The present invention provides a wafer substrate 200 having a stress release region 201 for forming a nitride semiconductor epitaxial layer.

[0021] In addition, a method for forming a power device wafer of a nitride semiconductor material of the present invention is as follows: In the first step, a wafer substrate 200 having a stress release region 201 is provided.

[0022] In the second step, a nitride semiconductor epitaxial layer is formed on the substrate by an epitaxial method under a high temperature environment, and then cooled to room temperature.

[0023] The third step is to continue processing to finally form a nitride semiconductor power device.

[0024] The wafer substrate 200 may be made of silicon, aluminum oxide, silicon carbide or aluminum nitride. In one embodiment, the wafer substrate 200 is made of silicon, and a gallium nitride epitaxial layer is formed on the substrate by an epitaxial method. In another embodiment, the wafer substrate 200 is made of silicon carbide, and a gallium nitride epitaxial layer is formed on the substrate by an epitaxial method.

[0025] Figure 1 Schematic diagram of the distribution of stress release regions 201 on a wafer substrate 200. There are more than four stress release regions 201 on the wafer, which are symmetrical with the center of the wafer and evenly distributed around the periphery of the wafer. The stress release region 201 has a different height from the rest of the wafer. The height of the stress release region 201 is usually higher than the wafer, 0.5-8um higher than the rest of the wafer.

[0026] The stress release region 201 itself is an axisymmetric figure, and its symmetry axis BB' usually points to the center of the wafer. The stress release region 201 gradually widens as it moves away from the center, and the height can also gradually increase, from 0μm at the end closest to the center to 8μm at the highest point at the end farthest from the center.

[0027] Figure 2The figures are top views of release areas 201 of different shapes. One embodiment is shown in 2A, in which the stress release area 201 is an isosceles triangle, and the angle pointing to the center of the wafer is an acute angle, and the angle is between 2-30°; one embodiment is shown in 2B, in which the stress release area 201 is an isosceles trapezoid, and the ratio of the base and the height of the isosceles trapezoid is between 0.05-0.5; a variation is shown in 2C, in which the side of the stress release area 201 pointing to the center of the circle is an arc edge; one embodiment is shown in 2D, in which the side of the stress release area 201 away from the center of the circle is an arc edge, and the arc edge may coincide with the edge of the wafer or be close to the edge of the wafer.

[0028] In some embodiments, the stress release region 201 may be disposed in a non-outermost region of the wafer, so the edge of the stress release region 201 away from the center may be a straight line, or an edge with a varying arc, or even other more complex boundaries.

[0029] Example 2 An implementation example Figure 3 FIG. 2 is a top view of the stress release region 201 in this embodiment. Figure 4 4A and 4B in are Figure 3 Schematic diagram of the section along the median tangent lines A-A' and B-B'.

[0030] In this embodiment, the stress release region 201 has a platform region 202 that is higher than the rest of the wafer, and a slope region 210 that transitions to the platform region 202. In an actual embodiment, the platform region 202 is 0.5-8 um higher than the rest of the wafer, and the angle between the slope surface of the slope region 210 and the wafer is between 2-45°. The gentler the slope, the lower the stress of the wafer substrate 200 and the epitaxial layer 102 at the slope corner, and the less likely crystal fracture occurs at the corner.

[0031] A nitride semiconductor epitaxial layer 102 is formed on a wafer substrate 200 by an epitaxial method. During the process of cooling from a high temperature to a normal temperature, due to the existence of the stress release region 201 , the stress direction in the epitaxial layer 102 changes according to the shape of the stress release region 201 .

[0032] Figure 5 5A and 5B in FIG. 4 are schematic diagrams of stress directions at corresponding positions of 4A and 4B during the process of cooling the nitride semiconductor epitaxial layer 102 to room temperature.

[0033] As shown in 5A, in the direction perpendicular to the wafer center axis (tangent line A-A'), the stress has a component in the height direction (Z axis), which is beneficial to reduce the stress in the horizontal direction and the wafer warpage in the direction of the tangent line A-A'.

[0034] As shown in 5B , along the wafer center axis direction (tangent line BB'), the stress has a component in the height direction (Z axis), which is beneficial to reduce the stress in the horizontal direction and the wafer warpage in the tangent line BB' direction.

[0035] Therefore, the stress release region 201 has stress release functions in two directions, namely, the direction perpendicular to the wafer center axis (tangent line A-A') and the direction of the wafer center axis (tangent line B-B'). Providing symmetrical and uniform stress release regions 201 on the wafer is beneficial to reducing the warpage of the entire wafer and the stress of the epitaxial layer on the wafer plane.

[0036] Example 3 exist Figure 4 Based on the embodiment, a variation of the implementation example Figure 6 As shown, Figure 7 They are Figure 6 Schematic diagram of the section along the midline A-A', B-B'.

[0037] In this embodiment, the stress release region 201 is a triangular pyramid structure, and its height gradually increases along the BB' direction of the symmetry axis, and Figure 4 Compared with the embodiment shown, there is no platform area 202, only a slope area 210. In this structure, the stress of the wafer substrate 200 and the epitaxial layer 102 at the slope corners is lower. This embodiment is conducive to setting a slope area 210 with a smaller slope, which is conducive to avoiding cracks at the bottom of the slope caused by stress.

[0038] In the above embodiment, the stress release region 201 and the wafer substrate 200 are formed of the same material by default. In some embodiments, the stress release region 201 may also be composed of a heterogeneous material different from the wafer substrate 200.

[0039] For example, in one embodiment, the wafer substrate 200 is made of silicon material, and the release region 201 above the substrate may be made of materials such as silicon carbide, aluminum nitride, and gallium nitride.

[0040] For another example, in one embodiment, the wafer substrate 200 is made of silicon carbide material, and the stress release region 201 above the substrate may be made of materials such as aluminum nitride, gallium nitride, and gallium oxide.

[0041] Example 4 There are many methods for forming the wafer structure of the wafer substrate 200 having the stress release region 201 mentioned in the above embodiments.

[0042] Among them, a feasible formation method is as follows: In the first step, a patterned photoresist is formed on a flat substrate.

[0043] The second step is to etch the exposed substrate area under the protection of photoresist.

[0044] The third step is to remove the photoresist. At this time, the area protected by the photoresist is the stress release area 201.

[0045] Another possible formation method is as follows: In the first step, a foreign material is formed on a flat substrate.

[0046] In the second step, a photoresist is formed on the heterogeneous material.

[0047] The third step is to perform photolithography on the heterogeneous material to form a patterned heterogeneous material.

[0048] The fourth step is to remove the photoresist. At this time, the patterned heterogeneous material area protected by the photoresist is the stress release area 201.

[0049] Another possible formation method is as follows: In the first step, a foreign material is formed on a flat substrate.

[0050] In the second step, a photoresist is formed on the heterogeneous material.

[0051] In the third step, the heterogeneous material is photolithographically processed to form a patterned heterogeneous material 232 and expose the substrate material.

[0052] Step 4: Remove the photoresist.

[0053] In the fifth step, the substrate material is etched under the protection of the patterned heterogeneous material 232, such as Figure 8 .

[0054] Step 6: Remove the heterogeneous material. At this time, the patterned substrate area protected by the heterogeneous material is the stress release area 201, such as Fig. 9 .

[0055] Example 5 In addition to the above-mentioned embodiments, the stress release region 201 described in the present invention may have a more complex distribution on the wafer according to the required stress release effect.

[0056] For example, on a larger wafer, more stress release regions 201 are provided. Fig.10 As shown in FIG. 10A , on a wafer larger than 8 inches, 8 or more stress release regions 201 with equal spacing are arranged on the periphery.

[0057] For another example, the stress release area 201 has multiple groups with different graphics and multiple groups with different distances from the center of the wafer. As shown in 10B, a group of inner circle stress release areas 217 and a group of outer circle stress release areas 218 are set in the wafer. Among them, corresponding to the different distances from the wafer circle, the inner circle stress release area 217 has a smaller area, and the outer circle stress release area 218 has a larger area. The inner circle stress release area 217 and the outer circle stress release area 218 can be the same as the stress release area 201 in the previous embodiment, or they can be different. This setting is conducive to balancing the in-plane stress of the wafer.

[0058] In a practical substrate structure embodiment, 8 or 16 symmetrical release areas are set on an 8-inch boron-doped silicon material wafer substrate 200 with a thickness between 700-1200um. The release area is an isosceles triangle with a short side length of 3-20um, and the angle of the angle pointing to the center of the wafer is 10-30 degrees. The release area 201 has a platform area 202 and a slope area 210. The platform area is 1-5um higher than the wafer, and the angle between the slope area 210 and the wafer is between 20-45 degrees.

[0059] In an embodiment of forming a gallium nitride device by an epitaxial method using the above substrate structure, the epitaxial temperature is between 1100-1250 degrees, the thickness of the gallium nitride epitaxial layer 102 is between 1-5um, and the warpage of the gallium nitride epitaxial wafer formed after epitaxy is less than 40um.

[0060] Example 6 In addition, since the stress release region 201 has the slope region 210, the slope region 210 may form more crystal defects and crystal dislocations in the subsequent epitaxial process. Therefore, the devices in the slope region 210 in the release region 201 can be removed from the final wafer to prevent the yield and reliability of the devices from being affected. Fig.11 As shown, in the wafer spot measurement and sorting process, the area of ​​100-3000um adjacent to the slope area 210 (the shaded area shown in the figure) is set as a defective product for screening, that is, the area can be directly eliminated as a defective product area.

[0061] In addition, those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more device structures and manufacturing processes of embodiments of the present invention.

[0062] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.

Claims

1. A wafer substrate for improving warping during epitaxial layer growth, characterized in that: A wafer substrate for growing an epitaxial layer includes a substrate and more than four first stress release areas arranged on the substrate, wherein the first stress release areas are arranged on the outer circle of the wafer and are symmetrically distributed around the center of the wafer; the first stress release areas are axially symmetrical figures with their symmetry axes pointing to the center of the circle, and the first stress release areas gradually widen along the symmetry axis away from the center of the circle.

2. The wafer substrate for improving warping during epitaxial layer growth as claimed in claim 1, characterized in that: A second stress release area with an area smaller than that of the first stress release area is provided above the substrate and in the middle of the adjacent first stress release areas. The second stress release area is provided in the inner circle of the wafer and is symmetrically distributed with the center of the wafer as the center. The second stress release area is an axially symmetrical figure with its axis of symmetry pointing to the center of the circle. The second stress release area gradually widens along the axis of symmetry away from the center of the circle.

3. The wafer substrate for improving warping during epitaxial layer growth as claimed in claim 1 or 2, characterized in that: The first stress release region includes a first platform region and a first slope region that uniformly transitions from the plane of the first platform region to the plane of the substrate, and the angle between the slope surface of the first slope region and the plane of the substrate is 2-45°; or The second stress release region includes a second platform region and a second slope region that uniformly transitions from the second platform region plane to the substrate plane, and the angle between the slope surface of the second slope region and the substrate plane is 2-45°.

4. The wafer substrate for improving warping during epitaxial layer growth as claimed in claim 1 or 2, characterized in that: The first stress release area or the second stress release area is in the shape of a triangular pyramid.

5. The wafer substrate for improving warping during epitaxial layer growth as claimed in claim 1 or 2, characterized in that: The first stress release area or the second stress release area is an isosceles triangle, and the acute angle pointing to the center of the wafer is 2-30°; or the first stress release area or the second stress release area is an isosceles trapezoid, and the ratio of the base to the height of the isosceles trapezoid is 0.05-0.

5.

6. The wafer substrate for improving warping during epitaxial layer growth as claimed in claim 5, characterized in that: The upper base and / or lower base of the isosceles trapezoid are arc-shaped edges, wherein the lower base is close to the edge of the wafer or coincides with the edge of the wafer.

7. The wafer substrate for improving warping during epitaxial layer growth as claimed in claim 1 or 2, characterized in that: The height of the first stress release area or the second stress release area gradually increases along the symmetry axis in a direction away from the center of the circle.

8. The use of a wafer substrate for improving warpage during epitaxial layer growth as claimed in claim 1 or 2, characterized in that: The wafer substrate is used to make power devices of nitride semiconductor materials, and the manufacturing method is as follows: first, under a high temperature environment, a nitride semiconductor epitaxial layer is formed on the wafer substrate by an epitaxial method, and then cooled to room temperature for further manufacturing of nitride semiconductor power devices.

9. The use of a wafer substrate for improving warpage during epitaxial layer growth as claimed in claim 8, characterized in that: The manufacturing method also includes: secondly, in the wafer spot measurement and sorting process, the area adjacent to the slope area with a thickness of 100-3000 um is set as a defective area for elimination.

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