Method for manufacturing semiconductor element
During the production process of semiconductor components, the heat treatment process is performed before forming the hard mask layer, and the fluorine atoms in the fluorine-containing dopant are diffused and removed, which solves the problem of peeling the hard mask layer and improves the properties and yield of the component.
Patent Information
- Application Number
- CN202311299003.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-09
- Publication Date
- 2025-04-11
AI Technical Summary
In the prior art, when forming a hard mask layer of a semiconductor element, peeling problems are prone to occur, which affects the properties and yield of the element.
Before forming the hard mask layer, a heat treatment production process is performed to diffuse the fluorine atoms in the fluorine-containing dopant to the substrate surface and remove it, reducing the chance of fluorine atoms diffuse into the hard mask layer.
By this method, the probability of peeling of the hard mask layer is reduced, and the properties and yield of the semiconductor element are improved.
Smart Images
Figure CN119815899A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor devices, and in particular to a method for manufacturing a semiconductor element with fluorine doping. Background Art
[0002] In order to increase the carrier mobility of the semiconductor device, compressive stress or tensile stress can be applied to the gate channel. For example, if compressive stress needs to be applied, the prior art often uses selective epitaxial growth (SEG) technology to form an epitaxial structure with the same lattice arrangement as the silicon substrate in a silicon substrate, such as a silicon germanium (SiGe) epitaxial structure. By taking advantage of the fact that the lattice constant of the silicon germanium epitaxial structure is greater than the lattice of the silicon substrate, stress is generated in the channel region of the p-type metal oxide semiconductor (PMOS) transistor, increasing the carrier mobility of the channel region and increasing the speed of the metal oxide semiconductor transistor. Conversely, if it is an n-type metal oxide semiconductor (NMOS) transistor, a silicon carbide (SiC) epitaxial structure can be formed in the silicon substrate to generate tensile stress on the gate channel region.
[0003] When forming the epitaxial structure, a hard mask may be formed and grooves may be formed in the substrate in advance by using photolithography, etching and other manufacturing processes to define the area where the epitaxial structure is to be set. However, the hard mask may peel off and affect the properties and yield of the semiconductor elements subsequently manufactured. Summary of the invention
[0004] An object of the present invention is to provide a method for manufacturing a semiconductor device to solve the above-mentioned problem.
[0005] According to one embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising the following steps: forming a gate structure on a substrate; injecting a fluorine-containing dopant into the substrate to form two lightly doped drain regions on two sides of the gate structure; performing a heat treatment process, wherein a portion of the fluorine atoms in the fluorine-containing dopant diffuses onto the surface of the substrate; and removing the portion of the fluorine atoms.
[0006] Compared to the prior art, the method for manufacturing a semiconductor element of the present invention performs a heat treatment process before forming a hard mask layer to diffuse a portion of the fluorine atoms in the fluorine-containing dopant onto the surface of the substrate and remove the portion of the fluorine atoms, thereby reducing the diffusion of fluorine atoms into the hard mask layer formed subsequently, which is beneficial to reducing the probability of peeling of the hard mask layer, thereby improving the properties and yield of the semiconductor element. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 1 is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to a first embodiment and a second embodiment of the present invention;
[0008] Fig.10 It is a schematic diagram of observation results of defects of an embodiment of the present invention and a comparative example.
[0009] Main component symbols
[0010] 1: Semiconductor components
[0011] 10: Base
[0012] 10a: Surface
[0013] 110, 112: Insulation structure
[0014] 120: Well region
[0015] 130: Gate structure
[0016] 132: Gate dielectric layer
[0017] 134: Gate material layer
[0018] 136: Mask layer
[0019] 140: Lightly doped drain region
[0020] 160: Groove
[0021] 180: Epitaxial layer
[0022] 200: Hard mask layer
[0023] 200a: gap wall
[0024] 210: First sublayer
[0025] 210a: first spacer
[0026] 220a: Second spacer
[0027] 220: Second sublayer
[0028] 300: Sacrificial layer
[0029] 400: Wafer
[0030] A1: Arrow
[0031] P1: Ion implantation process
[0032] P2: Heat treatment process
[0033] P3: Gas cleaning production process
[0034] R: Defect DETAILED DESCRIPTION
[0035] The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. In order to make the contents of the present invention clearer and easier to understand, the following drawings may be simplified schematic diagrams, and the elements therein may not be drawn to scale. In addition, the number and size of each element in the drawings are for illustration only and are not intended to limit the present invention. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, back, bottom, top, etc., are only for reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration, not for limitation of the present invention. In addition, in the following embodiments, the same or similar elements will use the same or similar reference numerals.
[0036] The description below regarding “a first feature is formed on or above a second feature” may refer to “the first feature is in direct contact with the second feature” or “there are other features between the first feature and the second feature” such that the first feature and the second feature are not in direct contact with each other.
[0037] The present invention uses the terms "first", "second", etc. to describe elements, regions, layers, and / or sections, but it should be understood that these terms are only used to distinguish a certain element, region, layer, and / or section from another element, region, layer, and / or section, and they do not imply or represent any previous ordinal number of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, region, layer, and / or section discussed below may also be referred to as the second element, region, layer, and / or section. These terms in the claims may not be the same as those in the specification, but may be replaced by "first", "second", "third", etc. according to the order of the elements declared in the claims.
[0038] Please refer to Figures 1 to 8, which is a schematic cross-sectional view of the steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. In this embodiment, a semiconductor device 1 (see Figure 8 ) is used as an example for explanation of the PMOS transistor. Figure 1 As shown, a gate structure 130 is first formed on a substrate 10. The substrate 10 may be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate or a silicon on insulator (SOI) substrate.
[0039] The substrate 10 may include insulating structures 110, 112 and a well region 120. For example, the insulating structures 110, 112 may be formed before the substrate 10, and the insulating structures 110, 112 are used to provide electrical isolation. For example, the substrate 10 may include at least one shallow trench isolation (STI) structure surrounding each active region (not separately labeled). Figure 1 The middle insulating structures 110 and 112 may be the left and right parts of a shallow trench isolation structure, and the area between the two insulating structures 110 and 112 may be an active area. The material of the insulating structures 110 and 112 may include a dielectric material, such as silicon dioxide. Next, an ion implantation process (not shown) may be performed to form a well region 120 in the substrate 10. Depending on whether the semiconductor element formed subsequently is suitable for an NMOS transistor or a PMOS transistor, the doping of the well region 120 may be adjusted. In the present embodiment, the semiconductor element 1 is taken as a PMOS transistor as an example, and therefore, the well region 120 is an N-type well region, and the well region 120 may be doped with N-type dopants, such as arsenic, phosphorus, etc.
[0040] The gate structure 130 includes, from bottom to top, a gate dielectric layer 132, a gate material layer 134, and a mask layer 136. In the present embodiment, the gate structure 130 can be manufactured by a gate first manufacturing process, a gate last manufacturing process of a high-k first manufacturing process, and a gate last manufacturing process of a high-k last manufacturing process according to the manufacturing process requirements. Taking the post-high-k dielectric layer fabrication process of the present embodiment as an example, a deposition process may be performed to sequentially form a gate dielectric material, a gate material, and a mask material on the substrate 10, and a pattern transfer process may be performed using a patterned photoresist (not shown) as a mask, and a portion of the mask material, a portion of the gate material, and a portion of the gate dielectric material may be removed by a single etching or a sequential etching process, and then the patterned photoresist may be stripped to form a gate structure 130 including a gate dielectric layer 132, a gate material layer 134, and a mask layer 136 on the surface 10a of the substrate 10. The material of the gate dielectric layer 132 may include, but is not limited to, oxides and / or nitrides, and the oxide may include, for example, silicon dioxide (SiO 2 ), the nitride may include, for example, silicon nitride (SiN). The material of the gate material layer 134 may include, but is not limited to, a non-metallic conductive material, such as polysilicon. The material of the mask layer 136 may include, but is not limited to, silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC) and / or silicon oxynitride (SiON).
[0041] In addition, although the present embodiment takes a planar transistor as an example, in other variations, the method for manufacturing a semiconductor element of the present invention can also be applied to a non-planar transistor, such as a transistor having a fin structure. In this case, Figure 1 The indicated substrate 10 corresponds to the fin structure formed on the substrate 10 .
[0042] Then, if Figure 2As shown, an offset spacer (not shown) can be selectively formed to surround the gate structure 130, and then an ion implantation process P1 is performed to implant fluorine-containing dopants into the substrate 10 to form two lightly doped drain regions 140 on both sides of the gate structure 130. The conductivity type of the two lightly doped drain regions 140 is the same and different from the conductivity type of the well region 120. In the present embodiment, the well region 120 is an N-type well region, and the conductivity type of the two lightly doped drain regions 140 is P-type, so the ion implantation process P1 is to implant P-type dopants into the substrate 10. The fluorine-containing dopant can be a component of a portion of the P-type dopant. The fluorine-containing dopant can include fluorides of elements of Group 13 (also known as Group IIIA), and the fluorine-containing dopant can be, for example, fluorides of boron (B), aluminum (Al), gallium (Ga), and indium (In). According to one embodiment of the present invention, the fluorine-containing dopant can include boron difluoride (BF 2 The energy of the fluorine-containing dopant implantation may be 10KeV to 35KeV, and the dose may be 1E13 atoms / cm 2 To 1E17atoms / cm 2 .
[0043] Then, if Figure 3 As shown, a heat treatment process P2 is performed, wherein a portion of the fluorine atoms in the fluorine-containing dopant diffuses onto the surface 10a of the substrate 10. The aforementioned "fluorine atom" refers generally to a substance containing fluorine atoms, for example, it may be a neutral fluorine atom (i.e., a fluorine atom that is electrically neutral because the number of electrons is the same as the number of protons) or a fluorine ion with a negative charge, but is not limited thereto. The heat treatment process P2 may be performed at 600° C. to 1300° C. for 10 seconds to 100 seconds. Since the process of injecting dopants into the substrate 10 (such as the ion implantation process for forming the well region 120 and the ion implantation process P1 for forming the lightly doped drain region 140) disrupts the lattice arrangement of the substrate 10, the lattice arrangement of the substrate 10 may be repaired by the heat treatment process P2.
[0044] Then, if Figure 4 As shown, for example, a gas cleaning process P3 may be performed to remove the fluorine atoms diffused onto the surface 10a of the substrate 10. Here, a gas is introduced to remove the fluorine atoms on the surface 10a of the substrate 10. Figure 4 The arrow A1 in the figure represents the flow direction of the gas, that is, the gas can remove fluorine atoms by physical means. The aforementioned gas may include oxygen (O 2 ), argon (Ar), carbon dioxide gas (CO 2 ) or hydrogen (H 2 ).
[0045] Then, if Figure 5As shown, a hard mask layer 200 is formed on the gate structure 130 and the two lightly doped drain regions 140. The hard mask layer 200 may include a first sub-layer 210 and a second sub-layer 220 from bottom to top. The material of the first sub-layer 210 may include an oxide, such as silicon dioxide, and the material of the second sub-layer 220 may include a nitride, such as silicon nitride, silicon oxynitride, or silicon carbide nitride.
[0046] Then, if Figure 6 As shown, the hard mask layer 200 is patterned to expose the surface 10a of the substrate 10 located on both sides of the gate structure 130. For example, an etching process can be performed to remove a portion of the hard mask layer 200 to form a spacer 200a surrounding the gate structure 130. Here, the spacer 200a includes a first spacer 210a and a second spacer 220a in sequence from the inside to the outside to form a composite structure. The first spacer 210a is formed by patterning the first sub-layer 210, and the second spacer 220a is formed by patterning the second sub-layer 220.
[0047] Then, if Figure 7 As shown, two grooves 160 are formed in the substrate 10 on two sides of the gate structure 130. For example, a dry etching and / or wet etching process can be performed, and the gate structure 130 and the spacer 200a are used as an etching mask, and a single or multiple etchings are performed downward along the spacer 200a to remove a portion of the substrate 10 to form two grooves 160 in the substrate 10 on two sides of the gate structure 130.
[0048] Then, if Figure 8 As shown, two epitaxial layers 180 are formed in the two grooves 160. For example, a selective epitaxial growth process can be performed to form two epitaxial layers 180 in the two grooves 160. The material of the epitaxial layer 180 can be, for example, silicon germanium (SiGe), but is not limited thereto. Before forming the two epitaxial layers 180, two buffer layers (not shown) can be selectively formed in the two grooves 160, and the two epitaxial layers 180 are respectively located on the two buffer layers. After forming the two epitaxial layers 180, two cap layers (not shown) can be selectively formed and respectively disposed on the epitaxial layers 180, and the material of the cap layers can include, for example, silicon. In this way, the production of the semiconductor element 1 can be completed.
[0049] The present invention can perform a doping process simultaneously (in-situ) when forming the epitaxial layer 180 and perform an annealing process in combination, so as to inject dopants into the epitaxial layer 180 to form source / drain regions (not separately labeled), or can choose to perform an ion implantation process only after the epitaxial layer 180 is formed and perform an annealing process in combination to form source / drain regions in the epitaxial layer 180, all of which are within the scope of the present invention.
[0050] Although not shown in the figure, the method for manufacturing a semiconductor device may also include other manufacturing processes for manufacturing transistors, such as sequentially forming a contact hole etch stop layer and an interlayer dielectric layer to cover the gate structure 130 and the epitaxial layer 180, performing a metal gate replacement (replacement metal gate, RMG) manufacturing process to convert the gate structure 130 including a non-metallic conductive material into a metal gate, and finally forming a contact plug in the interlayer dielectric layer to electrically connect the epitaxial layer 180 and / or the source / drain region.
[0051] Figures 1 to 8 In the disclosed method for manufacturing a semiconductor device, before forming the hard mask layer 200, a heat treatment process P2 is first performed to diffuse a portion of fluorine atoms in the fluorine-containing dopant onto the surface 10a of the substrate 10, and a gas is introduced to remove the fluorine atoms on the surface 10a of the substrate 10, and then the hard mask layer 200 is formed, which can reduce the probability of fluorine atoms diffusing into the hard mask layer 200. For example, the probability that the fluorine atoms relax the bonds between atoms in the first sub-layer 210, thereby causing the first sub-layer 210 to partially bulge (due to increased thickness) and cause the second sub-layer 220 to peel off can be reduced.
[0052] Please refer to the order Figure 1 , Figure 2 , Fig. 9 , Figures 5 to 8 , which is a schematic cross-sectional view of the steps of a method for manufacturing a semiconductor element according to a second embodiment of the present invention. In this embodiment, the semiconductor element is a PMOS transistor as an example for description. Figure 1 As shown in FIG. 1 , a gate structure 130 is first formed on the substrate 10. Then, as shown in FIG. Figure 2 As shown, an ion implantation process P1 is performed to implant fluorine-containing dopants into the substrate 10 to form two lightly doped drain regions 140 on two sides of the gate structure 130. Fig. 9 As shown, a sacrificial layer 300 is formed on the gate structure 130 and the two lightly doped drain regions 140. The material of the sacrificial layer 300 may include oxide, such as silicon dioxide. Then, a heat treatment process P2 is performed, wherein a portion of fluorine atoms in the fluorine-containing dopant diffuses onto the surface 10a of the substrate 10 and enters the sacrificial layer 300. Then, the sacrificial layer 300 is removed by, for example, an etching process. Next, as shown in FIG. Figure 5 As shown, a hard mask layer 200 is formed on the gate structure 130 and the two lightly doped drain regions 140. Figure 6 As shown, the hard mask layer 200 is patterned to expose the surface 10a of the substrate 10 located on both sides of the gate structure 130, and to form a spacer 200a surrounding the gate structure 130. Figure 7 As shown, a portion of the substrate 10 is removed to form two grooves 160 in the substrate 10 on two sides of the gate structure 130. Figure 8 As shown, two epitaxial layers 180 are formed in the two grooves 160 by using, for example, a selective epitaxial growth process to complete the manufacturing of the semiconductor device 1 .
[0053] The main difference between the second embodiment and the first embodiment is that the sacrificial layer 300 is formed before the heat treatment process P2. In the heat treatment process P2, a part of the fluorine atoms in the fluorine-containing dopant diffuses to the surface 10a of the substrate 10 and enters the sacrificial layer 300. Then, the fluorine atoms diffused to the surface 10a of the substrate 10 are removed by removing the sacrificial layer 300, and then the hard mask layer 200 is formed. Therefore, the second embodiment does not need to pass gas to remove the fluorine atoms on the surface 10a of the substrate 10. In addition, since the heat treatment process P2 is performed first, and the fluorine atoms diffused to the surface 10a of the substrate 10 are removed together with the sacrificial layer 300, the second embodiment can also reduce the probability of fluorine atoms diffusing into the hard mask layer 200. For example, the probability that the fluorine atoms relax the bonds between the atoms in the first sub-layer 210 and cause the first sub-layer 210 to locally bulge (due to the increase in thickness) and cause the second sub-layer 220 to peel off can be reduced.
[0054] Please refer to Fig.10 , which is a schematic diagram of observation results of defects according to an embodiment of the present invention and a comparative example. Fig.10 Part A and Part B are scanning results of a semiconductor device using a defect scanning machine according to an embodiment of the present invention and a comparative example, respectively. The semiconductor device corresponds to Figure 5 back, Figure 6 The manufacturing process stage before. Since the defect scanning machine does not scan the entire wafer 400, the completely blank area represents the area that has not been scanned, and the area with squares represents the area that has been scanned. Each square on the wafer 400 represents a bare die, wherein the squares marked with thick frames and dots represent bare die where defect R is observed, and defect R may represent that the hard mask layer has peeled off, and the squares not marked with thick frames and dots (i.e., blank squares) represent bare die where defect R is not observed. The semiconductor element of the embodiment is manufactured using the method of the first embodiment of the present invention, and the semiconductor element of the comparative example, whose manufacturing method is different from the method of the first embodiment, is that a heat treatment manufacturing process is performed after forming the hard mask layer and before patterning the hard mask layer, and a gas cleaning manufacturing process is not included. According to the manufacturing method of the semiconductor device of the comparative example, the heat treatment process causes a part of the fluorine atoms in the fluorine-containing dopant to diffuse onto the surface of the substrate and enter the first sublayer in the hard mask layer, so that the bonds between the atoms in the first sublayer are relaxed, and the thickness of the local area of the first sublayer increases and bulges upward, causing the second sublayer to peel off. Fig.10It can be seen that the number of bare crystals with defects R observed on the wafer 400 of the embodiment is far less than the number of bare crystals with defects R observed on the wafer 400 of the comparison example. It is obvious that the method for manufacturing semiconductor elements according to the present invention can greatly reduce the phenomenon of hard mask layer peeling of the manufactured semiconductor elements, and can greatly improve the properties and yield of the manufactured semiconductor elements.
[0055] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, comprising: forming a gate structure on the substrate; Implanting fluorine-containing dopants into the substrate to form two lightly doped drain regions on two sides of the gate structure; Performing a heat treatment process, wherein a portion of the fluorine atoms in the fluorine-containing dopant diffuses onto the surface of the substrate; and The fluorine atoms in this portion are removed.
2. The method according to claim 1, further comprising, after removing the fluorine atoms of the part: A hard mask layer is formed on the gate structure and the two lightly doped drain regions. 3 . The method of claim 2 , wherein the hard mask layer comprises a first sub-layer, and a material of the first sub-layer comprises oxide. 4 . The method according to claim 3 , wherein the hard mask layer further comprises a second sub-layer disposed on the first sub-layer, and a material of the second sub-layer comprises nitride.
5. The method of claim 2, further comprising: Patterning the hard mask layer to expose the surface of the substrate located on two sides of the gate structure; forming two grooves in the substrate on two sides of the gate structure; and Two epitaxial layers are formed in the two grooves.
6. The method of claim 1, wherein the fluorine-containing dopant comprises a fluoride of a Group 13 element.
7. The method according to claim 1, wherein the energy of implanting the fluorine-containing dopant is 10KeV to 35KeV and the dose is 1E13atoms / cm 2 To 1E17 atoms / cm 2 . 8 . The method according to claim 1 , wherein the heat treatment process is performed at 600° C. to 1300° C. for 10 seconds to 100 seconds.
9. The method of claim 1, wherein removing the portion of fluorine atoms comprises introducing a gas to remove the portion of fluorine atoms.
10. The method of claim 9, wherein the gas comprises oxygen, argon, carbon dioxide or hydrogen.