Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, the semiconductor structure comprises a substrate, and the substrate comprises a partition region and a device region; the device fin part is located on the substrate in the device region, and the isolation fin part is located on the substrate in the partition region. According to the invention, the isolation fin part is adopted to replace the device fin part in the isolation region, so that the step of removing the device fin part in the isolation region after the device fin part is formed in the prior art is omitted, the stress effect of the process of removing the device fin part on the residual device fin part is avoided, and the probability that the fin part of the device is bent is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In order to better adapt to the requirement of device size reduction, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistor (FinFET). Among them, in Fin Field Effect Transistor, the gate surrounds the fin-shaped channel on three sides. Compared with planar transistors, the gate of Fin Field Effect Transistor has stronger control over the channel and can better suppress the short channel effect.

[0004] In the semiconductor field, a fin cut process is usually used to remove unnecessary fins according to process requirements. However, the performance of the fin field effect transistor formed after the fin cut process still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, including: a substrate, the substrate including a partition region and a device region; a device fin located on the substrate in the device region, and an isolation fin located on the substrate in the partition region.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a partition region and a device region; forming a first isolation layer in the substrate in the partition region; patterning the substrate and the first isolation layer, forming a device fin on the remaining substrate in the device region, and forming an isolation fin on the remaining substrate in the partition region.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure provided by the embodiment of the present invention, the substrate includes a device area and a partition area, a device fin is located on the substrate in the device area, and an isolation fin is located on the substrate in the partition area; since the embodiment of the present invention provides the isolation fin in the partition area, the isolation between the device fins is achieved in the extension direction of the device fins through the isolation fins, and the reliability of the isolation achieved by the isolation fins is higher, thereby improving the performance of the semiconductor structure.

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming a first isolation layer in the substrate in the partition area, the substrate and the first isolation layer are patterned, a device fin is formed on the remaining substrate in the device area, and an isolation fin is formed on the remaining substrate in the partition area. Since the first isolation layer forms an isolation fin when the substrate is patterned, the isolation fin located in the partition area can play a role in isolating the device fins of each device area, that is, the embodiment of the present invention adopts an isolation fin to replace the device fin located in the partition area, thereby eliminating the step of removing the device fin in the partition area after forming the device fin in the prior art, avoiding the stress effect of the process of removing the device fin on the remaining device fin, thereby reducing the probability of the device fin bending problem, correspondingly improving the quality of the device fin, and further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 11 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Fig.12 and Fig.13 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 14 to 37 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0014] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed.

[0015] Figures 1 to 11 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 and Figure 2 , Figure 1 is a cross-sectional view along a first direction, Figure 2It is a cross-sectional view along the second direction at the top of the core layer. The first direction is perpendicular to the extension direction of the core layer, and the second direction is parallel to the extension direction of the core layer. A substrate 10 is provided, and the substrate 10 includes a device area I' and a partition area II'; a core layer (not marked) is formed on the substrate 10.

[0017] refer to Figure 3 and Figure 4 , Figure 3 is based on Figure 1 A cross-sectional view of Figure 4 is based on Figure 2 A mask sidewall material layer (not shown) is formed on the substrate 10 and on the sidewalls and top of the core layer (not shown).

[0018] After forming the mask sidewall material layer, the method further includes: removing the mask sidewall material layer on the substrate 10 and on the top of the core layer to form a mask sidewall (not shown) located on the sidewall of the core layer; after forming the mask sidewall, removing the core layer.

[0019] refer to Figure 5 and Figure 6 , Figure 5 is based on Figure 3 A cross-sectional view of Figure 6 is based on Figure 4 In a cross-sectional view, the substrate 10 is patterned with the mask sidewall as a mask, and a device fin 11 is formed in the device area I' and the partition area II', and the device fin 11 extends along the second direction and is arranged along the first direction.

[0020] refer to Figure 7 and Figure 8 , Figure 7 is based on Figure 5 A cross-sectional view of Figure 8 is based on Figure 6 , the device fin 11 in the partition area is removed.

[0021] refer to Fig. 9 and Fig.10 , Fig. 9 is based on Figure 7 A cross-sectional view of Fig.10 is based on Figure 8 In the cross-sectional view, an isolation layer 12 is formed on the substrate 10 at the side of the device fin 11 in the device region I', and the isolation layer 12 covers a portion of the side wall of each device fin 11.

[0022] like Fig.11As shown, it has been found through research that as the process point continues to shrink, the aspect ratio of the height of the device fin 11 and the space between adjacent device fins 11 continues to increase. After removing the device fins 11 in the partition area, a wet strip is usually performed. Since the capillary force between the chemical solution used in the wet stripping process and the device fins 11 changes, the chemical solution is difficult to be completely removed, so that the chemical solution remaining due to the capillary force has a stress effect on the device fins 11, which makes it easy for the device fins 11 to bend or even fuse adjacent device fins 11.

[0023] On the other hand, due to the removal of the device fins 11 in the isolation area II', the semiconductor structure has a dense area of ​​the device fins 11 and a sparse area of ​​the device fins 11, which makes it easy to generate stress on the device fins 11 during the process of forming the isolation layer 12 on the substrate 10 on the side of the device fins 11 in the device area I', and also leads to the problem of bending of the device fins 11 and even fusion of adjacent device fins 11.

[0024] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a device region and a partition region; a device fin located on the substrate in the device region, and an isolation fin located on the substrate in the partition region.

[0025] In the semiconductor structure provided by the embodiment of the present invention, the substrate includes a device area and a partition area, a device fin located on the substrate in the device area, and an isolation fin located on the substrate in the partition area; since the embodiment of the present invention adopts an isolation fin to replace the device fin located in the partition area, the step of removing the device fin in the partition area after forming the device fin in the prior art is omitted, and the stress of the process of removing the device fin on the remaining device fins is avoided, thereby reducing the probability of the device fin bending problem occurring, correspondingly improving the quality of the device fin, and further improving the performance of the semiconductor structure.

[0026] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] refer to Fig.12 and Fig.13 , Fig.12 and Fig.13 It is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0028] in, Fig.12 It is a cross-sectional view at the position of the partition area along the direction perpendicular to the extension direction of the device fin, Fig.13It is a cross-sectional view taken at the side of the partition region along a direction perpendicular to the extension direction of the device fin.

[0029] In this embodiment, the semiconductor structure includes: a substrate 110, the substrate 110 includes a partition region ii and a device region i; a device fin 120 located on the substrate 110 in the device region i; and an isolation fin 140 located on the substrate 110 in the partition region ii.

[0030] The substrate 110 is used to provide an operating basis for a semiconductor structure forming process.

[0031] In this embodiment, the substrate 110 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In this embodiment, the substrate 110 is used to form a fin field effect transistor (FinFET).

[0032] The isolation region ii is used to achieve isolation between device regions i, and is also used to provide a process platform for forming the first isolation layer 141 and the isolation fin 140 .

[0033] The device area i is used to provide a process platform for forming various semiconductor devices.

[0034] In the semiconductor structure provided by the embodiment of the present invention, the device fin 120 is located on the substrate 110 of the device area i, and the isolation fin 140 is located on the substrate 110 of the partition area ii. The isolation fin 140 located in the partition area ii can play a role in isolating the device fins 120 of each device area i, that is, the embodiment of the present invention is provided with an isolation fin 140 in the partition area ii, so that in the extension direction of the device fin 120, the isolation fin 140 is used to achieve isolation between the device fins 120, and the reliability of the isolation achieved by the isolation fin 140 is higher, thereby improving the performance of the semiconductor structure.

[0035] Specifically, the isolation fin 140 replaces the device fin located in the isolation region ii. That is, in the process of forming the semiconductor structure, there is no need to first form the device fin in the isolation region and then remove the device fin in the isolation region. Therefore, the step of removing the device fin in the isolation region ii after forming the device fin 120 in the prior art is omitted, and the stress of the device fin 120 in the device region i caused by the process of removing the device fin (that is, the fin cutting process) is avoided, resulting in the problem of fin bending of the device fin 120.

[0036] The device fin 120 provides a process basis for forming an active fin, which is used to provide a conductive channel when the semiconductor device is working.

[0037] The material of the device fin 120 includes one or more of silicon, silicon germanium, germanium and III-V semiconductor materials. The material of the device fin 120 is determined according to the channel conductivity type and performance requirements of the transistor.

[0038] In this embodiment, the device region i includes a first device region iP and a second device region iN. The device fins 120 of the first device region iP and the device fins 120 of the second device region iN are made of different materials. The device fins 120 of different materials can be used to form a double-channel semiconductor structure.

[0039] In this embodiment, the first device region iP is used to form a PMOS device, and the second device region iN is used to form an NMOS device.

[0040] As an example, the material of the device fin 120 of the second device region iN is silicon, the material of the device fin 120 of the second device region iN is the same as that of the substrate 110, and the material of the device fin 120 of the first device region iP is silicon germanium.

[0041] The isolation fin 140 plays a role of a dummy fin, and the isolation fin 140 is not used to form a semiconductor device.

[0042] In this embodiment, the isolation fins 140 can also isolate various semiconductor devices.

[0043] It should be noted that the material of the device fin 120 of the first device area iP is silicon germanium. Since silicon germanium is more susceptible to loss, the isolation fin 140 is used to replace the device fin located in the isolation area ii, thereby eliminating the step of removing the device fin in the isolation area ii after forming the device fin 120 in the prior art, thereby reducing the number of exposure times of the device fin 120 of silicon germanium material, thereby reducing the line width loss (CD loss) of the device fin 120 of silicon germanium material.

[0044] As an example, an isolation fin 140 is provided on the substrate 110 in the isolation region ii adjacent to the first device region iP, so as to avoid a fin cut operation on the device fin 120 made of silicon germanium material.

[0045] It is understandable that, in other embodiments, an isolation fin 140 may also be provided on the substrate 110 in the isolation region ii adjacent to the second device region iN, thereby avoiding the fin cutting operation on the device fin 120 made of silicon material.

[0046] The material of the isolation fin 140 is an insulating material, and the material of the isolation fin 140 includes one or more of silicon oxide, silicon oxynitride, silicon nitride and silicon carbide. As an example, the material of the isolation fin 140 is silicon oxide. Silicon oxide has good insulation and generates less stress, which is conducive to improving process reliability.

[0047] In this embodiment, the semiconductor structure further includes: a first isolation layer 141 located in the substrate 110 in the isolation region ii; and the isolation fin 140 is located on the first isolation layer 141 and is an integrated structure with the first isolation layer 141 .

[0048] During the formation of the semiconductor structure, the first isolation layer 141 is usually first formed in the substrate 110 of the isolation region ii, the substrate 110 and the first isolation layer 141 are patterned, the device fin 120 is formed on the substrate 110 of the device region i, and the isolation fin 140 is formed on the substrate 110 of the isolation region ii. Since the height of the first isolation layer 141 is greater than the preset fin height, the first isolation layer 141 in the remaining substrate 110 of the isolation region ii is retained so that the isolation fin 140 is located on the remaining first isolation layer 141.

[0049] Accordingly, the isolation fin 140 and the first isolation layer 141 are made of the same material.

[0050] In this embodiment, a first isolation layer 141 is further provided in the substrate 110 of the isolation region ii, which is beneficial for further isolating each semiconductor device and preventing leakage current from occurring between the devices.

[0051] It should be noted that the vertical distance d between the bottom of the first isolation layer 141 and the top of the substrate 110 of the device area i should not be too large or too small. If the vertical distance between the bottom of the first isolation layer 141 and the top of the substrate 110 of the device area i is too large, the stress of the device fin 120 adjacent to the first isolation layer 141 is easily affected, and the device fin is prone to bending in the subsequent process, which is not conducive to the subsequent formation of other structures on the device fin 120 (for example, not conducive to the filling of the material of the metal gate structure). If the vertical distance between the bottom of the first isolation layer 141 and the top of the substrate 110 of the device area i is too small, the effect of the isolation fin 140 being used to completely replace the device fin of the partition area ii is not good, that is, there are still residual device fins in the partition area ii, which affects the isolation effect and brings hidden defects. Therefore, in this embodiment, the vertical distance d between the bottom of the first isolation layer 141 and the top of the substrate 110 of the device area i is 10 nanometers to 60 nanometers.

[0052] In other embodiments, depending on the depth of the trench, the semiconductor structure may not include the first isolation layer.

[0053] In this embodiment, the semiconductor structure also includes: a second isolation layer 150, located on the substrate 110 on the sides of the device fin 120 and the isolation fin 140, the second isolation layer 150 covers part of the side wall of the device fin 120, and the top of the second isolation layer 150 is flush with the top of the isolation fin 140.

[0054] In this embodiment, the second isolation layer 150 covers part of the sidewall of the device fin 120 , which means that the top of the second isolation layer 150 is lower than the top of the device fin 120 , and the second isolation layer 150 exposes a part of the height of the device fin 120 in the device region i.

[0055] The second isolation layer 150 exposes a portion of the height of the device fin 120 in the device region i to serve as an effective fin.

[0056] The second isolation layer 150 is a shallow trench isolation (STI) structure, and the second isolation layer 150 is used to isolate each semiconductor device to prevent leakage current from occurring between the devices.

[0057] In this embodiment, the top of the second isolation layer 150 is flush with the top of the isolation fin 140, thereby providing a flat surface for subsequent processes, thereby reducing the impact of the isolation fin 140 retained in the isolation region ii on subsequent processes.

[0058] Moreover, in the process of forming the semiconductor structure, the device fin 120 and the isolation fin 140 can be formed in the same patterning step, that is, the initial height of the isolation fin 140 is relatively large, and the formation process of the second isolation layer 150 usually includes the step of removing a portion of the thickness of the second isolation material layer. Therefore, by making the top of the second isolation layer 150 flush with the top of the isolation fin 140, it is convenient to remove a portion of the height of the isolation fin in the process of removing a portion of the thickness of the second isolation material layer, so that the top of the remaining isolation fin is flush with the second isolation layer, thereby simplifying the process steps.

[0059] The material of the second isolation layer 150 is an insulating material. As an example, the material of the second isolation layer 150 is silicon oxide. Silicon oxide has good insulation properties, and the stress generated by silicon oxide is also small, which is conducive to improving process reliability. In other embodiments, the material of the second isolation layer can also be a suitable insulating material such as silicon oxynitride.

[0060] In this embodiment, the isolation fin 140 and the second isolation layer 150 are made of the same material.

[0061] By making the isolation fin 140 and the second isolation layer 150 made of the same material, the adhesion between the isolation fin 140 and the second isolation layer 150 is improved, which is beneficial to improving the reliability of the semiconductor structure.

[0062] Furthermore, during the formation of the semiconductor structure, the second isolation layer 150 initially covers the entire side wall of the device fin 120, and by removing a portion of the thickness of the second isolation layer 150, a portion of the height of the device fin 120 is exposed, so that the isolation fin 140 and the second isolation layer 150 are made of the same material, which is also beneficial for improving the consistency of the removal rate of the isolation fin 140 and the second isolation material layer when removing a portion of the thickness of the isolation fin 140 and a portion of the thickness of the second isolation material layer, thereby improving the consistency of the top height of the isolation fin 140 and the second isolation layer 150 in the semiconductor structure.

[0063] In other embodiments, different materials may be selected for the isolation fin and the second isolation layer according to process requirements.

[0064] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 14 to 37 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0065] refer to Fig.14 and Fig.15 , Fig.14 is a cross-sectional view along a first direction (not shown) at the position of the partition area, Fig.15 It is a cross-sectional view along a second direction (not shown) at the position of the partition area, and the first direction is perpendicular to the second direction.

[0066] The first direction is perpendicular to an extension direction of a device fin formed subsequently, and the second direction is parallel to an extension direction of a device fin formed subsequently.

[0067] A substrate 510 is provided, wherein the substrate 510 includes an isolation region II and a device region I.

[0068] The substrate 510 is used to provide a process platform for subsequent process steps.

[0069] In this embodiment, the substrate 510 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In this embodiment, the substrate 510 is used to form a fin field effect transistor.

[0070] The isolation region II is used to achieve isolation between device regions I, and is also used to provide a process platform for the subsequent formation of a first isolation layer.

[0071] The device area I is used to provide a process platform for forming various semiconductor devices in subsequent process steps.

[0072] In this embodiment, the device region I includes a first device region (not labeled) and a second device region (not labeled). The device fins subsequently formed in the first device region are made of a different material from the device fins formed in the second device region. Device fins of different materials can be used to form a dual-channel semiconductor structure.

[0073] In this embodiment, the first device region is used to form a PMOS device, and the second device region is used to form an NMOS device.

[0074] Therefore, in this embodiment, a channel material layer 521 is further formed in the substrate 510 .

[0075] Specifically, the channel material layer 521 is located in the substrate 510 of the first device region.

[0076] When forming device fins in a subsequent process, the channel material layer 521 provides a process basis for forming the device fins in the first device region.

[0077] As an example, the first device region is used to form a PMOS device, so the material of the channel material layer 521 is silicon germanium, and the substrate 510 is a silicon substrate, so that the material of the device fins subsequently formed in the first device region is silicon germanium, and the material of the device fins subsequently formed in the second device region is silicon.

[0078] As an example, after a groove is formed in the substrate 510 , the channel material layer 521 is formed in the groove by an epitaxial growth process.

[0079] In this embodiment, the forming method further includes: forming a first protection layer 511 covering the substrate 510 on the top of the substrate 510 .

[0080] Specifically, the first protection layer 511 also covers the channel material layer 521 .

[0081] In the subsequent process, it is necessary to form a metal catalyst material layer above the substrate. If the metal catalyst material layer directly contacts the substrate 510, metal ions may diffuse into the substrate 510 and contaminate the substrate 510. The first protective layer 511 can isolate the substrate 510 and the metal catalyst material layer. In addition, in the subsequent process (for example, in the subsequent back etching process of forming the second isolation layer), the first protective layer 511 can protect the top of the device fin in the first device area, reduce the loss of the device fin in the first device area, and help control the uniformity of the height of the device fin in the first device area.

[0082] The material of the first protection layer 511 includes single crystal silicon.

[0083] In this embodiment, the material of the first protective layer 511 is the same as that of the substrate 510 , and the material of the first protective layer 511 is silicon.

[0084] Making the material of the first protective layer 511 the same as that of the substrate 510 is conducive to directly forming the first protective layer 511 with good uniformity on the top of the substrate 510 by epitaxial growth.

[0085] It should be noted that, along the normal direction of the substrate 510, the thickness of the first protective layer 511 should not be too large or too small. If the thickness of the first protective layer 511 is too large, it will be more difficult to form the first protective layer 511 whose material is entirely single crystal silicon, and it will also affect the morphology of the device fins formed subsequently. In addition, when the device fins are formed in the subsequent process, it is easy to cause the top of the device fins in the first device area to still have a thicker first protective layer 511, which will affect the channel current at the top of the device fins; if the thickness of the first protective layer 511 is too small, it is easy for the first protective layer 511 to be removed prematurely in the subsequent process (for example, the first protective layer 511 may be removed before the second isolation layer is formed), thereby causing the first protective layer 511 to fail to play the role of protecting the top of the device fins in the first device area.

[0086] Continue to refer Fig.14 and Fig.15 , and combined with reference Figures 16 to 25 ,in, Fig.16 , Fig.18 , Fig. 20 , Fig. 22 and Fig.24 is a cross-sectional view along the first direction at the position of the partition area II, Fig.17 , Fig.19 , Fig.21 , Fig.23 and Fig.25 4 is a cross-sectional view taken along the second direction at the location of the partition region II, where a first isolation layer 560 is formed in the substrate 510 of the partition region II.

[0087] The first isolation layer 560 provides a process basis for forming isolation fins in a subsequent process.

[0088] In this embodiment, when the substrate 510 is etched to form device fins in a subsequent process, the first isolation layer 560 located in the isolation region II will simultaneously form isolation fins. Forming the first isolation layer 560 in the substrate 510 in the isolation region II first can more accurately limit the scope of the isolation region II, thereby providing a better process basis for the subsequent formation of isolation fins.

[0089] The material of the first isolation layer 560 is an insulating material, and the material of the first isolation layer 560 includes one or more of silicon oxide, silicon oxynitride, silicon nitride and silicon carbide. As an example, the material of the first isolation layer 560 is silicon oxide. Silicon oxide has good insulation and generates less stress, which is conducive to improving process reliability.

[0090] In this embodiment, in the step of forming a first isolation layer 560 in the substrate 510 of the isolation region II, the height of the first isolation layer 560 is greater than or equal to the preset fin height, thereby ensuring that the materials of the formed isolation fins are all insulating materials to improve the electrical isolation effect of the isolation fins.

[0091] As an example, the height of the first isolation layer 560 is greater than a preset fin height.

[0092] If the height of the first isolation layer 560 is greater than the height of the preset fin, a portion of the first isolation layer 560 will remain in the substrate 510 when etching to form the isolation fin in the subsequent process, which is beneficial for further isolating each semiconductor device and preventing leakage current between devices.

[0093] It should be noted that, in the step of forming the first isolation layer 560 in the substrate 510 of the partition area II, the difference between the height of the first isolation layer 560 and the preset fin height should not be too small or too large. If the difference between the height of the first isolation layer 560 and the preset fin height is too large, the stress of the device fin adjacent to the first isolation layer 560 is easily affected, and the device fin is prone to bending in the subsequent process, which is not conducive to the subsequent formation of other structures on the device fin (for example, not conducive to the filling of the material of the metal gate structure); if the difference between the height of the first isolation layer 560 and the preset fin height is too small, the effect of the isolation fin being used to completely replace the device fin of the partition area II is not good, that is, there are still residual device fins in the partition area II, which affects the isolation effect and brings hidden defects. Therefore, in the step of forming the first isolation layer 560 in the substrate 510 of the partition area II, the difference between the height of the first isolation layer 560 and the preset fin height is 10 nanometers to 60 nanometers.

[0094] Here, the height of the first isolation layer 560 refers to: the vertical distance between the bottom of the first isolation layer 560 and the top of the substrate 510 .

[0095] In this embodiment, the step of forming the first isolation layer 560 includes: referring to Figures 14 to 23 , a groove 550 (such as Fig. 22 and Fig.23 shown); Reference Figure 24 to Figure 25 , forming the first isolation layer 560 in the trench 550 .

[0096] By first forming the groove 550 and then forming the first isolation layer 560 in the groove, the complexity of forming the first isolation layer 560 is reduced, and it is easy to select a suitable material for the first isolation layer 560 so that the first isolation layer 560 can meet the requirements for electrical isolation effect.

[0097] In this embodiment, the groove 550 provides a space for subsequently forming a first isolation layer 560 .

[0098] Specifically, the substrate 510 below the isolation region II is etched to form a trench 550 .

[0099] In this embodiment, the process of etching the substrate 510 below the metal catalyst layer 531 is a metal assisted chemical etching (MACE) process.

[0100] The groove 550 formed using the metal-assisted chemical etching process has a corner that is closer to a right angle and a higher aspect ratio. When the first isolation layer 560 is formed in the subsequent process, the angle between the side wall of the first isolation layer 560 and the normal direction of the substrate 510 can be reduced, thereby reducing the occupation of the top area of ​​the substrate 510 by the first isolation layer 560.

[0101] The metal-assisted chemical etching process is described in detail below.

[0102] Combined with reference Figures 14 to 19 A metal catalyst layer 531 (such as Fig.18 and Fig.19 shown).

[0103] The metal catalyst layer 531 is formed in the isolation region II, so that the substrate 510 in the isolation region II can be etched later under the action of the metal catalyst layer 531 .

[0104] In this embodiment, the material of the metal catalyst layer 531 includes an inert metal catalyst, which is composed of an inert metal and a carrier. The inert metal includes one or more of platinum, gold, ruthenium and iridium; the carrier includes amorphous silicon oxide, mesoporous silicon oxide, covalent organic framework (Covalent Organic Framework, COF) or metal-organic framework (Metal-Organic Framework, MOF) materials, etc.

[0105] Specifically, the mass fraction of the precious metal in the metal catalyst layer 531 is 2 wt % (weight percentage) to 15 wt %.

[0106] More specifically, in this embodiment, the calcination temperature for preparing the metal catalyst layer 531 is between 300 degrees Celsius and 500 degrees Celsius to prevent agglomeration. In addition, in order to make the noble metal catalyst single atomic layer or atomic cluster highly dispersed in the metal catalyst layer 531, the metal catalyst layer 531 is obtained by ultrasonic dispersion synthesis method, and the synthesis temperature of the ultrasonic dispersion synthesis method is 40 degrees Celsius to 90 degrees Celsius.

[0107] It should be noted that if Fig.18 and Fig.19 As shown, along the normal direction of the substrate 510, the thickness w of the metal catalyst layer 531 should not be too large or too small. If the thickness w of the metal catalyst layer 531 is too large, when etching the substrate 510 to form the groove 550, it is easy to cause the depth of the middle position of the bottom of the groove 550 to be greater than the depth of the corner position, which is not conducive to controlling the corner shape of the groove 550; if the thickness w of the metal catalyst layer 531 is too small, it is easy to affect the uniformity of the metal catalyst layer 531. Therefore, in this embodiment, the thickness w of the metal catalyst layer 531 is 1 nanometer to 5 nanometers.

[0108] The steps of forming the metal catalyst layer 531 are described in detail below with reference to the accompanying drawings.

[0109] refer to Fig.14 and Fig.15 , a metal catalyst material layer 530 is formed on the top of the first protective layer 511 .

[0110] The metal catalyst material layer 530 is used to provide a process basis for forming a metal catalyst layer in a subsequent process.

[0111] Specifically, the process of forming the metal catalyst material layer 530 includes a metal catalyst deposition process (Metal Catalyst Deposition).

[0112] Continue to refer Fig.14 and Fig.15 After forming the metal catalyst material layer 530, a mask structure 540 is formed on the top of the metal catalyst material layer 530, and the mask structure 540 includes a patterned third mask layer 543, and the third mask layer 543 is located in the isolation region II.

[0113] The mask structure 540 is used as an etching mask for subsequent patterning of the metal catalyst material layer 530 .

[0114] Specifically, the mask structure 540 includes a first mask layer 541 , a second mask layer 542 , and a third mask layer 543 stacked sequentially from bottom to top.

[0115] More specifically, the first mask layer 541 serves as a hard mask material layer, and the material of the first mask layer 541 includes silicon oxide; the material of the second mask layer 542 includes a bottom anti-reflective coating (BARC) material to improve exposure uniformity and pattern transfer accuracy; the material of the third mask layer 543 includes photoresist (PR).

[0116] refer to Fig.16 and Fig.17 , using the third mask layer 543 as a mask, patterning the second mask layer 542 and the first mask layer 541 to form a hard mask layer 544 located in the isolation region II.

[0117] The hard mask layer 544 provides a process basis for subsequent patterning of the metal catalyst material layer 530 .

[0118] refer to Fig.18 and Fig.19 , using the hard mask layer 544 as a mask, patterning the metal catalyst material layer 530 to form a metal catalyst layer 531 located on the top of the substrate 510 in the isolation region II.

[0119] In this embodiment, the process of patterning the metal catalyst material layer 530 includes dry etching.

[0120] Specifically, the process parameters of the dry etching include: the reaction gas includes a fluorine-containing gas such as carbon tetrafluoride or nitrogen trifluoride, and the reaction temperature is 15 degrees Celsius to 200 degrees Celsius.

[0121] refer to Fig. 20 and Fig.21 Under the catalytic effect of the metal catalyst layer 531 , the substrate 510 located below the metal catalyst layer 531 is etched through a wet etching process to form a groove 550 .

[0122] Under the catalytic effect of the metal catalyst layer 531 , the etching rate of the substrate 510 located below the metal catalyst layer 531 can be accelerated, while the loss of the substrate 510 in other areas is small.

[0123] In this embodiment, the line width (CD) of the trench 550 is 80 nanometers to 150 nanometers.

[0124] Specifically, the process parameters of the wet etching process include: the etching solution includes a mixed solution of hydrofluoric acid and hydrogen peroxide, in which the volume ratio of hydrofluoric acid to hydrogen peroxide is 1:1 to 10:1, the solution temperature is 15 degrees Celsius to 35 degrees Celsius, and the reaction time is 2 minutes to 20 minutes.

[0125] It should be noted that the volume ratio of hydrofluoric acid to hydrogen peroxide should not be too small or too large. If the volume ratio of hydrofluoric acid to hydrogen peroxide is too small, it is easy to cause insufficient reaction; if the volume ratio of hydrofluoric acid to hydrogen peroxide is too large, it is easy to cause the hydrogen fluoride in the hydrofluoric acid to volatilize, affecting the stability of the solution. For this reason, in this embodiment, the volume ratio of hydrofluoric acid to hydrogen peroxide is 1:1 to 10:1.

[0126] It should also be noted that the solution temperature should not be too low or too high. If the solution temperature is too low, the reaction rate is too slow and it is difficult to form a stable equilibrium state; if the solution temperature is too high, the surface roughness of the groove 550 is poor. For this reason, in this embodiment, the solution temperature is 15 degrees Celsius to 35 degrees Celsius.

[0127] In addition, as the etching proceeds, the position of the metal catalyst layer 531 gradually decreases. Therefore, after the groove 550 is formed, the metal catalyst layer 531 is located at the bottom of the groove 550 .

[0128] refer to Fig. 22 and Fig.23 After forming the groove 550 , the metal catalyst layer 531 is also removed.

[0129] If the metal catalyst layer 531 is not removed after the groove 550 is formed, the metal catalyst layer 531 will remain in the substrate in subsequent processes because the metal material has a certain conductivity, which can easily affect the isolation effect between the device regions of the semiconductor structure.

[0130] In this embodiment, the metal catalyst layer 531 is removed by a wet process.

[0131] In this embodiment, the advantage of using a wet method to remove the metal catalyst layer 531 is that the metal catalyst layer 531 in deeper grooves can be removed, the process requirements for wet removal are lower, and the effect of removing the metal catalyst layer 531 is better.

[0132] In this embodiment, the reaction solution of the wet process for removing the metal catalyst layer 531 includes one or more of phosphoric acid, hydrofluoric acid, sulfuric acid, hydrogen peroxide and SC1. Here, SC1 solution refers to a mixed solution of ammonia water, hydrogen peroxide and water.

[0133] As an example, the process parameters of the wet removal process include: the reaction solution includes a mixed solution of hydrofluoric acid and hydrogen peroxide, in which the volume ratio of hydrofluoric acid to hydrogen peroxide is 1:10 to 5:1, the solution temperature is 15 degrees Celsius to 40 degrees Celsius, and the process time is 10 minutes to 2 hours.

[0134] It should be noted that in other embodiments, other methods may also be used to form the grooves located in the isolation area, for example, by forming a mask layer on the top of the substrate to define the position of the grooves, and using the mask layer as a mask to etch and form the grooves located in the isolation area.

[0135] refer to Fig.24 and Fig.25 , a first isolation layer 560 is formed in the trench 550 .

[0136] Specifically, the step of forming the first isolation layer 560 includes: forming a first isolation material layer (not shown) in the groove 550 ; planarizing the first isolation material layer, removing the first isolation material layer outside the groove 550 , and forming the first isolation layer 560 .

[0137] In this embodiment, the first isolation material layer is planarized, and the top of the first isolation layer 560 is flush with the top of the first protection layer 511 .

[0138] Specifically, the process of forming the first isolation material layer includes a flowable chemical vapor deposition process.

[0139] The flowable chemical vapor deposition process has good filling ability and is suitable for filling spaces with high aspect ratios. It is beneficial to reduce the probability of defects such as voids in the formation of the first isolation layer 560, and correspondingly improves the quality of the first isolation layer 560 and its insulation performance, thereby improving the performance of the semiconductor structure.

[0140] It should be noted that in other embodiments, the isolation layer may be formed without forming a groove. Specifically, the method of forming the first isolation layer in the substrate includes: injecting isolation ions into the substrate of the isolation region, and the substrate doped with isolation ions is used as the isolation layer.

[0141] The isolated ions may be any compatible and non-conductive ions.

[0142] refer to Figure 26 to Figure 34 ,in, Fig.26 , Fig.28 , Fig.30 and Fig.32 is a cross-sectional view along the first direction at the position of the partition area II, Fig.33 is a cross-sectional view in the first direction at the device region I position, Fig. 27 , Fig.29 , Fig.31 and Fig.34 It is a cross-sectional view along the second direction at the position of the partition area II.

[0143] The substrate 510 and the first isolation layer 560 are patterned, a device fin 591 is formed on the remaining substrate 510 in the device region I, and an isolation fin 590 is formed on the remaining substrate 510 in the isolation region II.

[0144] The steps of patterning the substrate 510 and the first isolation layer 560 include: Fig.26 and Fig. 27 As shown, a fin mask structure 570 is formed on the substrate 510 in the isolation region II and the device region I.

[0145] The fin mask structure 570 is used as an etching mask for forming device fins and isolation fins.

[0146] Specifically, the fin mask structure 570 includes a first fin mask layer 571 , a second fin mask layer 572 , a third fin mask layer 573 and a fourth fin mask layer 574 which are sequentially stacked from bottom to top.

[0147] In a specific embodiment, the first fin mask layer 571 serves as a liner layer, the material of the first fin mask layer 571 is silicon oxide, and the first fin mask layer 571 is formed by an atomic layer deposition process or a low-temperature thermal oxidation (thermal) process.

[0148] The second fin mask layer 572, the third fin mask layer 573 and the fourth fin mask layer 574 serve as hard mask layers for the fin etching process. The material of the second fin mask layer 572 is silicon nitride, and the second fin mask layer 572 can be formed by an atomic layer deposition process or a high aspect ratio process (High Aspect Ratio Process, HARP); the material of the third fin mask layer 573 is silicon oxide, and the third fin mask layer 573 is formed by an atomic layer deposition process or a low-temperature thermal oxidation process; the material of the fourth fin mask layer 574 is silicon nitride, and the fourth fin mask layer 574 can be formed by an atomic layer deposition process or a high aspect ratio process. In other words, the hard mask layer is an ONO (Oxide-SiN-Oxide) structure.

[0149] refer to Figure 28 to Figure 29 , patterning the fourth mask layer 574 to form a core layer 575.

[0150] In this embodiment, the core layer 575 provides a process platform for subsequently forming a spacer material layer.

[0151] refer to Figure 30 to Figure 31 , a spacer material layer 580 is formed on the substrate at the side of the core layer 575 , and the spacer material layer 580 covers the sidewall and top of the core layer 575 .

[0152] In this embodiment, the material of the sidewall material layer 580 includes silicon nitride. 。

[0153] In this embodiment, the spacer material layer 580 is formed by an atomic layer deposition process, so that the spacer material layer 580 conformally covers the sidewall and top of the core layer 575 .

[0154] Specifically, the process temperature of the atomic layer deposition process is 500 degrees Celsius to 600 degrees Celsius.

[0155] After forming the sidewall material layer 580, it also includes: removing the sidewall material layer 580 located at the top of the core layer 575 and the top of the substrate 510 through a maskless etching process to form a mask sidewall located at the sidewall of the core layer 575 (not shown); after forming the mask sidewall, removing the core layer 575.

[0156] The mask sidewalls provide a process basis for forming fins in subsequent processes.

[0157] refer to Figure 32 to Figure 34After forming a mask sidewall on the substrate 510, the substrate 510 and the first isolation layer 560 are etched using the mask sidewall as a mask to form a device fin 591 and an isolation fin 590; the device fin 591 is located in the device region I, and the isolation fin 590 is located in the isolation region II.

[0158] In this embodiment, a channel material layer 521 is further formed in the substrate 510 of the first device region IP. Therefore, when forming the device fin 591 , the channel material layer 521 is also etched.

[0159] Specifically, the device fin 591 is formed by etching the substrate 510 and the channel material layer 521 of the device region I, and the isolation fin 590 is formed by etching the first isolation layer 560 of the isolation region II.

[0160] Specifically, in the process of forming the device fin 591 and the isolation fin 590 by etching, the substrate 510 and the channel material layer 521 of the device area I are subjected to multiple first etchings, and the first isolation layer 560 of the isolation area II is subjected to multiple second etchings, and the first etching and the second etching are performed alternately.

[0161] Each first etching is used to etch a partial thickness of the substrate 510 and the channel material layer 521 , so that after multiple first etchings, a device fin 591 that meets height requirements is obtained.

[0162] Each second etching is used to etch a portion of the thickness of the first isolation layer 560 , so that after multiple second etchings, an isolation fin 590 that meets the height requirement is obtained.

[0163] Since the materials of the substrate 510 and the channel material layer 521 are different from the materials of the isolation fins 590, if the substrate 510, the channel material layer 521 and the first isolation layer 560 are etched at the same time, there is usually a certain etching selectivity ratio between the materials of the substrate 510 and the channel material layer 521 and the materials of the isolation fins 590. Therefore, by alternating the first etching and the second etching, the etching objects of the first etching are mainly the substrate 510 and the channel material layer 521, and the etching objects of the second etching are mainly the first isolation layer 560. It is easy to make the device fins 591 and the isolation fins 590 reach the target height by reasonably setting the respective parameters of the first etching and the second etching.

[0164] For example, by reasonably setting the parameters of the first etching and the second etching, the etching selectivity ratio of the material of the device fin 591 and the material of the isolation fin 590 is close to 1:1 as a whole, which is conducive to the simultaneous formation of the device fin 591 and the isolation fin 590 with the same morphology, thereby improving the height uniformity of the isolation fin 590 and the device fin 591.

[0165] It should be noted that, in other embodiments, based on different etching amounts, the bottom of the isolation fin may also be higher than the bottom of the device fin, that is, the height of the isolation fin is smaller than the height of the device fin.

[0166] In this embodiment, the etching process for forming the device fin 591 and the isolation fin 590 includes: a dry etching process.

[0167] The process parameters of the dry etching process include: the reaction gas includes hydrogen fluoride, ammonia, argon and nitrogen, the process temperature is 35 degrees Celsius to 110 degrees Celsius, the process pressure is 20 mTorr to 3000 mTorr, the process time is 10 seconds to 20 seconds, and the gas flow rate of the reaction gas is 30 standard cubic centimeters per minute to 500 standard cubic centimeters per minute.

[0168] The device fin 591 of the device region I provides a process basis for forming an effective fin, and the effective fin is used to provide a conductive channel when the semiconductor device is working.

[0169] The material of the device fin 591 includes one or more of silicon, silicon germanium, germanium and III-V semiconductor materials. The material of the device fin 591 is determined according to the channel conductivity type and performance requirements of the transistor.

[0170] In this embodiment, the device region I includes a first device region IP and a second device region IN. The device fins 591 of the first device region IP and the device fins 591 of the second device region IN are made of different materials. The device fins 591 of different materials can be used to form a dual-channel semiconductor structure.

[0171] As an example, the material of the device fin 591 of the second device region IN is silicon, the material of the device fin 591 of the second device region IN is the same as that of the substrate 510, and the material of the device fin 591 of the first device region IP is silicon germanium.

[0172] In this embodiment, the first device region IP is used to form a PMOS device, and the second device region IN is used to form an NMOS device.

[0173] Compared with the prior art, in the entire process of the formation method of this embodiment, the fin cutting step for the device fin 591 after the device fin 591 is formed is reduced, thereby reducing the loss of the IP device fin 591 in the first device area, improving the quality of the IP device fin 591 in the first device area, and further improving the performance of the semiconductor structure.

[0174] In this embodiment, in the step of forming the first isolation layer 560 in the substrate 510 of the isolation region II, the height of the first isolation layer 560 is greater than the preset fin height. Therefore, in the step of patterning the substrate 510 and the first isolation layer 560, the first isolation layer 560 in the remaining substrate 510 of the isolation region II is retained so that the isolation fin 590 is located on the remaining first isolation layer 560 and is an integrated structure with the remaining first isolation layer 560.

[0175] The isolation fin 590 plays a role of a dummy fin, and the isolation fin 590 is not used to form a semiconductor device.

[0176] In this embodiment, the isolation fins 590 can also isolate the semiconductor devices to prevent leakage current between the devices.

[0177] The material of the isolation fin 590 is an insulating material, and the material of the isolation fin 590 includes one or more of silicon oxide, silicon oxynitride, silicon nitride and silicon carbide. As an example, the material of the isolation fin 590 is silicon oxide.

[0178] The remaining first isolation layer 560 is helpful to further isolate each semiconductor device and prevent leakage current from occurring between the devices.

[0179] Accordingly, the isolation fin 590 and the first isolation layer 560 are made of the same material.

[0180] In other embodiments, depending on the depth of the trench, the semiconductor structure may not include the remaining first isolation layer.

[0181] In this embodiment, after forming the device fin 591 and the isolation fin 590, the formation method also includes: forming a pad material layer (not shown) on the substrate on the side of the device fin 591 and the isolation fin 590, and the pad material layer covers the side walls and top of the device fin 591 and the isolation fin 590.

[0182] When a portion of the second isolation material layer is removed in a subsequent process, the liner material layer can protect the sidewalls of the device fin 591 and reduce the loss of the device fin 591 caused by the back etching process.

[0183] Specifically, the material of the liner material layer includes silicon oxide.

[0184] refer to Figure 35 to Figure 37 ,in, Fig.35 is a cross-sectional view along the first direction at the position of the partition area II, Fig.36 is a cross-sectional view along the first direction at the device region I, Fig.37It is a cross-sectional view along the second direction at the position of the partition area II.

[0185] The method for forming the semiconductor structure further includes: forming a second isolation layer 562 on the substrate 510 at the sides of the device fin 591 and the isolation fin 590 , wherein the top of the second isolation layer 562 is lower than the top of the device fin 591 .

[0186] The second isolation layer 562 is used to further isolate each semiconductor device to prevent leakage current between devices.

[0187] The material of the second isolation layer 562 is an insulating material. As an example, the material of the second isolation layer 562 is silicon oxide. Silicon oxide has good insulation properties, and the stress generated by silicon oxide is also small, which is conducive to improving process reliability. In other embodiments, the material of the second isolation layer can also be a suitable insulating material such as silicon oxynitride.

[0188] Specifically, the step of forming the second isolation layer includes: forming a second isolation material layer (not shown) on the substrate on the side of the device fin and the isolation fin, and the second isolation material layer covers the side walls of the device fin 591 and the isolation fin 590.

[0189] In this embodiment, the process of forming the second isolation material layer includes a flowable chemical vapor deposition process.

[0190] The flowable chemical vapor deposition process has good filling capability and is suitable for filling spaces with high aspect ratios. It is beneficial to reduce the probability of defects such as voids in the formation of the second isolation layer 562, and correspondingly improves the quality and insulation performance of the second isolation layer 562, thereby improving the performance of the semiconductor structure.

[0191] Specifically, the step of forming the second isolation layer also includes: removing a portion of the thickness of the second isolation material layer to form a second isolation layer 562 covering a portion of the side wall of the device fin 591, and in the process of removing a portion of the thickness of the second isolation material layer, a portion of the height of the isolation fin 590 is simultaneously removed so that the top of the remaining isolation fin 590 is flush with the top of the second isolation layer 562.

[0192] As an example, a portion of the height of the isolation fin 590 and a portion of the thickness of the second isolation layer 562 are removed by etching back. For example, the etching back process may include a dry etching process.

[0193] In the process of forming the semiconductor structure, because the device fin 591 and the isolation fin 590 are formed in the same patterning step, that is, the initial height of the isolation fin 590 is relatively large, the formation process of the second isolation layer 562 usually includes the step of removing a portion of the thickness of the second isolation material layer. Therefore, by making the top of the second isolation layer 562 flush with the top of the isolation fin 590, it is convenient to remove a portion of the height of the isolation fin 590 in the process of removing a portion of the thickness of the second isolation material layer, so that the top of the remaining isolation fin 590 is flush with the second isolation layer 562, thereby simplifying the process steps.

[0194] The device fin 591 that exposes a portion of the height in the device region I is used as an effective fin. The effective fin is used to provide a conductive channel when the semiconductor device is working.

[0195] In this embodiment, the isolation fin 590 and the second isolation layer 562 are made of the same material.

[0196] Making the isolation fin 590 and the second isolation layer 562 of the same material is also beneficial in the subsequent process of removing a portion of the thickness of the isolation fin 590 and the second isolation layer 562 to expose a portion of the height of the device fin 591 in the device area I, thereby improving the consistency of the removal rate of the isolation fin 590 and the second isolation layer 562, thereby improving the consistency of the top height of the isolation fin 590 and the second isolation layer 562 of the semiconductor structure.

[0197] In other embodiments, different materials may be selected for the first isolation layer and the second isolation layer according to process requirements.

[0198] Specifically, in the process of removing a portion of the thickness of the second isolation material layer, the first fin mask layer 571, the second fin mask layer 572 and the third fin mask layer 573 remaining when the device fin 591 and the isolation fin 590 are formed are removed at the same time, and the pad material layer covering the side walls of the device fin 591 and the isolation fin 590 is also removed. The remaining pad material layer serves as a second protective layer 561, and the top of the second protective layer 561 is flush with the top of the second isolation layer 562.

[0199] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a partition region and a device region; A device fin, located on the substrate of the device region; The isolation fin is located on the substrate of the isolation area.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a first isolation layer located in the substrate of the isolation region; The isolation fin is located on the first isolation layer and is an integral structure with the first isolation layer.

3. The semiconductor structure according to claim 2, wherein: A vertical distance between a bottom of the first isolation layer and a top of the substrate is 10 nanometers to 60 nanometers.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes: a second isolation layer located on the substrate at the side of the device fin and the isolation fin, the second isolation layer covers a portion of the sidewall of the device fin, and the top of the second isolation layer is flush with the top of the isolation fin.

5. The semiconductor structure according to claim 4, characterized in that The material of the isolation fin is the same as that of the second isolation layer.

6. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The material of the isolation fin includes one or more of silicon oxide, silicon oxynitride, silicon nitride and silicon carbide.

7. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The device region includes a first device region and a second device region; The device fin in the first device region and the device fin in the second device region are made of different materials.

8. A method for forming a semiconductor structure, characterized in that: Providing a substrate, wherein the substrate comprises a partition region and a device region; forming a first isolation layer in the substrate of the partition region; The substrate and the first isolation layer are patterned, a device fin is formed on the remaining substrate in the device region, and an isolation fin is formed on the remaining substrate in the isolation region.

9. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming the first isolation layer comprises: forming a trench in the substrate of the partition region; forming the first isolation layer in the trench; or, The step of forming the first isolation layer includes: injecting isolation ions into the substrate of the isolation region, and the substrate doped with the isolation ions serves as the first isolation layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the trench includes a metal-assisted chemical etching process.

11. The method for forming a semiconductor structure according to claim 10, wherein: The steps of forming the groove include: forming a metal catalyst layer on top of the substrate in the partition region; Under the action of the metal catalyst layer, the substrate below the metal catalyst layer is etched by a wet etching process to form the groove; After forming the grooves, the metal catalyst layer is removed.

12. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the metal catalyst layer, the material of the metal catalyst layer includes an inert metal catalyst, and the inert metal catalyst is composed of an inert metal and a carrier, and the inert metal includes one or more of platinum, gold, ruthenium and iridium; the carrier includes amorphous silicon oxide, mesoporous silicon oxide, metal organic framework or covalent organic framework.

13. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the metal catalyst layer, the thickness of the metal catalyst layer is 1 nanometer to 5 nanometers.

14. The method for forming a semiconductor structure according to claim 11, wherein: Before forming the trench, the forming method further includes: forming a first protection layer covering the substrate.

15. The method for forming a semiconductor structure according to claim 14, wherein: In the step of forming a protection layer covering the substrate, the material of the first protection layer includes single crystal silicon.

16. The method for forming a semiconductor structure according to claim 14, wherein: In the step of forming a protective layer covering the substrate, the thickness of the first protective layer is 2 nanometers to 9 nanometers.

17. The method for forming a semiconductor structure according to claim 11, wherein: The process parameters of the wet etching process include: the etching solution includes a mixed solution of hydrofluoric acid and hydrogen peroxide, in which the volume ratio of hydrofluoric acid to hydrogen peroxide is 1:1 to 10:1, the solution temperature is 15 degrees Celsius to 35 degrees Celsius, and the reaction time is 2 minutes to 20 minutes.

18. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming a first isolation layer in the substrate of the partition region, the height of the first isolation layer is greater than a preset fin height; In the step of patterning the substrate and the first isolation layer, the first isolation layer in the remaining substrate of the isolation region is retained, so that the isolation fin is located on the remaining first isolation layer.

19. The method for forming a semiconductor structure according to claim 18, wherein: In the step of forming a first isolation layer in the substrate of the partition area, a difference between a height of the first isolation layer and a preset fin height is 10 nanometers to 60 nanometers.

20. The method for forming a semiconductor structure according to claim 8, wherein: After forming the device fin and the isolation fin, the forming method further comprises: forming a second isolation layer on the substrate at the side of the device fin and the isolation fin, wherein the top of the second isolation layer is lower than the top of the device fin; The step of forming the second isolation layer includes: forming a second isolation material layer on the substrate on the side of the device fin and the isolation fin, the second isolation material layer covering the side walls of the device fin and the isolation fin; removing a portion of the thickness of the second isolation material layer to form a second isolation layer covering a portion of the side walls of the device fin, and in the process of removing a portion of the thickness of the second isolation material layer, removing a portion of the height of the isolation fin so that the top of the remaining isolation fin is flush with the second isolation layer.

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