SIC MOSFET with saturation current clamping structure

Abstract

An improved silicon carbide (SiC) super junction (SJ) MOSFET includes at least two buried P-shield (BPS) regions disposed face-to-face to reduce gate oxide electric field intensity and saturation current. And the two BPS regions are separated from the body region and are adjacent to the side wall or the bottom of the P column region. Besides, a saturation current clamping (SCP) structure is formed in a junction field effect transistor (JFET) region between the two BPS regions, and the saturation current of the device in the forward conduction stage is limited, so that the short-circuit capability of the device is improved.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more specifically to a silicon carbide (SiC) super junction (SJ) metal oxide semiconductor field effect transistor (MOSFET), each unit of which includes at least two buried P-shield (BPS) regions placed face to face, the BPS region being separated from the body region and adjacent to the P column (PC) region of the SJ structure to reduce the electric field strength and specific on-resistance of the gate oxide layer. At least one saturation current clamping (SCP) structure is formed in a vertical junction field effect transistor (JFET) region located between the two BPS regions, which limits the saturation current of the device in the forward conduction stage, thereby improving the short-circuit capability of the device. Background Art

[0002] Due to the physical properties of SiC, SiC-MOSFETs have higher breakdown voltage, lower on-resistance and faster switching speed than Si-MOSFETs. However, since the breakdown electric field strength of SiC is 10 times that of Si, SiC-MOSFETs have higher gate oxide electric field strength than Si-MOSFETs. To solve this problem, a P+ shielding region is set below the N+ source region and the P-base region as a field relaxation layer near the gate oxide layer, as shown in Figure 1 (Figure 10.1 on page 260 of the book "Silicon Carbide Power Devices", author B. Jayant Baliga). However, since the area of ​​SiC-MOSFETs devices is much smaller than that of Si-MOSFETs, it will cause the junction temperature of SiC-MOSFETs devices to be higher before short circuit (SC) failure, so SC failure is still the most serious reliability problem of shielded SiC-MOSFETs devices. During the SC transient process, high direct current (DC) voltage and large saturation current will be applied to the device. If the device does not have sufficient SC tolerance, it will cause performance degradation or even serious burnout failure.

[0003] Therefore, in the field of design and manufacturing of SiC-MOSFETs, there is still a need to provide a new unit structure, device structure and manufacturing method to solve the difficulties and limitations involved above, so that SiC-MOSFETs have lower gate oxide layer electric field strength, obtain lower specific on-resistance and lower saturation current, so as to improve the short-circuit capability of the device. Summary of the invention

[0004] The present invention discloses a novel SiC SJ MOSFET, which has two BPS regions placed face to face, located in the drift region, and adjacent to the PC region of the SJ structure, and the BPS region is separated from the body region (or base region) to reduce the electric field strength of the gate oxide layer. The positions of the two BPS regions can be optimized to obtain a lower specific on-resistance while shielding the gate oxide layer interface to prevent it from being affected by the high electric field in the drift region. The two BPS regions are located on the sidewalls and / or the bottom of the PC region. In addition, an SCP structure is formed in the vertical JFET region between the two BPS regions to clamp the voltage, thereby limiting the saturation current of the device in the forward conduction phase to improve the short-circuit capability of the device.

[0005] According to one aspect of the present invention, a SiC device comprising a plurality of units is disclosed, wherein each unit is located in an active region, and further comprises: an epitaxial layer having a first conductivity type, grown on a substrate and comprising a plurality of sub-epitaxial layers; a source region having a first conductivity type, formed on the upper portion of the epitaxial layer and located in a body region having a second conductivity type; an SJ structure, comprising an epitaxial layer and a PC region, wherein the PC region has a second conductivity type, is located on the substrate and is connected to the body region; a planar gate composed of a doped polysilicon layer, lined with a gate oxide layer; a first type JFET region having a first conductivity type, formed between two adjacent body regions; at least Two BPS regions with a second conductivity type are placed face to face, have a doping concentration higher than that of the adjacent PC region, and are separated from the body region; a second type JFET region with a first conductivity type is formed between the two BPS regions; both the source region and the body region are connected to the source metal; the PC region has a linear, square, hexagonal or octagonal topology; because the hexagonal topology has the lowest specific on-resistance, the present invention discloses a topology with hexagonal units and describes it in detail as an example; the central part of the gate oxide layer has a thick oxide layer; the two BPS regions are adjacent to the side walls of the PC region, or adjacent to the bottom of the PC region and their widths are greater than the width of the PC region.

[0006] According to another aspect of the present invention, in some preferred embodiments, the substrate has a first conductivity type, the epitaxial layer is a single epitaxial layer with a uniform doping concentration and a resistivity of R, and the SiC device further includes a buffer layer located between the substrate and the PC region, having the first conductivity type and a resistivity of Rb, wherein the relationship between R and Rb is: R <Rb。

[0007] According to another aspect of the present invention, in some preferred embodiments, the substrate has a second conductivity type, the epitaxial layer is a single epitaxial layer with a uniform doping concentration and a resistivity of R, and the SiC device further includes a buffer layer located between the substrate and the epitaxial layer, having a first conductivity type and a resistivity of Rb, wherein the relationship between R and Rb is: R>Rb.

[0008] According to another aspect of the present invention, in some preferred embodiments, the substrate has a second conductivity type, and further includes a buffer layer having a first conductivity type located between the substrate and the PC region, and a plurality of heavily doped regions having the first conductivity type located in the substrate to form a plurality of P+ regions and N+ regions located in the substrate and arranged alternately.

[0009] According to another aspect of the present invention, an integrated circuit is also disclosed, wherein each unit of the integrated circuit includes a SiC MOSFET and a SiC SBR and has an asymmetric planar gate structure, which further includes: an epitaxial layer with a first conductivity type, grown on a substrate with the first conductivity type; an asymmetric planar gate structure, including a first gate and a second gate: the first gate is separated from the epitaxial layer by a first gate oxide layer of the SiC MOSFET, and the second gate is separated from the epitaxial layer by a second gate oxide layer of the SiC SBR, wherein the thickness of the second gate oxide layer is thinner than that of the first gate oxide layer; a source region with the first conductivity type, located on one side of the upper part of the epitaxial layer in the SiC MOSFET and in a first body region with the second conductivity type, and the SiC a second body region with a second conductivity type on the other side of the SBR; a first channel region formed between the first body region and the source region; a second channel region formed between the second body region and the source region; wherein the channel length of the second channel region is smaller than that of the first channel region; the integrated circuit further comprises: an SJ structure, comprising a PC region with a second conductivity type, located on the substrate and connected to the body region; at least two BPS regions with a second conductivity type, placed face to face and separated from the body region; a first type JFET region with a first conductivity type, formed between the first body region and the second body region; a second type JFET region with a first conductivity type, formed between the two BPS regions; the PC region, the source region and the body region are all connected to the source metal; the PC region has a linear, hexagonal or octagonal cell topology; the central portion of the gate oxide layer has a thick oxide layer; two BPS regions are adjacent to the sidewalls of the PC region, or adjacent to the bottom of the PC region and their widths are greater than the width of the PC region;

[0010] According to another aspect of the present invention, a SiC device is disclosed, wherein each unit is located in an active region, and further comprises: an epitaxial layer having a first conductivity type, grown on a substrate; a gate trench, formed in the epitaxial layer and surrounded by a source region having the first conductivity type, the source region being located in a body region having a second conductivity type on an upper portion of the epitaxial layer; the gate trench is filled with a gate, the gate being insulated from the epitaxial layer by a first insulating layer located at the bottom of the gate trench and a gate oxide layer along the sidewalls of the gate trench; the thickness of the first insulating layer is greater than the gate oxide layer; a source region having a first conductivity type, formed in a body region having a second conductivity type on an upper portion of the epitaxial layer; an SJ structure, comprising a PC region having a second conductivity type, located on the substrate and connected to the body region; at least two BPS regions, adjacent to the PC region and separated from the body region; the source region and the body region are both connected to a source metal; and a JFET region having a first conductivity type, formed between the two BPS regions.

[0011] The above and other objects and advantages of the present invention will undoubtedly be apparent to those skilled in the art by reading the following detailed description of the preferred embodiments with reference to the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The advantages of these and other embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, in which:

[0013] FIG. 1 is a cross-sectional view of a SiC shielded MOSFET device disclosed in the prior art.

[0014] Figure 2A is a top view of a preferred embodiment with a planar gate according to the present invention.

[0015] Figure 2B According to the present invention Figure 2A A cross-sectional view of a preferred SiC device at section A1-A1'.

[0016] Figure 2C According to the present invention Figure 2A FIG. 5 is a cross-sectional view of another preferred SiC device along the A1-A1′ section.

[0017] Figure 2D According to the present invention Figure 2A FIG. 5 is a cross-sectional view of another preferred SiC device along the A1-A1′ section.

[0018] Figure 2E According to the present invention Figure 2A FIG. 5 is a cross-sectional view of another preferred SiC device along the A1-A1′ section.

[0019] Figure 3AAccording to the present invention Figure 2A FIG. 5 is a cross-sectional view of another preferred SiC device along the A1-A1′ section.

[0020] Figure 3B According to the present invention Figure 2A FIG. 5 is a cross-sectional view of another preferred SiC device along the A1-A1′ section.

[0021] Figure 3C According to the present invention Figure 2A FIG. 5 is a cross-sectional view of another preferred SiC device along the A1-A1′ section.

[0022] Figure 4 According to the present invention Figure 2A FIG. 5 is a cross-sectional view of another preferred SiC device along the A1-A1′ section.

[0023] Figure 5A According to the present invention Figure 2A FIG. 5 is a cross-sectional view of another preferred SiC device along the A1-A1′ section.

[0024] Figure 5B According to the present invention Figure 2A FIG. 5 is a cross-sectional view of another preferred SiC device along the A1-A1′ section.

[0025] Fig. 6A is a top view of another preferred embodiment according to the present invention.

[0026] Figure 6B is a schematic top view of another preferred embodiment according to the present invention.

[0027] Figure 6C According to the present invention Fig. 6A A cross-sectional view of a preferred SiC device at section A2-A2'.

[0028] Fig.6D According to the present invention Fig. 6A FIG. 5 is a cross-sectional view of another preferred SiC device along section A2 - A2 ′.

[0029] Fig. 6E According to the present invention Fig. 6A FIG. 5 is a cross-sectional view of another preferred SiC device along section A2 - A2 ′.

[0030] Fig. 7A is a top view of another preferred embodiment according to the present invention.

[0031] Figure 7B According to the present invention Fig. 7A A cross-sectional view of a preferred SiC device at section A3-A3'.

[0032] Figure 7C According to the present invention Fig. 7A FIG. 5 is a cross-sectional view of another preferred SiC device along section A3 - A3 ′. DETAILED DESCRIPTION

[0033] The following is a detailed description of the preferred embodiments of practicing the present invention with reference to the various accompanying drawings. Some directional terms, such as "top", "bottom", "front", "back", "above", "below", etc., are described with reference to the directions of the various accompanying drawings. Since the elements in the embodiments can be placed in many different directions, the directional terms in the present invention are only used for description and cannot be regarded as limitations on the present invention. It should be understood that various structural or logical substitutions and modifications in the embodiments should be included in the true spirit and scope of the present invention. Therefore, the following detailed description cannot be regarded as a limitation on the present invention, and the scope of the present invention is defined by the attached claims. It should be understood that the inventive features of the various preferred embodiments described in the present invention can be combined with each other, except where otherwise specified.

[0034] Figure 2A 1 is a top view of a preferred SiC device according to the present invention, wherein the SiC device includes a plurality of cells located in an active region. Each cell includes a P column region 219 having a hexagonal topology structure and a source contact region 235, wherein the source contact region 235 is surrounded by a gate polysilicon layer 205 as a gate. In addition, an n+ boundary 211 having a hexagonal topology structure is formed between the gate polysilicon layer 205 and the PC region 219.

[0035] Figure 2B According to the present invention Figure 2AA cross-sectional view of a preferred A1-A1' section of the illustrated embodiment. The preferred embodiment includes a SiC device formed in an N-type SiC epitaxial layer 202', the epitaxial layer 202' being located on an N+ type SiC substrate 201', wherein the back side of the N+ type SiC substrate 201' is coated with a Ti / Ni / Ag back metal layer 220' used as a drain metal. A p-body region 210' and an n+ source region 211' are formed on the upper portion of the N-type SiC epitaxial layer 202', wherein the n+ source region 211' is located in the p-body region 210', and a first type JFET (JFET1, as shown in the figure) region 207' is formed between two adjacent p-body regions 210'. An N-drift (ND, as shown in the figure) region 203' having a first conductivity type is formed between the N+ substrate 201' and the JFET1 region 207'. In the N-type epitaxial layer 202', a plurality of P-column (PC, as shown in the figure) regions 219' extend vertically downward from the upper surface of the ND region 203', and do not contact the common interface 216' between the N-type epitaxial layer 202' and the N+ substrate 201', thereby forming a p+ heavily doped region 214' between the n+ source region 211' located above the PC region 219'. A super junction (SJ, as shown in the figure) structure is composed of the N-type epitaxial layer 202' and the PC region 219' located above the N+ substrate 201'. Between two adjacent PC regions 219' located in the ND region 203', two buried P-shielding (BPS, as shown in the figure) regions 218' are formed, which are placed face to face. The doping concentration of the BPS region 218' is higher than that of the PC region 219', and the BPS region 218' is adjacent to the sidewall of the PC region 219' and is separated from the p-body region 210'. In addition, a saturation current clamping (SCP) structure 213' is formed between two adjacent PC regions 219', which includes a second type JFET (JFET2, as shown) region 217' formed between two BPS regions 218', wherein the width W of the JFET2 region 217' is J2 Smaller than the width W of JFET1 region 207' J1, and the doping concentration of the JFET2 region 217' is higher than that of the JFET1 region 207'. On the N-type epitaxial layer 202', a doped polysilicon layer lined with a gate oxide layer 209' is formed as a planar gate 205', which covers the p-body region 210', the n+ source region 211', and the upper surface of the JFET1 region 207', and the gate oxide layer 209' has a thick oxide layer in its central part. A dielectric spacer layer 221' is formed on the planar gate 205', and a source metal 212' is formed on the dielectric spacer layer 221', the n+ source region 211', and the p+ region 214'. The PC region 219', the n+ source region 211', and the p-body region 210' are further connected to the source metal 212'. The manufacturing process of this preferred embodiment is compatible with the standard SJ manufacturing process using multi-epitaxial layer growth method and multi-ion implantation method. First, an SJ structure, a BPS region 218', and a JFET2 region 217' are formed in the 1st to the nth (1 st -n th ) sub-epitaxial layers, and then, an enhanced conductivity modulation (ECM, as shown in the figure) region 257' is formed in the (n + 1)th ((n + 1) th ) sub-epitaxial layer, where the ECM region 257' has a first conductivity type and its doping concentration is greater than or equal to that of the (1 st -n th ) sub-epitaxial layer. Then, in the (n + 2)th ((n + 2) th ) sub-epitaxial layer, the source region 211', the body region 210', the P+ region 214', and the JFET1 region 207' are formed. The ECM region 257' is formed in the ND region 203' between the JFET1 region 207' and the JFET2 region 217'.

[0036] Figure 2C is another cross-sectional view of a preferred A1 - A1' cross-section according to the embodiment shown in the present invention. The SiC device has a similar structure to Figure 2A the invention described, except that in the structure of the present invention, two second-type JFET regions are formed in the N-drift (ND, as shown in the figure) region 203" between two adjacent P-column (PC, as shown in the figure) regions 219": a bottom JFET (JFET2B, as shown in the figure) region 227" with a width of W Figure 2B and a top JFET (JFET2T, as shown in the figure) region 217" with a width of W J2B above the JFET2B region 227" and a width of W J2T , where the relationship between W J2B and W J2T is: WJ2B < WJ2T. At the same time, the width W J2Tsmaller than the width W of the first type JFET (JFET1, as shown) region 207″ J1 , so W J2B , W J2T and W J1 The relationship is: W J2B <W J2T <W J1 . In addition, the JFET2B region 227” and the JFET2T region 217” are respectively formed between two bottom buried P-shield (BPSB, as shown in the figure) regions 228” and between two top buried P-shield (BPST, as shown in the figure) regions 218”, and the BPSB region 228” and the BPST region 218” are adjacent to the sidewalls of the PC region 219”, and their doping concentrations are higher than the doping concentration of the PC region 219”.

[0037] Figure 2D According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC device and Figure 2B The invention described has a similar structure, except that in the structure of the present invention, a buried P-shield (BPS, as shown in the figure) region 218"' is adjacent to the bottom surface of a P-column (PC, as shown in the figure) region 219"' and extends laterally to the boundary of the PC region 219"' with a wider width than the PC region 219"'. In addition, a second type JFET (JFET2, as shown in the figure) region 217"' is formed between two adjacent BPS regions 218"', and the width W of the JFET2 region 217"' is J2 smaller than the width W of the first type JFET (JFET1, as shown) region 207″′ J1 An enhanced conductivity modulation (ECM, as shown) region 257''' having a first conductivity type is formed between the JFET1 region 207''' and the JFET2 region 217''', and the doping concentration of the ECM region 257''' is greater than or equal to the doping concentration of the epitaxial layer 202'''.

[0038] Figure 2E According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC device and Figure 2CThe invention described has a similar structure, except that in the structure of the present invention, a buried P-shield (BPSB, as shown) region 228"" is adjacent to the bottom surface of a P-column (PC, as shown) region 219"" and extends laterally to the boundary of the PC region 219"" with a wider width than the PC region 219"". In addition, a bottom second type JFET (JFET2B, as shown) region 227"" is formed between two adjacent BPSB regions 228"", and the width W of the JFET2B region 227"" is J2B smaller than the width W of the top second type JFET (JFET2T, as shown) region 217″″ J2T .

[0039] Figure 3A According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC device and Figure 2B The invention described has a similar structure, except that in the structure of the present invention, it further includes a p+ shield (P+S, as shown in the figure) region 324 located between the p body region 310 and the PC region 319.

[0040] Figure 3B According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC device and Figure 2C The invention described has a similar structure, except that in the structure of the present invention, it further includes a p+ shield (P+S, as shown) region 324' located between the p-body region 310' and the PC region 319'.

[0041] Figure 3C According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC device and Figure 2D The invention described has a similar structure, except that in the structure of the present invention, it further includes a p+ shield (P+S, as shown) region 324" located between the p body region 310" and the PC region 319".

[0042] Figure 4 According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC device and Figure 3BThe invention described has a similar structure, except that in the structure of the present invention, it further includes an N buffer layer (Nb, as shown in the figure) 422 with a resistivity of Rb located between the N+ substrate 401 and the P column (PC, as shown in the figure) region 419, and the N-type epitaxial layer 402 is a single epitaxial layer with a uniform doping concentration and a resistivity of R, wherein the relationship between Rb and R is: Rb>R.

[0043] Figure 5A According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC device and Figure 3B The invention has a similar structure except for a different substrate. In the present invention, the SiC device is formed on a P+ substrate 501, and further includes an N buffer layer (Nb, as shown) 522 with a resistivity of Rb located between the P+ substrate 501 and the P column (PC, as shown in the figure) region 519, and the N-type epitaxial layer 502 is a single epitaxial layer with a uniform doping concentration and a resistivity of R, wherein the relationship between Rb and R is: Rb <R。

[0044] Figure 5B According to the present invention Figure 2A Another preferred cross-sectional view of the A1-A1' section of the embodiment shown. The SiC device and Figure 5A The invention has a similar structure, except that in the SiC device described in the present invention, it further includes a plurality of heavily doped N+ regions 540' located on the P+ substrate 501' to form a plurality of P+ regions and N+ regions located on the substrate and arranged alternately.

[0045] Fig. 6A 6 is a top view of a preferred integrated circuit according to the present invention, wherein each cell includes a SiC MOSFET 630 and a SiC SBR 632 and has an asymmetric planar gate structure. Each MOSFET cell 630 includes a source contact region 635, wherein the source contact region 635 is surrounded by a gate polysilicon layer 605 used as a planar gate, and each SBR cell 632 includes an SBR gate contact region 637 and a source contact region 636 surrounded by a gate polysilicon layer 625. In addition, a poly spacer 608 is formed between the MOSFET cell 630 and the SBR cell 632.

[0046] Figure 6B is a simplified top view of a preferred SiC device integrated circuit according to the present invention, each unit of the integrated circuit includes a SiC MOSFET 630' and a SiC SBR 632', wherein each SiC SBR unit 632' is surrounded by six SiC MOSFETs 630'.

[0047] Figure 6C According to the present invention Fig. 6A A cross-sectional view of a preferred A2-A2' section of the embodiment shown, wherein a SiC MOSFET and a SiC SBR are integrated on the same unit with an asymmetric planar gate structure. Figure 3A The invention has a similar structure, except that there is a different structure above the N-drift (ND, as shown in the figure) region 603". In the present invention, the n+ source region 611" is located in the first p-body (p1, as shown in the figure) region 604" on one side of the upper part of the N-type epitaxial layer 602" in the SiC MOSFET, and in the second p-body (p2, as shown in the figure) region 610" on the other side of the SiC SBR. In addition, an asymmetric planar gate structure is formed, which includes a first gate 615" and a second gate 625". The first gate 615" is separated from the N-type epitaxial layer 602" by the first gate oxide layer 609" of the SiC MOSFET, and the second gate 625" is separated from the N-type epitaxial layer 602" by the SiC The second gate oxide layer 629" of the SBR is separated, wherein the thickness of the second gate oxide layer 629" is thinner than the first gate oxide layer 609". According to the present invention, a first channel region is formed between the p1 region 604" and the n+ source region 611", and a second channel region is formed between the p2 region 610" and the n+ source region 611", wherein the channel length of the second channel region is less than the channel length of the first channel region. In addition, the n+ source region 611", the p2 region 610" of the SiC SBR and the second gate 625" are connected to the source metal 612" through the source contact region 636" and the gate contact region 637". An enhanced conductivity modulation (ECM, as shown in the figure) region 657" is formed between the JFET1 region and the JFET2 region, and the doping concentration of the ECM region 657" is greater than or equal to the doping concentration of the epitaxial layer 602".

[0048] Fig.6D According to the present invention Fig. 6A Another preferred cross-sectional view of the A2-A2' section of the embodiment shown, wherein a SiC MOSFET and a SiC SBR are integrated on the same unit with an asymmetric planar gate structure. Figure 3BThe invention has a similar structure, except that there is a different structure above the N-drift (ND, as shown in the figure) region 603"'. In the present invention, the n+ source region 611"' is located in the first p-body (p1, as shown in the figure) region 604"' on one side of the upper part of the N-type epitaxial layer 602"' in the SiC MOSFET, and in the second p-body (p2, as shown in the figure) region 610"' on the other side of the SiC SBR. In addition, an asymmetric planar gate structure is formed, which includes a first gate 615"' and a second gate 625"', the first gate 615"' is separated from the N-type epitaxial layer 602"' by the first gate oxide layer 609"' of the SiC MOSFET, and the second gate 625"' is separated from the N-type epitaxial layer 602"' by the SiC The second gate oxide layer 629"' of the SBR is separated, wherein the thickness of the second gate oxide layer 629"' is thinner than that of the first gate oxide layer 609"'. According to the present invention, a first channel region is formed between the p1 region 604"' and the n+ source region 611"', and a second channel region is formed between the p2 region 610"' and the n+ source region 611"', wherein the channel length of the second channel region is less than the channel length of the first channel region.

[0049] Fig. 6E According to the present invention Fig. 6A Another preferred cross-sectional view of the A2-A2' section of the embodiment shown, wherein a SiC MOSFET and a SiC SBR are integrated on the same unit with an asymmetric planar gate structure. Figure 6C The invention described has a similar structure, except that in the structure of the present invention, a buried P-shield (BPS, as shown) region 618"" is adjacent to the bottom surface of a P-column (PC, as shown) region 619"" and extends laterally to the boundary of the PC region 619"" with a width wider than that of the PC region 619"". In addition, a second type JFET (JFET2, as shown) region 617"" is formed between two adjacent BPS regions 618"", and the width W of the JFET2 region 617"" is J2 smaller than the width W of the first type JFET (JFET1, as shown) region 607"" J1 .

[0050] Fig. 7A 1 is a top view of another preferred SiC device according to the present invention, wherein the SiC device includes a plurality of cells located in an active region. Each cell includes a P column region 719 having a hexagonal topology structure and a source contact region 735, and a gate trench 703 is formed between two adjacent PC regions 719. In addition, a gate oxide layer 709 is formed between the gate trench 703 and the gate 705.

[0051] Figure 7B According to the present invention Fig. 7A A cross-sectional view of a preferred A3-A3' section of the illustrated embodiment. The preferred embodiment includes a SiC device formed in an N-type SiC epitaxial layer 702', the epitaxial layer 702' being located on an N+ type SiC substrate 701', wherein the back side of the N+ type SiC substrate 701' is coated with a Ti / Ni / Ag back metal layer 720' used as a drain metal. In the N-type epitaxial layer 702', a plurality of gate trenches 703' extend vertically downward from the upper surface of the N-type epitaxial layer 702', and do not contact the common interface 716' between the N-type epitaxial layer 702' and the N+ substrate 701'. A gate (G, as shown in the figure) 705' is formed in the gate trench 703', and the gate 705' is surrounded by a thick bottom oxide layer located at the bottom of the gate trench 703' and serving as a first insulating layer 706', and a gate oxide layer 709' located at the sidewall of the gate trench 703', wherein the thickness of the gate oxide layer 709' is less than the first insulating layer 706'. Between every two adjacent gate trenches 703', a p-body region 710' having an n+ source region 711' is formed, which extends from near the upper surface of the N-type epitaxial layer 702' and surrounds the gate 705' lined with the gate oxide layer 709'. Between every two adjacent gate trenches 703' and below the p-body region 710', a P-column (PC, as shown in the figure) region 719' is formed, thereby forming a p+ heavily doped region 714' between the n+ source regions 711' located above the PC region 719'. In addition, a p+ shield (P+S, as shown in the figure) region 724' is formed between the p-body region 710' and the PC region 719'. A dielectric spacer 721' is formed on the N-type epitaxial layer 702', which covers the upper surface of the gate 705', the gate oxide layer 709' and a portion of the n+ source region 711'. Subsequently, a layer of source metal 712' is formed on the upper surface of the device to connect the PC region 719', the n+ source region 711' and the p-body region 710' together. Between two adjacent PC regions 719' below the gate trench 703', two buried P-shield (BPS, as shown in the figure) regions 718' are formed face to face. The doping concentration of the BPS region 718' is higher than that of the PC region 719'. It is adjacent to the sidewall of the PC region 719' and separated from the p-body region 710'. In addition, a saturated current clamping (SCP) structure 713' is located in an N-drift (ND, as shown in the figure) region 733' between the substrate 701' and the bottom of the gate trench 703', and the SCP structure 713' includes a JFET region 717' formed between two BPS regions 718'. An enhanced conductivity modulation (ECM, as shown in the figure) region 757' is formed in the ND region 733' located between the bottom of the gate trench 703' and the JFET region 717', and its doping concentration is greater than or equal to the doping concentration of the epitaxial layer 702'.

[0052] Figure 7C According to the present invention Fig. 7A Another preferred cross-sectional view of the A3-A3' section of the embodiment shown. The SiC device and Figure 7B The described invention has a similar structure, except that in the structure of the present invention, a buried P-shield (BPS, as shown in the figure) region 718" is adjacent to the bottom surface of a P-column (PC, as shown in the figure) region 719" and extends laterally to the boundary of the PC region 719" with a width wider than that of the PC region 719". In addition, a JFET region 717"' is formed between two adjacent BPS regions 718".

[0053] Although the present invention has been described in accordance with preferred embodiments, it should be understood that the above disclosure is not to be construed as limiting the present invention. The embodiments described above are generally N-channel devices, and the embodiments may also be applied to P-channel devices by reversing the polarity of the conductivity type. After reading the above disclosure, various substitutions and modifications will undoubtedly be apparent to those skilled in the art. Therefore, the appended claims should be interpreted as covering all substitutions and modifications that fall within the true spirit and scope of the present invention.

Claims

1. A silicon carbide (SiC) device comprising a plurality of cells, wherein each cell is located in an active region, further comprising: an epitaxial layer of a first conductivity type grown on the substrate and comprising a plurality of sub-epitaxial layers; a source region of the first conductivity type formed on the upper portion of the epitaxial layer and located in the body region of the second conductivity type; a super junction (SJ) structure, comprising the epitaxial layer and a P column (PC) region, wherein the PC region has the second conductivity type, is located on the substrate, and is connected to the body region; A planar gate made of a doped polysilicon layer lined with a gate oxide layer; a first type junction field effect transistor (JFET) region having the first conductivity type, formed between two adjacent body regions; an N-drift (ND) region having the first conductivity type formed between the substrate and the first type JFET region; at least two buried P-shield (BPS) regions of the second conductivity type, the two BPS regions being disposed face to face, having a doping concentration higher than that of the adjacent PC region, and being separated from the body region; a second type JFET region having the first conductivity type, formed between the two BPS regions; at least one saturation current clamping (SCP) region located between two adjacent PC regions, the SCP region including the second type JFET region and the two BPS regions; an enhanced conductivity modulation (ECM) region having the first conductivity type formed in the ND region between the first type JFET region and the second type JFET region; The source region and the body region are both connected to a source metal.

2. The SiC device according to claim 1, characterized in that The PC region has a linear, square, hexagonal or octagonal topological structure, and the PC region is formed by multiple epitaxial growth methods.

3. The SiC device according to claim 1, characterized in that: The central portion of the gate oxide layer has a thick oxide layer.

4. The SiC device according to claim 1, characterized in that The doping concentration of the ECM region is greater than or equal to the doping concentration of the sub-epitaxial layer located below the ECM region.

5. The SiC device according to claim 1, characterized in that: The two BPS regions are adjacent to the sidewalls of the PC region.

6. The SiC device according to claim 1, characterized in that: The two BPS regions are adjacent to the bottom surface of the PC region and extend laterally beyond the boundary of the PC region with a width wider than that of the PC region.

7. The SiC device according to claim 1, characterized in that: The first type JFET region has a width greater than that of the second type JFET region and a doping concentration lower than that of the second type JFET region.

8. The SiC device according to claim 1, characterized in that: The ND region includes two second type JFET regions: one with a width of W J2B A bottom JFET region, and a bottom JFET region having a width W located above the bottom JFET region J2T The top JFET region, where the W J2B and the W J2T The relationship is: W J2B <W J2T . 9 . The SiC device of claim 1 , further comprising a P+ shielding region having the second conductivity type and located between the body region and the PC region.

10. The SiC device according to claim 1, characterized in that: The substrate has the first conductivity type, the epitaxial layer is a single epitaxial layer with uniform doping concentration and resistivity R, and the SiC device further includes a buffer layer located between the substrate and the PC region, having the first conductivity type and resistivity Rb, wherein the relationship between R and Rb is: R <Rb。 11. The SiC device according to claim 1, characterized in that: The substrate has the second conductivity type, the epitaxial layer is a single epitaxial layer with uniform doping concentration and resistivity R, and the SiC device further includes a buffer layer located between the substrate and the PC region, having the first conductivity type and resistivity Rb, wherein the relationship between R and Rb is: R>Rb.

12. The SiC device according to claim 1, characterized in that: The substrate has the second conductivity type, the epitaxial layer is a single epitaxial layer with uniform doping concentration and resistivity R, and further includes a buffer layer located between the substrate and the PC region, having the first conductivity type and resistivity Rb, wherein the relationship between R and Rb is: R>Rb, and a plurality of heavily doped regions located in the substrate and having the first conductivity type to form a plurality of P+ regions and N+ regions located in the substrate and arranged alternately.

13. An integrated circuit wherein each cell comprises a SiC MOSFET and a SiC super barrier rectifier (SBR) and has an asymmetric planar gate structure, further comprising: an epitaxial layer of a first conductivity type grown on the substrate and comprising a plurality of sub-epitaxial layers; The asymmetric planar gate structure is formed in the epitaxial layer, and includes a first gate and a second gate, wherein the first gate is separated from the epitaxial layer by a first gate oxide layer of the SiC MOSFET, and the second gate is separated from the epitaxial layer by a second gate oxide layer of the SiC SBR, wherein the second gate oxide layer is thinner than the first gate oxide layer; A source region with the first conductivity type is located in a first body region with the second conductivity type on one side of the upper portion of the epitaxial layer in the SiC MOSFET, and in a second body region with the second conductivity type on the other side of the SiC SBR. a first channel region formed between the first body region and the source region; a second channel region formed between the second body region and the source region; wherein a channel length of the second channel region is smaller than a channel length of the first channel region; The source region and the second body region of the SiC SBR are connected to the second gate and connected to the source metal through the source contact region and the gate contact region of the SiC SBR; The integrated circuit further comprises: an SJ structure, comprising the epitaxial layer and a PC region, wherein the PC region has the second conductivity type, is located on the substrate, and is connected to the body region; a first type JFET region having the first conductivity type formed between the first body region and the second body region; an ND region having the first conductivity type, formed between the substrate and the first type JFET region; at least two BPS regions of the second conductivity type, the two BPS regions are placed face to face, have a doping concentration higher than that of the adjacent PC region, and are separated from the body region; a second type JFET region having the first conductivity type, formed between the two BPS regions; at least one SCP region, located between two adjacent PC regions, the SCP region including the second type JFET region and the two BPS regions; an ECM region of the first conductivity type, formed in the ND region between the first type JFET region and the second type JFET region, and having a doping concentration no less than a doping concentration of the sub-epitaxial layer below the ECM region; The source region, the first and second body regions are all connected to a source metal.

14. The integrated circuit of claim 13, wherein: The PC region has a hexagonal shape and is formed by a multiple epitaxial growth method.

15. The integrated circuit of claim 13, wherein: The central portions of the first and second gate oxide layers have a thick oxide layer.

16. The integrated circuit of claim 13, wherein: The BPS region is adjacent to a sidewall of the PC region, or adjacent to a bottom of the PC region and has a width greater than that of the PC region.

17. The integrated circuit of claim 13, wherein: It further includes a P+ shielding region, which has the second conductivity type and is located between the body region and the PC region.

18. The integrated circuit of claim 13, wherein: Each of the SiC SBR units is surrounded by six of the SiC MOSFET units.

19. A SiC device comprising a plurality of cells, wherein each cell is located in an active region, further comprising: an epitaxial layer of a first conductivity type grown on the substrate and comprising a plurality of sub-epitaxial layers; a gate trench formed in the epitaxial layer and surrounded by a source region having the first conductivity type, the source region being located in a body region having the second conductivity type on an upper portion of the epitaxial layer; The gate trench is filled with a gate, and the gate and the epitaxial layer are insulated by a first insulating layer located at the bottom of the gate trench and a gate oxide layer along the sidewall of the gate trench; The thickness of the first insulating layer is greater than the thickness of the gate oxide layer; a source region of the first conductivity type formed in the upper portion of the epitaxial layer and in the body region of the second conductivity type; an SJ structure comprising the epitaxial layer and a PC region, wherein the PC region has the second conductivity type, is located above the substrate, and is connected to the body region; an ND region having the first conductivity type, formed between the substrate and the bottom of the gate trench; at least two BPS regions of the second conductivity type, the two BPS regions are placed face to face, have a doping concentration higher than that of the adjacent PC region, and are separated from the body region; a JFET region having the first conductivity type, formed between the two BPS regions; a P+ shielding region having the second conductivity type, located between the body region and the PC region; at least one SCP region, located between the two adjacent PC regions, comprising a JFET region and the two BPS regions; an ECM region of the first conductivity type, formed in the ND region between the JFET region and the bottom of the gate trench, and having a doping concentration greater than or equal to a doping concentration of the sub-epitaxial layer below the ECM region; The source region and the body region are both connected to a source metal.

20. The SiC device according to claim 19, characterized in that: The BPS region is adjacent to a sidewall of the PC region, or adjacent to a bottom of the PC region and has a width greater than that of the PC region.

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