Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises sub-pixels and light-emitting control signal lines, the sub-pixels comprise first sub-pixels and second sub-pixels, the light-emitting control signal lines comprise first light-emitting control signal lines and second light-emitting control signal lines, the first sub-pixels comprise first transistors, and the second sub-pixels comprise second transistors. The grid of the first transistor is connected with a first light-emitting control signal line; the grid of the second transistor is connected with a second light-emitting control signal line; a channel area of the first transistor is different from a channel area of the second transistor. According to the display panel and the display device provided by the embodiment of the invention, the problem of color cast can be solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Flat panel display devices based on technologies such as light emitting diodes (LEDs) have the advantages of high image quality, power saving, thin body and wide application range, and are widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc., becoming the mainstream of display devices.

[0003] However, with the development of display technology, the functions of display panels are becoming more and more diversified, and the performance indicators of display panels are getting higher and higher. For example, users hope that the display effect of display panels is getting better and better. However, the display panels in the related art still have the problem of color deviation. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device to solve the color shift problem.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising sub-pixels and light-emitting control signal lines, the sub-pixels comprising a first sub-pixel and a second sub-pixel, the light-emitting control signal lines comprising a first light-emitting control signal line and a second light-emitting control signal line, the first sub-pixel comprising a first transistor, the second sub-pixel comprising a second transistor, the gate of the first transistor being connected to the first light-emitting control signal line, and the gate of the second transistor being connected to the second light-emitting control signal line; the channel area of ​​the first transistor is different from the channel area of ​​the second transistor.

[0006] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display device, comprising a display panel as described in the embodiment of the first aspect.

[0007] According to the display panel and the display device provided by the embodiments of the present application, the first transistor of the first sub-pixel is connected to the first light-emitting control signal line, the second transistor of the second sub-pixel is connected to the second light-emitting control signal line, and the channel area of ​​the first transistor is different from the channel area of ​​the second transistor. In this way, the size relationship between the channel area of ​​the first transistor and the channel area of ​​the second transistor can be flexibly designed according to the load size of the first light-emitting control signal line and the second light-emitting control signal line, so that the overall load of the first light-emitting control signal line and the overall load of the second light-emitting control signal line can be made consistent, and then the delay of the signals on the first light-emitting control signal line and the second light-emitting control signal line can be made consistent, so that the light-emitting time of the first sub-pixel and the second sub-pixel can be matched according to the target ratio, thereby helping to solve the problem of color offset in the displayed picture. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0009] Figure 1 A schematic diagram showing the structure of a display panel provided in an embodiment of the present application is shown;

[0010] Figure 2 A schematic diagram showing a circuit topology of a sub-pixel in a display panel provided by an embodiment of the present application is shown;

[0011] Figure 3 Another schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown;

[0012] Figure 4 Another schematic diagram of a circuit topology of a sub-pixel in a display panel provided by an embodiment of the present application is shown;

[0013] Figure 5 A schematic diagram showing a layout structure of a local area in a display panel provided in an embodiment of the present application;

[0014] Figure 6 A schematic diagram showing another circuit topology of a sub-pixel in a display panel provided by an embodiment of the present application;

[0015] Figure 7 A schematic diagram showing another circuit topology of a sub-pixel in a display panel provided by an embodiment of the present application;

[0016] Figure 8 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0017] Fig. 9 A schematic diagram showing another circuit topology of a sub-pixel in a display panel provided by an embodiment of the present application;

[0018] Fig.10 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0019] Fig.11 A schematic diagram showing a structure of a driving circuit in a display panel provided in an embodiment of the present application is shown;

[0020] Fig.12 A schematic diagram showing another circuit topology of a sub-pixel in a display panel provided by an embodiment of the present application;

[0021] Fig.13 A timing diagram of a display panel provided by an embodiment of the present application is shown;

[0022] Fig.14 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0024] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0025] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0026] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0027] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0028] The term "connect" may mean "electrically connected" or "not electrically connected through an intermediate transistor". The term "insulation" may mean "electrically insulating" or "electrically isolated". The term "drive" may mean "control" or "operate". The term "part" may mean "local". The term "pattern" may mean "component". The term "end" may mean "end segment" or "end edge". The display panel may be a display device or a module / part of a display device.

[0029] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0030] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0031] The display panel usually includes sub-pixels of multiple luminous colors. The sub-pixels are connected to luminous control signal lines. The luminous control signals on the luminous control signal lines control whether the sub-pixels emit light.

[0032] In view of the different characteristics of sub-pixels of different luminous colors, in some implementations, sub-pixels of different luminous colors may be connected to different luminous control signal lines, so that sub-pixels of different luminous colors may be controlled separately based on different luminous control signals.

[0033] However, the inventors have discovered that different loads of different light-emitting control signal lines may be different, resulting in different signal delays on different light-emitting control signal lines, making it impossible to accurately control the light-emitting time of different light-emitting color sub-pixels. As a result, the light-emitting time of different light-emitting color sub-pixels will not match, resulting in a color offset in the displayed image.

[0034] In order to solve the above-mentioned technical problems, the embodiments of the present application provide a display panel and a display device. The technical concepts of the present application include: differentiated design of the channel area of ​​transistors connected to different light-emitting control signal lines, so as to balance the loads of different light-emitting control signal lines, and thereby make the delays of signals on different light-emitting control signal lines tend to be consistent, so as to solve the color deviation problem.

[0035] Various embodiments of the display panel and the display device provided in the present application will be described below with reference to the accompanying drawings.

[0036] like Figure 1As shown, the display panel provided by the embodiment of the present application includes sub-pixels and light-emitting control signal lines. The sub-pixels include a first sub-pixel 1 and a second sub-pixel 2. The light-emitting control signal lines include a first light-emitting control signal line EM1 and a second light-emitting control signal line EM2.

[0037] Exemplarily, the first sub-pixel 1 and the second sub-pixel 2 have different luminous colors. The first sub-pixel 1 includes a first pixel circuit 10 and a first light-emitting element D1, the first pixel circuit 10 is connected to the first light-emitting control signal line EM1 and the first light-emitting element D1, and the first pixel circuit 10 is controlled by the first light-emitting control signal on the first light-emitting control signal line EM1, thereby controlling whether the first light-emitting element D1 emits light.

[0038] The second sub-pixel 2 includes a second pixel circuit 20 and a second light-emitting element D2. The second pixel circuit 20 is connected to the second light-emitting control signal line EM2 and the second light-emitting element D2. The second pixel circuit 20 is controlled by the second light-emitting control signal on the second light-emitting control signal line EM2, thereby controlling whether the second light-emitting element D2 emits light.

[0039] like Figure 2 As shown, the first pixel circuit 10 in the first sub-pixel includes a first transistor 11, and the gate of the first transistor 11 is connected to the first light-emitting control signal line EM1. The first light-emitting control signal on the first light-emitting control signal line EM1 can control the state of the first transistor 11. For example, when the first light-emitting control signal on the first light-emitting control signal line EM1 is at an effective level, the first transistor 11 is turned on, and the first light-emitting element D1 emits light; when the first light-emitting control signal on the first light-emitting control signal line EM1 is at a cut-off level, the first transistor 11 is turned off, and the first light-emitting element D1 does not emit light.

[0040] The second pixel circuit 20 in the second sub-pixel includes a second transistor 22, and the gate of the second transistor 22 is connected to the second light-emitting control signal line EM2. The second light-emitting control signal on the second light-emitting control signal line EM2 can control the state of the second transistor 22. For example, when the second light-emitting control signal on the second light-emitting control signal line EM2 is at an effective level, the second transistor 22 is turned on, and the second light-emitting element D2 emits light; when the second light-emitting control signal on the second light-emitting control signal line EM2 is at a cut-off level, the second transistor 22 is turned off, and the second light-emitting element D2 does not emit light.

[0041] In this article, "effective level" refers to the level used to control the transistor to turn on (conduct), and "cut-off level" refers to the level used to control the transistor to turn off (turn off). If the transistor is a P-type transistor, the "effective level" is a low level and the "cut-off level" is a high level; if the transistor is an N-type transistor, the "effective level" is a high level and the "cut-off level" is a low level. The drawings of this application illustrate the transistor as a P-type transistor, which is not intended to limit this application.

[0042] The channel area of ​​the first transistor 11 is different from the channel area of ​​the second transistor 12 .

[0043] The channel area is the product of the channel length and the channel width. The active layer of the transistor includes a channel and a source region and a drain region located on both sides of the channel. The channel of the transistor overlaps with the gate of the transistor, and the source region and the drain region do not overlap with the gate. The overlap of the channel and the gate of the transistor constitutes the parasitic capacitance of the transistor, and the parasitic capacitance constitutes an important component of the load of the wiring connected to the gate of the transistor. The size of the parasitic capacitance is affected by the channel area. The larger the channel area, the larger the parasitic capacitance, and the larger the load of the wiring connected to the gate of the transistor; the smaller the channel area, the smaller the parasitic capacitance, and the smaller the load of the wiring connected to the gate of the transistor. Therefore, the channel area of ​​the first transistor 11 will affect the load of the first light-emitting control signal line EM1, and the channel area of ​​the second transistor 12 will affect the load of the second light-emitting control signal line EM2.

[0044] Exemplarily, the size relationship between the channel area of ​​the first transistor 11 and the channel area of ​​the second transistor 12 can be designed according to actual conditions. For example, when other factors cause the load of the first light-emitting control signal line EM1 to be smaller than the load of the second light-emitting control signal line EM2, it can be designed that: the channel area of ​​the first transistor 11 is larger than the channel area of ​​the second transistor 12. For another example, when other factors cause the load of the first light-emitting control signal line EM1 to be larger than the load of the second light-emitting control signal line EM2, it can be designed that: the channel area of ​​the first transistor 11 is smaller than the channel area of ​​the second transistor 12. In this way, the overall load of the first light-emitting control signal line EM1 and the overall load of the second light-emitting control signal line EM2 can be made consistent.

[0045] It should be noted that Figure 2 Only the first transistor 11 in the first pixel circuit 10 and the second transistor 22 in the second pixel circuit 20 are shown, and the first pixel circuit 10 and the second pixel circuit 20 may also include other transistors. For example, the first pixel circuit 10 and the second pixel circuit 20 may also include a driving transistor, a transistor for writing a data voltage, a transistor for threshold compensation, a transistor for writing a reset voltage, etc. The present application does not limit the specific structure of the pixel circuit.

[0046] in addition, Figure 2 Only one first transistor 11 in the first pixel circuit 10 and one second transistor 22 in the second pixel circuit 20 are shown. The number of first transistors 11 in the first pixel circuit 10 may be more than one, and the number of second transistors 22 in the second pixel circuit 20 may be more than one. In the case where the first pixel circuit 10 includes a plurality of first transistors 11 and the second pixel circuit 20 includes a plurality of second transistors 22, the channel area of ​​at least one first transistor 11 is different from the channel area of ​​at least one second transistor 22.

[0047] According to the display panel provided by the embodiment of the present application, the first transistor of the first sub-pixel is connected to the first light-emitting control signal line, and the second transistor of the second sub-pixel is connected to the second light-emitting control signal line. The channel area of ​​the first transistor is different from the channel area of ​​the second transistor. In this way, the size relationship between the channel area of ​​the first transistor and the channel area of ​​the second transistor can be flexibly designed according to the load size of the first light-emitting control signal line and the second light-emitting control signal line, so that the overall load of the first light-emitting control signal line and the overall load of the second light-emitting control signal line can be made consistent, thereby making the delay of the signals on the first light-emitting control signal line and the second light-emitting control signal line consistent, so that the light-emitting time of the first sub-pixel and the second sub-pixel can be matched according to the target ratio, thereby helping to solve the problem of color offset in the displayed picture.

[0048] In some embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the display panel further includes a third sub-pixel 3, a third sub-pixel 3. Exemplarily, the luminous colors of the first sub-pixel 1, the second sub-pixel 2 and the third sub-pixel 3 are different from each other. For example, one of the first sub-pixel 1, the second sub-pixel 2 and the third sub-pixel 3 is a red sub-pixel, another is a green sub-pixel, and another is a blue sub-pixel. The first sub-pixel 1, the second sub-pixel 2 and the third sub-pixel constitute a pixel unit PU, and a plurality of pixel units PU are arranged in an array in a first direction X and a second direction Y, and the first direction X and the second direction Y intersect. Exemplarily, the first light emitting control signal line EM1 and the second light emitting control signal line EM2 extend along the first direction X. For example, the first direction X is a row direction, and a plurality of first sub-pixels 1 located in the same row are connected to the same first light emitting control signal line EM1, and a plurality of second sub-pixels 2 and a plurality of third sub-pixels 3 located in the same row are connected to the same second light emitting control signal line EM2.

[0049] The third sub-pixel 3 includes a third pixel circuit 30 and a third light-emitting element D3. The third pixel circuit 30 is connected to the second light-emitting control signal line EM2 and the third light-emitting element D3. The third pixel circuit 30 is controlled by the second light-emitting control signal on the second light-emitting control signal line EM2, thereby controlling whether the third light-emitting element D3 emits light. In this example, the second sub-pixel 2 and the third sub-pixel 3 are both connected to the second light-emitting control signal line EM2, and the number of sub-pixels connected to the second light-emitting control signal line EM2 is greater than the number of sub-pixels connected to the first light-emitting control signal line EM1.

[0050] like Figure 4 As shown, the third pixel circuit 30 in the third sub-pixel includes a third transistor 33, and the gate of the third transistor 33 is connected to the second light-emitting control signal line EM2. The second light-emitting control signal on the second light-emitting control signal line EM2 can control the state of the third transistor 33. For example, when the second light-emitting control signal on the second light-emitting control signal line EM2 is at an effective level, the third transistor 33 is turned on, and the third light-emitting element D3 emits light; when the second light-emitting control signal on the second light-emitting control signal line EM2 is at a cut-off level, the third transistor 33 is turned off, and the third light-emitting element D3 does not emit light.

[0051] The channel area of ​​the first transistor 11 is greater than the channel area of ​​the second transistor 22 , and the channel area of ​​the first transistor 11 is greater than the channel area of ​​the third transistor 33 .

[0052] For example, Figure 4 It is shown that the first sub-pixel includes two first transistors 11, which are respectively a first power supply write transistor M1_1 and a first light emission control transistor M1_2; the second sub-pixel includes two second transistors 22, which are respectively a second power supply write transistor M2_1 and a second light emission control transistor M2_2; the third sub-pixel includes two third transistors 33, which are respectively a third power supply write transistor M3_1 and a third light emission control transistor M3_2.

[0053] As an example, the channel area of ​​at least one first transistor 11 is greater than the channel area of ​​at least one second transistor 22 , and the channel area of ​​at least one first transistor 11 is greater than the channel area of ​​at least one third transistor 33 .

[0054] As another example, the channel area of ​​the first power write transistor M1_1 is greater than the channel area of ​​the second power write transistor M2_1 , and the channel area of ​​the first power write transistor M1_1 is greater than the channel area of ​​the third power write transistor M3_1 .

[0055] As yet another example, a channel area of ​​the first light emission control transistor M1_2 is greater than a channel area of ​​the second light emission control transistor M2_2 , and a channel area of ​​the first light emission control transistor M1_2 is greater than a channel area of ​​the third light emission control transistor M3_2 .

[0056] The first light-emitting control signal line is connected to the first sub-pixel, the second light-emitting control signal line is connected to the second sub-pixel and the third sub-pixel, the number of sub-pixels connected to the first light-emitting control signal line is less than the number of sub-pixels connected to the second light-emitting control signal line, and the number of first transistors connected to the first light-emitting control signal line is less than the number of transistors connected to the second light-emitting control signal line. In this embodiment, the channel area of ​​the first transistor is greater than the channel area of ​​any one of the second transistor and the third transistor. In this way, the overall load of the first light-emitting control signal line is increased by increasing the channel area of ​​the first transistor, so that the overall load of the first light-emitting control signal line and the overall load of the second light-emitting control signal line tend to be consistent, so as to solve the color shift problem.

[0057] In some embodiments, the channel area of ​​the first transistor 11 having the same function is equal to the sum of the channel area of ​​the second transistor 22 and the channel area of ​​the third transistor 33 .

[0058] by Figure 4 For example, the first transistor 11 includes a first power write transistor M1_1 and a first light emission control transistor M1_2, the second transistor 22 includes a second power write transistor M2_1 and a second light emission control transistor M2_2, and the third transistor 33 includes a third power write transistor M3_1 and a third light emission control transistor M3_2. Among them, the first power write transistor M1_1, the second power write transistor M2_1 and the third power write transistor M3_1 have the same function, which is to transmit the power signal on the first power line PVDD to the driving transistors connected to them respectively. The first light emission control transistor M1_2, the second light emission control transistor M2_2 and the third light emission control transistor M3_2 have the same function, which is to transmit the driving signal to the light emitting elements connected to them respectively.

[0059] The channel area of ​​the first power write transistor M1_1 is S1, the channel area of ​​the first light emission control transistor M1_2 is S2, the channel area of ​​the second power write transistor M2_1 is S3, the channel area of ​​the second light emission control transistor M2_2 is S4, the channel area of ​​the third power write transistor M3_1 is S5, and the channel area of ​​the third light emission control transistor M3_2 is S6.

[0060] For example, S1=S3+S5.

[0061] For another example, S2=S4+S6.

[0062] In other embodiments, if the first sub-pixel includes multiple first transistors, the second sub-pixel includes multiple second transistors, and the third sub-pixel includes multiple third transistors; the channel area of ​​the first transistor refers to: the sum of the channel areas of the multiple first transistors; the channel area of ​​the second transistor refers to: the sum of the channel areas of the multiple second transistors; the channel area of ​​the third transistor refers to: the sum of the channel areas of the multiple third transistors.

[0063] For example, still Figure 4 For example, S1+S2=S3+S4+S5+S6.

[0064] In this embodiment, by designing the channel area of ​​the first transistor to be equal to the sum of the channel area of ​​the second transistor and the channel area of ​​the third transistor, the load formed by the transistor for the first light-emitting control signal line and the load formed by the transistor for the second light-emitting control signal line are the same, so that the overall load of the first light-emitting control signal line and the overall load of the second light-emitting control signal line can be the same or tend to be the same, thereby solving the color deviation problem.

[0065] The channel area of ​​a transistor is determined by the channel length and width of the transistor. The channel area can be adjusted by adjusting at least one of the channel length and the channel width.

[0066] In some embodiments, the channel lengths of the first transistor 11, the second transistor 22, and the third transistor 33 with the same function are equal; and the channel width of the first transistor 11 with the same function is equal to the sum of the channel width of the second transistor 22 and the channel width of the third transistor 33. That is, in this embodiment, the channel length of the transistor may not be changed, and the channel area may be adjusted by adjusting the channel width of the transistor.

[0067] by Figure 4 For example, the channel length of the first power write transistor M1_1 is L1, and the channel width is w1; the channel length of the first light-emitting control transistor M1_2 is L2, and the channel width is w2; the channel length of the second power write transistor M2_1 is L3, and the channel width is w3; the channel length of the second light-emitting control transistor M2_2 is L4, and the channel width is w4; the channel length of the third power write transistor M3_1 is L5, and the channel width is w5; the channel length of the third light-emitting control transistor M3_2 is L6, and the channel width is w6.

[0068] For example, L1=L3=L5, w1+=w3+w5.

[0069] For another example, L2=L4=L6, w2=w4+w6.

[0070] In other embodiments, if the first sub-pixel includes a plurality of first transistors, the second sub-pixel includes a plurality of second transistors, and the third sub-pixel includes a plurality of third transistors; the channel width of the first transistor refers to: the sum of the channel widths of the plurality of first transistors; the channel width of the second transistor refers to: the sum of the channel widths of the plurality of second transistors; the channel width of the third transistor refers to: the sum of the channel widths of the plurality of third transistors. The channel length of the first transistor refers to: the channel length of any one of the first transistors; the channel length of the second transistor refers to: the channel length of any one of the second transistors; the channel length of the third transistor refers to: the channel length of any one of the third transistors.

[0071] For example, still Figure 4 For example, L1=L2=L3=L4=L5=L6, w1+w2=w3+w4+w5+w6.

[0072] For example, Figure 5 As shown, the channel width direction of the first transistor 11 is the same as the extension direction of the first light emission control signal line EM1, and the channel width directions of the second transistor 22 and the third transistor 33 are the same as the extension direction of the second light emission control signal line EM2. For example, the first light emission control signal line EM1 and the second light emission control signal line EM2 extend along the first direction X. In this example, the channel lengths of the transistors connected to the light emission control signal lines are the same, but the channel widths of the transistors are adjusted differently, so that the channel areas of different transistors can be adjusted without adjusting the line widths of the first light emission control signal line EM1 and the second light emission control signal line EM2, which can be relatively easy to implement in terms of process.

[0073] In some embodiments, the channel width of the second transistor 22 and the channel width of the third transistor 33 are equal.

[0074] As an example, w3=w5, w4=w6, w3≠w4, w1+w2=w3+w4+w5+w6.

[0075] As another example, w3=w4=w5=w6, w1+w2=w3+w4+w5+w6.

[0076] As yet another example, w1=w2=2*w3=2*w4=2*w5=2*w6.

[0077] As yet another example, w1≠w2, w1+w2=w3+w4+w5+w6.

[0078] The above embodiments describe how to balance the load of the first light-emitting control signal line and the load of the second light-emitting control signal line by differentially designing the channel areas of transistors connected to the light-emitting control signal lines in the first sub-pixel and the second sub-pixel.

[0079] In some other embodiments, the number of transistors connected to the light emitting control signal line in the first sub-pixel and the second sub-pixel may be differentiated to achieve load balancing. Some implementation methods of differentially designing the number of transistors are described below.

[0080] As an example, Figure 6 As shown, the first transistor 11 includes a first sub-transistor 111 and a second sub-transistor 112, the first sub-transistor 111 and the second sub-transistor 112 are connected in series, and the gate of the first sub-transistor 111 and the gate of the second sub-transistor 112 are both connected to the first light emission control signal line EM1. The channel area of ​​the first transistor 11 is equal to the sum of the channel areas of the first sub-transistor 111 and the second sub-transistor 112.

[0081] In this example, it is equivalent to splitting one first transistor 11 into two sub-transistors connected in series, thereby increasing the number of transistors connected to the first light emitting control signal line EM1.

[0082] For example, Figure 6 It is shown that the first sub-pixel includes two first transistors 11, which are respectively a first power supply write transistor M1_1 and a first light emission control transistor M1_2. The first power supply write transistor M1_1 includes a first sub-power supply write transistor M1_11 and a second sub-power supply write transistor M1_12, and the first light emission control transistor M1_2 includes a first sub-light emission control transistor M1_21 and a second sub-light emission control transistor M1_22.

[0083] The first electrode of the first sub-power supply write transistor M1_11 is connected to the first power supply line PVDD, the second electrode of the first sub-power supply write transistor M1_11 is connected to the first electrode of the second sub-power supply write transistor M1_12, and the second electrode of the second sub-power supply write transistor M1_12 is connected to the first electrode of the first driving transistor T1. The first electrode of the first sub-light emitting control transistor M1_21 is connected to the second electrode of the first driving transistor T1, the second electrode of the first sub-light emitting control transistor M1_21 is connected to the first electrode of the second sub-light emitting control transistor M1_22, and the second electrode of the second sub-light emitting control transistor M1_22 is connected to the first light emitting element D1.

[0084] The gates of the first and second sub-power supply write transistors M1_11 and M1_12 , and the first and second sub-light emission control transistors M1_21 and M1_22 are all connected to the first light emission control signal line EM1 .

[0085] The channel area of ​​the first power write transistor M1_1 is S1, the channel area of ​​the first sub-power write transistor M1_11 is S11, and the channel area of ​​the second sub-power write transistor M1_12 is S12, S1=S11+S12.

[0086] The channel area of ​​the first light emission control transistor M1_2 is S2, the channel area of ​​the first sub-light emission control transistor M1_21 is S21, and the channel area of ​​the second sub-light emission control transistor M1_22 is S22, S2=S21+S22.

[0087] For example, S11+S12=S3+S5.

[0088] For another example, S21+S22=S4+S6.

[0089] For another example, S11+S12+S21+S22=S3+S4+S5+S6.

[0090] Figure 6 Relative to Figure 4 In the example shown, the number of transistors connected to the first light emission control signal line EM1 in the first sub-pixel is increased. Figure 6 As shown, the first light-emitting control signal line EM1 connects 4 transistors in the first sub-pixel, the second light-emitting control signal line EM2 connects 2 transistors in the second sub-pixel and 2 transistors in the third sub-pixel, and the number of transistors connected to the first light-emitting control signal line EM1 is the same as the number of transistors connected to the second light-emitting control signal line EM2, so as to balance the load of the first light-emitting control signal line and the load of the second light-emitting control signal line.

[0091] In some embodiments, please refer to Figure 3 and Figure 6 , the channel areas of the first sub-transistor 111, the second sub-transistor 112, the second transistor 22 and the third transistor 33 are the same.

[0092] Illustratively, S11=S12=S21=S22=S3=S4=S5=S6.

[0093] It can be understood that in this example, S11+S12>S3, S11+S12>S5, S21+S22>S4, S21+S22>S5, and this example still complies with: the channel area of ​​the first transistor is greater than the channel area of ​​the second transistor, and the channel area of ​​the first transistor is greater than the channel area of ​​the third transistor.

[0094] In some embodiments, the channel widths of the first sub-transistor 111, the second sub-transistor 112, the second transistor 22 and the third transistor 33 are the same, and the channel lengths of the first sub-transistor 111, the second sub-transistor 112, the second transistor 22 and the third transistor 33 are the same.

[0095] Exemplarily, the first sub-power write transistor M1_11, the second sub-power write transistor M1_12, the first sub-light-emitting control transistor M1_21, the second sub-light-emitting control transistor M1_22, the second power write transistor M2_1, the second light-emitting control transistor M2_2, the third power write transistor M3_1 and the third light-emitting control transistor M3_2, the channel lengths of these eight transistors are equal, and the channel widths of these eight transistors are the same, so that only the number of connections to the first light-emitting control signal line in the first sub-pixel needs to be adjusted to achieve balanced loads on the first light-emitting control signal line and the second light-emitting control signal line.

[0096] The above embodiment introduces how to achieve load balancing by differentiating the number of transistors connected to the light emitting control signal line in the first sub-pixel and the second sub-pixel. In other embodiments, an additional compensation structure may be added to achieve load balancing of the first light emitting control signal line and the second light emitting control signal line. Some implementations of adding an additional compensation structure are described below.

[0097] In some embodiments, Figure 7 As shown, at least one of the first light emitting control signal line EM1 and the second light emitting control signal line EM2 is connected to a compensation structure 4, and the compensation structure 4 is used to compensate for the load of the light emitting control signal line connected thereto.

[0098] In this embodiment, the compensation structure can be flexibly designed according to the load size of the first light-emitting control signal line and the second light-emitting control signal line to make the overall load of the first light-emitting control signal line and the overall load of the second light-emitting control signal line tend to be consistent.

[0099] For example, when other factors cause the load of the first light-emitting control signal line EM1 to be smaller than the load of the second light-emitting control signal line EM2, it can be designed as follows: the first light-emitting control signal line EM1 is connected to the compensation structure 4, and the second light-emitting control signal line EM2 is not connected to the compensation structure. For another example, when other factors cause the load of the first light-emitting control signal line EM1 to be larger than the load of the second light-emitting control signal line EM2, it can be designed as follows: the first light-emitting control signal line EM1 is not connected to the compensation structure, and the second light-emitting control signal line EM2 is connected to the compensation structure. In this way, the overall load of the first light-emitting control signal line EM1 and the overall load of the second light-emitting control signal line EM2 can be made consistent.

[0100] As an example, Figure 7 As shown, the display panel also includes a third sub-pixel 3, the third sub-pixel 3 includes a third transistor 33, and the gate of the third transistor 33 is connected to the second light-emitting control signal line EM2. In this example, the second sub-pixel 2 and the third sub-pixel 3 are both connected to the second light-emitting control signal line EM2, and the number of sub-pixels connected to the second light-emitting control signal line EM2 is greater than the number of sub-pixels connected to the first light-emitting control signal line EM1. In this case, at least the first light-emitting control signal line EM1 is connected to a compensation structure 4, and the compensation structure 4 is used to increase the load of the first light-emitting control signal line EM1, thereby compensating for the relatively low load caused by the small number of sub-pixels connected to the first light-emitting control signal line EM1, thereby making the overall load of the first light-emitting control signal line EM1 and the overall load of the second light-emitting control signal line EM2 tend to be consistent.

[0101] In some embodiments, Figure 7 As shown, the compensation structure 4 includes a capacitor, one end of which is connected to the light-emitting control line, and the other end of which is connected to the fixed voltage signal line (not shown in the figure). The capacitor will be charged and discharged through the light-emitting control line to which it is connected, so the capacitor constitutes the load of the light-emitting control signal line. After increasing the capacitor, the load of the light-emitting control signal line can be increased.

[0102] Exemplarily, the other end of the capacitor is connected to a fixed voltage signal line including any one of the following: a first power line PVDD, a second power line PVEE, a reset signal line Vref, a high level signal line VGH, a low level signal line VGL, and a bias signal line DVH.

[0103] In some embodiments, Figure 7 As shown, the display panel further includes a third sub-pixel 3, the third sub-pixel 3 includes a third transistor 33, and the gate of the third transistor 33 is connected to the second light-emitting control signal line EM2. The compensation structure 4 includes at least a first capacitor C1, and the first capacitor C1 is connected to the first light-emitting control signal line EM1. Here, the first capacitor C1 can increase the load of the first light-emitting control signal line EM1, so that the overall load of the first light-emitting control signal line EM1 and the overall load of the second light-emitting control signal line EM2 tend to be consistent.

[0104] In some embodiments, Figure 8 As shown, the first capacitor C1 and the first sub-pixel 1 are arranged in a one-to-one correspondence, and the first capacitor C1 is arranged close to the first sub-pixel 1 corresponding to it.

[0105] Exemplarily, the first light-emitting control signal line EM1 is connected to multiple first sub-pixels 1 located in the same row, the number of first sub-pixels 1 connected to the first light-emitting control signal line EM1 is equal to the number of first capacitors C1, and a first capacitor C1 is provided corresponding to each first sub-pixel 1, so that for each first sub-pixel, a better signal delay balancing effect can be achieved.

[0106] In some embodiments, Figure 7 As shown, the first sub-pixel further includes a first storage capacitor Cst1, one end of the first storage capacitor Cst1 is connected to the gate of the first driving transistor T1, and the other end of the first storage capacitor Cst1 is connected to the first power line PVDD. The capacitance of the first capacitor C1 is smaller than that of the first storage capacitor Cst1.

[0107] The larger the capacitance of the first capacitor C1, the greater the added load for the first light-emitting control signal line EM1. If the capacitance of the first capacitor C1 is too large, the first light-emitting control signal line EM1 may not be able to effectively drive the first sub-pixel. In this embodiment, the capacitance of the first capacitor C1 is smaller than the capacitance of the first storage capacitor Cst1 to ensure that the first light-emitting control signal line EM1 can effectively drive the first sub-pixel.

[0108] The overlapping area of ​​the two plates of the capacitor affects the capacitance of the capacitor. For example, the overlapping area of ​​the two plates of the first capacitor C1 is smaller than the overlapping area of ​​the two plates of the first storage capacitor Cst1, thereby reducing the space occupied by the first capacitor C1 to avoid reducing the resolution of the display panel.

[0109] Exemplarily, the two plates of the first capacitor and the two plates of the first storage capacitor Cst1 are located in the same film layer.

[0110] Of course, in other embodiments, such as Fig. 9 As shown, in addition to adding a first capacitor C1 to connect the first light-emitting control signal line EM1, a second capacitor C2 can be added to connect the second light-emitting control signal line EM2, and the capacitance of the first capacitor C1 is greater than the capacitance of the second capacitor C2.

[0111] In this example, the second sub-pixel 2 and the third sub-pixel 3 are both connected to the second light-emitting control signal line EM2, and the number of sub-pixels connected to the second light-emitting control signal line EM2 is greater than the number of sub-pixels connected to the first light-emitting control signal line EM1. In this case, the capacitance of the first capacitor C1 is greater than the capacitance of the second capacitor C2, thereby compensating for the relatively low load caused by the small number of sub-pixels connected to the first light-emitting control signal line EM1, thereby making the overall load of the first light-emitting control signal line EM1 and the overall load of the second light-emitting control signal line EM2 tend to be consistent.

[0112] Exemplarily, the two plates of the second capacitor C2 and the two plates of the first capacitor C1 are located in the same film layer.

[0113] Figures 7 to 9 In the example shown, the compensation structure includes a capacitor for illustration. In other embodiments, the compensation structure may also include a resistor, or the compensation structure may also be other structures capable of increasing the load.

[0114] The impedance of the light-emitting control signal line itself also constitutes the load of the light-emitting control signal line. When the materials of the first light-emitting control signal line and the second light-emitting control signal line are the same, the smaller the line width, the greater its own impedance. Therefore, by differentiating the line widths of the first light-emitting control signal line and the second light-emitting control signal line, it is also possible to balance the loads of the first light-emitting control signal line and the second light-emitting control signal line.

[0115] In some embodiments, Fig.10 As shown, the first light emitting control signal line EM1 connects the first sub-pixel 1, the second light emitting control signal line EM2 connects the second sub-pixel 2 and the third sub-pixel 3, and the line width of the first light emitting control signal line EM1 is smaller than the line width of the second light emitting control signal line EM2. Fig.10 In the figure, the second light-emitting control signal line EM2 is indicated by a thicker line, and the first light-emitting control signal line EM1 is indicated by a thinner line. Exemplarily, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are made of the same material.

[0116] In this example, the number of sub-pixels connected to the second light-emitting control signal line EM2 is greater than the number of sub-pixels connected to the first light-emitting control signal line EM1. In this case, when the materials of the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are the same, the line width of the first light-emitting control signal line EM1 is smaller than the line width of the second light-emitting control signal line EM2. The smaller the line width, the greater its own impedance, which is equivalent to increasing the load of the routing, thereby compensating for the relatively low load caused by the small number of sub-pixels connected to the first light-emitting control signal line EM1, thereby making the overall load of the first light-emitting control signal line EM1 and the overall load of the second light-emitting control signal line EM2 tend to be consistent.

[0117] For example, Fig.10 As shown, the display panel further includes a first driving circuit 51 and a second driving circuit 52. The first driving circuit 51 is connected to the first light-emitting control signal line EM1, and the second driving circuit 52 is connected to the second light-emitting control signal line EM2. The first driving circuit 51 is used to generate a first light-emitting control signal, and the second driving circuit 52 is used to generate a second light-emitting control signal.

[0118] As an example, the circuit topology of the first drive circuit 51 and the second drive circuit 52 may be the same, and the parameters of the transistors with the same function in the first drive circuit 51 and the second drive circuit 52 may be the same. For example, the first drive circuit 51 includes a first output transistor 511 and a second output transistor 512, and the second drive circuit 52 includes a third output transistor 521 and a fourth output transistor 522. The first output transistor 511 and the third output transistor 521 are transistors with the same function, and the channel area of ​​the first output transistor 511 and the third output transistor 521 is the same. The second output transistor 512 and the fourth output transistor 522 are transistors with the same function, and the channel area of ​​the second output transistor 512 and the fourth output transistor 522 is the same. Exemplarily, the channel areas of the first output transistor 511, the second output transistor 512, the third output transistor 521 and the fourth output transistor 522 are the same.

[0119] As another example, the channel areas of the output transistors in the first driving circuit 51 and the second driving circuit 52 may be set differently to balance the loads of the first light emission control signal line and the second light emission control signal line. For example, the channel areas of the first output transistor 511 and the third output transistor 521 are different, and the channel areas of the second output transistor 512 and the fourth output transistor 522 are different.

[0120] For example, the first light-emitting control signal line EM1 connects the first sub-pixel 1, the second light-emitting control signal line EM2 connects the second sub-pixel 2 and the third sub-pixel 3, the channel area of ​​the first output transistor 511 is greater than the channel area of ​​the third output transistor 521, and the channel area of ​​the second output transistor 512 is greater than the channel area of ​​the fourth output transistor 522.

[0121] As an example, Fig.12 As shown, the first pixel circuit 10 and the second pixel circuit 20 both include a PWM (Pulse Width Modulation) module and a PAM (Pulse Amplitude Modulation) module. The combination of the PWM module and the PAM module can control the intensity of the driving current and the duration of the driving current to control the light-emitting state of the light-emitting element.

[0122] The PWM module is connected to the PAM module. The pixel circuit generates a driving current under the control of the PWM module and the PAM module. The PAM module is used to control the amplitude of the driving current, and the PWM module is used to adjust the pulse width of the voltage applied to the first electrode of the light-emitting element.

[0123] The PWM module adjusts the pulse width of the voltage applied to the first electrode of the light-emitting element, that is, the PWM module adjusts the actual emission period of the driving current applied to the light-emitting element, and at the same time, the driving current applied to the light-emitting element is maintained at a constant level to adjust the grayscale or brightness displayed by the light-emitting element, rather than only adjusting the grayscale or brightness displayed by the light-emitting element by adjusting the size of the driving current applied to the light-emitting element. Therefore, the PAM module can provide the driving current to the light-emitting element so that the light-emitting element is driven with the best luminous efficiency, and adjust the grayscale or brightness displayed by the light-emitting element by adjusting the light-emitting duty cycle of the light-emitting element (that is, the emission period of the light-emitting element) through the PWM module.

[0124] The PAM module directly determines the size of the driving current, so the PAM has a greater impact on the brightness of the light-emitting element. In the present application, when the pixel circuit includes a PWM module and a PAM module, the first light-emitting control signal line EM1 is connected to the PAM module in the first pixel circuit, and the second light-emitting control signal line EM2 is connected to the PAM module in the second pixel circuit.

[0125] Some of the above examples describe that transistors in different sub-pixels can be set differently. In some embodiments, parameters of multiple transistors in the same sub-pixel and connected to the same light-emitting control signal line can also be set differently.

[0126] In some embodiments, Figure 4 As shown, the first sub-pixel includes a first driving transistor T1 and a first light-emitting element D1, the first transistor 11 includes a first power supply writing transistor M1_1 and a first light-emitting control transistor M1_2, the first electrode of the first power supply writing transistor M1_1 is connected to the first power supply line PVDD, the second electrode of the first power supply writing transistor M1_1 is connected to the first electrode of the first driving transistor T1, the first electrode of the first light-emitting control transistor M1_2 is connected to the second electrode of the first driving transistor T1, and the second electrode of the first light-emitting control transistor M1_2 is connected to the first light-emitting element D1. The gates of the first power supply writing transistor M1_1 and the first light-emitting control transistor M1_2 are both connected to the first light-emitting control signal line EM1.

[0127] The channel width-to-length ratio of the first power writing transistor M1_1 is smaller than the channel width-to-length ratio of the first light emission control transistor M1_2.

[0128] The channel width-to-length ratio of the transistor is equal to the ratio of the channel width to the channel length of the transistor. Exemplarily, the channel lengths of the first power write transistor M1_1 and the first emission control transistor M1_2 are the same, and the channel width of the first power write transistor M1_1 is smaller than the channel width of the first emission control transistor M1_2.

[0129] The first electrode of the first power write transistor M1_1 is the source, and the second electrode of the first power write transistor M1_1 is the drain; the first electrode of the first light emission control transistor M1_2 is the source, and the second electrode of the first light emission control transistor M1_2 is the drain.

[0130] The gates of the first power supply write transistor M1_1 and the first light emission control transistor M1_2 are both connected to the first light emission control signal line EM1, and the gate voltages of the first power supply write transistor M1_1 and the first light emission control transistor M1_2 are the same. The first light emission control transistor M1_2 is close to the first light emitting element D1, the first power supply write transistor M1_1 is close to the first power supply line PVDD, and the source voltage of the first light emission control transistor M1_2 is small, so the absolute value of the gate-source voltage difference |Vgs| of the first light emission control transistor M1_2 is small, and when the width-to-length ratio of the first light emission control transistor M1_2 is large, the first power supply write transistor M1_1 and the first light emission control transistor M1_2 can both maintain a good conduction state.

[0131] In some embodiments, Figure 3 and Figure 4 As shown, the display panel further includes a third sub-pixel 3, the third sub-pixel 3 includes a third transistor 33, and a gate of the third transistor 33 is connected to the second light emitting control signal line EM2.

[0132] The second sub-pixel includes a second driving transistor T2 and a second light-emitting element D2, and the second transistor 22 includes a second power supply writing transistor M2_1 and a second light-emitting control transistor M2_2, wherein the first electrode of the second power supply writing transistor M2_1 is connected to the first power line PVDD, the second electrode of the second power supply writing transistor M2_1 is connected to the first electrode of the second driving transistor T2, the first electrode of the second light-emitting control transistor M2_2 is connected to the second electrode of the second driving transistor T2, and the second electrode of the second light-emitting control transistor M2_2 is connected to the second light-emitting element D2. The gates of the second power supply writing transistor M2_1 and the second light-emitting control transistor M2_2 are both connected to the second light-emitting control signal line EM2.

[0133] The third sub-pixel 3 includes a third driving transistor T3 and a third light-emitting element D3, the third transistor includes a third power supply writing transistor M3_1 and a third light-emitting control transistor M3_2, the first electrode of the third power supply writing transistor M3_1 is connected to the first power line PVDD, the second electrode of the third power supply writing transistor M3_1 is connected to the first electrode of the third driving transistor T3, the first electrode of the third light-emitting control transistor M3_2 is connected to the second electrode of the third driving transistor T3, and the second electrode of the third light-emitting control transistor M3_2 is connected to the third light-emitting element D3. The gates of the third power supply writing transistor M3_1 and the third light-emitting control transistor M3_2 are both connected to the second light-emitting control signal line EM2.

[0134] The channel width-to-length ratio of the second power write transistor M2_1 is smaller than that of the second emission control transistor M2_2, and / or the channel width-to-length ratio of the third power write transistor M3_1 is smaller than that of the third emission control transistor M3_2.

[0135] Exemplarily, the channel length of the second power write transistor M2_1 is equal to the channel length of the second light emission control transistor M2_2, and the channel width of the second power write transistor M2_1 is smaller than the channel width of the second light emission control transistor M2_2.

[0136] Exemplarily, the channel length of the third power write transistor M3_1 is equal to the channel length of the third light emission control transistor M3_2, and the channel width of the third power write transistor M3_1 is smaller than the channel width of the third light emission control transistor M3_2.

[0137] Similarly, the second light-emitting control transistor M2_2 is close to the second light-emitting element D2, the second power supply write transistor M2_1 is close to the first power supply line PVDD, and the source voltage of the second light-emitting control transistor M2_2 is relatively small. Therefore, the absolute value of the gate-source voltage difference |Vgs| of the second light-emitting control transistor M2_2 is small. When the width-to-length ratio of the second light-emitting control transistor M2_2 is large, the second power supply write transistor M2_1 and the second light-emitting control transistor M2_2 can both maintain a good conduction state.

[0138] The third light-emitting control transistor M3_2 is close to the third light-emitting element D3, the third power supply write transistor M3_1 is close to the first power supply line PVDD, and the source voltage of the third light-emitting control transistor M3_2 is relatively small. Therefore, the absolute value of the gate-source voltage difference |Vgs| of the third light-emitting control transistor M3_2 is small. When the width-to-length ratio of the third light-emitting control transistor M3_2 is large, the third power supply write transistor M3_1 and the third light-emitting control transistor M3_2 can both maintain a good conduction state.

[0139] In some embodiments, the channel width-to-length ratio of the second power write transistor M2_1 is equal to the channel width-to-length ratio of the third power write transistor M3_1, and / or the channel width-to-length ratio of the second light-emitting control transistor M2_2 is equal to the channel width-to-length ratio of the third light-emitting control transistor M3_2. The second power write transistor M2_1 and the third power write transistor M3_1 are both used to write the power supply voltage into the driving transistors connected to them, and both are transistors with the same function. The second light-emitting control transistor M2_2 and the third light-emitting control transistor M3_2 are both used to transmit the driving current to the light-emitting elements connected to them, and both are transistors with the same function. In this embodiment, the transistors with the same function in the second sub-pixel and the third sub-pixel are designed to have the same channel width-to-length ratio, which will not lead to a large difference in the driving of the two sub-pixels and will not increase the difficulty of the process.

[0140] Exemplarily, the light-emitting element in the present application includes but is not limited to a micro light-emitting diode (Micro LED) or a mini light-emitting diode (Mini LED). To realize color display, LED devices of three colors, red, green and blue, are required. There are differences in luminous efficiency between devices of different colors. The inventors have found that the luminous efficiency of the red sub-pixel is quite different from that of the green sub-pixel and the blue sub-pixel, while the luminous efficiency of the green sub-pixel and the blue sub-pixel is close.

[0141] In some embodiments, the first sub-pixel includes a red sub-pixel, one of the second sub-pixel and the third sub-pixel is a green sub-pixel, and the other is a blue sub-pixel. In this embodiment, the red sub-pixel is connected to the first light-emitting control signal line alone, and the second sub-pixel and the third sub-pixel share the second light-emitting control signal line, so that the light-emitting duration of the red sub-pixel can be adjusted, thereby compensating for the difference in light-emitting efficiency of different light-emitting elements and improving the display effect of the display panel.

[0142] In some embodiments, when the first light emitting control signal line is connected to the red sub-pixel and the second light emitting control signal line is connected to the green sub-pixel and the blue sub-pixel, Fig.13 As shown, within one frame, the duration t11 of the effective level on the first light emitting control signal line EM1 is greater than the duration t12 of the effective level on the second light emitting control signal line EM2.

[0143] Fig.13 It is understood that when the transistors controlled by the first light emitting control signal line EM1 and the second light emitting control signal line EM2 are both N-type transistors, the effective levels of both are high.

[0144] in addition, Fig.13 In one frame, the first light control signal line EM1 includes one valid level, and the second light control signal line EM2 includes one valid level. In other examples, in one frame, the first light control signal line EM1 may include multiple valid levels, and the second light control signal line EM2 may include multiple valid levels, and the total duration of the multiple valid levels on the first light control signal line EM1 is greater than the total duration of the multiple valid levels on the second light control signal line EM2.

[0145] In this embodiment, the effective level on the first light emitting control signal line EM1 lasts longer, which can make the red sub-pixel emit light for a longer time, thereby compensating for the problem of low light emitting efficiency of the red sub-pixel.

[0146] The present application also provides a display device, including the display panel provided by the present application. Fig.14 , Fig.14 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.14 The provided display device 1000 includes a display panel 100 , and the display panel 100 is the display panel provided by any of the above embodiments of the present application. Fig.14 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0147] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: sub-pixels and light-emission control signal lines, the sub-pixels include a first sub-pixel and a second sub-pixel, the light-emission control signal lines include a first light-emission control signal line and a second light-emission control signal line, the first sub-pixel includes a first transistor, the second sub-pixel includes a second transistor, a gate of the first transistor is connected to the first light-emission control signal line, and a gate of the second transistor is connected to the second light-emission control signal line; A channel area of ​​the first transistor is different from a channel area of ​​the second transistor.

2. The display panel according to claim 1, characterized in that: The display panel further includes a third sub-pixel, the third sub-pixel includes a third transistor, and a gate of the third transistor is connected to the second light emitting control signal line; A channel area of ​​the first transistor is greater than a channel area of ​​the second transistor, and a channel area of ​​the first transistor is greater than a channel area of ​​the third transistor.

3. The display panel according to claim 2, characterized in that: A channel area of ​​the first transistor is equal to a sum of a channel area of ​​the second transistor and a channel area of ​​the third transistor.

4. The display panel according to claim 3, characterized in that: The channel lengths of the first transistor, the second transistor and the third transistor are equal; The channel width of the first transistor is equal to the sum of the channel width of the second transistor and the channel width of the third transistor.

5. The display panel according to claim 4, characterized in that: A channel width of the second transistor is equal to a channel width of the third transistor.

6. The display panel according to claim 1, characterized in that: The first transistor includes a first sub-transistor and a second sub-transistor, the first sub-transistor and the second sub-transistor are connected in series, and the gate of the first sub-transistor and the gate of the second sub-transistor are both connected to the first light-emitting control signal line; A channel area of ​​the first transistor is equal to a sum of channel areas of the first sub-transistor and the second sub-transistor.

7. The display panel according to claim 6, characterized in that: The display panel further includes a third sub-pixel, the third sub-pixel includes a third transistor, and a gate of the third transistor is connected to the second light emitting control signal line; The channel areas of the first sub-transistor, the second sub-transistor, the second transistor and the third transistor are the same.

8. The display panel according to claim 7, characterized in that: The channel widths of the first sub-transistor, the second sub-transistor, the second transistor and the third transistor are the same, and the channel lengths of the first sub-transistor, the second sub-transistor, the second transistor and the third transistor are the same.

9. The display panel according to claim 1, characterized in that: At least one of the first light-emitting control signal line and the second light-emitting control signal line is connected to a compensation structure, and the compensation structure is used to compensate for the load of the light-emitting control signal line connected thereto.

10. The display panel according to claim 9, characterized in that: The compensation structure includes a capacitor, one end of which is connected to a light-emitting control line, and the other end of which is connected to a fixed voltage signal line.

11. The display panel according to claim 10, characterized in that: The display panel further includes a third sub-pixel, the third sub-pixel includes a third transistor, and a gate of the third transistor is connected to the second light emitting control signal line; The capacitor at least includes a first capacitor, and the first capacitor is connected to the first light-emitting control signal line.

12. The display panel according to claim 11, characterized in that: The first capacitors and the first sub-pixels are arranged in a one-to-one correspondence, and the first capacitors are arranged close to the corresponding first sub-pixels.

13. The display panel according to claim 11, characterized in that: The first sub-pixel further includes a first storage capacitor, and the capacitance of the first capacitor is smaller than the capacitance of the first storage capacitor.

14. The display panel according to claim 11, characterized in that: The capacitor also includes a second capacitor, the second capacitor is connected to the second light-emitting control signal line, and the capacitance of the first capacitor is greater than the capacitance of the second capacitor.

15. The display panel according to claim 2, characterized in that: A line width of the first light emission control signal line is smaller than a line width of the second light emission control signal line.

16. The display panel according to claim 1, characterized in that: The first sub-pixel includes a first driving transistor and a first light emitting element, wherein the first transistor includes a first power writing transistor and a first light emitting control transistor (, The first power writing transistor is connected between the first electrode of the first driving transistor and the first power line, and the first light emission control transistor is connected between the second electrode of the first driving transistor and the first light emitting element; A channel width-to-length ratio of the first power supply writing transistor is smaller than a channel width-to-length ratio of the first light emission controlling transistor.

17. The display panel according to claim 16, characterized in that: The display panel further includes a third sub-pixel, the third sub-pixel includes a third transistor, and a gate of the third transistor is connected to the second light emitting control signal line; The second sub-pixel includes a second driving transistor and a second light-emitting element, the second transistor includes a second power supply writing transistor and a second light-emitting control transistor, the second power supply writing transistor is connected between a first electrode of the second driving transistor and a first power line, and the second light-emitting control transistor is connected between a second electrode of the second driving transistor and the second light-emitting element; The third sub-pixel includes a third driving transistor and a third light-emitting element, the third transistor includes a third power supply writing transistor and a third light-emitting control transistor, the third power supply writing transistor is connected between the first electrode of the third driving transistor and the first power line, and the third light-emitting control transistor is connected between the second electrode of the third driving transistor and the third light-emitting element; The channel width-to-length ratio of the second power supply write transistor is smaller than that of the second light emission control transistor, and / or the channel width-to-length ratio of the third power supply write transistor is smaller than that of the third light emission control transistor.

18. The display panel according to claim 17, characterized in that: The channel width-to-length ratio of the second power supply write transistor is equal to the channel width-to-length ratio of the third power supply write transistor, and / or the channel width-to-length ratio of the second emission control transistor is equal to the channel width-to-length ratio of the third emission control transistor.

19. The display panel according to claim 1, characterized in that: The first sub-pixel includes a red sub-pixel, one of the second sub-pixel and the third sub-pixel is a green sub-pixel, and the other is a blue sub-pixel.

20. The display device according to claim 19, characterized in that In one frame, a duration of a valid level on the first light-emitting control signal line is longer than a duration of a valid level on the second light-emitting control signal line.

21. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1-20.

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