Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a substrate, a chip assembly, a connecting wire and a flexible circuit board, the chip assembly comprises a low-level power signal input pin, a low-level power signal output pin and a dummy bonding pad, and the low-level power signal input pin and the low-level power signal output pin are arranged on the two opposite sides of the chip assembly at intervals; at least part of the dummy pads are arranged between the low-level power supply signal input pin and the low-level power supply signal output pin at intervals; the connecting line comprises a first connecting line, a second connecting line and a third connecting line, the two ends of the first connecting line are electrically connected with the two dummy bonding pads respectively, the first end of the second connecting line and the first end of the third connecting line are electrically connected with the first connecting line respectively, and the second end of the second connecting line is electrically connected with the low-level power signal input pin; the flexible circuit board comprises a low-level power signal output terminal, and the low-level power signal output terminal is electrically connected with the low-level power signal input pin and the second end of the second connecting line.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The resolution of existing OLED (Organic Light-Emitting Diode) display panels is getting higher and higher, which makes the power consumption of the driver chip higher and higher. The increase in the power consumption of the driver chip makes the temperature of the driver chip too high, which affects the output capacity of the driver chip and even causes the driver chip to burn out, resulting in a decrease in the display effect of the display panel. Therefore, how to effectively reduce the heat generated by the driver chip to control the temperature of the driver chip is an urgent problem to be solved. Summary of the invention

[0003] The present application provides a display panel and a display device, which can effectively reduce the heat generated by a driving chip to control the temperature of the driving chip.

[0004] On the one hand, an embodiment of the present application provides a display panel, which includes: a substrate, a chip component, a connecting wire and a flexible circuit board, wherein the substrate is arranged on the substrate, the chip component includes a low-level power signal input pin, a high-level power signal input pin, an output pin and a dummy pad, the low-level power signal input pin, the high-level power signal input pin and the output pin are arranged at opposite sides of the chip component, and at least part of the dummy pad is arranged between the low-level power signal input pin and the output pin; the connecting wire is arranged on the substrate, and the connecting wire includes a first connecting wire, a second connecting wire and a and a third connecting line, the two ends of the first connecting line are respectively electrically connected to the two dummy pads, the first end of the second connecting line and the first end of the third connecting line are respectively electrically connected to the first connecting line, and the second end of the second connecting line is electrically connected to the low-level power signal input pin; the flexible circuit board is arranged on at least one side of the substrate, and the flexible circuit board includes a low-level power signal output terminal and a high-level power signal output terminal, the low-level power signal output terminal is electrically connected to the low-level power signal input pin and the second end of the second connecting line, and the high-level power signal output terminal is electrically connected to the high-level power signal input pin.

[0005] Optionally, in some embodiments of the present application, the plurality of dummy pads include a plurality of first dummy pads and a plurality of second dummy pads, the plurality of first dummy pads are arranged at intervals along a first direction and are located between the low-level power signal input pin and the output pin; the plurality of second dummy pads are arranged at intervals along a second direction and are located on one side of the low-level power signal input pin and the output pin along the first direction, and the first direction intersects with the second direction; wherein, at least some of the first dummy pads are electrically connected through the first connecting wire to form a first path, at least some of the second dummy pads are electrically connected through the first connecting wire to form a second path, and the first path and the second path are electrically connected through the first connecting wire, the first path and the low-level power signal input pin are electrically connected through the second connecting wire, and the second path and the low-level power signal output terminal are electrically connected through the third connecting wire.

[0006] Optionally, in some embodiments of the present application, the connecting line also includes a fourth connecting line, a first end of the fourth connecting line is electrically connected to the low-level power signal output terminal, and a second end of the fourth connecting line is electrically connected to the low-level power signal input pin; wherein the fourth connecting line includes a first sub-connecting line and a second sub-connecting line, the first sub-connecting line is arranged on a side of the second sub-connecting line away from the substrate, the first end of the first sub-connecting line and the first end of the second sub-connecting line are both electrically connected to the low-level power signal output terminal, and the second end of the first sub-connecting line and the second end of the second sub-connecting line are both electrically connected to the low-level power signal input pin; an insulating layer is arranged between the first sub-connecting line and the second sub-connecting line, and the orthographic projection of the insulating layer on the substrate covers the orthographic projection of the first sub-connecting line on the substrate and the orthographic projection of the second sub-connecting line on the substrate.

[0007] Optionally, in some embodiments of the present application, a through hole is provided on the insulating layer, and the first sub-connection line is electrically connected to the second sub-connection line through the through hole.

[0008] Optionally, in some embodiments of the present application, a plurality of the first sub-connection lines are sequentially spaced apart along the first direction, and a plurality of the second sub-connection lines are sequentially spaced apart along the first direction.

[0009] Optionally, in some embodiments of the present application, the orthographic projection of the first sub-connection line on the substrate at least partially covers the orthographic projection of the second sub-connection line on the substrate.

[0010] Optionally, in some embodiments of the present application, the connecting wiring also includes a plurality of fifth connecting lines, the plurality of fifth connecting lines are arranged at intervals along the first direction, the first end of the fifth connecting line is electrically connected to the low-level power signal output terminal, and the second end of the fifth connecting line is electrically connected to the low-level power signal input pin; the display panel includes a first metal layer, an insulating layer and a second metal layer, the insulating layer is arranged between the first metal layer and the second metal layer, the second metal layer is arranged on a side of the first metal layer away from the substrate, and the plurality of fifth connecting lines are staggered along the first direction on the first metal layer and the second metal layer.

[0011] Optionally, in some embodiments of the present application, a cross-sectional width of the fifth connecting line along the first direction is greater than a cross-sectional width of the fourth connecting line along the first direction.

[0012] Optionally, in some embodiments of the present application, the cross-sectional width of the second connecting line along the first direction is greater than the cross-sectional width of the first connecting line along the second direction, and the cross-sectional width of the third connecting line along the first direction is greater than the cross-sectional width of the first connecting line along the second direction, and the first direction intersects with the second direction.

[0013] In addition, an embodiment of the present application further provides a display device, comprising the display panel as described above and a driving circuit, wherein the driving circuit is electrically connected to the display panel, and the driving circuit is used to drive the display panel.

[0014] In the display panel and display device provided by the present application, at least part of the dummy pads in the chip assembly are electrically connected by setting a first connecting line, and the first connecting line is electrically connected to the low-level power signal input pin and the low-level power signal output terminal in the flexible circuit board by setting a second connecting line. At the same time, the first connecting line is electrically connected to the low-level power signal output terminal in the flexible circuit board by setting a third connecting line, so as to reduce the impedance of the line between the chip assembly and the flexible circuit board, thereby effectively reducing the heat generated by the driving chip to control the temperature of the driving chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a first structure of a display panel provided in an embodiment of the present application;

[0016] Figure 2 is a schematic diagram of a second structure of a display panel provided in an embodiment of the present application;

[0017] Figure 3 is a first cross-sectional view of a display panel provided by an embodiment of the present application along the AA' direction;

[0018] Figure 4 is a second cross-sectional view of the display panel provided by the embodiment of the present application along the AA' direction;

[0019] Figure 5 is a third cross-sectional view of the display panel provided by the embodiment of the present application along the AA' direction;

[0020] Figure 6 is a fourth cross-sectional view of the display panel provided by the embodiment of the present application along the AA' direction;

[0021] Figure 7 This is a third structural schematic diagram of the display panel provided in the embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0023] The various embodiments provided in this application are similar, and features in different embodiments are combined with each other.

[0024] like Figures 1 to 3As shown, an embodiment of the present application provides a display panel 100, which includes: a substrate 10, a chip assembly 20, a connecting trace 30 and a flexible circuit board 40. The substrate 10 is arranged on the substrate 10, and the chip assembly 20 includes a low-level power signal input pin 21, an output pin 22, a dummy pad 23 and a high-level power signal input pin 24. The low-level power signal input pin 21, the high-level power signal input pin 24 and the output pin 22 are arranged at opposite sides of the chip assembly 20 at intervals, and at least part of the dummy pad 23 is arranged between the low-level power signal input pin 21 and the output pin 22. Specifically, the low-level power signal input pin 21 and the high-level power signal input pin 24 are arranged at intervals along the first direction X on the side of the chip assembly 20 close to the flexible circuit board 40. The connection trace 30 is disposed on the substrate 10, and the connection trace 30 includes a first connection line 31, a second connection line 32, and a third connection line 33. The two ends of the first connection line 31 are electrically connected to the two dummy pads 23, respectively. The first end of the second connection line 32 and the first end of the third connection line 33 are electrically connected to the first connection line 31, respectively. The second end of the second connection line 32 is electrically connected to the low-level power signal input pin 21. The flexible circuit board 40 is disposed on at least one side of the substrate 10, and the flexible circuit board 40 includes a low-level power signal output terminal 41 and a high-level power signal output terminal 42. The low-level power signal output terminal 41 is electrically connected to the low-level power signal input pin 21 and the second end of the second connection line 32. The high-level power signal output terminal 42 is electrically connected to the high-level power signal input pin 24.

[0025] The display panel provided by the embodiment of the present application electrically connects at least part of the dummy pads 23 in the chip assembly 20 by setting a first connecting line 31, and electrically connects the first connecting line 31 with the low-level power signal input pin 21 and the low-level power signal output terminal 41 in the flexible circuit board 40 by setting a second connecting line 32. At the same time, the first connecting line 31 is electrically connected to the low-level power signal output terminal 41 in the flexible circuit board 40 by setting a third connecting line 33, so as to reduce the impedance of the line between the chip assembly 20 and the flexible circuit board 40, thereby effectively reducing the heat generated by the driving chip to control the temperature of the driving chip.

[0026] In an embodiment of the present application, the chip assembly 20 includes a plurality of low-level power signal input pins 21, a plurality of output pins 22, and a plurality of dummy pads 23, wherein the plurality of low-level power signal input pins 21 are arranged at intervals along a first direction X, the plurality of output pins 22 are arranged at intervals along the first direction X, and the low-level power signal input pins 21 and the output pins 22 are arranged at intervals along a second direction Y. The first direction X is the length direction of the chip assembly 20, and the second direction Y is the width direction of the chip assembly 20.

[0027] In an embodiment of the present application, the plurality of dummy pads 23 include a plurality of first dummy pads 231 and a plurality of second dummy pads 232, the plurality of first dummy pads 231 are arranged at intervals along the first direction X and are located between the low-level power signal input pin 21 and the output pin 22; the plurality of second dummy pads 232 are arranged at intervals along the second direction Y and are located on one side of the low-level power signal input pin 21 and the output pin 22 along the first direction X, and the first direction X intersects with the second direction Y; wherein at least some of the first dummy pads 231 are electrically connected through the first connecting wire 31 to form a first passage 23a, at least some of the second dummy pads 232 are electrically connected through the first connecting wire 31 to form a second passage 23b, and the first passage 23a is electrically connected to the second passage 23b through the first connecting wire 31, the first passage 23a is electrically connected to the low-level power signal input pin 21 through the second connecting wire 32, and the second passage 23b is electrically connected to the low-level power signal output terminal 41 through the third connecting wire 33.

[0028] In the embodiment of the present application, the cross-sectional shape of the first dummy pad 231 along the horizontal direction is different from the cross-sectional shape of the second dummy pad 232 along the first direction X. Specifically, the cross-sectional width of the first dummy pad 231 along the first direction X is smaller than the cross-sectional width of the second dummy pad 232 along the first direction X, and the cross-sectional width of the first dummy pad 231 along the second direction Y is greater than the cross-sectional width of the second dummy pad 232 along the second direction Y.

[0029] In an embodiment of the present application, the chip component 20 also includes a chip body 25, which is arranged on a side of the low-level power signal input pin 21, the output pin 22 and the dummy pad 23 away from the substrate 10, and the chip body 25 is electrically connected to the low-level power signal input pin 21 and the output pin 22.

[0030] like Figure 1 As shown, a first connection line 31 is disposed between two adjacent dummy pads 23 , and the two adjacent dummy pads 23 are electrically connected through the first connection line 31 .

[0031] like Figure 2 As shown, a first connection line 31 is provided between each of the plurality of first dummy pads 231, and two adjacent first dummy pads 231 are electrically connected via the first connection line 31. A first connection line 31 is provided between only a portion of the second dummy pads 232 close to one side of the flexible circuit board 40, and two adjacent second dummy pads 232 are electrically connected via the first connection line 31. A portion of the second dummy pads 232 away from one side of the flexible circuit board 40 are spaced apart and are only used to support the chip body 25.

[0032] In the embodiment of the present application, the connection trace 30 further includes a fourth connection line 34, a first end of the fourth connection line 34 is electrically connected to the low-level power signal output terminal 41, and a second end of the fourth connection line 34 is electrically connected to the low-level power signal input pin 21. The fourth connection line 34 includes a first sub-connection line 341 and a second sub-connection line 342, and the first sub-connection line 341 is arranged on a side of the second sub-connection line 342 away from the substrate 10. By setting the fourth connection line 34 between the chip assembly 20 and the flexible circuit board 40 as a double-layered first sub-connection line 341 and a second sub-connection line 342, the first end of the first sub-connection line 341 and the first end of the second sub-connection line 342 are both electrically connected to the low-level power signal output terminal 41, and the second end of the first sub-connection line 341 and the second end of the second sub-connection line 342 are both electrically connected to the low-level power signal input pin 21, so as to further reduce the impedance of the line between the chip assembly 20 and the flexible circuit board 40, thereby reducing the heat generated by the chip assembly 20 to control the temperature of the chip assembly 20, and avoiding the chip assembly 20 from being overheated and affecting its output stability or being overheated and causing the chip assembly 20 to burn out. Part of the fourth connection line 34 is also used to connect the high-level power signal output terminal 42 and the high-level power signal input pin 24.

[0033] like Figure 3 As shown, the display panel 100 includes a first metal layer 50, an insulating layer 60 and a second metal layer 70, the insulating layer 60 is disposed between the first metal layer 50 and the second metal layer 70, the second metal layer 70 is disposed on a side of the first metal layer 50 away from the substrate 10, and a plurality of fifth connection lines 35 are staggered on the first metal layer 50 and the second metal layer 70 along the first direction X. The second metal layer 70 includes a first sub-connection line 341, and the first metal layer 50 includes a second sub-connection line 342. The orthographic projection of the insulating layer 60 on the substrate 10 covers the orthographic projection of the first sub-connection line 341 on the substrate 10 and the orthographic projection of the second sub-connection line 342 on the substrate 10.

[0034] In the embodiment of the present application, the orthographic projection of the first sub-connection line 341 on the substrate 10 at least partially covers the orthographic projection of the second sub-connection line 342 on the substrate 10. That is, the cross-sectional width of the first sub-connection line 341 along the first direction X is greater than or equal to the cross-sectional width of the second sub-connection line 342 along the first direction X, and the first sub-connection line 341 and the second sub-connection line 342 at least partially overlap. Figure 3 It is exemplarily shown that the cross-sectional width of the first sub-connection line 341 along the first direction X is equal to the cross-sectional width of the second sub-connection line along the first direction X, and the orthographic projection of the first sub-connection line 341 on the substrate 10 covers the orthographic projection of the second sub-connection line 342 on the substrate 10.

[0035] In the embodiment of the present application, the cross-sectional width of the second connection line 32 along the horizontal direction is equal to the cross-sectional width of the first connection line 31 along the horizontal direction and the cross-sectional width of the third connection line 33 along the horizontal direction.

[0036] like Figure 4 As shown, an embodiment of the present application provides a display panel 200 , the difference between the display panel 200 and the display panel 100 is that a through hole 61 is provided on the insulating layer 60 in the display panel 200 , and the first sub-connection line 341 is electrically connected to the second sub-connection line 342 through the through hole 61 .

[0037] In an embodiment of the present application, the orthographic projection of the first sub-connection line 341 on the substrate 10 covers the orthographic projection of the second sub-connection line 342 on the substrate 10, and the cross-sectional area of ​​the through hole 61 along the first direction X is less than or equal to the cross-sectional area of ​​the second sub-connection line 342 along the horizontal direction, and the cross-sectional area of ​​the second sub-connection line 342 along the horizontal direction is less than or equal to the cross-sectional area of ​​the first sub-connection line 341 along the horizontal direction.

[0038] Figure 4 It is exemplarily shown that the orthographic projection of the first sub-connection line 341 on the substrate 10 covers the orthographic projection of the second sub-connection line 342 on the substrate 10, and the cross-sectional area of ​​the through hole 61 along the first direction X is equal to the cross-sectional area of ​​the second sub-connection line 342 along the first direction X, and the cross-sectional area of ​​the second sub-connection line 342 along the first direction X is equal to the cross-sectional area of ​​the first sub-connection line 341 along the horizontal direction.

[0039] In the embodiment of the present application, the orthographic projection of the first sub-connection line 341 on the substrate 10 partially covers the orthographic projection of the second sub-connection line 342 on the substrate 10, and the through hole 61 is arranged corresponding to the overlapping area of ​​the first sub-connection line 341 and the second sub-connection line 342, and the first sub-connection line 341 and the second sub-connection line 342 are electrically connected through the through hole 61. The cross-sectional area of ​​the through hole 61 along the horizontal direction is less than or equal to the cross-sectional area of ​​the overlapping area of ​​the first sub-connection line 341 and the second sub-connection line 342 along the horizontal direction.

[0040] The other structures of the display panel 200 are the same as those of the display panel 100 .

[0041] like Figure 5 As shown, an embodiment of the present application provides a display panel 300 , which differs from the display panel 100 in that a plurality of first sub-connection lines 341 are sequentially spaced along a first direction X, and a plurality of second sub-connection lines 342 are sequentially spaced along the first direction X.

[0042] Specifically, a plurality of fourth connection lines 34 in the display panel 300 are arranged at intervals along the first direction X, and the first sub-connection lines 341 and the second sub-connection lines 342 are arranged in an alternating manner along the first direction X.

[0043] In the embodiment of the present application, the orthographic projection of the first sub-connection line 341 on the substrate 10 is located on one side of the orthographic projection of the second sub-connection line 342 on the substrate 10. This reduces the impedance of the line between the chip assembly 20 and the flexible circuit board 40 while reducing the parasitic capacitance between the first sub-connection line 341 and the second connection line 32, thereby improving the stability of the signal.

[0044] The other structures of the display panel 300 are the same as those of the display panel 100 .

[0045] like Figure 6 As shown, an embodiment of the present application provides a display panel 400, and the difference between the display panel 400 and the display panel 200 is that: the connecting wiring 30 in the display panel 200 also includes a plurality of fifth connecting wires 35, and the plurality of fifth connecting wires 35 are arranged at intervals along the first direction X, and the first end of the fifth connecting wire 35 is electrically connected to the low-level power signal output terminal 41, and the second end of the fifth connecting wire 35 is electrically connected to the low-level power signal input pin 21.

[0046] The display panel 400 includes a first metal layer 50, an insulating layer 60 and a second metal layer 70, the insulating layer 60 is arranged between the first metal layer 50 and the second metal layer 70, the second metal layer 70 is arranged on a side of the first metal layer 50 away from the substrate 10, and a plurality of fifth connecting lines 35 are staggered along the first direction X on the first metal layer 50 and the second metal layer 70.

[0047] In the embodiment of the present application, the fourth connection line 34 and the fifth connection line 35 are arranged at intervals along the first direction X. Among them, the fourth connection line 34 includes a first sub-connection line 341 and a second sub-connection line 342. A through hole 61 is provided on the insulating layer 60. The orthographic projection of the first sub-connection line 341 on the substrate 10 covers the orthographic projection of the second sub-connection line 342 on the substrate 10, and the cross-sectional area of ​​the through hole 61 along the horizontal direction is equal to the cross-sectional area of ​​the second sub-connection line 342 along the horizontal direction, and the cross-sectional area of ​​the second sub-connection line 342 along the horizontal direction is equal to the cross-sectional area of ​​the first sub-connection line 341 along the horizontal direction.

[0048] In the embodiment of the present application, a cross-sectional width of the fifth connection line 35 along the first direction X is greater than a cross-sectional width of the fourth connection line 34 along the first direction X. Figure 6 It is exemplarily shown that the fourth connection lines 34 and the fifth connection lines 35 are alternately arranged along the first direction X, and the cross-sectional width of the fifth connection lines 35 along the first direction X is greater than the cross-sectional width of the fourth connection lines 34 along the first direction X.

[0049] like Figure 7 As shown, the embodiment of the present application provides a display panel 500, and the difference between the display panel 500 and the display panel 100 is that: in the display panel 500, the cross-sectional width of the second connection line 32 along the first direction X is greater than the cross-sectional width of the first connection line 31 along the second direction Y, and the cross-sectional width of the third connection line 33 along the first direction is greater than the cross-sectional width of the first connection line 31 along the second direction Y. The cross-sectional width of the second connection line 32 along the first direction X is equal to the cross-sectional width of the third connection line 33 along the first direction X.

[0050] In the embodiment of the present application, the cross-sectional width of the fourth connection line 34 along the first direction X is greater than the cross-sectional width of the second connection line 32 along the first direction X and the cross-sectional width of the third connection line 33 along the first direction X.

[0051] Specifically, the display panel 500 includes: a substrate 10, a chip assembly 20, a connection line 30 and a flexible circuit board 40. The substrate 10 is arranged on the substrate 10, the chip assembly 20 includes a low-level power signal input pin 21, an output pin 22 and a dummy pad 23, the low-level power signal input pin 21 and the output pin 22 are arranged at opposite sides of the chip assembly 20, and at least part of the dummy pad 23 is arranged between the low-level power signal input pin 21 and the output pin 22. The connection line 30 is arranged on the substrate 10, and the connection line 30 includes a first connection line 31, a second connection line 32, a third connection line 33 and a fourth connection line 34, the two ends of the first connection line 31 are electrically connected to the two dummy pads 23 respectively, the first end of the second connection line 32 and the first end of the third connection line 33 are electrically connected to the first connection line 31 respectively, and the second end of the second connection line 32 is electrically connected to the low-level power signal input pin 21. The flexible circuit board 40 is disposed on at least one side of the substrate 10 , and includes a low-level power signal output terminal 41 , which is electrically connected to the low-level power signal input pin 21 and the second end of the second connection line 32 .

[0052] In the embodiment of the present application, the first end of the fourth connection line 34 is electrically connected to the low-level power signal output terminal 41, and the second end of the fourth connection line 34 is electrically connected to the low-level power signal input pin 21. The fourth connection line 34 includes a first sub-connection line 341 and a second sub-connection line 342, and the first sub-connection line 341 is arranged on a side of the second sub-connection line 342 away from the substrate 10. By setting the fourth connection line 34 between the chip assembly 20 and the flexible circuit board 40 as a double-layered first sub-connection line 341 and a second sub-connection line 342, the impedance of the line between the chip assembly 20 and the flexible circuit board 40 is further reduced, thereby reducing the heat generated by the chip assembly 20 to control the temperature of the chip assembly 20, and avoiding the chip assembly 20 from being overheated and affecting the stability of its output or being overheated and causing the chip assembly 20 to burn out.

[0053] In the embodiment of the present application, an insulating layer 60 is disposed between the first sub-connection line 341 and the second sub-connection line 342, and the orthographic projection of the insulating layer 60 on the substrate 10 covers the orthographic projection of the first sub-connection line 341 on the substrate 10 and the orthographic projection of the second sub-connection line 342 on the substrate 10. That is, the cross-sectional width of the first sub-connection line 341 along the first direction X is greater than or equal to the cross-sectional width of the second sub-connection line 342 along the first direction X, and the first sub-connection line 341 and the second sub-connection line 342 at least partially overlap.

[0054] In the embodiment of the present application, the cross-sectional width of the second connection line 32 along the horizontal direction is equal to the cross-sectional width of the first connection line 31 along the horizontal direction and the cross-sectional width of the third connection line 33 along the horizontal direction.

[0055] In an embodiment of the present application, the chip component 20 includes a plurality of low-level power signal input pins 21 and a plurality of output pins 22, wherein the plurality of low-level power signal input pins 21 are arranged at intervals along a first direction X, the plurality of output pins 22 are arranged at intervals along the first direction X, and the low-level power signal input pins 21 and the output pins 22 are arranged at intervals along a second direction Y.

[0056] In an embodiment of the present application, the plurality of dummy pads 23 include a plurality of first dummy pads 231 and a plurality of second dummy pads 232, the plurality of first dummy pads 231 are arranged at intervals along the first direction X and are located between the low-level power signal input pin 21 and the output pin 22; the plurality of second dummy pads 232 are arranged at intervals along the second direction Y and are located on one side of the low-level power signal input pin 21 and the output pin 22 along the first direction X, and the first direction X intersects with the second direction Y; wherein at least some of the first dummy pads 231 are electrically connected through the first connecting wire 31 to form a first passage 23a, at least some of the second dummy pads 232 are electrically connected through the first connecting wire 31 to form a second passage 23b, and the first passage 23a is electrically connected to the second passage 23b through the first connecting wire 31, the first passage 23a is electrically connected to the low-level power signal input pin 21 through the second connecting wire 32, and the second passage 23b is electrically connected to the low-level power signal output terminal 41 through the third connecting wire 33.

[0057] In an embodiment of the present application, the chip component 20 also includes a chip body 25, which is arranged on a side of the low-level power signal input pin 21, the output pin 22 and the dummy pad 23 away from the substrate 10, and the chip body 25 is electrically connected to the low-level power signal input pin 21 and the output pin 22.

[0058] like Figure 1 As shown, a first connection line 31 is disposed between two adjacent dummy pads 23 , and the two adjacent dummy pads 23 are electrically connected through the first connection line 31 .

[0059] In the embodiment of the present application, a first connection line 31 is provided between each of the plurality of first dummy pads 231, and two adjacent first dummy pads 231 are electrically connected via the first connection line 31. A first connection line 31 is provided between only a portion of the second dummy pads 232 close to one side of the flexible circuit board 40, and two adjacent second dummy pads 232 are electrically connected via the first connection line 31. A portion of the second dummy pads 232 away from one side of the flexible circuit board 40 are spaced apart and are only used to support the chip body 25.

[0060] In addition, an embodiment of the present application further provides a display device, including the display panel as described above and a driving circuit, wherein the driving circuit is electrically connected to the display panel, and the driving circuit is used to drive the display panel.

[0061] In the display panel of the display device provided in the present application, at least part of the virtual pads in the chip assembly are electrically connected by setting a first connecting line, and the first connecting line is electrically connected to the low-level power signal input pin and the low-level power signal output terminal in the flexible circuit board by setting a second connecting line. At the same time, the first connecting line is electrically connected to the low-level power signal output terminal in the flexible circuit board by setting a third connecting line. Furthermore, the display panel also double-layers the fourth connecting line used to connect the chip assembly and the flexible circuit board to reduce the impedance of the line between the chip assembly and the flexible circuit board, thereby effectively reducing the heat generated by the driving chip to control the temperature of the driving chip.

[0062] A display panel and a display device provided by the embodiments of the present application are introduced in detail above. The description of the above embodiments is only used to help understand the core idea of ​​the present application, and the above description should not be understood as limiting the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A chip assembly is arranged on the substrate, the chip assembly comprises a low-level power signal input pin and a plurality of dummy pads, the plurality of dummy pads comprises a plurality of first dummy pads and a plurality of second dummy pads; Connecting wires are arranged on the substrate, and the connecting wires include a first connecting wire, a second connecting wire, a third connecting wire and a fourth connecting wire; A flexible circuit board is arranged on at least one side of the substrate, and the flexible circuit board includes a low-level power signal output terminal; Among them, at least part of the first dummy pads are electrically connected through the first connecting line to form a first path, at least part of the second dummy pads are electrically connected through the first connecting line to form a second path, and the first path and the second path are electrically connected through the first connecting line, the first path and the low-level power signal input pin are electrically connected through the second connecting line, the second path and the low-level power signal output terminal are electrically connected through the third connecting line, the first end of the fourth connecting line is electrically connected to the low-level power signal output terminal, and the second end of the fourth connecting line is electrically connected to the low-level power signal input pin.

2. The display panel according to claim 1, characterized in that: The chip assembly further includes an output pin, the low-level power signal input pin and the output pin are spaced apart at two opposite sides of the chip assembly, and at least part of the dummy pads are spaced apart between the low-level power signal input pin and the output pin; The two ends of the first connecting line are electrically connected to the two dummy pads respectively, the first end of the second connecting line and the first end of the third connecting line are electrically connected to the first connecting line respectively, the second end of the second connecting line is electrically connected to the low-level power signal input pin, and the low-level power signal output terminal is electrically connected to the low-level power signal input pin and the second end of the second connecting line.

3. The display panel according to claim 2, characterized in that: A plurality of the first dummy pads are arranged at intervals along a first direction and are located between the low-level power signal input pin and the output pin; A plurality of the second dummy pads are arranged at intervals along a second direction and are located on one side of the low level power signal input pin and the output pin along the first direction, and the first direction intersects the second direction.

4. The display panel according to claim 3, characterized in that: The fourth connecting line includes a first sub-connecting line and a second sub-connecting line, the first sub-connecting line is arranged on a side of the second sub-connecting line away from the substrate, the first end of the first sub-connecting line and the first end of the second sub-connecting line are both electrically connected to the low-level power signal output terminal, and the second end of the first sub-connecting line and the second end of the second sub-connecting line are both electrically connected to the low-level power signal input pin.

5. The display panel according to claim 4, characterized in that: A plurality of the first sub-connection lines are sequentially arranged at intervals along the first direction, and a plurality of the second sub-connection lines are sequentially arranged at intervals along the first direction.

6. The display panel according to claim 4, characterized in that: The orthographic projection of the first sub-connection line on the substrate at least partially covers the orthographic projection of the second sub-connection line on the substrate.

7. The display panel according to claim 4, characterized in that: An insulating layer is arranged between the first sub-connection line and the second sub-connection line, and the orthographic projection of the insulating layer on the substrate covers the orthographic projection of the first sub-connection line on the substrate and the orthographic projection of the second sub-connection line on the substrate. A through hole is arranged on the insulating layer, and the first sub-connection line is electrically connected to the second sub-connection line through the through hole.

8. The display panel according to claim 7, characterized in that: The connecting wires further include a plurality of fifth connecting wires, the plurality of fifth connecting wires are arranged at intervals along the first direction, a first end of the fifth connecting wire is electrically connected to the low-level power signal output terminal, and a second end of the fifth connecting wire is electrically connected to the low-level power signal input pin; The display panel includes a first metal layer, an insulating layer and a second metal layer located on the substrate, the insulating layer is arranged between the first metal layer and the second metal layer, the second metal layer includes the first sub-connecting line, the first metal layer includes the second sub-connecting line, the second metal layer is arranged on a side of the first metal layer away from the substrate, and a plurality of the fifth connecting lines are alternately arranged on the first metal layer and the second metal layer along the first direction.

9. The display panel according to claim 8, characterized in that: A cross-sectional width of the fifth connecting line along the first direction is greater than a cross-sectional width of the fourth connecting line along the first direction.

10. The display panel according to claim 2, characterized in that: The chip assembly also includes a high-level power signal input pin, and the flexible circuit board also includes a high-level power signal output terminal. The low-level power signal input pin, the high-level power signal input pin and the output pin are spaced apart on opposite sides of the chip assembly, and the high-level power signal output terminal is electrically connected to the high-level power signal input pin.

11. The display panel according to claim 1, characterized in that: A cross-sectional width of the second connection line along the horizontal direction is greater than a cross-sectional width of the first connection line along the horizontal direction, and a cross-sectional width of the third connection line along the horizontal direction is greater than a cross-sectional width of the first connection line along the horizontal direction.

12. A display device, characterized in that: It comprises a display panel as described in any one of claims 1 to 11 and a driving circuit, wherein the driving circuit is electrically connected to the display panel, and the driving circuit is used to drive the display panel.

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