Display panel and display device

Abstract

The embodiment of the present application discloses a display panel and a display device, which comprises a first thin film transistor and a capacitor located in a pixel opening area, the capacitor comprises at least three stacked and spaced plates, and the difference between the height of the first thin film transistor and the height of the capacitor is less than 4500 angstroms. The present application improves the capacitance and raises the terrain of the capacitor area by arranging at least three plates, so that the topography of the first thin film transistor and the capacitor is similar, and the flatness of the pixel opening area is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In an organic light-emitting display panel under inkjet printing, the topography flatness of the pixel opening area of the driving backplane determines the uniformity of the film layer after the ink solidification. In addition, based on the improvement of the resolution of the display panel, the area of the compensation capacitor is compressed, thereby reducing the capacitance of the compensation capacitor. Furthermore, based on the improvement of the resolution of the display panel, the driving thin film transistor and the compensation capacitor are arranged in the pixel opening area, and thus the topography of the driving thin film transistor and the compensation capacitor affects the flatness of the pixel opening area. SUMMARY

[0003] Embodiments of the present application provide a display panel and a display device, which can improve the capacitance of the capacitor and the topography flatness of the pixel opening area.

[0004] Embodiments of the present application provide a display panel, which comprises:

[0005] a substrate;

[0006] a first thin film transistor arranged on the substrate;

[0007] a capacitor arranged on the substrate and located at one side of the first thin film transistor;

[0008] an anode arranged at a side of the first thin film transistor and the capacitor away from the substrate; and

[0009] a pixel definition layer arranged at a side of the anode away from the substrate, the pixel definition layer being provided with a pixel opening, and the pixel opening exposing the anode;

[0010] wherein the first thin film transistor and the capacitor respectively partially overlap the anode, the capacitor comprises at least three stacked and spaced apart plates, and the difference between the height of the first thin film transistor and the height of the capacitor is less than 4500 angstroms.

[0011] Optionally, in some embodiments of the present application, the display panel further comprises a light shielding portion, a buffer layer and an interlayer dielectric layer, the first thin film transistor comprises a first active portion, a first gate insulating portion, a first gate electrode, a first electrode and a second electrode, and the capacitor comprises a first plate, a second plate and a third plate.

[0012] The first electrode plate is arranged in the same layer as the light shielding part, the buffer layer covers the first electrode plate and the light shielding part, the second electrode plate is arranged in the same layer as the first active part, the first gate insulating part is arranged on the side of the first active part away from the substrate, the first gate electrode is arranged on the side of the first gate insulating part away from the substrate, the interlayer dielectric layer covers the first gate electrode and the capacitor, and the first electrode and the second electrode are arranged on the side of the interlayer dielectric layer away from the substrate.

[0013] In the thickness direction of the display panel, the third electrode plate is located on one side of the first electrode plate, and one of the first electrode plate and the second electrode plate farther away from the third electrode plate is electrically connected with the third electrode plate.

[0014] Optionally, in some embodiments of the present application, the display panel further comprises a first insulating layer and a switching part, the first insulating layer covers the first gate electrode and the second electrode plate, the third electrode plate is arranged on the side of the first insulating layer away from the substrate, the interlayer dielectric layer covers the first insulating layer and the third electrode plate, the switching part, the first electrode and the second electrode are arranged in the same layer, and the switching part connects the first electrode plate and the third electrode plate.

[0015] Optionally, in some embodiments of the present application, in the display panel in the top view, the light shielding part is connected with the first electrode plate, the second electrode plate is arranged in a spaced manner with the first active part, the second electrode plate comprises a first sub-part and a second sub-part connected with each other, the first sub-part extends along a first direction, the second sub-part extends along a second direction intersecting with the first direction, the first sub-part is located on one side of the first active part in the second direction, the second sub-part is located on one side of the first active part in the first direction, and the first sub-part and the second sub-part are arranged in an overlapping manner with the first electrode plate.

[0016] Optionally, in some embodiments of the present application, in the display panel in the top view, the third electrode plate comprises a third sub-part and a fourth sub-part connected with each other, the third sub-part extends along a first direction, the fourth sub-part extends along a second direction intersecting with the first direction, the third sub-part overlaps with the first sub-part, and the fourth sub-part overlaps with the second sub-part.

[0017] Optionally, in some embodiments of the present application, in the display panel in the top view, the switching part covers part of the fourth sub-part and at least part of the third sub-part, and the switching part is connected with the second electrode.

[0018] Optionally, in some embodiments of the present application, the display panel further comprises a second thin film transistor in the gate driving circuit region, the second thin film transistor comprising a second active part, a second gate insulating part, a second gate electrode, a third electrode and a fourth electrode, the second active part being disposed on the side of the buffer layer away from the substrate, the second gate insulating part being disposed on the side of the second active part away from the substrate, the second gate electrode being disposed on the side of the second gate insulating part away from the substrate, the first insulating layer and the interlayer dielectric layer sequentially covering the second gate electrode, the third electrode and the fourth electrode being disposed on the side of the interlayer dielectric layer away from the substrate.

[0019] The display panel further comprises a peripheral trace in the gate driving circuit region, the peripheral trace being located on the side of the second thin film transistor away from the substrate, and the peripheral trace being electrically connected to the second thin film transistor.

[0020] Optionally, in some embodiments of the present application, the first gate insulating part comprises a first sub-layer and a second sub-layer which are stacked.

[0021] The display panel further comprises a second thin film transistor in the gate driving circuit region, the second thin film transistor comprising a protection part, a second active part, a second gate insulating part, a second gate electrode, a third electrode and a fourth electrode, the protection part being disposed on the side of the buffer layer away from the substrate, the second active part being disposed on the side of the protection part away from the substrate, the second gate insulating part being disposed on the side of the second active part away from the substrate, the second gate electrode being disposed on the side of the second gate insulating part away from the substrate, the first insulating layer and the interlayer dielectric layer sequentially covering the second gate electrode, the third electrode and the fourth electrode being disposed on the side of the interlayer dielectric layer away from the substrate.

[0022] The display panel further comprises a peripheral trace in the gate driving circuit region, the peripheral trace being located on the side of the second thin film transistor away from the substrate, and the peripheral trace being electrically connected to the second thin film transistor.

[0023] Optionally, in some embodiments of the present application, the display panel further comprises a first insulating layer and a switching part, the third electrode plate being disposed on the side of the first electrode plate close to the substrate, the first insulating layer covering the third electrode plate and the substrate, the buffer layer covering the first insulating layer, the switching part being disposed on the side of the interlayer dielectric layer away from the substrate in the same layer as the first electrode, and the switching part connecting the second electrode plate and the third electrode plate.

[0024] Optionally, in some embodiments of the present application, the display panel further comprises a second thin film transistor in the gate driving circuit region, the second thin film transistor comprising a second active layer, a second gate insulating layer, a second gate electrode, a third electrode and a fourth electrode, the second active layer being disposed on the side of the buffer layer away from the substrate, the second gate insulating layer being disposed on the side of the second active layer away from the substrate, the second gate electrode being disposed on the side of the second gate insulating layer away from the substrate, the interlayer dielectric layer sequentially covering the second gate electrode, the third electrode and the fourth electrode being disposed on the side of the interlayer dielectric layer away from the substrate.

[0025] The display panel further comprises a peripheral trace in the gate driving circuit region, the peripheral trace being located on the side of the second thin film transistor away from the substrate, and the peripheral trace being electrically connected to the second thin film transistor.

[0026] Optionally, in some embodiments of the present application, the first gate insulating layer comprises a first sub-layer and a second sub-layer which are stacked.

[0027] The display panel further comprises a second thin film transistor in the gate driving circuit region, the second thin film transistor comprising a protective layer, a second active layer, a second gate insulating layer, a second gate electrode, a third electrode and a fourth electrode, the protective layer being disposed on the side of the buffer layer away from the substrate, the second active layer being disposed on the side of the protective layer away from the substrate, the second gate insulating layer being disposed on the side of the second active layer away from the substrate, the second gate electrode being disposed on the side of the second gate insulating layer away from the substrate, the interlayer dielectric layer covering the second gate electrode, the third electrode and the fourth electrode being disposed on the side of the interlayer dielectric layer away from the substrate.

[0028] The display panel further comprises a peripheral trace in the gate driving circuit region, the peripheral trace being located on the side of the second thin film transistor away from the substrate, and the peripheral trace being electrically connected to the second thin film transistor.

[0029] Optionally, in some embodiments of the present application, the display panel further comprises a first planar layer and a second planar layer sequentially covering the first thin film transistor and the capacitor, and the anode is disposed on the side of the second planar layer away from the substrate.

[0030] Correspondingly, the present application further provides a display device comprising the display panel as described in any one of the above embodiments.

[0031] The display panel and the display device provided by the embodiments of the present application comprise a first thin film transistor and a capacitor located in a pixel opening area, the capacitor comprises at least three plates which are stacked and arranged at intervals, and the difference between the height of the first thin film transistor and the height of the capacitor is less than 4500 angstroms, based on the side of the substrate close to the anode. By arranging at least three plates, the present application not only increases the capacitance but also raises the ground level of the capacitor area, so that the topography of the first thin film transistor and the capacitor is similar, and the flatness of the pixel opening area is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 FIG. 1 is a structural schematic diagram of a display panel provided by the embodiments of the present application;

[0033] Figure 2 FIG. 2 is a partial top view schematic diagram of the display panel provided by the embodiments of the present application;

[0034] Figure 3 FIG. 3 is a plan view schematic diagram of the film layer where the light shielding part and the first plate are located in FIG. 1; Figure 2

[0035] FIG. 4 is a plan view schematic diagram of the film layer where the first active part and the second plate are located in FIG. 1; Figure 4 Figure 3 FIG. 5 is a plan view schematic diagram of the film layer where the first gate is located in FIG. 1;

[0036] Figure 5 Figure 4 FIG. 6 is a plan view schematic diagram of the film layer where the third plate is located in FIG. 1;

[0037] Figure 6 FIG. 7 is a plan view schematic diagram of the film layer where the first electrode, the second electrode and the switching part are located in FIG. 1; Figure 5

[0038] FIG. 8 is another structural schematic diagram of the display panel provided by the embodiments of the present application; Figure 7 Figure 6 FIG. 9 is still another structural schematic diagram of the display panel provided by the embodiments of the present application;

[0039] Figure 8 FIG. 10 is yet another structural schematic diagram of the display panel provided by the embodiments of the present application;

[0040] Figure 9 FIG. 11 is a structural schematic diagram of a display device provided by the embodiments of the present application.

[0041] Figure 10

[0042] Figure 11 DETAILED DESCRIPTION

[0043] ​​​​​The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the embodiments can be combined with each other but will not be described one by one, and the positional words such as "upper" and "lower" are generally used to refer to the upper and lower of the device in the actual use or working state, and the specific is the direction of the drawing surface in the drawings; and "inner" and "outer" are used in relation to the outline of the device; the words "first", "second", "third" and the like are only used as labels, and do not impose a numerical requirement or establish an order.

[0044] The present application provides a display panel and a display device, which are described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0045] Please refer to Figure 1 and Figure 2 The present application provides a display panel 100, which comprises a substrate 101, a first thin film transistor t1, a capacitor c1, an anode 201 and a pixel definition layer 202.

[0046] The first thin film transistor t1 is arranged on the substrate 101. The capacitor c1 is arranged on the substrate 101 and located on one side of the first thin film transistor t1. The anode 201 is arranged on the side of the first thin film transistor t1 and the capacitor c1 away from the substrate 101. The pixel definition layer 202 is arranged on the side of the anode 201 away from the substrate 101, and the pixel definition layer 202 is provided with a pixel opening 2a which exposes the anode 201.

[0047] The first thin film transistor t1 and the capacitor c1 partially overlap the anode 201 respectively. The capacitor c1 comprises at least three stacked and spaced apart plates. Taking the side of the substrate 101 close to the anode 201 as a reference, the difference gd between the height of the first thin film transistor t1 and the height of the capacitor c1 is less than 4500 angstroms.

[0048] The display panel 100 of the present application comprises the first thin film transistor t1 and the capacitor c1 in the pixel opening 2a region. By arranging at least three plates, the present application not only improves the capacitance but also raises the ground level of the capacitor c1 region, so that the topographic difference between the first thin film transistor t1 and the capacitor c1 is below 4500 angstroms, and the two are close to each other, thereby improving the flatness of the pixel opening 2a region.

[0049] It can be understood that, in the thickness direction of the display panel 100, the difference gd between the height of the first thin film transistor t1 and the height of the capacitor c1 is less than 4500 angstroms, such as the height difference between the two is 4400 angstroms, 4300 angstroms, 4200 angstroms, 4100 angstroms, 4000 angstroms, 3900 angstroms, 3800 angstroms, 3700 angstroms, 3600 angstroms, 3500 angstroms, 3400 angstroms, 3300 angstroms, 3200 angstroms, 3100 angstroms, 3000 angstroms, 2900 angstroms, 2800 angstroms, 2700 angstroms, 2600 angstroms, 2500 angstroms, 2400 angstroms, 2300 angstroms, 2200 angstroms, 2100 angstroms, 2000 angstroms, 1900 angstroms, 1800 angstroms, 1700 angstroms, 1600 angstroms, 1500 angstroms, 1400 angstroms, 1300 angstroms, 1200 angstroms, 1100 angstroms, 1000 angstroms, 900 angstroms, 800 angstroms, 700 angstroms, 600 angstroms, 500 angstroms, 400 angstroms, 300 angstroms, 200 angstroms, 100 angstroms, 90 angstroms, 80 angstroms, 70 angstroms, 60 angstroms, 50 angstroms, 40 angstroms, 30 angstroms, 20 angstroms, 10 angstroms or 0 angstroms.

[0050] It can be understood that the more the number of plates of the capacitor c1 has, the higher the terrain of the capacitor c1 is, which is closer to the height of the first thin film transistor t1, so that the flatness of the pixel opening 2a region is higher.

[0051] The first thin film transistor t1 is a driving thin film transistor and is located in the display area, and the first thin film transistor t1 is connected to the anode 201.

[0052] Optionally, the display panel 100 further comprises a light-emitting functional layer disposed on the anode 201. The light-emitting functional layer is formed by a plurality of layers including one or more of an emitting layer, a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer. In the case where the light-emitting functional layer includes all the above layers, the hole injection layer can be disposed on the anode 201, and the hole transport layer, the emitting layer, the electron transport layer and the electron injection layer can be sequentially laminated on the hole injection layer.

[0053] Optionally, in some embodiments of the present application, the display panel 100 further comprises a light shielding portion 102, a buffer layer 103 and an interlayer dielectric layer 109. The first thin film transistor t1 comprises a first active portion 104, a first gate insulating portion 105, a first gate electrode 106, a first electrode 107 and a second electrode 108. The capacitor c1 comprises a first plate c01, a second plate c02 and a third plate c03.

[0054] The first electrode plate c01 is arranged in the same layer as the light shielding part 102. The buffer layer 103 covers the first electrode plate c01 and the light shielding part 102. The second electrode plate c02 is arranged in the same layer as the first active part 104. The first gate insulating part 105 is arranged on the side of the first active part 104 away from the substrate 101. The first gate electrode 106 is arranged on the side of the first gate insulating part 105 away from the substrate 101. The interlayer dielectric layer 109 covers the first gate electrode 106 and the capacitor c1. The first electrode 107 and the second electrode 108 are arranged on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0055] In the thickness direction of the display panel 100, the third electrode plate c03 is located on the side of the first electrode plate c01, and the one of the first electrode plate c01 and the second electrode plate c02 that is farther away from the third electrode plate c03 is electrically connected to the third electrode plate c03.

[0056] It can be understood that the thickness of the conductive film layer of the first thin film transistor t1 is large, so the conductive film layer has a large influence on the topography of the first thin film transistor t1. Based on this, the first electrode plate c01 is arranged in the same layer as the light shielding part 102, and the second electrode plate c02 is arranged in the same layer as the first active part 104, so as to offset the topography difference of the two conductive film layers. Secondly, the capacitor c1 is provided with the third electrode plate c03 to offset the topography difference of the first gate electrode 106 of the first thin film transistor t1, thereby reducing the topography height difference between the first thin film transistor t1 and the capacitor c1, and improving the flatness.

[0057] Optionally, in some embodiments of the present application, the display panel 100 further comprises a first planar layer 111 and a second planar layer 112 covering the first thin film transistor t1 and the capacitor c1 in sequence, and the anode 201 is arranged on the side of the second planar layer 112 away from the substrate 101.

[0058] It can be understood that the planar layer has a certain flow leveling property. Based on the process limitation of the existing equipment, there is an upper limit for the flow leveling of the topography of a planar layer. Therefore, based on the topography height difference between the first thin film transistor t1 and the capacitor c1 being less than 4500 angstroms, the embodiments of the present application compensate for the topography height difference between the first thin film transistor t1 and the capacitor c1 by arranging the first planar layer 111 and the second planar layer 112, improve the flatness of the pixel opening 2a region, and further improve the flatness of the anode 201.

[0059] Optionally, in some embodiments, based on the topography height difference gd between the first thin film transistor t1 and the capacitor c1 being less than or equal to 2600 angstroms, the embodiments of the present application completely flow level the topography height difference between the first thin film transistor t1 and the capacitor c1 by arranging the first planar layer 111 and the second planar layer 112, improve the flatness of the pixel opening 2a region, and further improve the flatness of the anode 201.

[0060] In some embodiments, the display panel 100 further comprises a third planar layer 113 disposed on a side of the second planar layer 112 away from the substrate 101. It can be understood that, in the pixel opening 2a region, in addition to the topography of the first thin film transistor t1 and the capacitor c1, a topography formed by an inorganic insulating layer stack is also disposed, wherein the inorganic stack topography formed by the inorganic insulating layer stack is lower than the topography of the first thin film transistor t1, so that the first planar layer 111 and the second planar layer 112 cannot completely compensate for the height difference between the first thin film transistor t1 and the inorganic stack topography, and therefore the third planar layer 113 is disposed to further compensate for the height difference between the first thin film transistor t1 and the inorganic stack topography, to improve the flatness of the pixel opening 2a region, and further improve the flatness of the anode 201.

[0061] Optionally, the inorganic stack topography comprises the buffer layer 103 and the interlayer dielectric layer 109.

[0062] Optionally, in some embodiments of the present application, the display panel 100 further comprises a first insulating layer 114 and a switching portion 115. The first insulating layer 114 covers the first gate 106 and the second plate c02. The third plate c03 is disposed on a side of the first insulating layer 114 away from the substrate 101. The interlayer dielectric layer 109 covers the first insulating layer 114 and the third plate c03, the switching portion 115, the first electrode 107 and the second electrode 108 are disposed in the same layer, and the switching portion 115 connects the first plate c01 and the third plate c03.

[0063] It can be understood that the third plate c03 is disposed on a side of the second plate c02 away from the substrate 101, so that the switching portion 115 is closer to the third plate c03, to reduce the depth of the via.

[0064] Optionally, the switching portion 115 connects the third plate c03 through a first via g1, and the second electrode 108 connects the first active portion 104 through another first via g1. The switching portion 115 connects the first plate c01 through a second via g2.

[0065] Optionally, the thickness of the first gate 106 is equal to the thickness of the third plate c03, the thickness of the first active portion 104 is equal to the thickness of the second plate c02, and the thickness of the light shielding portion 102 is equal to the thickness of the first plate c01, but is not limited thereto. For example, the thickness of the first gate 106 can be less than the thickness of the third plate c03, the thickness of the first active portion 104 can be equal to the thickness of the second plate c02, and the thickness of the light shielding portion 102 can be equal to the thickness of the first plate c01, to further reduce the height difference between the topography of the first thin film transistor t1 and the capacitor c1.

[0066] Optionally, in some embodiments, the light shielding portion 102 and the first plate c01 are formed by the same photomask, and the second plate c02 and the first active portion 104 are formed by the same photomask.

[0067] Optionally, please refer to Figures 2 to 7 In some embodiments of the present application, in the display panel 100 viewed from above, the light shielding portion 102 is connected with the first plate c01, and the second plate c02 is arranged in a spaced manner with the first active portion 104. The second plate c02 includes a first sub-portion c21 and a second sub-portion c22 connected with each other. The first sub-portion c21 extends along a first direction F1, and the second sub-portion c22 extends along a second direction F2 intersecting the first direction F1. The first sub-portion c21 is located on one side of the first active portion 104 in the second direction F2, and the second sub-portion c22 is located on one side of the first active portion 104 in the first direction F1. The first sub-portion c21 and the second sub-portion c22 are both arranged in an overlapping manner with the first plate c01.

[0068] Optionally, the first direction F1 is perpendicular to the second direction F2, but is not limited thereto, for example, the first direction F1 and the second direction F2 are non-perpendicularly intersected. Optionally, the second direction F2 is the extension direction of the data line d1.

[0069] It can be understood that the light shielding portion 102 and the first plate c01 are connected to form an integral whole, which not only reduces the preparation difficulty, but also equivalently increases the layout area of the first plate c01.

[0070] Secondly, the first sub-portion c21 and the second sub-portion c22 are connected to form a shape of semi-surrounding the first active portion 104, so that the overlapping area of the second plate c02 and the first plate c01 is increased in the limited space, thereby increasing the capacitance of the capacitor c1 and the area of the pixel opening 2a region, and better providing the flatness of the pixel opening 2a region.

[0071] Optionally, in some embodiments of the present application, in the display panel 100 viewed from above, the third plate c03 includes a third sub-portion c33 and a fourth sub-portion c34 connected with each other, the third sub-portion c33 extends along the first direction F1, and the fourth sub-portion c34 extends along the second direction F2 intersecting the first direction F1. The third sub-portion c33 overlaps the first sub-portion c21, and the fourth sub-portion c34 overlaps the second sub-portion c22.

[0072] It can be understood that the third sub-portion c33 of the third plate c03 overlaps the first sub-portion c21, and the fourth sub-portion c34 of the third plate c03 overlaps the second sub-portion c22, so that the overlapping area of the second plate c02 and the third plate c03 is increased in the limited space, thereby increasing the capacitance of the capacitor c1 and the area of the pixel opening 2a region, and better providing the flatness of the pixel opening 2a region.

[0073] Optionally, in some embodiments of the present application, in the display panel 100 viewed from above, the adapter 115 covers part of the fourth sub-section c34 and at least part of the third sub-section c33. The adapter 115 is connected to the second electrode 108.

[0074] It can be understood that the adapter 115 covers part of the third plate c03, which can reduce the influence of the signal line on the side of the capacitor c1 away from the substrate 101 on the capacitor c1. Secondly, the adapter 115 covers the third plate c03 to increase the topography of the capacitor c1 region, thereby reducing the height difference between the first thin film transistor t1 region and the capacitor c1, and improving the flatness.

[0075] Optionally, in some embodiments of the present application, the adapter 115 partially extends beyond the third plate c03 and the second plate c02. The extended part 15a of the adapter 115 is connected to the second electrode 108. The extended part 15a of the adapter 115 is connected to the second electrode 108 to form a compensation plate c04, and the compensation plate c04 and the light shielding part 102 are partially overlapped to form a compensation capacitor.

[0076] It can be understood that the compensation plate c04 and the light shielding part 102 form a compensation capacitor, which not only increases the capacitance of the capacitor c1, but also increases the area of the pixel opening 2a region to better provide the flatness of the pixel opening 2a region.

[0077] Optionally, in some embodiments of the present application, the second plate c02 further comprises a first protrusion c23 connected to the intersection of the first sub-section c21 and the second sub-section c22 and close to the first active section 104, and the first protrusion c23 is overlapped with the first plate c01. The third plate c03 further comprises a second protrusion c35 connected to the intersection of the third sub-section c33 and the fourth sub-section c34 and close to the first active section 104, and the second protrusion c35 is overlapped with the first protrusion c23.

[0078] It can be understood that the first protrusion c23 and the second protrusion c35 are arranged, which not only increases the capacitance of the capacitor c1, but also increases the area of the pixel opening 2a region to better provide the flatness of the pixel opening 2a region.

[0079] Optionally, in some embodiments, the display panel 100 further comprises a connecting part 116 arranged in the same layer as the adapter 115 and spaced apart. The connecting part 116 connects the first gate 106 and the second plate c02 through the third via hole g3.

[0080] Optionally, in some embodiments of the present application, the display panel 100 further comprises a second thin film transistor t2 in the gate driving circuit region, the second thin film transistor t2 comprising a second active layer 121, a second gate insulating layer 122, a second gate electrode 123, a third electrode 124 and a fourth electrode 125. The second active layer 121 is disposed on the side of the buffer layer 103 away from the substrate 101. The second gate insulating layer 122 is disposed on the side of the second active layer 121 away from the substrate 101. The second gate electrode 123 is disposed on the side of the second gate insulating layer 122 away from the substrate 101. The first insulating layer 114 and the interlayer dielectric layer 109 are sequentially disposed on the second gate electrode 123. The third electrode 124 and the fourth electrode 125 are disposed on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0081] Optionally, the second active layer 121 and the first active layer 104 are disposed in the same layer and are manufactured by using the same mask. The second gate insulating layer 122 and the first gate insulating layer 105 are disposed in the same layer and are manufactured by using the same mask. The second gate electrode 123 and the first gate electrode 106 are disposed in the same layer and are manufactured by using the same mask. The third electrode 124, the fourth electrode 125, the first electrode 107 and the second electrode 108 are disposed in the same layer and are manufactured by using the same mask.

[0082] The display panel 100 further comprises a peripheral wire 131 in the gate driving circuit region. The peripheral wire 131 is disposed on the side of the second thin film transistor t2 away from the substrate 101. The peripheral wire 131 is electrically connected to the second thin film transistor t2.

[0083] Optionally, the display panel 100 further comprises a passivation layer 110 covering the first electrode 107, the second electrode 108, the third electrode 124 and the fourth electrode 125, and the first planarization layer 111 covers the passivation layer 110. The peripheral wire 131 is disposed on the side of the first planarization layer 111 away from the substrate 101. The second planarization layer 112 covers the peripheral wire 131 and the first planarization layer 111.

[0084] Optionally, the peripheral wire 131 is arranged in the gate driving circuit region to reduce the width of the frame. One peripheral wire 131 is connected to the second gate electrode 123, and another peripheral wire 131 is connected to the fourth electrode 125.

[0085] Optionally, the peripheral wire 131 connected to the second gate electrode 123 is a clock signal line, and the peripheral wire connected to the fourth electrode 125 is a power supply line or a reset signal line.

[0086] Optionally, the display panel 100 further comprises a wire changing part 132 in the display region, the wire changing part 132 and the peripheral wire 131 are disposed in the same layer on the side of the first planarization layer 111 away from the substrate 101. The second electrode 108 of the first thin film transistor t1 is connected to the anode 201 through the wire changing part 132.

[0087] Figure 8 Another structural schematic diagram of the display panel 100 of the embodiment of the present application is shown. In Figure 8 Different parts from the above-mentioned embodiments will be described in the following to avoid redundancy.

[0088] In Figure 8 In some embodiments of the present application, the first gate insulating part 105 comprises a first sub-layer 051 and a second sub-layer 052 which are stacked.

[0089] The display panel 100 further comprises a second thin film transistor t2 in the gate driving circuit area, which comprises a protection part 120, a second active part 121, a second gate insulating part 122, a second gate electrode 123, a third electrode 124 and a fourth electrode 125. The protection part 120 is disposed on the side of the buffer layer 103 away from the substrate 101. The second active part 121 is disposed on the side of the protection part 120 away from the substrate 101, the second gate insulating part 122 is disposed on the side of the second active part 121 away from the substrate 101, the second gate electrode 123 is disposed on the side of the second gate insulating part 122 away from the substrate 101, the first insulating layer 114 and the interlayer dielectric layer 109 are sequentially arranged on the second gate electrode 123, and the third electrode 124 and the fourth electrode 125 are disposed on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0090] It should be noted that, Figure 8 The display panel 100 of the corresponding embodiment is different from the above-mentioned embodiments in that the first gate insulating part 105 comprises a first sub-layer 051 and a second sub-layer 052 which are stacked, and the second thin film transistor t2 further comprises a protection part 120. The carrier mobility of the first thin film transistor t1 is less than that of the second thin film transistor t2.

[0091] Optionally, the first sub-layer 051 and the protection part 120 are formed by the same photomask process, and have the same material and thickness. The second sub-layer 052 and the second gate insulating part 122 are formed by the same photomask process, and have the same material and thickness.

[0092] In this embodiment of the present application, Figure 8 The planar layout structure of the display panel 100 of the corresponding embodiment is similar or identical to that of the display panel 100 of the above-mentioned embodiments, and specific details can be referred to Figures 2 to 7 , which will not be described here.

[0093] Figure 9 Another structural schematic diagram of the display panel 100 of the embodiment of the present application is shown. In Figure 9 Different parts from the above-mentioned embodiments will be described in the following to avoid redundancy.

[0094] InFigure 9 In some embodiments of the present application, the display panel 100 further comprises a first insulating layer 114 and a transition part 115. The third plate c03 is arranged on the side of the first plate c01 close to the substrate 101. The first insulating layer 114 covers the third plate c03 and the substrate 101. The buffer layer 103 covers the first insulating layer 114. The transition part 115 is arranged on the side of the interlayer dielectric layer 109 away from the substrate 101 in the same layer as the first electrode 107. The transition part 115 connects the second plate c02 and the third plate c03.

[0095] Optionally, the transition part 115 connects the second plate c02 through the first via g1, and the transition part 115 connects the third plate c03 through the second via g2.

[0096] Compared with the display panel 100 of each of the above embodiments, Figure 9 The display panel 100 of the corresponding embodiment arranges the third plate c03 on the side of the first plate c01 close to the substrate 101, so as to save the wiring space above and facilitate wiring. That is, the film layer in which the third plate c03 is arranged is transferred to the side of the film layer in which the light shielding part 102 is arranged close to the substrate 101. Figure 1

[0097] Optionally, in some embodiments of the present application, the display panel 100 further comprises a second thin film transistor t2 in the gate driving circuit area. The second thin film transistor t2 comprises a second active part 121, a second gate insulating part 122, a second gate 123, a third electrode 124 and a fourth electrode 125. The second active part 121 is arranged on the side of the buffer layer 103 away from the substrate 101. The second gate insulating part 122 is arranged on the side of the second active part 121 away from the substrate 101. The second gate 123 is arranged on the side of the second gate insulating part 122 away from the substrate 101. The interlayer dielectric layer 109 covers the second gate 123, the third electrode 124 and the fourth electrode 125 in sequence, and the third electrode 124 and the fourth electrode 125 are arranged on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0098] Optionally, the second active part 121, the second plate c02 and the first active part 104 are arranged in the same layer and manufactured by the same mask. The second gate insulating part 122 and the first gate insulating part 105 are arranged in the same layer and manufactured by the same mask. The second gate 123 and the first gate 106 are arranged in the same layer and manufactured by the same mask. The third electrode 124, the fourth electrode 125, the first electrode 107 and the second electrode 108 are arranged in the same layer and manufactured by the same mask.

[0099] The display panel 100 further comprises a peripheral wiring 131 in the gate driving circuit area. The peripheral wiring 131 is arranged on the side of the second thin film transistor t2 away from the substrate 101, and the peripheral wiring 131 is electrically connected to the second thin film transistor t2.​

[0100] The outer peripheral traces 131 are arranged in the gate driving circuit region to reduce the frame width. One outer peripheral trace 131 is connected to the second gate 123, and another outer peripheral trace 131 is connected to the fourth electrode 125. Optionally, the outer peripheral trace 131 connected to the second gate 123 is a clock signal line, and the outer peripheral trace connected to the fourth electrode 125 is a power supply line or a reset signal line.

[0101] Optionally, the third plate c03 is a black plate to improve the effect of integral black.

[0102] It should be noted that, Figure 9 The planar structures of the light shielding portion 102, the first plate c01, the second plate c02, the third plate c03, and the adapter portion 115 in the corresponding embodiment are similar or identical to those of the display panel 100 in the above-mentioned embodiments. The difference is that the first plate c01 is spaced between the third plate c03 and the second plate c02, and the third plate c03 and the second plate c02 overlap the first plate c01 to form a capacitor c1. Secondly, the adapter portion 115 connects the second plate c02 and the third plate c03. Since the third plate c03 is below the first plate c01, compared with the above-mentioned embodiments, Figure 9 In the corresponding embodiment, the third plate c03 further extends a contact portion beyond the first plate c01, and the contact portion is connected to the adapter portion 115. The first plate c01 is electrically connected to the first gate 106.

[0103] Figure 10 Another structure schematic diagram of the display panel 100 of the embodiment of the present application is shown. Figure 10 In the following, the parts different from those of the above-mentioned embodiments will be described to avoid redundancy.

[0104] In the following, Figure 10 In some embodiments of the present application, the first gate insulating portion 105 includes a first sub-layer 051 and a second sub-layer 052 arranged in a stack.

[0105] The display panel 100 further comprises a second thin film transistor t2 located in the gate driving circuit region, the second thin film transistor t2 comprising a protection portion 120, a second active portion 121, a second gate insulating portion 122, a second gate electrode 123, a third electrode 124 and a fourth electrode 125. The protection portion 120 is disposed on the side of the buffer layer 103 away from the substrate 101. The second active portion 121 is disposed on the side of the protection portion 120 away from the substrate 101. The second gate insulating portion 122 is disposed on the side of the second active portion 121 away from the substrate 101. The second gate electrode 123 is disposed on the side of the second gate insulating portion 122 away from the substrate 101, the interlayer dielectric layer 109 covers the second gate electrode 123, and the third electrode 124 and the fourth electrode 125 are disposed on the side of the interlayer dielectric layer 109 away from the substrate 101.

[0106] Optionally, the first sub-layer 051 and the protection portion 120 are formed by the same photomask process, and the materials and thicknesses of the first sub-layer 051 and the protection portion 120 are the same. The second sub-layer 152 and the second gate insulating portion 122 are formed by the same photomask process, and the materials and thicknesses of the second sub-layer 152 and the second gate insulating portion 122 are the same.

[0107] The display panel 100 further comprises a peripheral trace 131 located in the gate driving circuit region, the peripheral trace 131 being located on the side of the second thin film transistor t2 away from the substrate 101, and the peripheral trace 131 being electrically connected to the second thin film transistor t2.

[0108] Please refer to Figure 11 Correspondingly, the application further provides a display device 1000 comprising the display panel 100 according to any one of the above embodiments.

[0109] The display device 1000 according to the embodiments of the application comprises the first thin film transistor t1 and the capacitor c1 located in the pixel opening 2a region, and the capacitor c1 comprises at least three plates which are stacked and spaced apart. With the side of the substrate 101 close to the anode 201 as the reference, the difference between the height of the first thin film transistor t1 and the height of the capacitor c1 is less than 4500 angstroms. By arranging at least three plates, the application not only increases the capacitance but also raises the ground level of the capacitor c1 region, so that the topography of the first thin film transistor t1 and the capacitor c1 is similar, and the flatness of the pixel opening 2a region is improved.

[0110] It should be noted that the structure of the display panel 100 of the display device 1000 according to the embodiments of the application is similar or identical to the structure of the display panel 100 according to the above embodiments, and the specific structure can be referred to the description of Figures 1 to 10 Therefore, the description is not repeated here.

[0111] The display panel and the display device provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application. In conclusion, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A display panel, characterized in that, include: substrate; A first thin-film transistor is disposed on the substrate; A capacitor is disposed on the substrate and located on one side of the first thin-film transistor; The anode is disposed on the side of the first thin-film transistor and the capacitor away from the substrate; as well as A pixel definition layer is disposed on the side of the anode away from the substrate, and the pixel definition layer has pixel openings that expose the anode; Wherein, the first thin-film transistor and the capacitor respectively partially overlap with the anode, the capacitor includes at least three stacked and spaced plates, and with the side of the substrate closest to the anode as a reference, the difference between the height of the first thin-film transistor and the height of the capacitor is less than 4500 angstroms; The first thin-film transistor includes a first active portion, and the capacitor includes a first electrode plate, a second electrode plate, and a third electrode plate. In the thickness direction of the display panel, the first electrode plate, the second electrode plate, and the third electrode plate are disposed in pairs in different layers. The third electrode plate is located on one side of the first electrode plate, and the one of the first electrode plate and the second electrode plate that is farther away from the third electrode plate is electrically connected to the third electrode plate. In the display panel viewed from above, the second electrode plate is spaced apart from the first active portion. The second electrode plate includes a first sub-portion and a second sub-portion connected together. The first sub-portion extends along a first direction, and the second sub-portion extends along a second direction intersecting the first direction. The first sub-portion is located on the side of the first active portion in the second direction, and the second sub-portion is located on the side of the first active portion in the first direction. Both the first sub-portion and the second sub-portion overlap with the first electrode plate.

2. The display panel according to claim 1, characterized in that, The display panel further includes a light-shielding portion, a buffer layer, and an interlayer dielectric layer; the first thin-film transistor includes a first gate insulating portion, a first gate, a first electrode, and a second electrode. The first electrode plate is disposed in the same layer as the light-shielding part, the buffer layer covers the first electrode plate and the light-shielding part, the second electrode plate is disposed in the same layer as the first active part, the first gate insulating part is disposed on the side of the first active part away from the substrate, the first gate is disposed on the side of the first gate insulating part away from the substrate, the interlayer dielectric layer covers the first gate and the capacitor, and the first electrode and the second electrode are disposed on the side of the interlayer dielectric layer away from the substrate.

3. The display panel according to claim 2, characterized in that, The display panel further includes a first insulating layer and a transition portion. The first insulating layer covers the first gate and the second electrode plate. The third electrode plate is disposed on the side of the first insulating layer away from the substrate. The interlayer dielectric layer covers the first insulating layer and the third electrode plate. The transition portion, the first electrode, and the second electrode are disposed in different layers. The transition portion connects the first electrode plate and the third electrode plate.

4. The display panel according to claim 3, characterized in that, In the display panel viewed from above, the third electrode plate includes a third sub-part and a fourth sub-part connected together. The third sub-part extends along a first direction, and the fourth sub-part extends along a second direction intersecting the first direction. The third sub-part overlaps with the first sub-part, and the fourth sub-part overlaps with the second sub-part.

5. The display panel according to claim 4, characterized in that, In the display panel viewed from above, the light-shielding portion is connected to the first electrode plate, and the second electrode plate further includes a first protrusion connecting the intersection of the first sub-part and the second sub-part and close to the first active part. The first protrusion overlaps with the first electrode plate. The third electrode plate further includes a second protrusion connecting the intersection of the third sub-part and the fourth sub-part and close to the first active part. The second protrusion overlaps with the first protrusion.

6. The display panel according to claim 5, characterized in that, In the display panel viewed from above, the adapter covers a portion of the fourth sub-section and at least a portion of the third sub-section, and the adapter is connected to the second electrode.

7. The display panel according to claim 3, characterized in that, The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The second active portion is disposed on the side of the buffer layer away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The first insulating layer and the interlayer dielectric layer sequentially cover the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

8. The display panel according to claim 3, characterized in that, The first gate insulation portion includes a first sublayer and a second sublayer stacked together; The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a protective portion, a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The protective portion is disposed on the side of the buffer layer away from the substrate. The second active portion is disposed on the side of the protective portion away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The first insulating layer and the interlayer dielectric layer sequentially cover the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

9. The display panel according to claim 2, characterized in that, The display panel further includes a first insulating layer and a connecting portion. The third electrode plate is disposed on the side of the first electrode plate close to the substrate. The first insulating layer covers the third electrode plate and the substrate. The buffer layer covers the first insulating layer. The connecting portion is disposed on the side of the interlayer dielectric layer away from the substrate, in the same layer as the first electrode. The connecting portion connects the second electrode plate and the third electrode plate.

10. The display panel according to claim 9, characterized in that, The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The second active portion is disposed on the side of the buffer layer away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The interlayer dielectric layer sequentially covers the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

11. The display panel according to claim 9, characterized in that, The first gate insulation portion includes a first sublayer and a second sublayer stacked together; The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a protective portion, a second active portion, a second gate insulating portion, a second gate, a third electrode, and a fourth electrode. The protective portion is disposed on the side of the buffer layer away from the substrate. The second active portion is disposed on the side of the protective portion away from the substrate. The second gate insulating portion is disposed on the side of the second active portion away from the substrate. The second gate is disposed on the side of the second gate insulating portion away from the substrate. The interlayer dielectric layer covers the second gate. The third electrode and the fourth electrode are disposed on the side of the interlayer dielectric layer away from the substrate. The display panel also includes peripheral traces located in the gate drive circuit area. The peripheral traces are located on the side of the second thin-film transistor away from the substrate, and the peripheral traces are electrically connected to the second thin-film transistor.

12. The display panel according to any one of claims 1-11, characterized in that, The display panel further includes a first planarization layer and a second planarization layer that sequentially cover the first thin-film transistor and the capacitor, with the anode disposed on the side of the second planarization layer away from the substrate.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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