Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes: a selector pattern configured to exhibit different electrical conductivity characteristics with respect to a threshold voltage in response to an applied voltage; an interlayer insulating layer surrounding a sidewall of the selector pattern and having an opening disposed over the selector pattern; and an electrode disposed in the opening and having a maximum width at an uppermost portion of the opening, and wherein the uppermost portion of the opening has a rounded edge in a cross-sectional view.

Description

[0001] Priority claims and cross-references to related applications

[0002] This patent document claims priority to Korean Patent Application No. 10-2023-0135099, filed on October 11, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present patent document relates to semiconductor technology, and more particularly to a semiconductor device including a selector and a method for manufacturing the semiconductor device. Background Art

[0004] Recently, as electronic devices tend to be miniaturized, low-power, high-performance, multifunctional, etc., semiconductor devices capable of storing information in various electronic devices such as computers, portable communication devices, etc. have been required in the art, and semiconductor devices have been studied. Such semiconductor devices include semiconductor devices capable of storing data using a characteristic of switching between different resistance states according to an applied voltage or current, such as RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), E-fuse, etc. Summary of the invention

[0005] In an embodiment, a semiconductor device may include: a selector pattern configured to exhibit different electrical conduction characteristics relative to a threshold voltage in response to an applied voltage; an interlayer insulating layer surrounding a sidewall of the selector pattern and having an opening disposed above the selector pattern; and an electrode disposed in the opening and having a maximum width at an uppermost portion of the opening, and wherein the uppermost portion of the opening has a rounded edge in a cross-sectional view.

[0006] In an embodiment, a method for manufacturing a semiconductor device may include: providing a stacked structure in which a selector pattern and a sacrificial electrode are stacked on each other, wherein the selector pattern is configured to exhibit different electrical conduction characteristics relative to a threshold voltage in response to an applied voltage; forming an interlayer insulating layer around the sidewalls of the stacked structure; removing the sacrificial electrode to form an initial opening; expanding the width of the uppermost portion of the initial opening to form an opening; and forming an electrode filled in the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0008] FIG. 2A to FIG. 2F is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure.

[0009] Figure 2G is a cross-sectional view showing an example of a variable resistance pattern.

[0010] FIG. 3A to FIG. 3C is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure.

[0011] FIG. 4A to FIG. 4C is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure.

[0012] FIG. 5A to FIG. 5C is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure.

[0013] Fig. 6A and Figure 6B is a cross-sectional view illustrating a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Hereinafter, various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0015] The drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may be enlarged to clearly illustrate certain features of the described embodiments. When presenting a specific example in a drawing or description with two or more layers in a multilayer structure, the relative positioning relationship of these layers or the order of the arrangement layers shown reflects the specific implementation of the described or shown example, and different relative positioning relationships or the order of the arrangement layers are also possible. In addition, the example of the multilayer structure described or shown may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two shown layers). As a specific example, when the first layer in the multilayer structure described or shown is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0016] Figure 1 is a perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0017] Reference Figure 1, the semiconductor device of the present embodiment may include: a substrate 100; a plurality of first conductive lines 110 disposed on the substrate 100 and extending in a first direction; a plurality of second conductive lines 120 disposed on the first conductive lines 110 and extending in a second direction intersecting the first direction; and a plurality of memory cells MC disposed between the first conductive lines 110 and the second conductive lines 120 and overlapping with intersection regions of the first conductive lines 110 and the second conductive lines 120, respectively. Here, the first direction and the second direction may correspond to a horizontal direction substantially parallel to an upper surface of the substrate 100. A direction substantially perpendicular to an upper surface of the substrate 100 will hereinafter be referred to as a vertical direction.

[0018] The substrate 100 may include a semiconductor material such as silicon. In addition, a desired lower structure (not shown) may be formed in the substrate 100. For example, an integrated circuit for driving the first conductive line 110 and / or the second conductive line 120 may be formed in the substrate 100.

[0019] A plurality of first conductive lines 110 may be arranged to be spaced apart from each other in the second direction. The first conductive lines 110 may include at least one of a plurality of conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti), a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or a combination thereof, and may have a single-layer structure or a multi-layer structure.

[0020] A plurality of second conductive lines 120 may be arranged to be spaced apart from each other in the first direction. The second conductive lines 120 may include at least one of a plurality of conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti), a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or a combination thereof, and may have a single-layer structure or a multi-layer structure.

[0021] Each of the plurality of memory cells MC may include a memory unit MU as a portion that actually stores data and a selector unit SU that controls access to the memory unit MU. As an example, the memory cell MC may include a stacked structure of a lower electrode layer 130, a selector layer 140, an intermediate electrode layer 150, a variable resistance layer 160, and an upper electrode layer 170. Here, the selector unit SU may include the lower electrode layer 130, the selector layer 140, and the intermediate electrode layer 150, and the memory unit MU may include the intermediate electrode layer 150, the variable resistance layer 160, and the upper electrode layer 170. The intermediate electrode layer 150 may be shared by the selector unit SU and the memory unit MU.

[0022] The lower electrode layer 130 and the upper electrode layer 170 may be located at both ends of the memory cell MC, that is, at the bottom and the top of the memory cell MC, respectively, and may be used to transmit the voltage or current required for the operation of the memory cell MC. The intermediate electrode layer 150 may be used to physically separate and electrically connect the selector layer 140 and the variable resistance layer 160. The lower electrode layer 130, the intermediate electrode layer 150, or the upper electrode layer 170 may include at least one of a plurality of conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti), a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), or a combination thereof. Alternatively, the lower electrode layer 130, the intermediate electrode layer 150, or the upper electrode layer 170 may include a carbon electrode.

[0023] The selector layer 140 can control access to the variable resistance layer 160, and can prevent or reduce current leakage occurring between the memory cells MC sharing the first conductive line 110 or the second conductive line 120. The selector layer 140 can have a threshold switching characteristic by presenting two different electrical conduction states: a first electrical conduction state, in which the current is blocked or hardly flows in the selector layer 140 when the magnitude of the voltage supplied to the selector layer 140 is less than a predetermined threshold voltage; and a second electrical conduction state, in which the current quickly flows through the selector layer 140 when the voltage is equal to or higher than the threshold voltage. Therefore, the selector layer 140 can be turned on when it is higher than the threshold voltage, and turned off when it is lower than the threshold voltage. Since the selector layer 140 presents different electrical conduction characteristics in response to the applied voltage relative to the threshold voltage, it can be controlled by the applied voltage to select one of the two different electrical conduction states, so the selector layer 140 is used as a selector for selecting whether to select a memory cell including the selector layer 140.

[0024] The selector layer 140 may include a diode, an OTS (Ovonic Threshold Switching) material such as a chalcogenide-based material, a MIEC (Mixed Ion Electron Conducting) material such as a metal-containing chalcogenide-based material, a MIT (Metal Insulator Transition) material such as NbO2 or VO2, or a tunnel insulating material with a relatively wide bandgap such as SiO2 or Al2O3.

[0025] In some embodiments, the selector layer 140 may include an insulating material doped with a dopant. Here, the insulating material may include a silicon-containing insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, an insulating metal oxide, an insulating metal nitride, or a combination thereof. The dopant may be used to generate a trap site for capturing conductive carriers moving within the insulating material, and provide a channel for the trapped conductive carriers to move again. In order to form such a trap site, at least one of a variety of elements that can generate an energy level for accommodating conductive carriers within the insulating material may be used as a dopant. As an example, when the insulating material includes silicon, the dopant may include a metal having a different valence state from silicon, such as gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or a combination thereof. In some embodiments, when the insulating material includes a metal, the dopant may include another metal having a different valence state from the metal, or silicon. In an example, the selector layer 140 may include silicon dioxide (SiO2) doped with arsenic (As). When a voltage equal to or higher than the threshold voltage is applied to the selector layer 140, the conductive carriers move through the trap sites, thereby achieving an on-state in which current flows through the selector layer 140. When the voltage applied to the selector layer 140 is reduced to less than the threshold voltage, an off-state in which the conductive carriers do not move can be achieved.

[0026] The variable resistance layer 160 may be a part of the memory cell MC for storing data. In an example, the variable resistance layer 160 may have a variable resistance characteristic that switches between different resistance states according to a voltage applied thereto. The variable resistance layer 160 may include at least one of a variety of materials that can be used for RRAM, PRAM, FRAM, MRAM or others, for example, a metal oxide (such as a transition metal oxide or a perovskite-based material), a phase change material (such as a chalcogenide-based material), a ferroelectric material or a ferromagnetic material, and may have a single-layer structure or a multi-layer structure. In an example, the variable resistance layer 160 may include a magnetic tunnel junction structure that can store data by switching between different resistance states by changing the magnetization direction. When the variable resistance layer 160 has a high resistance state, the memory cell MC may store, for example, data "0", and when the variable resistance layer 160 has a low resistance state, the memory cell MC may store, for example, data "1". In some other embodiments, the variable resistance layer 160 may store data “1” when the variable resistance layer 160 has a high resistance state, and may store data “0” when the variable resistance layer 160 has a low resistance state.

[0027] The memory cell MC may have a pillar shape overlapping a crossing region of the first conductive line 110 and the second conductive line 120. Figure 1In the embodiment, the memory cell MC is shown to have a cylindrical shape, but the present disclosure is not limited thereto, and the memory cell MC may have at least one of a variety of shapes such as a square column shape, a rectangular column shape, or an elliptical column shape. Figure 1 , the layers 130 to 170 for forming the memory cell MC are shown as having sidewalls aligned with each other by patterning using a single mask, but the present disclosure is not limited thereto. For example, when the variable resistance layer 160 has a multilayer structure such as a magnetic tunnel junction structure, it may be difficult to use a single mask to etch the layers 130 to 170 for forming the memory cell MC together. In an example, the layers 130 to 170 may be patterned using multiple masks. For example, the selector layer 140 and the variable resistance layer 160 may be patterned separately using different masks, so they may have sidewalls that are not aligned with each other. In an example, the lower electrode layer 130 may be patterned together with the selector layer 140. In an example, the upper electrode layer 170 may be patterned together with the variable resistance layer 160. In an example, the intermediate electrode layer 150 may be patterned together with the selector layer 140 and the variable resistance layer 160.

[0028] In some embodiments, the layer structure of the memory cell MC may be modified in various ways without limitation. Figure 1 As shown in . The stacking order of the layers of the memory cell MC may be changed, one or more layers of the memory cell MC may be omitted, or one or more additional layers may be added to the memory cell MC. As an example, one or more of the lower electrode layer 130, the middle electrode layer 150, and the upper electrode layer 170 may be omitted. Alternatively, the positions of the selector layer 140 and the variable resistance layer 160 may be opposite to each other. That is, the selector layer 140 may be located above the middle electrode layer 150, and the variable resistance layer 160 may be located below the middle electrode layer 150. Alternatively, one or more layers (not shown) may be added to the memory cell MC to improve the process or characteristics of the memory cell MC.

[0029] In some embodiments, due to the difficulty of the patterning process, the diffusion of dopants when contacting the selector layer 140, etc., there are restrictions on the material and / or thickness of the intermediate electrode layer 150 located between the selector layer 140 and the variable resistance layer 160. If there are restrictions on the material and / or thickness of the intermediate electrode layer 150, it may be difficult to form an intermediate electrode layer 150 with desired characteristics (e.g., desired bandwidth and / or desired resistance). In addition, after the intermediate electrode layer 150 is formed, a process of forming an interlayer insulating layer to fill the space between the intermediate electrode layers 150 may be performed. In some embodiments, a planarization process for the insulating material may be required, such as etch-back or CMP (chemical mechanical polishing). During this planarization process, the intermediate electrode layer 150 including metal or the like may protrude above the interlayer insulating layer, and therefore, the upper surface of the intermediate electrode layer 150 and the upper surface of the interlayer insulating layer may form an uneven surface. If the variable resistance layer 160 is formed on such an uneven surface, the characteristics of the variable resistance layer 160 may be degraded. For example, when the variable resistance layer 160 includes a magnetic tunnel junction structure in which a tunnel barrier layer is inserted between two magnetic layers, various problems may occur due to the uneven surface formed by the intermediate electrode layer 150 and the interlayer insulating layer. For example, crystal growth of the magnetic layer may not occur normally over the uneven surface. In addition, for example, bending of the tunnel barrier layer may occur, which may cause defects such as Neel coupling.

[0030] Hereinafter, a semiconductor device and a method of manufacturing the same which can overcome the limitation on the intermediate electrode layer 150 and can form an interlayer insulating layer having an upper surface planarized together with an upper surface of the intermediate electrode layer 150 will be described.

[0031] FIG. 2A to FIG. 2F Detailed description of parts substantially the same as those of the above-described embodiment will be omitted.

[0032] First, the manufacturing method will be described.

[0033] Reference Figure 2A A substrate 200 having a predetermined lower structure formed therein may be provided. The substrate 200 may include at least one of a variety of circuits. For example, the substrate 200 may include a circuit similar to the above Figure 1 The first conductive wire 110 is a conductive wire.

[0034] Subsequently, a stack structure of a lower electrode 210, a selector pattern 220, and a sacrificial intermediate electrode 240 may be formed on the substrate 200. The stack structure of the lower electrode 210, the selector pattern 220, and the sacrificial intermediate electrode 240 may be formed by sequentially forming a lower electrode material, a selector material, and a sacrificial electrode material on the substrate 200 and selectively etching them. The stack structure of the lower electrode 210, the selector pattern 220, and the sacrificial intermediate electrode 240 may have a column shape. In the present embodiment, a stack structure of three lower electrodes 210, selector patterns 220, and sacrificial intermediate electrodes 240 spaced apart from each other is shown, but the present disclosure is not limited thereto, and the number or arrangement of the stack structure of the lower electrode 210, the selector pattern 220, and the sacrificial intermediate electrode 240 may be modified in various ways.

[0035] The lower electrode 210 and the selector pattern 220 may be respectively formed by Figure 1 The lower electrode layer 130 and the selector layer 140 are formed of the same material or respectively include Figure 1 The lower electrode layer 130 and the selector layer 140 are made of the same material.

[0036] The sacrificial intermediate electrode 240 may include at least one of a plurality of materials that can be easily removed in a subsequent removal process. In addition, in the example, the thickness and material of the above-mentioned sacrificial intermediate electrode 240 may adopt materials commonly used for intermediate electrodes in the art. By designing the sacrificial intermediate electrode 240 to have the thickness and material used in the art, it is possible to facilitate the etching process of forming the sacrificial intermediate electrode 240, because the thickness and material have been appropriately adjusted in consideration of the difficulty of the patterning process. In the example, the sacrificial intermediate electrode 240 may include titanium nitride. In the example, because the sacrificial intermediate electrode 240 is used as an etching barrier together with a mask pattern (not shown) used during the etching process of forming the lower electrode 210 and the selector pattern 220, the sacrificial intermediate electrode 240 may be formed to have a thickness greater than the thickness of the lower electrode 210.

[0037] The sidewall slope of the sacrificial intermediate electrode 240 may be greater than the sidewall slope of each of the lower electrode 210 and the selector pattern 220. In an example, an angle θ1 formed by the sidewall of each of the lower electrode 210 and the selector pattern 220 relative to the upper surface of the substrate 200 may be smaller than an angle θ2 formed by the sidewall of the sacrificial intermediate electrode 240 relative to the upper surface of the substrate 200. The angle θ1 may be, for example, 90 degrees, and the angle θ2 may be, for example, an obtuse angle. Therefore, the width of the sacrificial intermediate electrode 240 may increase from the top to the bottom, and the width of the uppermost portion of the sacrificial intermediate electrode 240 may be smaller than the width of the lower electrode 210 and / or the selector pattern 220. Since the thickness of the sacrificial intermediate electrode 240 is much greater than the thickness of each of the lower electrode 210 and the selector pattern 220, the sidewall slope of the sacrificial intermediate electrode 240 may be formed. In some embodiments, the sidewall slope of the sacrificial intermediate electrode 240 may be formed by adjusting a process recipe. However, the present disclosure is not limited thereto, and the sidewall slope of the sacrificial intermediate electrode 240 may be substantially the same as the sidewall slope of the lower electrode 210 and / or the selector pattern 220 .

[0038] Reference Figure 2B , the initial spacer 250 may be formed on the sidewall of the stack structure including the lower electrode 210, the selector pattern 220, and the sacrificial intermediate electrode 240. The initial spacer 250 may have the function of protecting the selector pattern 220 during the subsequent formation process of the interlayer insulating layer 260. The initial spacer 250 may be conformally formed to have a thin thickness without completely filling the space between the stack structure including the lower electrode 210, the selector pattern 220, and the sacrificial intermediate electrode 240. In an example, the initial spacer 250 may be formed along the sidewall of the stack structure including the lower electrode 210, the selector pattern 220, and the sacrificial intermediate electrode 240. For example, the initial spacer 250 may be formed by depositing an insulating material such as silicon nitride. For example, the initial spacer 250 may be omitted. In this case, the interlayer insulating layer 260 may be in direct contact with the sidewall of the stack structure including the lower electrode 210, the selector pattern 220, and the sacrificial intermediate electrode 240.

[0039] Subsequently, an interlayer insulating layer 260 may be formed to fill between the stacked structure of the lower electrode 210, the selector pattern 220, and the sacrificial intermediate electrode 240. The interlayer insulating layer 260 may include an insulating material such as silicon oxide. In addition, the interlayer insulating layer 260 may be formed by the following steps: depositing an insulating material thick enough to cover the stacked structure including the lower electrode 210, the selector pattern 220, and the sacrificial intermediate electrode 240, while fully filling the space between the stacked structures; and performing a planarization process (e.g., etching back or CMP (chemical mechanical polishing)) on the insulating material until the upper surface of the sacrificial intermediate electrode 240 is exposed. During the planarization process, the interlayer insulating layer 260 may be lowered from the upper surface of the sacrificial intermediate electrode 240 to a certain extent, and therefore, the upper end of the sacrificial intermediate electrode 240 may protrude above the interlayer insulating layer 260. During the planarization process, the preliminary spacer 250 formed of and including an insulating material may also be lowered together with the interlayer insulating layer 260 , and may have an upper surface located at substantially the same height as that of the interlayer insulating layer 260 .

[0040] Reference Figure 2C , the sacrificial intermediate electrode 240 may be removed. The sacrificial intermediate electrode 240 may be removed using an appropriate method (e.g., a wet leaching method). When the sacrificial intermediate electrode 240 includes titanium nitride, the sacrificial intermediate electrode 240 may be removed by a leaching method using hydrogen peroxide (H2O2). In this case, only the sacrificial intermediate electrode 240 may be selectively removed without causing substantial loss to the selector pattern 220, the initial spacer 250, and / or the interlayer insulating layer 260 located around the sacrificial intermediate electrode 240.

[0041] The space formed by removing the sacrificial intermediate electrode 240 will be referred to as the initial opening OP1 hereinafter. The initial opening OP1 may have a hollow shape such as a hole shape, and may have the narrowest width at the uppermost portion (which corresponds to the entrance of the interior of the initial opening OP1). The initial opening OP1 may have a width that increases from the top to the bottom. The width of the entrance of the initial opening OP1 may be smaller than the width of the lower electrode 210 and / or the width of the selector pattern 220. The upper surface of the selector pattern 220 may be exposed by forming the initial opening OP1.

[0042] Reference Figure 2D , the opening OP1 ′ may be formed by expanding the width of the upper portion of the initial opening OP1 .

[0043] The formation process of the opening OP1' may be performed using a suitable method (e.g., a wet cleaning method). When the initial spacer 250 includes silicon nitride and the interlayer insulating layer 260 includes silicon oxide, wet cleaning may be performed using HF-based chemicals. During this process, the portion of the initial spacer 250 exposed by the initial opening OP1 may be removed, and thus, a spacer 250' surrounding the sidewalls of the lower electrode 210 and the selector pattern 220 may be formed. In addition, the interlayer insulating layer 260 exposed by partially removing the initial spacer 250 may also be partially removed. Since the time that the initial opening OP1 is exposed to the chemical decreases from top to bottom, the amount of removal of the interlayer insulating layer 260 may also decrease from top to bottom. As a result, an opening OP1' having a maximum width at the top may be formed. The opening OP1' may have a width that decreases from top to bottom. In addition, due to the influence of the wet chemical, the top of the opening OP1' may have a rounded edge in a cross-sectional view.

[0044] Reference Figure 2E , an intermediate electrode 270 filling the opening OP1 ′ may be formed.

[0045] Can be done through Figure 2D A conductive material having a thickness sufficient to fill the opening OP1' is deposited on the process result of the intermediate electrode 270, and a planarization process (e.g., CMP or etch-back) is performed until the upper surface of the interlayer insulating layer 260 is exposed to form the intermediate electrode 270. The deposition of the conductive material for forming the intermediate electrode 270 may be performed using a method such as PVD (physical vapor deposition) or ALD (atomic layer deposition). In addition, the conductive material for forming the intermediate electrode 270 may include a metal such as iridium (Ir), platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti), a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), a non-metal such as polysilicon doped with impurities, or a combination thereof. The impurities may include carbon, boron, or others.

[0046] As a result of this process, the intermediate electrode 270 may be formed to have the largest width at the uppermost portion and to decrease in width from the top to the bottom. In addition, the uppermost portion of the intermediate electrode 270 may have rounded edges in a cross-sectional view.

[0047] During this process, since the opening OP1' has the largest width at the uppermost portion and the width of the opening OP1' decreases from the top to the bottom, the filling characteristics of the conductive material can be improved, which reduces and prevents the occurrence of defects such as voids formed in the intermediate electrode 270. Figure 2BUnlike the process of planarization, since the conductive material including metal or the like is planarized, the intermediate electrode 270 may have an upper surface that is substantially planarized / planarized together with the interlayer insulating layer 260. Therefore, the upper surface of the intermediate electrode 270 and the upper surface of the interlayer insulating layer 260 may be located at substantially the same height in the vertical direction. This may be because, during etch-back or CMP, the insulating material is more likely to be recessed than the metal material, while the metal material is less likely to be recessed than the insulating material. In addition, since the width of the uppermost portion of the opening OP1' is enlarged, it may be more advantageous to planarize the upper surface of the intermediate electrode 270 and the upper surface of the interlayer insulating layer 260 that fill the opening OP1'.

[0048] Reference Figure 2F , the variable resistance pattern 280 and the upper electrode 290 may be formed on Figure 2E on the process results.

[0049] The stacked structure of the variable resistance pattern 280 and the upper electrode 290 may contact the intermediate electrode 270 to be electrically connected to the intermediate electrode 270. The variable resistance pattern 280 and the upper electrode 290 may be connected to each other by Figure 2E The variable resistance pattern 280 and the upper electrode 290 are formed by depositing a material for forming the variable resistance pattern 280 and a conductive material for forming the upper electrode 290 on the process result and selectively etching them. Since the variable resistance pattern 280 and the upper electrode 290 are patterned using another mask different from the mask used to form the lower electrode 210, the selector pattern 220, and the middle electrode 270, the sidewalls of the variable resistance pattern 280 and the upper electrode 290 may not be aligned with the sidewalls of the lower electrode 210, the selector pattern 220, and the middle electrode 270.

[0050] In the present embodiment, the variable resistance pattern 280 is formed on the selector pattern 220, but the present disclosure is not limited thereto. In another embodiment, the variable resistance pattern 280 may be formed under the lower electrode 210 before forming the lower electrode 210. Therefore, the variable resistance pattern 280 may be formed under the selector pattern 220. Even in this case, the variable resistance pattern 280 may be electrically connected to the selector pattern 220 through the lower electrode 210.

[0051] In an example, the variable resistance pattern 280 may include a magnetic tunnel junction structure, which will refer to Figure 2G Give a description.

[0052] Figure 2G is a cross-sectional view showing an example of a variable resistance pattern.

[0053] Reference Figure 2G The variable resistance pattern 280 may be a magnetic tunnel junction structure, and may include a pinned layer 282 , a tunnel barrier layer 284 , and a free layer 286 .

[0054] The pinned layer 282 may be a layer having a fixed magnetization direction that can be compared with the magnetization direction of the free layer 286, and may also be referred to as a reference layer. The free layer 286 may be a layer capable of storing different data by having a variable magnetization direction, and may also be referred to as a storage layer. The tunnel barrier layer 284 may physically separate the pinned layer 282 and the free layer 286, and may enable tunnel transmission of electrons therebetween. Each of the pinned layer 282 and the free layer 286 may have a single-layer structure or a multi-layer structure including a ferromagnetic material. As an example, each of the pinned layer 282 and the free layer 286 may include an alloy containing Fe, Ni or Co as a main component, such as a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy or a Co-Fe-B alloy, or at least one of a stacked structure of Co / Pt and Co / Pd. The tunnel barrier layer 284 may have a single-layer structure or a multi-layer structure including an insulating material. As an example, the tunnel barrier layer 284 may include an insulating oxide such as MgO, CaO, SrO, TiO, VO, or NbO.

[0055] In the magnetic tunnel junction structure, the magnetization direction of the free layer 286 can be changed according to the applied voltage or current. When the magnetization direction of the free layer 286 is parallel to the magnetization direction of the pinned layer 282, the magnetic tunnel junction structure can have a low resistance state and, for example, can store data "1". On the other hand, when the magnetization direction of the free layer 286 is antiparallel to the magnetization direction of the pinned layer 282, the magnetic tunnel junction structure can have a high resistance state and, for example, can store data "0".

[0056] As long as the magnetic tunnel junction structure includes a pinned layer 282, a free layer 286, and a tunnel barrier layer 284 therebetween, the layer structure of the magnetic tunnel junction structure can be modified in a variety of ways. For example, the positions of the pinned layer 282 and the free layer 286 can be reversed with each other. In the example, although not shown, one or more layers for improving the characteristics of the magnetic tunnel junction structure can also be added to the magnetic tunnel junction structure.

[0057] It may be important for the magnetic tunnel junction structure to be formed on a flat surface (i.e., a flattened surface). This may be because, if the magnetic tunnel junction structure is not formed on a flat surface, crystal growth of the magnetic material is difficult and bending defects of the tunnel barrier layer occur, thereby deteriorating the switching characteristics of the magnetic tunnel junction structure.

[0058] Refer again Figure 2FWhen the variable resistance pattern 280 includes a magnetic tunnel junction structure, the variable resistance pattern 280 may be located on the upper surface of the intermediate electrode 270 and the upper surface of the interlayer insulating layer 260 forming a substantially flat surface. Therefore, degradation of characteristics of the variable resistance pattern 280 may be prevented and / or reduced.

[0059] A semiconductor device can be manufactured using the above-described method.

[0060] Refer again Figure 2F The semiconductor device of this embodiment may include: a substrate 200, a stack structure including a lower electrode 210, a selector pattern 220 and an intermediate electrode 270 arranged on the substrate 200, an interlayer insulating layer 260 filling the space between the stack structure of the lower electrode 210, the selector pattern 220 and the intermediate electrode 270, a spacer 250' arranged between the interlayer insulating layer 260 and the lower electrode 210 and between the interlayer insulating layer 260 and the selector pattern 220, and a variable resistance pattern 280 and an upper electrode 290 formed on the intermediate electrode 270 and the interlayer insulating layer 260.

[0061] Here, the interlayer insulating layer 260 may be in direct contact with the sidewall of the intermediate electrode 270, and the upper surface of the interlayer insulating layer 260 and the upper surface of the intermediate electrode 270 may form a flat surface. The width of the intermediate electrode 270 may be the largest at the uppermost portion, that is, at the upper surface. In addition, the intermediate electrode 270 may have a width that decreases from the top to the bottom. In a cross-sectional view, the uppermost portion of the intermediate electrode 270 may have a rounded edge.

[0062] A more detailed description of the components of the semiconductor device of the present embodiment has been described in the course of explaining the manufacturing method, and thus will be omitted here.

[0063] According to the semiconductor device and the manufacturing method thereof as described above, since the intermediate electrode 270 is formed without using an etching process, the intermediate electrode 270 may not be limited by the etching process. Therefore, various desired materials may be used as the intermediate electrode 270.

[0064] In addition, since the intermediate electrode 270 is formed in the opening OP1 ′ having the enlarged uppermost portion, filling characteristics of a conductive material used to form the intermediate electrode 270 may be improved, and thus filling defects may be reduced and / or prevented.

[0065] In addition, since the planarization process is performed on the conductive material used to form the intermediate electrode 270, a flat surface formed by the upper surface of the intermediate electrode 270 and the upper surface of the interlayer insulating layer 260 can be easily formed. Specifically, since the intermediate electrode 270 is formed in the opening OP1' having the enlarged uppermost portion, the formation of the flat surface can be more favorable. As a result, the variable resistance pattern 280 can be located on the flat surface, and therefore, the characteristics of the variable resistance pattern 280, such as the magnetic tunnel junction structure, can be ensured.

[0066] As a result, it is possible to ensure characteristics required for the memory cell and prevent and / or reduce the occurrence of defects.

[0067] FIG. 3A to FIG. 3C 2 is a cross-sectional view showing a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure. The description will focus on the differences from the above-described embodiment.

[0068] Reference Figure 3A , a stack structure of a lower electrode 310 , a selector pattern 320 , a buffer pattern 330 , and a sacrificial intermediate electrode 340 may be formed over a substrate 300 having a predetermined lower structure formed therein.

[0069] Here, when the sacrificial intermediate electrode 340 is removed later, the buffer pattern 330 may be used to protect the selector pattern 320. In an embodiment, the buffer pattern 330 may include a material having an etching rate different from that of the sacrificial intermediate electrode 340 during a wet dip-out process for removing the sacrificial intermediate electrode 340. In the present embodiment, since the buffer pattern 330 is not removed but interposed between the intermediate electrode (to be described later) and the selector pattern 320, the buffer pattern 330 may have an electrical conductivity characteristic for electrical connection between the intermediate electrode and the selector pattern 320. In addition, the buffer pattern 330 may include a material having a relatively high resistivity. For example, the buffer pattern 330 may include a material having a resistivity greater than that of a material used to form the intermediate electrode. In this case, the buffer pattern 330 may be used as a resistive layer to reduce the holding current of the selector pattern 320. As an example, the buffer pattern 330 may include amorphous carbon. However, the present disclosure is not limited thereto, and various modifications may be made to the material used to form the buffer pattern 230, as long as the buffer pattern 330 includes a material having an etching rate different from that of the selector pattern 320.

[0070] Next, an initial spacer 350 may be formed on the sidewalls of the stacked structure of the lower electrode 310, the selector pattern 320, the buffer pattern 330 and the sacrificial intermediate electrode 340, and then an interlayer insulating layer 360 may be formed to fill the space between the stacked structure of the lower electrode 310, the selector pattern 320, the buffer pattern 330 and the sacrificial intermediate electrode 340.

[0071] Reference Figure 3B , the initial opening OP2 may be formed by removing the sacrificial intermediate electrode 340. The sacrificial intermediate electrode 340 may be removed using a wet dip method. When the sacrificial intermediate electrode 340 is removed, the buffer pattern 330 may cover the upper surface of the selector pattern 320, and thus the selector pattern 320 may not be exposed to chemicals used in the wet dip process and may be protected. Therefore, when the buffer pattern 330 is used, it may be advantageous to ensure the characteristics of the selector pattern 320.

[0072] Reference Figure 3C , the opening OP2' may be formed by expanding the width of the upper portion of the initial opening OP2. The formation process of the opening OP2' may be performed using a wet cleaning method. During the wet cleaning process, the buffer pattern 330 may cover the upper surface of the selector pattern 320, so the selector pattern 320 may not be exposed to the chemicals used during the wet cleaning and may be protected. Therefore, it may be more advantageous to ensure the characteristics of the selector pattern 320.

[0073] The opening OP2' may have the largest width at the uppermost portion, and may have a shape in which the width decreases from the top to the bottom. In addition, in a cross-sectional view, the uppermost portion of the opening OP2' may have a rounded edge.

[0074] During the formation of the opening OP2 ′, a portion of the preliminary spacer 350 may be removed, and a spacer 350 ′ disposed between the sidewalls of the lower electrode 310 , the selector pattern 320 , and the buffer pattern 330 , and the interlayer insulating layer 360 may be formed.

[0075] Next, although not shown, subsequent processes, such as a formation process of an intermediate electrode filled in the opening OP2 ′, may be performed.

[0076] According to this embodiment, all the advantages of the above-described embodiments can be obtained. In addition, by forming the buffer pattern 330 to cover the selector pattern 320, there can be an advantage of protecting the selector pattern 320 during the formation of the initial opening OP2 and the formation of the opening OP2'. In addition, by adjusting the resistance of the buffer pattern 330, the characteristics of the selector pattern 320, such as the holding current, can be more accurately adjusted.

[0077] FIG. 4A to FIG. 4C 2 is a cross-sectional view showing a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure. The description will focus on the differences from the above-described embodiment.

[0078] Reference Figure 4A, a stack structure of a lower electrode 410 , a selector pattern 420 , a buffer pattern 430 , and a sacrificial intermediate electrode 440 may be formed over a substrate 400 having a predetermined lower structure formed therein.

[0079] Here, the buffer pattern 430 may be used to protect the selector pattern 420 when the sacrificial intermediate electrode 440 is removed later. To this end, the buffer pattern 430 may include a material having an etching rate different from that of the sacrificial intermediate electrode 440 during a wet immersion process for removing the sacrificial intermediate electrode 440. Since the buffer pattern 430 will be removed in the present embodiment, the buffer pattern 430 may not need to have an electrical conductive property, and at least one of a plurality of materials such as a conductive material or an insulating material may be used. The buffer pattern 430 may have a material that can be easily removed.

[0080] Next, an initial spacer 450 may be formed on the sidewalls of the stacked structure of the lower electrode 410, the selector pattern 420, the buffer pattern 430 and the sacrificial intermediate electrode 440, and then an interlayer insulating layer 460 may be formed to fill the space between the stacked structure of the lower electrode 410, the selector pattern 420, the buffer pattern 430 and the sacrificial intermediate electrode 440.

[0081] Reference Figure 4B , the sacrificial intermediate electrode 440 may be removed, and then the buffer pattern 430 exposed by removing the sacrificial intermediate electrode 440 may be removed, thereby forming an initial opening OP3. The sacrificial intermediate electrode 440 may be removed using a wet immersion method. The buffer pattern 430 may be removed by at least one of a plurality of removal methods. When the buffer pattern 430 includes carbon, the buffer pattern 430 may be removed by a stripping process including oxygen.

[0082] Reference Figure 4C , the opening OP3' may be formed by expanding the width of the upper portion of the initial opening OP3. The formation process of the opening OP3' may be performed using a wet cleaning method.

[0083] The opening OP3' may have the largest width at the uppermost portion, and may have a shape in which the width decreases from the top to the bottom. In addition, in a cross-sectional view, the uppermost portion of the opening OP3' may have a rounded edge.

[0084] During the formation of the opening OP3 ′, a portion of the preliminary spacer 450 may be removed, and a spacer 450 ′ disposed between the sidewall of the lower electrode 410 and the interlayer insulating layer 460 and between the sidewall of the selector pattern 420 and the interlayer insulating layer 460 may be formed.

[0085] According to the present embodiment, all the advantages of the above-described embodiment can be obtained. In addition, by forming the buffer pattern 430 to cover the selector pattern 420, there can be an advantage of protecting the selector pattern 420 during the removal of the sacrificial intermediate electrode 440.

[0086] FIG. 5A to FIG. 5C 2 is a cross-sectional view showing a semiconductor device and a method for manufacturing the semiconductor device according to another embodiment of the present disclosure. The description will focus on the differences from the above-described embodiment.

[0087] Reference Figure 5A A stack structure of a lower electrode 510, a selector pattern 520, an additional electrode 575, a buffer pattern 530, and a sacrificial intermediate electrode 540 may be formed over a substrate 500 having a predetermined lower structure formed therein.

[0088] Here, the additional electrode 575 may serve to protect the selector pattern 520 when the buffer pattern 530 is later removed, and may be used together with an intermediate electrode to be described later as an electrode located above the selector pattern 520. The additional electrode 575 may include substantially the same material as the intermediate electrode.

[0089] Subsequently, an initial spacer 550 may be formed on the side walls of the stacked structure of the lower electrode 510, the selector pattern 520, the additional electrode 575, the buffer pattern 530 and the sacrificial intermediate electrode 540, and then an interlayer insulating layer 560 may be formed to fill the space between the stacked structure of the lower electrode 510, the selector pattern 520, the additional electrode 575, the buffer pattern 530 and the sacrificial intermediate electrode 540.

[0090] Reference Figure 5B , the sacrificial intermediate electrode 540 may be removed, and then the buffer pattern 530 exposed by removing the sacrificial intermediate electrode 540 may be removed, thereby forming the initial opening OP4. When the buffer pattern 530 is removed, the additional electrode 575 may protect the selector pattern 520.

[0091] Reference Figure 5C , the opening OP4' may be formed by expanding the width of the upper portion of the initial opening OP4. The formation process of the opening OP4' may be performed using a wet cleaning method. During the wet cleaning process, the additional electrode 575 may protect the selector pattern 520.

[0092] The opening OP4' may have a maximum width at the uppermost portion, and may have a shape in which the width decreases from the top to the bottom. Therefore, the opening OP4' may have a tapered shape having a maximum width at the top of the opening OP4'. In addition, the uppermost portion of the opening OP4' may have a rounded edge in the cross-sectional view. The rounded edge of the uppermost portion of the opening OP4' may refer to a side having a curved shape.

[0093] During the formation of the opening OP4 ′, a portion of the preliminary spacer 550 may be removed, and a spacer 550 ′ disposed between the sidewalls of the lower electrode 510 , the selector pattern 520 , and the additional electrode 575 and the interlayer insulating layer 560 may be formed.

[0094] According to the present embodiment, the advantages of the above-described embodiments can be obtained. In addition, by forming the buffer pattern 530 to cover the selector pattern 520, there can be an advantage of protecting the selector pattern 520 during the removal of the sacrificial intermediate electrode 540. In addition, by inserting the additional electrode 575 between the buffer pattern 530 and the selector pattern 520, there can be an advantage of protecting the selector pattern 520 when the buffer pattern 530 is removed and a subsequent cleaning process is performed. Since the additional electrode 575 performs an electrode function together with the intermediate electrode, a separate removal process of the additional electrode 575 may not be required.

[0095] Fig. 6A and Figure 6B 2 is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. The description will focus on the differences from the above-described embodiment.

[0096] Reference Fig. 6A , by executing Figure 2A and Figure 2B A process basically the same as the process of the process can form a stacked structure of the lower electrode 610, the selector pattern 620 and the sacrificial intermediate electrode, a spacer 650 formed on the sidewall of the stacked structure of the lower electrode 610, the selector pattern 620 and the sacrificial intermediate electrode, and an interlayer insulating layer 660.

[0097] Next, the sacrificial intermediate electrode can be removed, but unlike the above-described embodiment, only a portion of the sacrificial intermediate electrode can be removed so that the lower portion of the sacrificial intermediate electrode can remain on the selector pattern 620. The sacrificial intermediate electrode can be partially removed by adjusting the time of the wet immersion process. The lower portion of the sacrificial intermediate electrode remaining on the selector pattern 620 will be referred to as the sacrificial intermediate electrode pattern 640' hereinafter. In addition, the space formed by forming the sacrificial intermediate electrode pattern 640' will be referred to as the initial opening OP5 hereinafter. The sacrificial intermediate electrode pattern 640' can be used to protect the selector pattern 620 during the cleaning process described later. In addition, the sacrificial intermediate electrode pattern 640' can be used together with the intermediate electrode as an electrode located above the selector pattern 620.

[0098] Reference Figure 6B, the opening OP5' may be formed by expanding the width of the upper portion of the initial opening OP5. The formation process of the opening OP5' may be performed using a wet cleaning method. During the wet cleaning process, the sacrificial intermediate electrode pattern 640' may protect the selector pattern 620.

[0099] The opening OP5' may have a maximum width at the uppermost portion, and may have a shape in which the width decreases from the top to the bottom. Therefore, the opening OP5' may have a tapered shape having a maximum width at the top of the opening OP5'. In addition, in the cross-sectional view, the uppermost portion of the opening OP5' may have a rounded edge. The rounded edge of the uppermost portion of the opening OP5' may refer to a side having a curved shape.

[0100] During the formation of the opening OP5 ′, a portion of the preliminary spacer 650 may be removed, and the spacer 650 ′ disposed between the sidewalls of the lower electrode 610 , the selector pattern 620 , and the sacrificial intermediate electrode pattern 640 ′ and the interlayer insulating layer 660 may be formed.

[0101] According to the present embodiment, the advantages of the above-described embodiments can be obtained. In addition, by forming the sacrificial intermediate electrode pattern 640' to cover the selector pattern 620, the selector pattern 620 can be protected during the cleaning process. The sacrificial intermediate electrode pattern 640' may include the same material as the intermediate electrode to be filled in the opening OP5', or may include a material different from the intermediate electrode.

[0102] According to the above-described embodiments of the present disclosure, it is possible to ensure the characteristics of a memory cell and reduce and / or prevent the occurrence of defects.

[0103] Although the disclosed technology has been shown and described with respect to particular embodiments, it should be understood that numerous enhancements and modifications to the disclosed embodiments and other embodiments may be made based on what is described and illustrated in this patent document.

Claims

1. A semiconductor device, comprising: a selector pattern that: exhibits different electrical conduction characteristics in response to an applied voltage relative to a threshold voltage; an interlayer insulating layer surrounding a sidewall of the selector pattern and having an opening disposed above the selector pattern; and an electrode disposed in the opening and having a maximum width at an uppermost portion of the opening, and Wherein, the uppermost portion of the opening has a rounded edge in the cross-sectional view.

2. The semiconductor device according to claim 1, wherein The width of the opening decreases from an uppermost portion to a bottom portion of the opening.

3. The semiconductor device according to claim 1, further comprising: A spacer is disposed between the sidewall of the selector pattern and the interlayer insulating layer.

4. The semiconductor device according to claim 1, further comprising: A buffer pattern is provided between the selector pattern and the electrode.

5. The semiconductor device according to claim 4, wherein: The buffer pattern includes a material having a higher resistivity than that of the electrode.

6. The semiconductor device according to claim 4, wherein: The buffer pattern includes amorphous carbon.

7. The semiconductor device according to claim 4, further comprising: A spacer is disposed between the sidewall of the selector pattern and the interlayer insulating layer and between the sidewall of the buffer pattern and the interlayer insulating layer.

8. The semiconductor device according to claim 1, further comprising: An additional electrode is disposed between the selector pattern and the electrode.

9. The semiconductor device according to claim 8, further comprising: A spacer is disposed between the sidewall of the selector pattern and the interlayer insulating layer and between the sidewall of the additional electrode and the interlayer insulating layer.

10. The semiconductor device according to claim 1, wherein The electrode and the interlayer insulating layer have planarized upper surfaces.

11. The semiconductor device according to claim 10, further comprising: A magnetic tunnel junction structure is formed on the planarized upper surface and is electrically connected to the electrode.

12. A method for manufacturing a semiconductor device, comprising: providing a stack structure in which a selector pattern and a sacrificial electrode are stacked on each other, wherein the selector pattern exhibits different electrical conduction characteristics with respect to a threshold voltage in response to an applied voltage; forming an interlayer insulating layer surrounding the sidewalls of the stack structure; removing the sacrificial electrode to form an initial opening; expanding the width of the uppermost portion of the initial opening to form an opening; as well as An electrode is formed to fill the opening.

13. The method according to claim 12, wherein: Forming the openings is performed using wet cleaning.

14. The method according to claim 12, wherein: The sacrificial electrode comprises titanium nitride, and The sacrificial electrode is removed using hydrogen peroxide.

15. The method according to claim 12, wherein: Forming the electrode comprises: depositing a conductive material over the interlayer insulating layer to fill the opening; and A planarization process is performed to expose an upper surface of the interlayer insulating layer.

16. The method according to claim 15, wherein: The electrode has an upper surface that is planarized together with the upper surface of the interlayer insulating layer, and The method further comprises: After forming the electrode, a magnetic tunnel junction structure is formed over the upper surface of the interlayer insulating layer and the upper surface of the electrode to be electrically connected to the electrode.

17. The method according to claim 12, further comprising: Before forming the interlayer insulating layer, forming a spacer on the sidewall of the stack structure, and Wherein, in the step of forming the opening, a portion of the spacer exposed by the initial opening is removed.

18. The method according to claim 12, wherein: The stack structure further includes a buffer pattern disposed between the sacrificial electrode and the selector pattern.

19. The method according to claim 18, wherein: In the step of forming the initial opening, the buffer pattern is retained.

20. The method according to claim 18, wherein: In the step of forming the initial opening, the buffer pattern is further removed.

21. The method according to claim 18, wherein: The stack structure further includes an additional electrode disposed between the buffer pattern and the selector pattern, and In the step of forming the initial opening, the additional electrode is retained.

22. The method according to claim 12, wherein: In the step of forming the initial opening, a portion of the sacrificial electrode remains located above the selector pattern.

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