Electronic system for determining most frequent data values from plurality of electrical signals

Abstract

The invention relates to an electronic system for determining, during use of the electronic system, a most frequent value in a data array A comprising a plurality N of data values A [i], i = 1,..., N, N > = 4, each data value A [i] corresponding to a respective data signal S [i], the electronic system comprising a first electronic subsystem comprising: a signal input interface for receiving the data signals; a first set of comparators determining a respective comparison signal representing whether A [i] is equal to A [j]; counters COi, i = 1,..., N for determining respective count signals CO [i], i = 1,..., N, each count signal CO [i] representing the number of occurrences of the data value A [i] in the data array A; the selector comprises a signal input end SelIn1i and a signal input end SelIn2i which are used for receiving corresponding signal sets; the selection line SelLinei is used for determining which signal set is output; the selectors Seli, i = 1,..., M are interconnected such that the output selector Selout provides as output a set of signals {S [jmax], CA [jmax], CO [jmax]}, 1 < = jmax < = N, characterized by no other data values A [k], k = 1,..., N having a count CO [k] higher than the count CO [jmax] of the data values A [jmax]. A corresponding method is also provided.

Description

Technical Field

[0001] The present disclosure relates to processing of data signals in electronic systems, and in particular to determining a most frequent data value among a plurality of data values ​​corresponding to a plurality of input data signals. Background Art

[0002] Multiple data signals obtained, for example, from a continuously operating measuring device such as a charge coupled device (CCD) or a microphone typically generate a large amount of data. The data can be obtained for many different purposes. For example, a charge coupled device can be used to observe the emission of infrared radiation emitted from a building over time or to record a movie. Depending on the data and the purpose, the data is processed in different ways. For example, the colors in a movie frame can be adjusted to create a certain impression on the viewer, and data corresponding to thermal emissions can be processed to determine the temperature distribution and size of areas corresponding to different temperature intervals. Similarly, data obtained from a microphone may need to be analyzed, for example to characterize the sound emission of a noisy place or to identify a certain auditory fingerprint, such as the voice of a specific person or the sound of a window breaking, to name a few. Summary of the invention

[0003] The present disclosure provides an electronic system for effectively determining the most frequent value among a plurality of data values. This need is not met in the prior art, which does not solve the problem of finding the most frequent value among a plurality of data values ​​in an efficient and fast manner. Various uses for determining the most frequent value are described below.

[0004] In a first aspect, the present disclosure provides an electronic system for determining a most frequent value in a data array A during use of the electronic system, the data array A comprising a plurality of N data values ​​A[i], i=1, ..., N, N≥4, each data value A[i] corresponding to a corresponding data signal S[i], i=1, ..., N, the electronic system comprising a first electronic subsystem, the first electronic subsystem comprising:

[0005] (i) a signal input interface, used to receive the data signal S[i], i=1,...,N;

[0006] (ii) First comparator set CA i,j , used to determine the corresponding comparison signal CA[i,j], i=1,...,N, j=1,...,N, wherein each comparison signal CA[i,j] indicates whether the data value A[i] is equal to the data value A[j];

[0007] (iii) Counter set CO i, i=1, ..., N, for determining corresponding counting signals CO[i], i=1, ..., N, wherein each counting signal CO[i] represents the number of times the data value A[i] appears in the plurality of data values ​​A;

[0008] (iv) Selector set Sel i , i = 1, ..., M, each selector Sel in the selector set i include:

[0009] - The first signal input terminal set SelIn1 i , which is configured to receive a first signal set {S[j], CA[j], CO[j]}, where 1≤j≤N and CA[j]={CA[j,1],...,CA[j,N]}, and

[0010] - The second signal input terminal set SelIn2 i , which is configured to receive a second signal set {S[k], CA[k], CO[k]}, where 1≤k≤N, k≠j,

[0011] -Select Line SelLine i , used to receive the selection signal SelSig i , the selection signal SelSig i Indicates whether CO[j]>CO[k] is determined by the corresponding selection line comparator,

[0012] -Signal output terminal set SelOut i , the selector Sel i Configured to be in SelSig i Indicates that CO[j]>CO[k] outputs the signal set {S[j],CA[j],CO[j]}, and in SelSig i Indicates the output signal set {S[j],CA[j],CO[j]} or the signal set {S[k],CA[k],CO[k]} when CO[j]≤CO[k],

[0013] The selector set Sel i , i = 1, ..., M includes output selector Sel out , the output selector Sel out are interconnected so that the output selector Sel out Provides a signal set {S[j max ],CA[j max ],CO[j max ]},1≤j max ≤N as the output signal, where the signal set {S[j max],CA[j max ],CO[j max ]} is characterized by the fact that no other data value A[k], k=1,...,N has a higher max ] count CO[j max ] high count CO[k]. It can be seen that the above system has a high i Indicates that when CO[j]≤CO[k], the output signal set {S[j],CA[j],CO[j]} or the signal set {S[k],CA[k],CO[k]} is output. Therefore, the selector Sel i It can be configured to output the signal set {S[j], CA[j], CO[j]} or the signal set {S[k], CA[k], CO[k]} when CO[j]=CO[k]. In some embodiments, the set Sel i , i = 1, ..., all selectors in M ​​are configured to i In other embodiments, the set Sel i , i = 1, ..., all selectors in M ​​are configured to i In other embodiments, the set Sel i , i=1,...,M, one or more selectors are configured to i In the case of CO[j]=CO[k], the output is {S[k], CA[k], CO[k]}, and the set Sel i , i = 1, ..., the other selectors in M ​​are configured to i In the case where CO[j]=CO[k], the output signal {S[j], CA[j], CO[j]} is output. This is a design issue. All the above implementations result in the output signal set {S[j], CA[j], CO[j]}. max ],CA[j max ],CO[j max ]}, signal set {S[j max ],CA[j max ],CO[j max ]} is characterized by the fact that no other data value A[k], k=1,...,N has a higher max ] count CO[j max ] high count CO[k]. In other words, the choice is just a matter of how to implement the inventive concept.

[0014] As described above, in the detailed description below, the electronic system is configured to output {S[k], CA[k], CO[k]} when CO[j]≤CO[k] (including the case where CO[j]=CO[k]), that is, different from the signal set {S[j], CA[j], CO[j]} output when the count satisfies CO[j]>CO[k].

[0015] In some embodiments, log2(N) is an integer, and the first selector subset SelSub1 in the selector set i , each selector in i=1,...,N / 2 is configured to receive N signal sets {S[j],CA[j],CO[j]},j=1,...,N, at its first signal input terminal set and its second signal input terminal set, respectively, whereby the first selector subset outputs N / 2 signal sets, at least one of the N / 2 signal sets corresponding to the data value A[j max ].

[0016] In some embodiments, the second selector subset SelSub2 in the selector set i , each selector in i=1,...,N / 4 is configured to receive the first selector subset SelSub1 i , i=1, ..., N / 2 outputs a corresponding pair of the N / 2 signal sets, whereby the second selector subset outputs N / 4 signal sets, at least one of the N / 4 signal sets corresponding to the data value A[j max In some embodiments, N≥8, and the selector set further comprises one or more additional selector subsets SelSub arranged in series with each other and arranged in series with the second selector subset l , each further selector subset provides at its signal output a number of output signal sets that is half the number of output signal sets that said further selector subset receives at its signal input, at least one of said output signal sets from each further selector subset corresponding to the signal set {S[j max ],CA[j max ],CO[j max ]}, the final additional selector subset includes the output selector Sel out , whereby the signal set {S[j], CA[j], CO[j]}, j=1,...,N is gradually reduced by the electronic system to the output selector Sel out The signal output terminal outputs a single signal set {S[j max ],CA[j max],CO[j max ]}.

[0017] A selector is also called a multiplexer.

[0018] Advantageously, the number of selectors M is equal to N-1. This may be the minimum number required. The fact that M is equal to or greater than N-1 follows from the claimed invention: the system / method outputs a signal set {S[j max ],CA[j max ],CO[j max ]}(signal set {S[j max ],CA[j max ],CO[j max ]} is characterized in that no other data value A[k], k=1,...,N has a higher max ] count CO[j max ] high count CO[k]), and to achieve this, at least N-1 selectors are needed, because each selector discards a signal set. In all examples presented in the specific implementation, M is equal to N-1.

[0019] In some embodiments, the selector set includes a first selector SelCasc1, the first selector SelCasc1 is configured to receive a first pair of signals in the signal set {S[j], CA[j], CO[j]}, j=1,...,N, and the selector set also includes another selector set SelCasc i , i=2,...,N-1, the other selector SelCasc i , each selector in i=2, ..., N-1 is arranged to receive the signal from the previous selector SelCasc at its first signal input terminal set. i-1 , i=2,...,N-1 output signals and receives at its second signal input terminal set {S[j],CA[j],CO[j]},j=1,...,N signal sets that have not been provided as input to the selector set until all signal sets have been provided as input to the selectors in the selector set, whereby the signal set {S[j],CA[j],CO[j]} is received. max ],CA[j max ],CO[j max ]} is provided as the selector in the selector set SelCasc N-1 The signal output at the output terminal.

[0020] In some embodiments, the electronic system further comprises:

[0021] An image sensor, the image sensor comprising a plurality of pixels p[i], i=1, ..., I, I≥4, for capturing an image signal, the image signal representing a set of intensity values ​​I[i], i=1, ..., I, each intensity value I[i], i=1, ..., I representing an amount of radiation captured by a corresponding pixel p[i], i=1, ..., I of the image sensor,

[0022] an analog-to-digital interface (ADC), the ADC being configured to receive the image signal from the image sensor and to provide a corresponding digital image signal, the corresponding digital image signal representing the intensity value I[i], i=1,...,I ​​captured by the corresponding pixel p[i], i=1,...,I ​​in the image sensor, the ADC also comprising an ADC output interface connected to the signal input interface to provide at least a portion of the digital image signal to the first electronic subsystem.

[0023] Image sensors typically collect light over relatively short periods of time in order to maintain a dynamic range in the amount of radiation captured by the different pixels. If the capture time is too long, the image sensor eventually saturates and will not represent the object being imaged. This is well known. Therefore, implicitly, the image sensor operates in a manner that renders the object being imaged. In low light conditions, longer exposure times may be required, and in conditions with a lot of radiation, relatively short exposure times may be required.

[0024] The image sensor may, for example, be particularly sensitive to light having one or more wavelengths in the range of 200 to 15000 nm, such as in the range of 200 to 3000 nm, such as in the range of 300 to 3000 nm, such as in the range of 200 to 300 nm or in the range of 300 to 380 nm or in the range of 380 to 750 nm or in the range of 750 to 3000 nm or in the range of 3000-6000 nm or in the range of 6000-15000 nm, or in a range overlapping two of these ranges, for example in the range of 600-1600 nm.

[0025] In some embodiments, the ADC is configured to output in parallel on the ADC output interface a portion of the digital image signal corresponding to N of the intensity values. In some embodiments, the N intensity values ​​extracted from the intensity values ​​I[i], i=1,...,I ​​correspond to a subset formed by N pixels arranged consecutively in the image sensor. In some embodiments, the N pixels P[i] are arranged in a two-dimensional array of L×P pixels, where L, P≥2, for example, L, P≥3, for example, L, P≥4. In some embodiments, L=P. In some embodiments, log2(L) and / or log2(P) are positive integers.

[0026] In some embodiments, the ADC is further configured to sequentially provide the intensity values ​​I[i], i=1, ..., I, to the first electronic subsystem in blocks of N intensity values, the electronic system further comprising a transmitter system coupled to the first electronic subsystem and configured to output the intensity values ​​I[i] from the output selector Sel out receiving the output signal, the transmitter system is further configured to provide a transmission signal T, the transmission signal T comprising a value representing the most frequent value A[j max In some embodiments, the transmitted signal T includes a first signal portion T1 representing a count C0[j max In some embodiments, the transmitted signal T includes a second signal portion T2 representing the comparison array CA[j max In some embodiments, the transmitted signal T includes a second signal portion T2 representing the data array A except the most frequent value A[j max ] other than the third signal portion T3.

[0027] In some embodiments, the first electronic subsystem is included in an application specific integrated circuit ASIC, the application specific integrated circuit comprising:

[0028] (i) the signal input interface,

[0029] (ii) the first set of comparators,

[0030] (iii) the set of counters,

[0031] (iv) the selector set,

[0032] (v) the select line comparator, and

[0033] (vi) a signal output interface configured to receive a signal from the output selector Sel out Provide the output signal {S[j max ],CA[jmax ],CO[j max ]}.

[0034] A second aspect of the present invention provides an ASIC, the ASIC comprising:

[0035] (i) the signal input interface,

[0036] (ii) the first set of comparators,

[0037] (iii) the set of counters,

[0038] (iv) the selector set,

[0039] (v) the select line comparator, and

[0040] (vi) the signal output interface, the signal output interface being configured to provide the signal from the output selector Sel out The output signal {S[j max ],CA[j max ],CO[j max ]}.

[0041] A third aspect of the present invention provides an ASIC, which includes the electronic system according to the first aspect of the present invention.

[0042] The signal input interface and / or the signal output interface may be externally accessible, for example for integration (eg by soldering) on ​​a printed circuit board. In some embodiments, the ASIC comprises a plurality of first electronic subsystems.

[0043] In the following description, the terms data signal S and data array A are used interchangeably because multiple signals S[i] correspond to multiple data values ​​A[i], but data signals S are physical signals that have physical characteristics (such as amplitude) that represent data values, but they do not themselves "have values". This is well known to those skilled in the art. For example, data signal S[1] is typically a continuous signal that varies according to the input received on the signal input interface. The characteristics (such as the amplitude of the data signal) vary over time, reflecting that a certain data value (such as data value 6) has been received. However, references to comparisons of data signals rather than comparisons of corresponding data values ​​are less intuitive and would unnecessarily complicate the claims and the description of the invention. Multiple data values ​​A[i], i=1,...,N are interchangeably referred to as data values ​​A. Similarly, data signals S[i], i=1,...,N are interchangeably referred to as data signals S.

[0044] The same applies to comparison signals, which may be interchangeably referred to as comparison arrays to emphasize the value represented by the comparison signal. Similarly, count signals may be interchangeably referred to as counts or count arrays to emphasize the value represented by the count signal.

[0045] In a fourth aspect, the present invention provides a method for determining a most frequent value in a data array A, wherein the data array A comprises a plurality of N data values ​​A[i], i=1, ..., N, N≥4, each data value A[i] corresponding to a corresponding data signal S[i], i=1, ..., N, the method being performed in an electronic system, the method comprising the following steps:

[0046] (i) receiving the data signal S[i] at the signal input interface of the electronic system, i=1, ..., N,

[0047] (ii) determining a comparison signal set CA[i,j], i=1, ..., N, j=1, ..., N, wherein each comparison signal CA[i,j] indicates whether the data value A[i] is equal to the data value A[j],

[0048] (iii) determining a counting signal set CO[i], i=1, ..., N, wherein each counting signal CO[i] represents the number of times a data value A[i] appears in the plurality of data values ​​A; the data signal, the comparison signal and the counting signal constitute a plurality of signal sets {S[i], CA[i], CO[i]}, i=1, ..., N, wherein CA[i]={CA[i,1], ..., CA[i,N]},

[0049] (iv) in a selector set, performing a plurality of signal selections, wherein each signal set in a signal set {S[i], CA[i], CO[i]}, i=1, ..., N, is selected or discarded based on a comparison with at least one other signal set {S[j], CA[j], CO[j]}, 1≤j≤N, i≠j, wherein the comparison is based on respective counts CO[i] and CO[j], each selection comprising:

[0050] - where CO[i]>CO[j], select the signal set {S[i], CA[i], CO[i]} for comparison with another signal set {S[k], CA[k], CO[k]}, i≠j≠k, and discard the signal set {S[j], CA[j], CO[j]}, or

[0051] - where CO[i]≤CO[j], select one of the signal sets {S[i],CA[i],CO[i]} and {S[j],CA[j],CO[j]} for comparison with the other signal set {S[k],CA[k],CO[k]}, 1≤k≤N, i≠j≠k, and discard the other of the signal sets {S[i],CA[i],CO[i]} and {S[j],CA[j],CO[j]},

[0052] (v) continuing step (iv) until one of the comparisons contains only a single signal set {S[j max ],CA[j max ],CO[j max ]}, 1≤j max All signals other than ≤N have been discarded, and

[0053] (vi) providing a signal set {S[j max ],CA[j max ],CO[j max ]}.

[0054] Similar to the electronic system according to the first aspect of the invention, the method according to the invention provides a most frequent data value A[j] among the N data values ​​A corresponding to the corresponding data signal S. max ] corresponding output signal.

[0055] In a fifth aspect, the present invention provides an electronic system, such as an ASIC, configured such as to perform a method according to the fourth aspect of the present invention.

[0056] The considerations described above with respect to the first aspect are also applicable to the second aspect, the third aspect, the fourth aspect and the fifth aspect. For example, the data signal S may be a signal originating from an image sensor. As an example, the data signal S corresponds to corresponding N signals captured by the image sensor, and each of the N signals represents the amount of radiation captured by corresponding N pixels in the image sensor, such as N consecutive pixels in the image sensor.

[0057] Similarly, the number N of data signals may be an even number. In some implementations, log2(N) is an integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. The accompanying drawings illustrate exemplary ways of implementing the present invention and should not be interpreted as limiting the scope of protection to those exemplary implementations.

[0059] Figure 1a to Figure 1dAn electronic system according to aspects of the present invention and a method of operating the electronic system are illustrated.

[0060] Figure 2 Another electronic system according to the present invention is illustrated.

[0061] Figures 3a to 3e Another electronic system according to aspects of the present invention, and a method of operating the electronic system are illustrated.

[0062] Figure 4 Another electronic system according to aspects of the invention is illustrated, the electronic system including a CCD that acquires data for processing.

[0063] Figure 5 Another electronic system according to aspects of the invention is illustrated, the electronic system including a CCD that acquires data for processing.

[0064] Figure 6a Figures 6e to 6e illustrate the different transmit parts that may be transmitted based on the output of the output selector. DETAILED DESCRIPTION

[0065] Various exemplary embodiments and details are described below, with reference to the accompanying drawings in some cases. It should be noted that the drawings may or may not be drawn to scale, and elements of similar structure or function may be represented by the same reference numerals in different drawings. The drawings are intended to facilitate the description of the embodiments. They do not provide an exhaustive description of the invention, and they should not be interpreted as limiting the scope of protection.

[0066] Figure 1a to Figure 1d An electronic system 100 according to the present invention is illustrated. The electronic system comprises a signal input interface 120 for receiving a plurality of data signals S, in this case four data signals. The electronic system further comprises a computing unit set Compute of four computing units for performing processing of the data signals. i , i=1,...,4, 101, 102, 103, 104. A plurality of data signals S[1], S[2], S[3] and S[4] are provided to each computing unit through corresponding signal lines (interconnections) 121, 122, 123 and 124. That is, each computing unit receives all 4 data signals.

[0067] The term signal is used interchangeably with the terms signal line and input and output lines because each signal line is associated with a particular signal during operation of an electronic system. For example, signal S[1] is associated with line 121, S[2] is associated with line 122, and so on. In some cases, a signal line connects two elements, and depending on the perspective, the output signal from one element is the input signal to another element.

[0068] Compute unit for processing data signals i In the following about Figure 1b to Figure 1c Discuss in more detail. Each computing unitCompute i A respective one of the data signals S is also received on corresponding input lines 131, 132, 133, 134. Compute1 receives S[1] via line 131, Compute2 receives S[2] via line 132, and so on.

[0069] From the corresponding computing unit Compute i The output signals of are provided on lines 141, 142, 143, 144, which connect the corresponding computational units to the selector set SelPar i , i = 1, ..., 3 selectors SelPar1 and SelPar2. i With two input terminals SelIn1 i and SelIn2 i Each input terminal is configured to receive one of the data signals S[i], the corresponding comparison signal CA[i] and the corresponding count signal CO[i]. Figure 1b The signals CA[i] and CO[i] are described in more detail.

[0070] exist Figure 1a In the example of , the selector SelPar1 receives the data signal S[1] at the signal input SelIn11 via the line 131. The data signal S[1] is received via the signal input interface 120 together with the other data signals S[2], S[3] and S[4], but is provided to the computing unit Compute1 twice, as shown. The selector SelPar1 also receives at the signal input SelIn11 the comparison signal CA[1] and the count signal CO[1] contained in the signal 141 provided by the computing unit Compute1, as shown. Figure 1a shown.

[0071] Furthermore, selector SelPar1 receives at signal input SelIn21 a data signal S[2] from a plurality of data signals S received at signal input interface 120. Selector SelPar1 also receives at signal input SelIn21 a corresponding comparison signal CA[2] and a corresponding count signal CO[2] contained in signal 142 provided by calculation unit Compute2.

[0072] The selector SelPar1 also includes an output terminal SelOut1 for outputting any one of the signal set {S[1], CA[1], CO[1]} or the signal set {S[2], CA[2], CO[2]}. The output is determined based on the selection signal SelSig1 received on the selection line SelLine1 in the selector SelPar1. In this example, if the selection signal SelSig1 corresponds to a "true" indication, the selector SelPar1 outputs the signal set {S[1], CA[1], CO[1]} (corresponding to the "yes" branch), and if the selection signal SelSig1 corresponds to a "false" indication, the selector SelPar1 outputs the signal set {S[2], CA[2], CO[2]} (corresponding to the "no" branch).

[0073] The selection signal SelSig1 is determined based on the comparison of two counts performed in the comparator 171. More specifically, the comparator 171 compares the count signal CO[1] from the computing unit Compute1 with the count signal CO[2] from the computing unit Compute2. Figure 1b and Figure 1c As explained in more detail, each count signal CO[i] represents the frequency of data value A[i] in the plurality of data values ​​A. The selected data signal set {S[1], CA[1], CO[1]} or {S[2], CA[2], CO[2]} selected in dependence on the selection signal SelSig1 is output as output signal 151 at the selector output terminal SelOut1 of the selector SelPar1. Figure 1a As indicated, the outputs on the three output lines 151 are S[1] or S[2], CA[1] or CA[2], and CO[1] or CO[2], respectively, depending on the selection signal SelSig1 as described above.

[0074] Similarly, the selector SelPar2 receives a data signal S[3] from the plurality of data signals S at a signal input SelIn12 via line 133. As described above, the data signal S[3] is received via the signal input interface 120. The selector SelPar2 also receives a comparison signal CA[3] and a count signal CO[3] from a calculation unit Compute3 at a signal input SelIn12, the comparison signal CA[3] and the count signal CO[3] being obtained based on the data signal S, as described with respect to Figure 1c Described in more detail.

[0075] The selector SelPar2 also receives a data signal S[4] from the plurality of data signals S at a signal input SelIn22 via line 134. The selector SelPar2 also receives a comparison signal CA[4] and a count signal CO[4] from a calculation unit Compute4 at a signal input SelIn22, as described with respect to Figure 1c Described in more detail.

[0076] Similar to the selector SelPar1, the selector SelPar2 also includes an output terminal SelOut2 for outputting the signal set {S[3], CA[3], CO[3]} or the signal set {S[4], CA[4], CO[4]} on three output lines 152. The output is determined based on the selection signal SelSig2 received on the selection line SelLine2 of the selector SelPar2. If the selection signal SelSig2 corresponds to a "true" indication, the selector SelPar2 outputs the signal set {S[3], CA[3], CO[3]} (corresponding to the "yes" branch), and if the selection signal SelSig2 corresponds to a "false" indication, the selector SelPar2 outputs the signal set {S[4], CA[4], CO[4]} (corresponding to the "no" branch).

[0077] Similar to the selection signal SelSig1, the selection signal SelSig2 is determined based on a comparison of two values ​​performed in a comparator, in this case the comparator 172. The comparator 172 compares the count signal CO[3] from the calculation unit Compute3 with the count signal CO[4] from the calculation unit Compute4. Figure 1c Explained in more detail, count signals CO[3] and CO[4] correspond to the frequencies of data values ​​A[3] and A[4] in data array A, respectively.

[0078] like Figure 1a As indicated, the output signals from SelPar2 on each of the three lines 152 are S[3] or S[4], CA[3] or CA[4], and CO[3] or CO[4], respectively, depending on the select signal SelSig2 as described above.

[0079] Since the output terminals SelOut1 and SelOut2 correspond to the signal sets with the highest counts, CO[1] or CO[2] from SelOut1 and CO[3] or CO[4] from SelOut2, the most frequent data values ​​will correspond to the output signal 151 or the output signal 152. These signals are input to the signal input terminals SelIn13 and SelIn23 on the third selector SelPar3, respectively. Selector SelPar3 performs the same kind of processing as selectors SelPar1 and SelPar2. The select line SelLine3 of selector SelPar3 receives a signal from a comparator 173, which compares the count signals of the two corresponding signal sets input to the selector. If the count in the signal set provided on the upper signal input terminal SelIn13 is higher than the count in the signal set provided on the lower signal input terminal SelIn23, the signal set input on the signal input terminal SelIn13 is output on the output terminal SelOut3 of selector SelPar3, as illustrated by signal 161. If the count in the signal set provided at the upper signal input SelIn13 is not higher than the count provided at the supply input SelIn23, the signal set input at the signal input SelIn23 is output at the output SelOut3 of the selector SelPar3, as illustrated by signal 161. This is illustrated in more detail below.

[0080] According to the invention, selector SelPar3 in this example is used as an output selector, because there are no more signal sets to compare. The invention ensures this by ensuring that all signal sets {S[i], CA[i], CO[i]} have been compared with other signal sets, and in such a way that the corresponding Figure 1a The output signal set of signal 161 in is the following signal set, for which the data value A[j max ] is characterized by the fact that no other data value in the data array A has a value greater than that of the data value A[j max ] frequency (count) higher than the frequency (count). This can be achieved in different ways. Figure 1a to Figure 1d The method described in uses what can be considered a "parallel" configuration, since it evaluates sets of signals pairwise in parallel. Figure 1aAs can be seen and in accordance with the above description, the evaluation of the signal sets {S[1], CA[1], CO[1]} and {S[2], CA[2], CO[2]} in SelPar1 111 overlaps in time with the evaluation of {S[3], CA[3], CO[3]} and {S[4], CA[4], CO[4]} in SelPar2 112. This allows the signal sets selected in SelPar1 and SelPar2, respectively, and represented by signals 151 and 152, to arrive at the signal inputs SelIn13 and SelIn23 of the selector SelPar3 overlapping in time for evaluation in the selector. Once the present disclosure is understood, it will be readily understood by those skilled in the art that the computational units, selectors, and interconnections (such as transmission lines connecting different functional elements) are configured to ensure that signal processing occurs as described above. In other words, the electronic system is configured so that pairs of signal sets to be evaluated in the respective selectors arrive overlappingly (in a sense: "sufficiently simultaneously") to allow selection to be performed between corresponding signals as described. Similarly, the select lines and select line comparators associated with the different selectors are configured to ensure that the selection can occur. If a select line signal such as SegSig1 arrives too early or too late compared to the input signal to the selector, the output of the selector SelPar1 is unreliable at best. As described above, these points are readily understood by those skilled in the art, so it is implicit that the transmission and processing times are adapted as described above.

[0081] Figure 1b In more detail, Figure 1a The signal processing occurring in computing units Compute1 and Compute2 of electronic system 100 is shown.

[0082] from Figure 1b It can be seen that each of the computation units Compute1 and Compute2 receives a plurality of data signals S, and corresponding individual data signals S[i] as described above.

[0083] like Figure 1b As shown, Compute1 receives all four data signals and also receives the data signal S[1] separately. The computing unit Compute1 includes a comparator set CP 1,1 , CP 1,2 , CP 1,3 , CP 1,4 ,, each comparator compares the individual data signal S[1] with each of the data signals S[1], S[2], S[3], and S[4] to determine whether the multiple signals correspond to the individual value S[1]. In the example, the data signal S represents the data value set A1={1,3,4,1}.

[0084] Comparator CP1,1 S[1] received via line 131 is compared with S[1] from multiple data signals received via line 121. Similar to lines 132 to 134, this line is preferably connected to the signal input interface 120 because this will reduce the number of input terminals (e.g., pins) required to process multiple data signals S.

[0085] The result of the comparison is a comparison signal CA[1, 1]. The comparison signal CA[1, 1] is indicated by the value "1", which indicates that the compared values ​​are equal. In a practical circuit, as also described above, the signal is a physical signal having characteristics that represent the value. For example, the comparison signal can be a current or voltage with an amplitude that represents that the two values ​​are equal. Similarly, "0" will be used here to indicate that a comparison is made between two values ​​that are not equal. The characteristics of the comparison signal will be different from the characteristics corresponding to the equality of the values.

[0086] Comparator CP 1,2 S[1] received via signal line 131 is compared with S[2] from the plurality of data signals S received via line 121. That is, value 1 is compared with value 3. The result of the comparison is a comparison signal CA[1,2]. The comparison signal CA[1,2] is indicated by "0" to indicate that the two values ​​are not equal. In an actual electronic system, the comparison signal from the comparator CP 1,1 and CP 1,2 The output signals are different because one comparison evaluates to true and the other evaluates to false.

[0087] Similarly, comparator CP 1,3 S[1] is compared with S[3], that is, the value 1 is compared with the value 4. The result of the comparison is a comparison signal CA[1,3] represented by "0", indicating that S[1] is different from S[3].

[0088] Finally, the comparator CP 1,4 S[1] is compared with S[4], that is, the value 1 is compared with the value 1. The result of the comparison is a comparison signal CA[1,4] indicated by "1" to indicate that S[1] is equal to S[4].

[0089] The comparison generates four comparison signals CA[1,1], CA[1,2], CA[1,3] and CA[1,4]. For simplicity, Figure 1a and Figure 1b It is referred to as CA[1]. Figure 1a As described and shown, the comparison signal CA[1] is output from the computing unit Compute1 and is provided as input to the selector SelPar1 via the line 141a at the signal input SelSig11. Figure 1b The comparison signal CA[1] is a "signal array" and is Figure 1b It is represented as CA[1]={1, 0, 0, 1}, which represents the different comparisons in the above-mentioned computing unit Compute1.

[0090] The calculation unit Compute1 also counts based on the comparison signal CA[1] (including 4 signals). The counter CO1 counts the number of "1" in the comparison signal CA[1] to obtain the value of Figure 1a Count signal CO[1] is illustrated. Since data signal S represents data value 1 twice (in other words, data value 1 appears twice in data array A), count signal CO[1] represents a count of 2 (as discussed above with respect to comparison signals, count signals are electrical signals having the characteristic of representing that value 1 is represented twice in data array A).

[0091] like Figure 1b As shown, the comparison signal CA[1] and the count signal CO[1] are provided on signal lines 141a and 141b, respectively, which are connected to the signal input terminal SelIn1 of the selector SelPar1.

[0092] Similarly, the computing unit Compute2 receives all four data signals S[i], i=1, ..., 4 via the signal line 122 and receives a single data signal S[2] on the signal line 132. Similar to Compute1, Compute2 includes a comparator set CP 2，1 , CP 2，2 , CP 2，3 , CP 2，4 , each comparator compares the individual data signal S[2] with each of the data signals S[1], S[2], S[3] and S[4] to determine whether the data signals correspond to the same data value A[2].

[0093] In more detail, the comparator CP in Compute2 2，1 S[1] is compared to S[2], i.e., the value 1 is compared to the value 3. A separate signal S[2] from signal line 132 is input on a separate signal, which is preferably connected to the signal input interface 120, as this will reduce the number of input terminals (e.g., pins) required, as described above with respect to Compute1.

[0094] The comparison generates a comparison signal CA[2, 1], which corresponds to "0" because the two corresponding values ​​A[1] and A[2] are different.

[0095] Comparator CP in Compute2 2，2 S[2] is compared with S[2], ie, the value 3 is compared with the value 3, which results in a comparison signal "1". Comparator CP2，3 Comparing value 4 and value 3 results in a comparison signal CA[2,3] corresponding to "0" because value 4 and value 3 are different. Finally, comparator CP 2，4 Comparing the value 1 and the value 3, a comparison signal CA[2, 4] corresponding to "0" is obtained because the values ​​1 and 3 are different.

[0096] The comparison generates four comparison signals CA[2,1], CA[2,2], CA[2,3], CA[2,4]. Figure 1a and Figure 1b For simplicity, it is referred to as CA[2]. Figure 1a As described, the comparison signal CA[2] is output from the calculation unit Compute2 and is provided as input to the selector SelPar1, in this case via the line 142a at the signal input SelIn21. Figure 1b As shown and according to the above description, the comparison signal CA[2] corresponds to a signal array having values ​​{0, 1, 0, 0}.

[0097] Similar to the calculation unit Compute1, the calculation unit Compute2 also performs counting based on the comparison signal CA[2] (comprising 4 signals). The counter CO2 counts the number of "1"s of the comparison signal CA[2]. Since the data signal S represents the data value 3 (S[2]) once, the count signal CO[2] corresponds to 1. As discussed above with respect to the count signal CO[1], the count signal CO[2] is an electrical signal having the property of representing that the value 3 is represented once by the data signal S.

[0098] The comparison signal CA[2] and the count signal CO[2] are provided on lines 142a and 142b, respectively, as inputs to the signal input terminal SelIn21 of the selector SelPar1, as described with respect to Figure 1a described.

[0099] The signal SelSig1 on the select line SelLine1 of the selector SelPar1 determines whether the selector SelPar1 is to output the signal set {S[1], CA[1], CO[1]} or the signal set {S[2], CA[2], CO[2]} at the signal output SelOut1.

[0100] According to the present invention, the signal SelSig1 on the selection line SelLine1 represents the result of determining whether one count is higher than another count, specifically, whether CO[1]>CO[2], as also described with respect to Figure 1aAs described. Since the counter CO[1] in Compute1 determines that the data value 1 appears twice, and the counter CO[2] in Compute2 determines that the data value 3 appears only once, the evaluation result in the comparator 171 is "true", and the "yes" branch is selected, resulting in the signal set {S[1], CA[1], CO[1]} being output on the signal output terminal SigOut1 on the signal lines 151c, 151a and 151b, respectively, as shown Figure 1b shown.

[0101] As also described above, the different data signals S that propagate from the signal input and through Compute1 and Compute2 overlap in time in SelPar1 so that selection can be performed. Similarly, providing count signals CO[1] and CO[2] to comparator 171 must allow select signal SelSig1 to arrive at SelPar1 in time for the selector to select between the data signal sets {S[1], CA[1], CO[1]} and {S[2], CA[2], CO[2]}.

[0102] It should also be noted that for simplicity, the output signal from the selector is explained and shown as being the same as the input to the computation unit and the selector. Figure 1a and Figure 1b As shown, the output of SelPar1 is {S[1], CA[1], CO[1]} or {S[2], CA[2], CO[2]}, which is the same set of signals provided on the signal input terminal. In actual circuits, there are losses in the transmission lines and selectors, and a certain degree of noise is applied to the signals. Therefore, the output data signal from SelPar1 is different from the data signal received on the signal input interface. However, the information represented by the different signals provided on the signal input terminal and output on the signal output terminal is the same, and therefore the same labels are used. This is also easily understood by those skilled in the art, especially when the present disclosure is understood.

[0103] As a result of the above process, the signal {S[1]=1, CA[1]={1, 0, 0, 1}, CO[1]=2} is provided at the output terminal SelOut1.

[0104] Refer to above Figure 1b The described processing is performed in parallel based on the respective data signals S[3] and S[4]. Figure 1c This figure corresponds to Figure 1b , but this portion of the electronic system 100 uses computing units Compute3 and Compute4, each of which is connected via signal lines 123 and 124 (see Figure 1a) receives a plurality of data signals S, and receives corresponding individual data signals S[3] and S[4] via lines 133 and 134, as Figure 1a and Figure 1c shown.

[0105] therefore, Figure 1c The description of will be quite brief, as the process is similar to the above description of Figure 1b The process described is largely the same.

[0106] exist Figure 1c In the example, the computing unit Compute3 compares the data signal S received on the signal line 123 with the data signal S[3] received on the signal line 133. 3，1 , CP 3，2 , CP 3，3 and CP 3，4 The comparison performed in generates a comparison signal CA[3] representing the comparison result {0, 0, 1, 0}. These results reflect that the data value corresponding to the data signal S[3], i.e., the data value 4, only appears in the data signal S[3]. The corresponding count signal obtained by the counter CO3 represents the value 1, indicating that the data value 4 appears once. That is, the number of "1"s represented by the comparison signal CA[3] is 1. The comparison signal CA[3] and the count signal CO[3] are output on signal lines 143a and 143b, respectively, and the signal lines 143a and 143b are connected to the signal input terminal SigIn12 of the selector SelPar2. The data signal S[3] is also provided to the signal input terminal Sigin12 of the selector SelPar2 via the signal line 133.

[0107] Similarly, the computing unit Compute4 compares the data signal S received on the signal line 124 with the data signal S[4] received on the signal line 134. 4，1 , CP 4，2 , CP 4，3 and CP 4，4 The comparison performed in generates a comparison signal CA[4] indicating the comparison result {1, 0, 0, 1}. These results reflect the data value of the data signal S[4], that is, the data value 1 corresponds to the data signal S[1] and the data signal S[4]. The corresponding count signal CO[4] obtained by the counter CO4 represents the value 2, reflecting that the data value 1 appears twice. That is, the number of "1"s represented by the comparison signal CA[4] is 2. The comparison signal CA[4] and the count signal CO[4] are output on signal lines 144a and 144b, respectively, and the signal lines 144a and 144b are connected to the signal input terminal SigIn22 of the selector SelPar2. The data signal S[4] is also provided to the signal input terminal SigIn22 of the selector SelPar2 via the signal line 134.

[0108] After signal S has been processed in computation units Compute3 and Compute4, the resulting signals {S[3], CA[3], CO[3]} and {S[4], CA[4], CO[4]} are provided as inputs to signal inputs SelIn12 and SelIn22, respectively, as described above. This should occur at the same time as {S[1], CA[1], CO[1]} and {S[2], CA[2], CO[2]} are provided as inputs to signal inputs SelIn11 and SelIn21, respectively, of selector SelPar1, to allow the outputs of selectors SelPar1 and SelPar1 to overlap in time in SelPar3.

[0109] Similar to SelLine1, the select signal SelSig2 on the select line SelLine2 represents the result of determining whether one count is higher than the other count, specifically, whether CO[3]>CO[4], as also described with respect to Figure 1a As described. Since the counter CO[3] in Compute3 determines that the corresponding data value 4 appears once, and the counter CO[4] in Compute4 determines that the corresponding data value 1 appears twice, the evaluation result in comparator 172 is "false", and the "no" branch is selected, resulting in the signal set {S[4], CA[4], CO[4]} being output on the signal output terminal SigOut2 of the selector SelPar2 on the signal lines 152c, 152a and 152b respectively, as shown Figure 1c shown.

[0110] As described above, the output of the signal set {S[1], CA[1], CO[1]} at the output terminal SelOut1 of selector SelPar1 and the output of {S[4], CA[4], CO[4]} at the output terminal SelOut2 of selector SelPar2 will occur overlapping in time ("substantially simultaneously") to allow comparison of correct signals.

[0111] Figure 1dThe last part of determining the most frequent value among the data values ​​represented by the data signal S is illustrated. The output signals 151a, 151b and 151c from the signal output terminal SelOut1 of the selector SelPar1 are provided as inputs on the signal input terminal SelIn13 of the selector SelPar3, and the output signals 152a, 152b and 152c from the signal output terminal SelOut2 of the selector SelPar2 are provided as inputs on the signal input terminal SelIn13 of the selector SelPar3. The output signal from SelPar3 on the signal output terminal SelOut3 is determined by the selection signal SelSig3 on the selection line SelLine3. Similar to the selection lines SelLine1 and SelLine2, the selection signal SelSig3 on the selection line SelLine3 indicates whether one count is higher than the other count, specifically whether CO[1]>CO[4]. Since both counts are equal to 2, the comparison result in the comparator 173 is "false". Selector SelPar3 thus selects as output the signal set {S[4], CA[4], CO[4]} corresponding to the most frequent value 1, the comparison signal corresponding to the array {1, 0, 0, 1} and the count signal CO[4] corresponding to the value 2. These signals are provided on signal lines 161c, 161a and 161b, respectively.

[0112] The input data array A1 may correspond to the intensity values ​​(radiation intensities) I[i] measured by the corresponding pixels in the CCD device 401, such as Figure 4 exemplified. Figure 4 The electronic system 400 includes the above Figure 1a to Figure 1d and Figure 2 The described electronic system 100 or 200, and a CCD 401 coupled to the electronic system 100 or 200 via an analog-to-digital interface 402 (ADC), is used to read out intensity values ​​in blocks of 4 digital values, which are provided to the electronic system 100 or 200 in parallel. Figure 4 The set of pixels 411 shown in FIG. 4 corresponds to Figure 1a to Figure 1d , and therefore, when a block of four pixels 411 is processed by the electronic system 100 or 200, a signal set {S[4], CA[4], CO[4]} is output from the electronic system 400. Thus, the electronic system 400 determines from the CCD signal that intensity 1 is dominant in the pixel block 411 of the image signal obtained by the CCD 401.

[0113] Return to reference Figure 1a to Figure 1cIn the example in , the two inputs to the output selector SelPar3 correspond to the same data value 1. If the data values ​​had been sorted as {1, 1, 3, 4} instead of {1, 3, 4, 1}, the signal set input on the upper signal input terminal SelIn13 of SelPar3 would be {S[2], CA[2], CO[2]} (corresponding to the data value 1), and the signal set input on the lower signal input terminal SelIn23 of SelPar3 would be {S[4], CA[4], CO[4]} (corresponding to the data value 4). The "yes" branch in SelPar3 will be selected, resulting in the signal set {S[2], CA[2], CO[2]} being output on SelOut3. The result is of course the same, because the signal set {S[2], CA[2], CO[2]} also corresponds to the most frequent value 1, which is unique. The count CO[2] and the comparison array CA[2] are also identical.

[0114] If the data array is already {1, 1, 2, 2}, the electronic system 100 will determine that the most frequent value is 2, count 2, and the comparison array will be {0, 0, 1, 1}. If the same data is sorted as {2, 1, 2, 1}, the most frequent value will be determined to be 1, still counted as 2. The comparison array will be {0, 1, 0, 1}. This illustrates that the most frequent value is not necessarily unique. This is called a multimodal distribution in statistics, where the term most frequent value is used even if several values ​​are "most frequent". Therefore, the meaning of the term "most frequent value" is clear to those skilled in the art.

[0115] The above example also illustrates that the most frequent value determined in the case of a multimodal distribution depends on the ordering of the data values ​​corresponding to the data signal S.

[0116] Figure 2 Another electronic system 200 according to the present invention is illustrated. The signal input interface can be connected to Figure 1a to Figure 1d The function of the signal input interface is to receive data signals S and provide them as input to the computing units 101 to 104, which can also communicate with the related Figure 1a to Figure 1d The computing unit described in the electronic system 100 is the same as that in the electronic system 200. The principle is the same, but the architecture in the electronic system 200 is different. Figure 1a to Figure 1d An electronic system 100.

[0117] The selector SelCasc in the electronic system 200 i is arranged so that each selector except the first selector SelCasc1 receives a signal set {S[i], CA[i], CO[i]} that has not yet been evaluated for the signal corresponding to the most frequent value, which is consistent with Figure 1a to Figure 1dThe selector SelPar3 in receives a signal set that has been compared with another signal set. In addition, Figure 1a to Figure 1d The scheme in is parallel in the sense that four signal sets (or more) are evaluated pairwise essentially simultaneously.

[0118] exist Figure 2 In the implementation manner, the computing unit Compute i The electronic system 100 operates as described above with respect to providing a count CO[i] and a comparison array CA[i] for each data signal S[i]. The selector may also be associated with Figure 1a to Figure 1d The selector SelPar described in the embodiment shown in i Therefore, with respect to this embodiment, the detailed inputs and outputs are not shown or described in detail. The same applies to the selection signals provided by the comparators 221, 222 and 223, which compare the counts associated with the various signal sets.

[0119] Similar to Figure 1a and Figure 1b In SelPar1, the first selector SelCasc1 211 receives two signal sets {S[1], CA[1], CO[1]} and {S[2], CA[2], CO[2]}. Therefore, the output is also the same. For the input signal corresponding to the data array A1 = {1, 3, 4, 1}, the output signal 251 from SelCasc1 will be {S[1], CA[1], CO[1]}, as shown in Figure 1b as described, because data value 1 has a count of 2 and data value 3 has a count of 1.

[0120] exist Figure 2 In the electronic system 200 in FIG. 2 , the output signal from SelCasc1 is then used as input to SelCasc2 212 along with signal S[3] and signals CA[3] and CO[3] from Compute3. In the case of data array A1={1, 3, 4, 1}, the output signal 252 from SelCasc2 will be {S[1], CA[1], CO[1]} because the counts corresponding to the signal set {S[3], CA[3], CO[3]} are lower than the counts corresponding to the other signal set {S[1], CA[1], CO[1]}. Therefore, comparator 222 will evaluate to true and the "yes" branch will be selected, resulting in the output of SelCasc2 being {S[1], CA[1], CO[1]}.

[0121] Finally, the output signal from SelCasc2 is used as input to SelCasc3 213 along with the signals S[4], CA[4], and CO[4] (the latter two provided by Compute4). In the case of data array A1 = {1, 3, 4, 1}, the output signal 261 from SelCasc3 will be {S[4], CA[4], CO[4]} because the two counts evaluated by comparator 223 are equal, both corresponding to a count of 2. Therefore, comparator 223 will evaluate to false and the "no" branch will be selected. This results in the output of the signal set {S[4], CA[4], CO[4]}, whereby it has been determined that the data value 1 is the most frequent value. The result is of course the same as Figure 1a to Figure 1d The electronic system 100 illustrated in FIG. 1 provides the same result.

[0122] Similar to About Figure 1a to Figure 1d Discussion, Figure 2 The electronic system 200 in is designed so that the transmission lines and processing times allow the output and input to be provided substantially simultaneously when required, in particular in order to allow different signals to overlap in time in the selector. For example, the transmission time of the signal set {S[3], CA[3], CO[3]} from the interface 120 via lines 123, 133 and 143 to SelCasc2 and the processing time in Compute3 should substantially correspond to the transmission time and processing time of the input signal set that is ultimately provided at the input end of the selector SelCasc2. This includes the transmission time from the interface 120 via signal lines 121 and 122, the processing in the computing units Compute1 and Compute2, the selection in the selector SelCasc1 and the transmission via line 251. Once the present disclosure is understood, it is easy for a person skilled in the art to understand this.

[0123] As from Figure 1a to Figure 1d and Figure 2 As can be seen from the discussion of , the most frequent value obtained is (of course) the same, but it is obtained in two very different ways. Figure 1a to Figure 1d The embodiment 100 in FIG. 1 operates with a parallel comparison as described above, but Figure 2 The selectors in the embodiment 200 shown in FIG. 2 are cascaded in a sense.

[0124] Figure 3a Another electronic system 300 according to the present invention is illustrated. It is similar in architecture to Figure 1a to Figure 1d. Instead of 4 inputs, the electronic system 300 processes 8 input signals S[1:8]. These signals are received at the signal interface 320 and are available to the corresponding calculation units 301 to 308. The calculation units 301 to 308 use the same principles as the calculation units 101 to 104 of the electronic systems 100 and 200. Each calculation unit 301 to 308 receives the data signal S[1:8] and a corresponding individual data signal S[i] for comparison and counting with the data signal S[1:8], similar to the calculation units 101 to 104 of the electronic systems 100 and 200. Figure 1b and Figure 1c . In the present case, each computing unit has 8 comparators to compare each of the 8 data signals S with a corresponding individual data signal S[i]. Similarly, the counters in the computing units in this embodiment are configured to count based on 8 comparison signals rather than 4 signals as in electronic systems 100 and 200. For simplicity, elements such as select line comparators, select lines, and selector inputs and outputs are not explicitly shown, but it will be readily understood that they form part of electronic system 300, as described with respect to electronic systems 100 and 200.

[0125] 8 signal sets {S[i], CA[i], CO[i]} (i=1,...,8) are provided in pairs to 4 selectors Sel i (i=1, ...4). The signal set {S[1], CA[1], CO[1]} and the signal set {S[2], CA[2], CO[2]} are provided to the selector Sel1 311, the signal set {S[3], CA[3], CO[3]} and the signal set {S[4], CA[4], CO[4]} are provided to the selector Sel2 312, the signal set {S[5], CA[5], CO[5]} and the signal set {S[6], CA[6], CO[6]} are provided to the selector Sel3 313, and the signal set {S[7], CA[7], CO[7]} and the signal set {S[8], CA[8], CO[8]} are provided to the selector Sel4 314. The corresponding count signals CO[i] from the calculation units 301 to 308 are used as the selectors Sel i , i = 1, ..., 4, the basis for selection is similar to that for Figure 1a to Figure 1d and Figure 2 Describe the process.

[0126] In this way, the eight signal sets are first reduced to four signal sets outputted from the four selectors as signals 351, 352, 353 and 354, respectively. With the aid of the selectors, one (or more) of the four signal sets corresponds to the most frequent data value. i, i=1, ..., 4 form a first selector subset 321, which reduces the number of signal sets from N to N / 2. In this example, N=8.

[0127] The output signals 351, 352, 353 and 354 from the first selector subset 331 are provided in pairs to the selectors in the second selector subset 332. In this case, two selectors Sel are required. i , i=5, 6. The second selector subset 332 reduces the set of 4 output signals from the first selector subset 331 from 4 to 2. The second selector subset 332 provides output signals 355 and 356, one or more of which correspond to the most frequent data values.

[0128] Finally, the two output signal sets 355 and 356 are provided to a third selector subset 333, which consists of a single selector Sel7 for evaluating which of the signal sets 355 and 356 corresponds to the most frequent value. Furthermore, selector Sel7 is an output selector in the sense that the signal set provided by output selector Sel7 as output 361 is guaranteed to correspond to the most frequent value.

[0129] Refer to the following Figure 3b to Figure 3e The electronic system 300 and its operation are described in further detail.

[0130] Figure 3b Focus on the computing units 101 to 104 and the selectors Sel1 and Sel2. The input data signal S in this example corresponds to the data array A2 = {3, 3, 3, 4, 5, 3, 8, 8}. The signal S[i], i = 1, 2 is input to the computing unit Compute i , i=1,2, which determines the corresponding comparison signal CA[i] and count signal CO[i], i=1,2. Compute1 compares the individual signal S[1] across all 8 data signals S. It is determined that the individual data value 3 is equal to the data value of the data array A2 at index 1, 2, 3 and 6. Therefore, the comparison array is {1, 1, 1, 0, 0, 1, 0, 0}, as shown in Figure 3b exemplified. The corresponding count is 4. Similarly, Compute1 compares individual signal S[2] across all 8 data signals S. It is again determined that individual data value 3 is equal to the data values ​​of data array A2 at indices 1, 2, 3, and 6. Therefore, the comparison array is {1, 1, 1, 0, 0, 1, 0, 0}.

[0131] The signal sets {S[1], CA[1], CO[1]} and {S[2], CA[2], CO[2]} are provided to the selector Sel1 311 as described above. The selector Sel1 outputs the signal set {S[2], CA[2], CO[2]}, and since the corresponding count CO[2] (=4) is equal to CO[1] (=4), the "No" branch is selected.

[0132] In the same way, the signal S[i], i=3,4 is input to the calculation unit Compute i , i=3,4, which determines the corresponding comparison signal CA[i] and count signal CO[i], i=3,4. As described above, the comparison signals CA[3] and CA[4] and the count signals CO[3] and CO[4] are determined by the computation unit based on the data signal S and the individual data signals S[3] and S[4]. Compute3 compares the individual signal S[3] across all data signals S, and again determines that the individual data value 3 is equal to the data value of the data array A2 at indexes 1, 2, 3 and 6, and determines the comparison array {1, 1, 1, 0, 0, 1, 0, 0}, as Figure 3b Compute4 compares the individual signal S[4] across all data signals S and determines that the individual data value 4 is equal to the data value of the data array A2 at index 4 and determines the comparison array {0, 0, 0, 1, 0, 0, 0, 0}, as Figure 3b exemplified.

[0133] The signal sets {S[3], CA[3], CO[3]} and {S[4], CA[4], CO[4]} are provided to the selector Sel2 312 as described above. The selector Sel2 outputs the signal set {S[3], CA[3], CO[3]} because the corresponding count CO[3] (=4) is higher than CO[4] (=1).

[0134] Similarly, Figure 3c The comparison and counting based on the input signals S[5], S[6], S[7] and S[8] are illustrated. Figure 3b The description of applies mutatis mutandis. Selector Sel3 will output the signal set {S[6], CA[6], CO[6]} because the count CO[5] of the data value 5 (S[5]) is 1 and the count CO[6] of the data value 3 (S[6]) is 4. Selector Sel4 will output the signal set {S[8], CA[8], CO[8]} because the count CO[7] of the upper input data value 8 is the same as (i.e., not greater than) the count CO[8] of the lower input data value, which is also 8.

[0135] In this way, the eight signal sets are in the first selector subset 331 (see Figure 3a ) has been reduced to 4 signal sets, namely, Figure 3b {S[2], CA[2], CO[2]} and {S[3], CA[3], CO[3]} as described above and Figure 3c Described as {S[6], CA[6], CO[6]} and {S[8], CA[8], CO[8]}.

[0136] like Figure 3d As illustrated, these four signal sets are then provided in pairs to Figure 3a The second selector subset 332 is shown, including selectors Sel5 315 and Sel6 316. The data values ​​input to selector Sel5 are both 3 (= S[2], S[3]) and therefore have the same count 4 (= CO[2], CO[3]). Therefore, the signal set {S[3], CA[3], CO[3]} is output from Sel5. Selector Sel6 selects the signal set {S[6], CA[6], CO[6]} because the count CO[6] (= 4) is higher than the count CO[8] (= 2), so the "yes" branch is selected. As a side note, the subsystem including calculation units 301 to 304, selectors 311 to 312 and selector 315 is itself an embodiment of the present invention. For this subsystem, selector 315 is an "output selector" in the sense of the claimed invention. Similarly, the subsystem comprising computing units 305 to 308, selectors 313 to 314 and selector 316 is itself also an embodiment of the present invention. For this subsystem, selector 316 is an "output selector" in the sense of the claimed invention. Thus, a larger electronic system according to the present invention having a signal input interface configured to receive, for example, 8 or 16 signal sets will inherently include a plurality of subsystems having four inputs for receiving four data values ​​A[m], m=1, ..., 4, and having three selectors and outputting signal sets characterized in that no other data value A[m], m=1, ..., 4 has a higher value than the data value A[m] max ] count CO[m max ]High count CO[m].

[0137] Similar to the first selector subset 331 (Sel i , i = 1, ..., 4), the signal set output by the first selector subset 331 is output by the second selector subset 332 (Sel i , i=5,6) is reduced from 4 to 2.

[0138] like Figure 3d As shown, the third and final selector subset 333 (see also Figure 3a) selects between the two input signal sets {S[3], CA[3], CO[3]} and {S[6], CA[6], CO[6]} output by the second selector subset 332. In this case, the two sets are identical, so the "no" branch is selected. Therefore, the output from output selector Sel7 is the signal set {S[6], CA[6], CO[6]}. The most frequent data value is determined to be 3 (S[6]), with a frequency of 4 (CO[6]), and the corresponding comparison array is {1, 1, 1, 0, 0, 1, 0, 0}. Again, the comparison array shows where the most frequent value appears (via 1) and where it does not appear (via 0).

[0139] Similar to About Figure 4 , the input data array A2 may correspond to the intensity values ​​I[i] measured by the corresponding pixels in the CCD device 401, such as Figure 5 exemplified. Figure 5 The electronic system 500 includes the above Figures 3a to 3e The depicted electronic system 300 , and the CCD 401 coupled to the electronic system 300 via the analog-to-digital interface 502 , is used to read out the intensity values ​​in blocks of 8 digital values, which are provided to the electronic system 300 in parallel. Figure 5 The set of pixels 511 shown in corresponds to Figure 3b to Figure 3e , and therefore, when a block of eight pixels 511 is processed by the electronic system 300, a signal set {S[6], CA[6], CO[6]} is output from the electronic system 500. As a result, intensity 3 is determined to be dominant in the pixel block 511 of the image signal obtained by the CCD 401.

[0140] Similar to the example provided with respect to a 4-pixel input, in the case where there are two (or more) data values ​​that are both most frequent (multimodal distribution), different orders of the data values ​​may result in different results. For example, processing the data value array {1, 3, 1, 3, 1, 3, 4, 4} in electronic system 300 will result in a most frequent value of 3 and a comparison array of {0, 1, 0, 1, 0, 1, 0, 0}, while processing the data value array {1, 3, 1, 3, 3, 1, 4, 4} results in a most frequent value of 1 and a comparison array of {1, 0, 1, 0, 0, 1, 0, 0}, even though the data values ​​are identical except for the other positions in which they appear in the data array.

[0141] Electronic systems according to the present invention, such as electronic systems 100, 200 and 300, may also be used in combination with lossy or lossless data compression, such as for transmission over a data network.

[0142] If the only value of interest from a respective pixel block is the most frequent value, then instead of sending all data values, only the most frequent value (MFV) of the respective block is sent as part of the transmitted signal T, wherein the determined most frequent value is represented by a first signal portion T1, as shown in Figure 6a As shown. Figure 1b to Figure 1d In the example, the most frequent value is 1, and Figure 3b to Figure 3e In the example above, the most frequent value is 3. Figure 6a The value 3 is shown as an example ( Figure 3b to Figure 3e The most frequent value in the example) is included in the transmission part T1, such as Figure 6a As shown, in the case of an 8-bit resolution, this is equivalent to only 8 bits.

[0143] If the CCD consists of 1920x1080 pixels (processed by electronic system 100 or 200 in blocks of 4 pixels), the number of values ​​to be transmitted is reduced by a factor of 4, from 2073600 to 518400. If the pixels are divided into blocks of 8 instead of 4, as in electronic system 300, the number of values ​​to be transmitted is 259200.

[0144] In some cases, it may be desirable to know not only the most frequent value, but also its frequency within each block. This is achieved by sending the most frequent value and its frequency in the transmitted signal T, such as Figure 6b As shown, it also includes a count CO[j max ] of the second transmission part T2. Figure 3b to Figure 3e In the example in , the count of the most frequent value 3 is 4, so it is included, as Figure 6b As shown, for the data array {3, 3, 3, 4, 5, 3, 8, 8}, it is equivalent to 16 bits to be sent. Alternatively, as Figure 6c As shown, this is done by Figure 6a and Figure 6b The most frequent value MFV is transmitted in the first signal portion T1 and the comparison array CA is transmitted in the second signal portion T2 of the transmission signal T. max ] to achieve this. Figure 3b to Figure 3e In the example, the comparison array CA[j max ] is {1, 1, 1, 0, 0, 1, 0, 0}, so it is included, such as Figure 6c exemplified. exist Figure 6cIn the example of , it is equivalent to 16 bits. The latter embodiment has many advantages. In the case where each block processed corresponds to 8 pixels, the comparison array consists of 8 bits. On the receiving side, the number of 1 bits can be counted, which will correspond to the frequency of the most frequent value. In addition, since each element of the comparison array maps to a specific element within the pixel block, it can be derived which specific pixels have a value equal to the most frequent value. For Figure 4 In the array {1, 3, 4, 1}, it can be derived from comparing the array {1, 0, 0, 1} and the most frequent value 1 that the top left pixel and the bottom right pixel have the value 1. Figure 3b to Figure 3e In the example used in , the comparison array is {3, 3, 3, 4, 5, 3, 8, 8}, the most frequent value is 3, and the comparison array is {1, 1, 1, 0, 0, 1, 0, 0}, and it can be easily derived on the receiving side that the first three pixels in the top row and the second pixel in the bottom row have the most frequent value 3, and that the position information is equivalent to a single byte (one bit for each of the 8 data values). If the number of pixels in a block is 16, then two bytes (excluding the additional compression or encoding method applied) can be used to send the position information.

[0145] As will be readily appreciated by those skilled in the art, the order in which the information is sent may be as desired.

[0146] In another embodiment, in addition to the most frequent value, additional data values ​​are also transmitted, whereby the entire block is transmitted without loss. In this case, the transmitted signal T also contains a third signal portion T3, which contains values ​​that are not the most frequent values. This Figure 6d The data array {3, 3, 3, 4, 5, 3, 8, 8} is exemplified in FIG. Figure 6d As shown, the most frequent value 3 is sent as part T1 together with the comparison array {3, 3, 3, 4, 5, 3, 8, 8} sent as part T2 as described above, and the other values ​​4, 5, 8 and 8 are sent in this order in the third signal part T3. At the receiver, the values ​​4, 5, 8, 8 sent in the signal part T3 can be mapped to the positions of the comparison array with the value 0, whereby all information is sent without loss. In the example, instead of sending 8 values, only 5 values ​​(5×8 bits) need to be sent together with the comparison array, which requires one byte in the case of 8 pixels in the block. As also shown Figure 6d As shown in the example in , this amounts to 48 bits, rather than the 64 bits that would be required if the value were not sent using this method as shown in FIG. 6e.

[0147] If the redundancy is greater, the savings are also greater. On the other hand, if all values ​​are different, the system will need to send more information than necessary, namely both the most frequent value MFV (8 bits) and the comparison array, which is an extra byte. This makes a total of 72 bits when sending 8 pixels with 8-bit values. This can be overcome by sending the data value normally instead, which requires 64 bits instead of 72 bits. This is illustrated in Figure 6e.

[0148] In the present example where there are 8 pixels with 8-bit values, when there are 3 or more pixels with the same value, the system results in a reduced transmission requirement. If 2 pixels have the same value, the amount of data to be transmitted is the same as transmitting the data value indiscriminately, i.e. 8 bytes: 1 byte for the most frequent value, 1 byte constituting a comparison array, and 6 bytes corresponding to 6 values ​​other than the determined most frequent value. As described above, when the frequency of the most frequent value (i.e., the count CO[i] provided by the electronic system 300) is 1, the data values ​​in the block can be transmitted value by value. As described above, this will save 8 bits corresponding to the redundant comparison array (when the number of data values ​​is 8). In all other cases, the amount of data to be transmitted is the same (when the count of the most frequent value is equal to 2) or lower (when the count of the most frequent value is greater than 2). This depends on the number of pixels in the block and the resolution of the data value.

[0149] As will be readily appreciated by those skilled in the art, the electronic system according to the present invention is advantageously implemented as an integrated circuit, such as in a silicon chip. The logic described in detail above is implemented as a circuit obtained, for example, in a process comprising a synthesis process and a further process of converting the logic into an actual circuit layout (such as a CMOS-based circuit, e.g., based on silicon).

[0150] It should also be noted that the same logic can be provided in an infinite number of ways ("combinatorial"), which is also well known. The layout also depends on the technology node (65nm process, 40nm process, ...). Therefore, it would not be practical, clear or concise to define the invention in terms of physical circuit layout. Therefore, the invention has been described and defined in part in logical terms.

[0151] The different elements described herein may be provided as a single unit, or may be combined in various ways without departing from the scope of the claims, as will be readily appreciated by those skilled in the art after understanding the present disclosure. Functional units may be split into different units or combined with other units. Similarly, the transmission signal T may be organized in various ways without departing from the scope of the claims. In addition, as can be seen from the independent claims, different embodiments may be combined, such as embodiments 100 and 200, without departing from the scope of the claims.

[0152] Reference numerals list

[0153] 100: Electronic Systems

[0154] 101 to 104: Computing unit

[0155] 111 to 113: Selectors set in parallel configuration

[0156] 120: Signal input interface

[0157] 121 to 124: Input signal line

[0158] 131 to 133: Input signal line

[0159] 141 to 144: Signal lines connecting the output of the calculation unit and the input of the selector

[0160] 151 to 152: Signal line connecting the selector output terminal and the selector input terminal

[0161] 161: Output selector output signal line

[0162] 200: Electronic Systems

[0163] 211 to 213: Selectors set in cascade configuration

[0164] 251 to 152: Signal line connecting the selector output and the selector input

[0165] 300: Electronic Systems

[0166] 301 to 308: Computing unit

[0167] 311 to 317: Selectors set in parallel configuration

[0168] 320: Signal input interface

[0169] 321 to 328: Input signal line

[0170] 331 to 333: Selector subset

[0171] 341, 348: Signal lines connecting the output of the calculation unit and the input of the selector

[0172] 351 to 356: Signal lines connecting the selector output and the selector input

[0173] 361: Output selector output signal line

[0174] 400: Electronic Systems

[0175] 401: Image Sensor

[0176] 402: Analog-to-digital converter

[0177] 411: Pixels

[0178] 500: Electronic Systems

[0179] 502: Analog-to-digital converter

[0180] 511: Pixels

Claims

1. An electronic system (100, 200, 300, 400, 500), the electronic system being used to determine the most frequent value in a data array A during use of the electronic system, the data array A comprising a plurality of N data values ​​A[i], i=1, ..., N, N≥4, each data value A[i] corresponding to a corresponding data signal S[i], i=1, ..., N, the electronic system comprising a first electronic subsystem (100, 200, 300), the first electronic subsystem comprising: (i) a signal input interface (120, 320), used to receive the data signal S[i], i=1,...,N; (ii) First comparator set CA i,j , used to determine the corresponding comparison signal CA[i,j], i=1,...,N, j=1,...,N, wherein each comparison signal CA[i,j] indicates whether the data value A[i] is equal to the data value A[j]; (iii) Counter set CO i , i=1, ..., N, for determining corresponding counting signals CO[i], i=1, ..., N, wherein each counting signal CO[i] represents the number of times the data value A[i] appears in the plurality of data values ​​A; (iv) Selector set Sel i , i = 1, ..., M, each selector Sel in the selector set i include: - The first signal input terminal set SelIn1 i , which is configured to receive a first signal set {S[j], CA[j], CO[j]}, where 1≤j≤N and CA[j]={CA[j,1],...,CA[j,N]}, and - The second signal input terminal set SelIn2 i , which is configured to receive a second signal set {S[k], CA[k], CO[k]}, where 1≤k≤N, k≠j, -Select Line SelLine i , used to receive the selection signal SelSig i , the selection signal SelSig i Indicates whether CO[j]>CO[k] determined by the corresponding selection line comparator (171, 172, 173, 221, 222, 223), -Signal output terminal set SelOut i , the selector Sel i Configured to be in SelSig i In the case where CO[j]>CO[k], the output signal set {S[j], CA[j], CO[j]} is i Indicates the output signal set {S[j],CA[j],CO[j]} or the signal set {S[k],CA[k],CO[k]} when CO[j]≤CO[k], The selector set Sel i , i = 1, ..., M includes output selector Sel out , the output selector Sel out are interconnected so that the output selector Sel out Provides a signal set {S[j max ],CA[j max ],CO[j max ]},1≤j max ≤N as the output signal, where the signal set {S[j max ],CA[j max ],CO[j max ]} is characterized by the fact that no other data value A[k], k=1,...,N has a higher max ] count CO[j max ]High count CO[k].

2. The electronic system according to claim 1, wherein: Each selector Sel i , i = 1, ..., M is configured to be in SelSig i It represents the output signal set {S[j], CA[j], CO[j]} when CO[j]=CO[k].

3. The electronic system according to claim 1, wherein: Each selector Sel i , i = 1, ..., M is configured to be in SelSig i It represents the output signal set {S[k], CA[k], CO[k]} when CO[j]=CO[k].

4. The electronic system according to any one of claims 1 to 3, wherein: log2(N) is an integer, and wherein the first selector subset SelSub1 in the selector set i , each selector in i=1,...,N / 2 is configured to receive N signal sets {S[j],CA[j],CO[j]},j=1,...,N, at its first signal input terminal set and its second signal input terminal set, respectively, whereby the first selector subset outputs N / 2 signal sets, at least one of the N / 2 signal sets corresponding to the data value A[j max ].

5. The electronic system according to claim 4, wherein: The second selector subset SelSub2 in the selector set i , each selector in i=1,...,N / 4 is configured to receive the first selector subset SelSub1 i , i=1, ..., N / 2 outputs a corresponding pair of the N / 2 signal sets, whereby the second selector subset outputs N / 4 signal sets, at least one of the N / 4 signal sets corresponding to the data value A[j max ].

6. The electronic system according to claim 5, wherein: N≥8, and wherein the selector set further comprises one or more additional selector subsets SelSub arranged in series with each other and arranged in series with the second selector subset l , each further selector subset provides at its signal output a number of output signal sets that is half the number of output signal sets that said further selector subset receives at its signal input, at least one of said output signal sets from each further selector subset corresponding to the signal set {S[j max ],CA[j max ],CO[j max ]}, the final additional selector subset includes the output selector Sel out , whereby the signal set {S[j], CA[j], CO[j]}, j=1,...,N is gradually reduced by the electronic system to the output selector Sel out The signal output terminal outputs a single signal set {S[j max ],CA[j max ],CO[j max ]}.

7. The electronic system according to any one of claims 1 to 3, wherein: The selector set includes a first selector SelCasc1, which is configured to receive a first pair of signal sets in the signal set {S[j], CA[j], CO[j]}, j=1, ..., N, and further includes another selector set SelCasc1. i , i=2,...,N-1, the other selector SelCasc i , each selector in i=2, ..., N-1 is arranged to receive the signal from the previous selector SelCasc at its first signal input terminal set. i-1 , i=2,...,N-1 output signals and receives at its second signal input terminal set {S[j],CA[j],CO[j]},j=1,...,N signal sets that have not been provided as input to the selector set until all signal sets have been provided as input to the selectors in the selector set, whereby the signal set {S[j],CA[j],CO[j]} is received. max ],CA[j max ],CO[j max ]} is provided as the selector in the selector set SelCasc N-1 The signal output at the output terminal.

8. The electronic system according to any one of the preceding claims, further comprising: (i) an image sensor (401), the image sensor comprising a plurality of pixels p[i], i=1, ..., I, I≥4, for capturing an image signal, the image signal representing a set of intensity values ​​I[i], i=1, ..., I, each intensity value I[i], i=1, ..., I representing an amount of radiation captured by a corresponding pixel p[i], i=1, ..., I of the image sensor, (ii) an analog-to-digital interface ADC (402, 502), the ADC being configured to receive the image signal from the image sensor and to provide a corresponding digital image signal, the corresponding digital image signal representing the intensity value I[i], i=1,...,I ​​captured by the corresponding pixel p[i], i=1,...,I ​​in the image sensor, the ADC also comprising an ADC output interface, the ADC output interface being connected to the signal input interface (120, 320) to provide at least a portion of the digital image signal to the electronic system.

9. The electronic system according to claim 8, wherein: The ADC is configured to output portions of the digital image signal corresponding to N of the intensity values ​​in parallel on the ADC output interface.

10. The electronic system according to claim 9, wherein: The N intensity values ​​extracted from the intensity values ​​I[i], i=1, . . . , I correspond to a subset formed by N pixels p[i] arranged consecutively in the image sensor.

11. The electronic system according to claim 10, wherein: The N pixels P[i] are arranged in a two-dimensional array of L×P pixels, where L, P≥2, for example, L, P≥3, for example, L, P≥4.

12. The electronic system according to any one of claims 9 to 11, wherein: The ADC is further configured to sequentially provide the intensity values ​​I[i], i=1, ..., I, to the first electronic subsystem in blocks of N intensity values, the electronic system further comprising a transmitter system coupled to the first electronic subsystem and configured to output the intensity values ​​I[i] from the output selector Sel out receiving the output signal, the transmitter system is further configured to provide a transmission signal T, the transmission signal T comprising a value representing the most frequent value A[j max ]’s first signal part T1.

13. The electronic system according to claim 12, wherein: The transmission signal T includes a signal indicating the comparison array CA[j max ]’s second signal part T2.

14. The electronic system according to claim 12 or 13, wherein: The transmitted signal T comprises a third signal portion T3, wherein the third signal portion T3 represents the data in the data array A except the most frequent value A[j max ] other than the different data values.

15. An electronic system according to any one of the preceding claims, wherein: The first electronic subsystem is included in an application specific integrated circuit ASIC, the application specific integrated circuit comprising: (i) the signal input interface, (ii) the first set of comparators, (iii) the set of counters, (iv) the selector set, (v) the select line comparator, and (vi) a signal output interface configured to receive a signal from the output selector Sel out Provide the output signal {S[j max ],CA[j max ],CO[j max ]}.

16. A method for determining the most frequent value in a data array A, wherein the data array A comprises a plurality of N data values ​​A[i], i=1, ..., N, N≥4, each data value A[i] corresponding to a corresponding data signal S[i], i=1, ..., N, the method being performed in an electronic system (100, 200, 300), the method comprising the following steps: (i) receiving the data signal S[i] at the signal input interface of the electronic system, i=1, ..., N, (ii) determining a comparison signal set CA[i,j], i=1, ..., N, j=1, ..., N, wherein each comparison signal CA[i,j] indicates whether the data value A[i] is equal to the data value A[j], (iii) determining a counting signal set CO[i], i=1, ..., N, wherein each counting signal CO[i] represents the number of times a data value A[i] appears in the plurality of data values ​​A; the data signal, the comparison signal and the counting signal constitute a plurality of signal sets {S[i], CA[i], CO[i]}, i=1, ..., N, wherein CA[i]={CA[i,1], ..., CA[i,N]}, (iv) in a selector set, performing a plurality of signal selections, wherein each signal set in a signal set {S[i], CA[i], CO[i]}, i=1, ..., N, is selected or discarded based on a comparison with at least one other signal set {S[j], CA[j], CO[j]}, 1≤j≤N, i≠j, wherein the comparison is based on respective counts CO[i] and CO[j], each selection comprising: - in the case where CO[i]>CO[j], selecting in one of the selectors the signal set {S[i], CA[i], CO[i]} for comparison with the other signal set {S[k], CA[k], CO[k]}, i≠j≠k, and discarding the signal set {S[j], CA[j], CO[j]}, or - for CO[i]≤CO[j], selecting in one of the selectors one of the signal sets {S[i],CA[i],CO[i]} and {S[j],CA[j],CO[j]} for comparison with the other signal set {S[k],CA[k],CO[k]}, 1≤k≤N, i≠j≠k, and discarding the other of the signal sets {S[i],CA[i],CO[i]} and {S[j],CA[j],CO[j]}, (v) continuing step (iv) until one of the comparisons contains only a single signal set {S[j max ],CA[j max ],CO[j max ]}, 1≤j max All signals other than ≤N have been discarded, and (vi) providing a signal set {S[j max ],CA[j max ],CO[j max ]}.

17. The method according to claim 16, wherein: The data signal S corresponds to respective N signals captured by an image sensor, wherein each of the N signals represents an amount of radiation captured by respective N pixels in the image sensor, such as N consecutive pixels in the image sensor.

Images