Memory calibration and tolerance checking

Abstract

Memory calibration with margin checking is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes calibration circuitry configured to: perform horizontal memory calibration for some of a plurality of performance states during an initialization process; and determine information indicating a set of differences between calibration results for pairs of performance states in the plurality of performance states and store the information in a memory circuit. The memory controller is further configured to: after the initialization process and in response to a change from a first performance state in the plurality of performance states to a second performance state in the plurality of performance states, set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

Description

Background Art Technical Field

[0002] The present disclosure relates to memory subsystems, and more particularly to calibration performed in memory subsystems.

[0003] Related technical description

[0004] An eye pattern or eye diagram is a graphical representation of the time and amplitude at which a digital signal can be sampled at its correct value. In various types of systems, including data transmission, it is desirable to sample a signal (e.g., a data signal synchronized by a clock signal) near the center of the eye, based on both timing and sampling voltage. This can provide the signal with both sufficient setup and hold times while also making it less susceptible to noise. This can enable more accurate determination of logic values ​​(e.g., logic 1 or logic 0) based on a reference voltage used to distinguish one logic value from another, based on timing and sampling voltage.

[0005] In the memory subsystem, calibration can be performed to determine the points within the eye diagram at which signals are sampled. Calibration is performed to determine an eye diagram that enables accurate sampling of signals and therefore includes calibration based on both timing (sometimes referred to as horizontal calibration) and sampling reference voltage (sometimes referred to as vertical calibration). Performing these calibrations typically involves adjusting a number of different parameters that govern the transfer of data between the memory controller and the memory. These parameters include the delay applied to the data strobe signal during horizontal calibration. Vertical calibration can include multiple horizontal calibrations performed at different reference voltages. Such calibrations can be performed during system startup and can also be performed periodically thereafter. Calibration can also be performed in response to changes in performance status. Summary of the Invention

[0006] Memory calibration with margin checking is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes calibration circuitry configured to: perform horizontal memory calibration for some of a plurality of performance states during an initialization process; and determine information indicating a set of differences between calibration results for pairs of performance states in the plurality of performance states and store the information in a memory circuit. The memory controller is further configured to: after the initialization process and in response to a change from a first performance state in the plurality of performance states to a second performance state in the plurality of performance states, set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

[0007] In one embodiment, after commencing operation in the second performance state, the calibration circuitry may perform a margin check calibration. When performing the margin check calibration, the calibration circuitry runs a calibration routine at two points. The points correspond to delay values ​​applied to a data strobe signal used to synchronize data transfers between the memory and the memory controller. The first point of the margin check calibration is at a delay less than the most recently calibrated value, while the second point is at a delay greater than the most recently calibrated value. If a passing result is obtained at both points, the full level calibration is skipped and operation continues using the most recently calibrated parameter values ​​(e.g., those parameter values ​​applied based on the set of differences). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0009] Figure 1 is a block diagram of one embodiment of a memory subsystem.

[0010] Figure 2 is a block diagram of one embodiment of a memory controller.

[0011] Figure 3 is a block diagram of one embodiment of a system.

[0012] Figure 4 is a diagram of one embodiment of a tolerance limit check calibration.

[0013] Figure 5 is a flow chart of one embodiment of a method for operating a memory subsystem.

[0014] Figure 6 is a flow chart of one embodiment of a method for operating a memory subsystem.

[0015] Figure 7 is a flow chart of one embodiment of a method for operating a memory subsystem.

[0016] Figure 8 is a block diagram of one embodiment of an example system. DETAILED DESCRIPTION

[0017] This disclosure relates to various methods for calibrating parameters used in the operation of a memory subsystem and setting these parameters for normal operation. Memory calibration includes horizontal calibration, in which multiple different delays are applied to a data strobe signal used to synchronize data transfers between a memory controller and memory. When performing these calibrations, optimal delay values ​​can be determined.

[0018] Memory calibration can be time-consuming to perform. During the time that calibration is performed in the memory subsystem, the memory is unavailable for normal read and write traffic, thereby impacting other agents that need to read data from or write data to the memory.

[0019] Memory calibration is performed not only periodically but also in response to frequency changes (e.g., changes in the frequency of the clock signal). In multi-rank memory systems (systems with multiple DRAMs sharing common pins), the time spent on calibration increases. For real-time applications, the time spent calibrating the memory during frequency changes can negatively impact overall system performance.

[0020] Many computing systems operate in different ones of a plurality of performance states. A performance state is defined herein as a unique combination of operating voltage and clock frequency. Certain performance states may be used when performance is a priority (e.g., when there is a high workload), while other performance states may be used when power conservation is a priority (e.g., when the workload is light). During certain initialization operations (e.g., such as a cold boot), calibration may be performed in each of a plurality of different performance states. The present disclosure utilizes the insight that calibration results may be recorded, just as the difference between calibration results obtained in two different performance states may be recorded.

[0021] Thus, the present disclosure includes a memory controller having circuitry for performing calibration in each of various possible system performance states during an initialization process and determining the difference in the results between each possible pair of states within these states. This insight also recognizes that operating conditions encountered during the initialization process may differ from those encountered during normal operation (e.g., non-calibrated, post-initialization operation of the system performing its intended functions). The differences between each possible pair of performance states are calculated and stored in a memory circuit. Thereafter, when a change is made from a first performance state to a second performance state, the calculated differences in calibrated operating parameters are used to set operating parameters for the second performance state. For example, if the calculated difference in calibrated digital strobe delays between a first performance state and a second performance state is a certain number of picoseconds, upon entering the second performance state, the delay of the second state can be set by adjusting the delay of the first state by the calculated difference. After adjusting the parameters by the calculated difference between the two performance states, operation can begin without performing a level calibration. Consequently, the start of operation in the second performance state is not delayed by the amount of time required to perform a full level calibration, thereby reducing the amount of time the memory subsystem is unavailable.

[0022] The present disclosure also exploits the insight that time can be saved by performing a tolerance check on specific calibration parameters (e.g., the delay value applied to the data strobe). Accordingly, the present disclosure contemplates a tolerance check calibration. In a tolerance check calibration, a limited number of points (e.g., two) can be checked to determine whether they produce a passing result (e.g., where a passing result includes that the data read from the memory is equal to the expected data). In one embodiment, this can be performed by performing calibration at a first delay point having a delay that is less than the current operating delay point and a second delay point having a delay amount that is greater than the current operating delay point. If a passing result is obtained at these two points, the full horizontal calibration is skipped. This can significantly reduce the amount of time that the memory is unavailable for normal operation. On the other hand, if at least one of these delay points returns a failing result, a full horizontal calibration can be performed.

[0023] Using the various methods described herein, memory unavailability can be significantly reduced. Furthermore, through the various examples of the aforementioned full-level calibration, power savings and systems with better power-performance ratios can be achieved.

[0024] Various details of a memory subsystem and methods for operating the memory subsystem according to the present disclosure will now be discussed. This discussion begins with various apparatus embodiments, including a more detailed discussion of the memory subsystem, memory controller, and larger systems. An illustration of one embodiment of margin check calibration is then described, followed by a discussion of various method embodiments. The description concludes with a discussion of various embodiments of an example system that may include a memory subsystem according to the present disclosure.

[0025] Memory Subsystem Implementation :

[0026] Figure 1 is a block diagram of one embodiment of a memory subsystem. In the illustrated embodiment, the memory subsystem 100 includes a memory controller 105 and a memory 110. In one embodiment, the memory 110 is a dynamic random access memory (DRAM), but other types of memory are possible and contemplated. The memory controller 105 and the memory 110 are coupled to transmit data signals between each other to perform read and write operations. Additionally, the memory controller 105 is configured to transmit a data strobe signal to the memory 110. The data strobe signal is a clock signal that is used to synchronize the transfer of data between the memory controller 105 and the memory 110 during the execution of read and write operations. It is noted that in some embodiments, separate data strobe signals may be used to perform read and write operations, wherein the memory controller 105 and the memory 110 are configured accordingly.

[0027] The memory controller 105 in the illustrated embodiment includes calibration circuitry 106 and storage circuitry 107. Calibration circuitry 106 can be used to perform calibration operations to ensure that data can be written to and received from memory 110 at the correct values. Calibration can include horizontal calibration, in which a delay value is applied to a data strobe signal while the data received from memory 110 is evaluated to ensure that it is correct. The delay value can be applied within a specific range, and the calibration value can be selected based at least in part on a delay value that provides sufficient timing margin.

[0028] A vertical calibration may also be performed, where the vertical calibration comprises multiple horizontal calibrations performed at different values ​​of a reference voltage used to distinguish between a logic 1 and a logic 0 for a signal received from the memory. The vertical calibration may be used to select a reference voltage that provides sufficient voltage margin for reading data returned from the memory. Thus, the results of the horizontal and vertical calibrations may generate an eye diagram that defines the delay range and voltage range over which data may be correctly read from the memory. While performing the horizontal and vertical calibrations, the memory controller 105 may perform a series of writes to the memory and a series of reads of data from the memory. Comparing the read data with the expected (e.g., written) data may determine whether a particular calibration point passed or failed.

[0029] The memory subsystem 100 can operate in multiple different performance states. A performance state is defined herein as a unique combination of operating voltage and clock frequency. The operating voltage is represented herein by the supply voltage Vdd, while the clock frequency is represented by the clock signal input Clk_In. Different performance states may be used depending on the desired performance of the system. For high workloads, such as when multiple different agents are requesting access to the memory 110, a higher performance state (e.g., a higher clock frequency and / or operating voltage) may be used. For lower performance requirements (e.g., when memory access requests are relatively infrequent), the memory subsystem 100 may operate in a lower performance state (e.g., a lower clock frequency and / or a lower supply voltage). The various calibrations discussed above may be performed for each of the different performance states available for the memory subsystem. In one embodiment, each of the performance states may undergo calibration as discussed above during an initialization process (e.g., when an initialize signal is asserted). This initialization process may include various system boot procedures, including cold boot and warm boot. Exiting a sleep state is another initialization process during which calibration may be performed for all performance states.

[0030] In the illustrated embodiment, calibration results may be stored in storage circuit 107. The calibration results indicate the range of delays and reference voltages for which pass results were obtained, as well as the specific delay points and reference voltage points selected for operation. During the initialization process described above, calibration circuit 106 may store the results of various calibrations performed in different performance states in storage circuit 107. Furthermore, in the illustrated embodiment, calibration circuit 106 may calculate the differences in various parameters for pairs of performance states and store these differences in storage circuit 107. These differences may be used in subsequent operations during a change from one performance state to another. For example, during a change from a first performance state to a second performance state, the parameters used upon entering the second performance state are determined by applying the differences between the first and second performance states to the parameters of the first performance state. Setting the parameters in the second performance state in this manner, rather than directly using the calibration parameters for the second performance state, may account for operating conditions (e.g., temperature) that may have changed since the time the previous calibration was performed.

[0031] As described above, after applying the difference to set operating parameters for the second performance state, normal operation can begin without performing a level calibration. Thus, by setting parameters based on the applied difference instead of a full level calibration, the amount of time the memory subsystem is unavailable during the switch from the first performance state to the second performance state is reduced.

[0032] At some point after normal operation in the second performance state, a margin check calibration may be performed to verify that the current operating parameters are still valid. Margin check calibration is a limited calibration in which only a few delay points are checked to determine the result. In one embodiment, margin check calibration is performed at a first delay point having a smaller delay than the current delay point and a second delay point having a larger delay than the current delay point. If a passing result is obtained at both the first delay point and the second delay point, margin check calibration is not performed, and operation in the second performance state is resumed using the current parameters. On the other hand, if at least one of these delay points returns a failing result, a full margin check calibration is performed (which may also or alternatively include invoking a fatal interrupt). When the full margin check calibration is performed, the results of the second performance state stored in storage circuit 107 may be updated. Additionally, the difference between the calibration results of the first and second performance states may also be updated based on the results of the full margin check calibration performed in the second performance state. Note that in some instances, a heuristic may be used to determine the updated difference rather than directly applying the difference. For example, a heuristic may be applied based on the difference in operating conditions (e.g., temperature) between the current time and the previous time at which the difference was calculated to compensate for the changed operating conditions.

[0033] In some embodiments, the number of times a tolerance check calibration can be performed is limited to a certain threshold. Thus, when determining whether to perform a tolerance check calibration, a determination is made as to the number of times that type of calibration has been performed since entering the second performance state. If this number does not exceed the threshold, a tolerance check calibration can be performed. Furthermore, assuming a passing result is returned each time, a tolerance check calibration can be performed periodically as long as the threshold is not exceeded. However, if the number of level calibrations exceeds the threshold, a full level calibration is performed. This full level calibration can include updating the calibration parameters for the second performance state and the differences of the paired performance states including the second performance state.

[0034] Figure 2 2 is a block diagram of one embodiment of a memory controller. In the illustrated embodiment, memory controller 205 includes calibration control circuitry 206 and physical interface 214. Calibration control circuitry 206 in the illustrated embodiment implements various circuit elements, including data comparator 218, eye calculator 211, and state machine 210. Physical interface 214 implements circuitry for communicating with a memory (not shown here). The circuitry of physical interface 214 includes transceiver 220 and delay circuit 230. Data to be written to the memory can be received by the memory controller via the DQ_In signal path. Data read from the memory can be transmitted to the requester via the DQ_Out data bus.

[0035] In the illustrated embodiment, the transceiver 220 of the physical interface 214 is coupled to a data bus including a data signal path DQ[N-1:0]. Additionally, the physical interface 214 includes a delay circuit 230 from which a data strobe signal DQS is generated (based on a variable frequency clock signal Clk_In) and transmitted to the memory to synchronize data transfer. The physical interface 214 may also include circuitry (not shown here) for adjusting various I / O settings associated with sending and receiving signals to and from the memory. This may include circuitry for adjusting the drive strength of the signal, controlling the impedance and / or termination of the signal line, and the like.

[0036] It should be noted that in various embodiments, additional signal paths may be coupled to the physical interface 214. These signal paths may include paths for transmitting write enable signals, read enable signals, address signals, etc. from the memory controller 205 to the correspondingly coupled memories. Similarly, the physical interface 214 may include circuitry for generating these signals and may include additional circuitry for receiving signals. For simplicity, these additional signal paths and circuitry are omitted here, but their absence from the figures is not intended to limit the present disclosure in any way.

[0037] During a read operation, transceiver 220 can receive signals transmitted from the memory via signal paths DQ[N-1:0]. Transceiver 220 can also use a reference voltage value (e.g., generated by a reference voltage generator circuit, not shown here) to interpret the received signal. This reference voltage can be set by eye calculator 211 via the ReadV signal path. Using this reference voltage, transceiver 220 can determine whether a single data signal in the received data signal should be interpreted as a logic 0 or a logic 1. During normal operation, when transceiver 220 is operating to receive data from the memory, the output of the transceiver is the DQ_Out signal path, where the data is transmitted to other units (e.g., to a requesting agent such as a processor core).

[0038] The delay circuit 230 in the illustrated embodiment is coupled to receive an input clock signal, Clk_In, provided from a source external to the memory controller 205. Although not explicitly shown, the delay circuit 230 may include one or more delay-locked loops (DLLs) or other types of delay circuits. A delay may be applied to the input clock signal to generate a data strobe signal, DQS, which is used to synchronize the transfer of other signals (e.g., DQ[N-1:0]) between the memory and the memory controller 205. The amount of delay applied may be based on a delay control signal, Dly_Ctl, provided by the eye calculator 211 in the calibration control circuit 206. In addition to transmitting the data strobe signal to the memory, the delay circuit 230 in the illustrated embodiment is also coupled to provide a clock signal to the transceiver 220.

[0039] The calibration operation may include changing the reference voltage and the amount of delay applied to the data strobe signal. Horizontal calibration may include changing the delay at multiple different values ​​at a specific reference voltage. Vertical calibration may include performing multiple horizontal calibrations at different reference voltage values. At each combination of delay and reference voltage, data may be read from the memory and compared to the expected value by the data comparator 218 to determine whether any bit failures have occurred. A bit failure may be defined herein as a bit corresponding to a signal transmitted on a specific signal path of the data bus that does not match its expected value (e.g., when a logic 1 is expected, the bit is read as a logic 0). In some embodiments, the compared data may be received by the data comparator 218 via the DQ_In input, and therefore the corresponding calibration operation may include writing the data to the memory.

[0040] A bit failure may be reported to the eye calculator 211. In response to receiving information about a bit failure, the eye calculator 211 may record the failed bit along with a reference voltage value and a delay value. Based on the data from the failed bit and the corresponding reference voltage value and delay value, the eye calculator 211 may calculate an eye diagram. In some embodiments, the eye diagram may be calculated separately for each bit position, where the eye diagram is calculated based on, for example, an average value of a single signal path.

[0041] In addition to multiple data reads from memory, some calibration operations may also include multiple data writes to memory. Through multiple iterations, eye calculator 211 may cause adjustments to both the delay used to generate the data strobe signal (via the Dly_Ctl signal) and the voltage used to distinguish between a logic 1 and a logic 0. Performing these operations for multiple different delay values ​​and reference voltage values ​​may be used to define an eye diagram for the calibrated signal path. Figure 2 An example eye diagram is shown in FIG, wherein the height H of the eye diagram is defined along the vertical voltage axis V and the width W is defined along the time axis T. The voltage axis represents the value of the reference voltage, while the time axis represents the delay value applied to the data strobe signal by the delay circuit 230. Values ​​within the boundaries indicated in the figure (defined in part by the height and width of the eye diagram) indicate the area in which the data bits transmitted in the signal can be correctly interpreted as a logic 1 or a logic 0. Areas toward the center of the eye diagram generally have a greater amount of timing tolerance and voltage tolerance than areas located toward the boundaries.

[0042] In the illustrated embodiment, the state machine 210 is configured to coordinate calibration operations. In response to receiving a calibration signal (Cal) from within another portion of the memory controller 205 or from an external source, the state machine 210 may initiate a calibration operation. Assertion of the calibration signal may occur in conjunction with system startup, upon exiting a sleep state, at periodic intervals, and in response to changes in performance state, among other conditions. During a calibration operation, the state machine 210 may communicate with the eye calculator 211, the data comparator 218, and the transceiver 220. Among the functions that the state machine 210 may perform are issuing commands to send data for write operations, causing the memory controller 205 to read data from memory, and causing changes in delay and reference voltage values. Upon completion of a given calibration, the eye calculator 211 may store the determined reference voltage and delay values. These values ​​may then be used to set reference voltage and delay values ​​for normal (e.g., non-calibration) operation.

[0043] State machine 210 may also cause calculation of differences between pairs of performance states, for example, through eye calculator 211. These differences, along with the calibration results on which they are based, may be stored in storage circuit 207. During a change from one performance state to another, calibration circuit 206 may access these differences and cause eye calculator 211 to set operating parameters (delays and reference voltages) for operating in the newly entered performance state. Subsequently, in some embodiments, state machine 210 may cause margin check calibration to be performed and, if a passing result is obtained, cause level calibration to be skipped. In some embodiments, state machine 210 may also determine whether the number of margin check calibrations has exceeded a threshold. If it is determined that the number of margin check calibrations has exceeded the threshold, state machine 210 may cause a full level calibration to be performed. Otherwise, if the number is less than the threshold, state machine 210 may instead cause another instance of margin check calibration to be performed instead of performing a full level calibration. However, if the margin check calibration returns a failure result, state machine 210 may, in response, cause a full level calibration to be performed.

[0044] Figure 3 is a block diagram of one embodiment of a system including a memory controller and a dual-rank memory. In the embodiment shown, the memory controller 305 may be a memory controller according to the embodiments discussed above. More generally, the memory controller 305 in the embodiment shown is capable of performing Figure 1 and Figure 2 , regardless of its internal arrangement. Memory controller 305 is coupled to various agents (not shown here), such as one or more processor cores, one or more graphics processors, and one or more input / output circuits. In general, memory controller 305 can be coupled to any agent that utilizes system memory. The actual coupling of memory controller 305 to these agents can be performed through an on-chip network / fabric including circuitry such as a crossbar switch.

[0045] The dual-rank memory in the illustrated embodiment includes a memory 310-1 (rank 1) and a memory 310-2 (rank 2). The two memories are coupled to a memory controller 305 via a memory bus configured to transmit data signals DQ[N-1:0]. Select signals are also provided from the memory controller 305 to the memories 310-a and 310-2 to select one of the memories for read and / or write operations.

[0046] System 300 also includes power management circuitry 320, a power converter 325, and a clock generator 321. In the illustrated embodiment, power converter 325 is configured to generate an adjustable supply voltage, Vdd, that is provided to memory controller 305 and memories 310-1 and 310-2. Any suitable type of power converter may be used, including various types of buck converters, boost converters, low-dropout regulators, and the like. Clock generator 321 is configured to generate a clock signal provided to memory controller 305, wherein the clock signal has an adjustable frequency. The circuitry of clock generator 321 may include a phase-locked loop, a ring oscillator, and / or any other suitable circuitry for generating clock signals at multiple different frequencies. Power management circuitry 320 in the illustrated embodiment may control the performance state of system 300. The Vctrl signal, shown here, may represent one or more signals or commands for causing power converter 325 to reach an operating voltage at a desired performance state. Similarly, the power management circuit 320 may send a command labeled Fctrl to the clock generator 321 to set the frequency of the clock signal Clk_In to a value corresponding to the desired performance state. Although not explicitly shown here, the power management circuit 320 may be coupled to a plurality of other circuits within the system 300 (including circuits not shown here) and may monitor operating conditions through various telemetry to select the optimal performance state.

[0047] Graphical representation of tolerance limit check calibration :

[0048] Figure 4 is a diagram of an embodiment of a tolerance check calibration according to the present disclosure. The tolerance check calibration can be used to verify that the current delay value applied to the data select signal determined by a previous calibration is still valid. This can be performed by calibrating at two points, tolerance calibration point 1 and tolerance calibration point 2. Tolerance calibration point 1 represents a delay that is less than the current operating point determined by the previous / initial calibration. Tolerance calibration point 2 represents a delay that is greater than the current operating point. At these two points, multiple data writes to the memory and multiple data reads from the memory can be performed. The data read from the memory is then compared with the expected data (e.g., the data that has been written) to determine whether they match. If the data read matches the expected data at both tolerance calibration points, the tolerance check calibration is considered to have passed, and operation continues using the same operating point. If the data read from the memory does not match the expected data at one or both points, the tolerance check calibration is considered to have failed, and a full level calibration is then performed.

[0049] A successful margin check calibration that produces a passing result can be performed in significantly less time than a full level calibration.Thus, a passing instance of a margin check calibration can significantly reduce the time that the memory subsystem is unavailable.

[0050] Method flow chart :

[0051] Figure 5 is a flow chart of one embodiment of a method for operating a memory controller. Method 500 may be performed by any of the device embodiments discussed above. In addition, device embodiments capable of performing method 500 but not explicitly disclosed herein are also considered to fall within the scope of this disclosure.

[0052] Method 500 includes performing, by a memory controller, horizontal memory calibration for some of a plurality of performance states during an initialization process (block 505). The method also includes determining, by the memory controller, a set of differences between calibration results for pairs of performance states in the plurality of performance states (block 510), and storing, by the memory controller, information indicating the set of differences (block 515). After the initialization process and in response to a change from a first performance state in the plurality of performance states to a second performance state in the plurality of performance states, the method includes setting initial memory parameters for the second performance state in the plurality of performance states, the initial memory parameters based on the set of differences (block 520), and starting operation in the second performance state in the plurality of performance states using the initial memory parameters without performing an initial horizontal memory calibration (block 525).

[0053] In various embodiments, the method includes performing a margin check calibration using a calibration circuit. Performing the margin check calibration includes determining whether a calibration result at a first point provides a passing result, wherein the first point corresponds to a delay value less than a calibrated delay point, and determining whether a calibration result at a second point provides a passing result, wherein the second point corresponds to a delay value greater than the calibrated delay point. In response to determining that the calibration results at the first point and the second point are passing results, the method includes skipping performing a full level calibration in the second performance state. Otherwise, the method includes performing a full level calibration if at least one of the calibration results from one of the first point and the second point does not produce a passing result. Alternative embodiments are also possible and contemplated in which an interrupt can be called in response to failing the margin check calibration. In such embodiments, an interrupt handler can be used to disable the use of future margin check calibrations during operation in a particular performance state, for example, in the event of excessive failures.

[0054] A given performance state of one of the plurality of performance states includes a unique combination of operating voltage and clock frequency relative to other performance states in the plurality of performance states. The initialization process may be a startup routine (e.g., a system boot procedure). The present disclosure contemplates that the initialization routine may also be a wakeup from a sleep state or a system reset that does not otherwise include a full system reboot.

[0055] Figure 6 6 is a flow chart of another embodiment of a method for operating a memory subsystem. Method 600 may be performed by various device embodiments discussed above. Device embodiments capable of performing method 600 but not otherwise disclosed herein are also considered to fall within the scope of this disclosure.

[0056] Method 600 begins by performing calibration in some of a plurality of different performance states during an initialization routine and storing the results in a storage circuit along with the differences between the calibration results in the various performance states (block 605). The calibration performed includes horizontal calibration, in which various delay amounts are applied to a data strobe signal to determine a delay value to be applied to sampling during subsequent operation. The present disclosure further contemplates performing vertical calibration, which includes performing horizontal calibration at a plurality of different reference voltage values, where the reference voltage is a sampling voltage used to determine whether a received signal is a logic 0 or a logic 1. By performing these calibrations, an eye diagram can be determined so that the signal can be sampled with an optimal amount of timing and voltage tolerance.

[0057] After calibration is completed during the initialization routine, normal operation then begins in the first performance state. Normal operation is defined herein as the memory subsystem performing its intended operations to support the intended system functions. For the memory subsystem, this includes reading data to be provided to other agents (e.g., reading operands to be used in operations performed by the processor core), writing and storing data received from other agents (e.g., writing / storing results from operations performed by the processor core), etc. The initialization routine can be system startup (e.g., cold boot), reset (e.g., warm boot), wakeup from a sleep state, etc. The first performance state can be any of a plurality of performance states for which calibration is performed during the initialization routine.

[0058] Method 600 also includes changing from operation in the first performance state to a second performance state and setting an operating parameter based on the difference between these states while skipping the execution of a horizontal calibration in the second performance state (block 615). For example, if there is a particular difference between the delay value for sampling a signal in the first performance state and the delay value for sampling a signal in the second performance state, the parameter is adjusted by that amount upon entering the second performance state. Other parameters (e.g., reference voltage) may also be similarly adjusted. These adjustments may be made to allow operation in the second performance state to begin with minimal delay relative to the delay that would be incurred by performing a full horizontal calibration.

[0059] At some point after normal operation begins in the second performance state, a margin check calibration is performed (block 620). As discussed above, the margin check calibration is a limited calibration that can be performed in lieu of a full-level calibration and can be performed by executing the calibration routine at two different delay points. The delay at the first point is less than the delay at the current operating point, while the delay at the second point is greater than the delay at the current operating point. If the margin check calibration obtains a passing result at both points (block 625, yes), the full-level calibration is skipped (block 630). A passing result is defined herein as data read from the memory being equal to the expected data. A passing margin check calibration may indicate that current operating parameters remain valid under the current operating conditions in the second performance state. Additionally, performing the margin check calibration in lieu of the full-level calibration may reduce the amount of time the memory subsystem is unavailable for normal memory transactions due to calibration. If the margin check calibration fails to obtain a passing result from at least one of the first or second points (block 625, no), a full-level calibration is performed (block 635).

[0060] Figure 7 is a flow chart of another embodiment of a method for operating a memory subsystem. Method 700 may be performed by various device embodiments discussed above. Device embodiments capable of performing method 700 but not otherwise disclosed herein are also considered to fall within the scope of this disclosure.

[0061] Method 700 begins by operating in a second performance state using difference-based parameters after switching from operating in a first performance state (block 705). The difference-based parameters are those determined based on calculated differences determined when performing horizontal memory calibration in various performance states during the system initialization process. After operating in the second performance state for a period of time, a check may be performed to determine the number of margin check calibrations that have been performed since entering that state (block 710). If the number of margin check calibrations is not greater than a certain threshold (block 710, no), a capacity check calibration is performed (block 715). As discussed above, margin check calibration involves performing calibration at two different delay points relative to the current operating delay point and determining whether a passing result is obtained. If the margin check calibration produces a passing result at both points (block 720, yes), the full horizontal calibration is skipped (block 725), and method 700 returns to block 705.

[0062] If it is determined that the number of margin check calibrations performed while operating in the second performance state has exceeded the threshold (block 710, yes), a full horizontal calibration is performed (block 730). The full horizontal calibration may be performed at a plurality of different points within a wider range of delay values ​​than the margin check calibration. If the number of margin check calibrations does not exceed the threshold (block 710, no), but at least one of the points did not provide a passing result during the margin check calibration (block 720, no), a full horizontal calibration is performed.

[0063] In the embodiment of the method 700 illustrated herein, it is assumed that once the number of tolerance check calibrations has exceeded a threshold, the subsequent periodic calibrations performed while maintaining the current performance state are full level calibrations. However, embodiments are possible and contemplated in which a full level calibration is performed only when the number of tolerance check calibrations following a level calibration exceeds a threshold or when a particular tolerance check calibration provides a failure result. Otherwise, as long as the tolerance check calibration continues to produce a passing result, the tolerance check calibration can be performed at periodic intervals until the number of tolerance calibrations performed since the most recent level calibration exceeds a threshold. In this way, the majority of calibrations performed after entering a particular performance state can be tolerance check calibrations, thereby further reducing the amount of time the memory subsystem is unavailable for normal memory transactions.

[0064] It is also noted that the calculated differences can be updated after a full level calibration is performed. For example, when a full level calibration is performed in a second performance state after having previously operated in a first performance state, the results from the full level calibration (in the second state) can be used to calculate updated differences relative to the results of the most recent level calibration performed in the first performance state. In this way, the current set of differences can more accurately reflect the system operating conditions that change over time. As further noted above, embodiments are possible and contemplated in which heuristics can be applied to, for example, take into account changes in operating conditions (such as temperature) rather than directly applying the differences. Thus, previously calculated differences can be modified by heuristics to take into account current operating conditions relative to those operating conditions that existed during their initial calculation.

[0065] Example System :

[0066] Next go to Figure 8, which shows a block diagram of one embodiment of a system 800 that can incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 800 includes at least one instance of a system on a chip (SoC) 806, which can include various types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other communication structures, as well as interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 806 include multiple execution lanes and instruction issue queues. In various embodiments, SoC 806 is coupled to external memory 802, peripheral devices 804, and a power supply 808.

[0067] A power supply 808 is also provided that supplies a supply voltage to the SoC 806 and one or more supply voltages to the memory 802 and / or peripherals 804. In various embodiments, the power supply 808 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, or tablet computer, or other device). In some embodiments, more than one instance of the SoC 806 is included (also including more than one external memory 802).

[0068] The memory 802 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3, etc., and / or low-power versions of SDRAM such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the device can be mounted together with an SoC or integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

[0069] The SoC 806 in the illustrated embodiment may include at least one memory controller coupled to the memory 802, wherein the memory controller and the memory form a memory subsystem. The memory controller may include calibration circuitry that performs various memory calibrations as discussed above. These calibrations may include level calibrations and margin check calibrations as disclosed herein.

[0070] Depending on the type of system 800, peripherals 804 include any desired circuitry. For example, in one embodiment, peripherals 804 include devices for various types of wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, and the like. In some embodiments, peripherals 804 also include additional memory, including RAM storage, solid-state storage, or disk storage. Peripherals 804 include user interface devices such as a display, including a touch display or a multi-touch display, a keyboard or other input device, a microphone, a speaker, and the like.

[0071] As shown, system 800 is shown as having applications in a wide range of fields. For example, system 800 can be used as part of a chip, circuit, component, etc. of a desktop computer 810, a laptop computer 820, a tablet computer 830, a cellular or mobile phone 840, or a television 850 (or a set-top box coupled to a television). Also shown are a smartwatch and a health monitoring device 860. In some embodiments, smartwatch 860 can include various general computing-related functions. For example, smartwatch 860 can provide access to email, mobile phone services, the user's calendar, etc. In various embodiments, the health monitoring device can be a dedicated medical device or otherwise include dedicated health-related functionality. For example, the health monitoring device can monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communications to emergency services in the event of a health crisis, etc. In various embodiments, the smartwatch described above may or may not include some or all of the health monitoring-related functions. Other wearable devices are also contemplated, such as devices worn around the neck, devices that can be implanted in the human body, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0072] The system 800 can also be used as part of a cloud-based service 870. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, the system 800 can be used in one or more devices in a home other than those previously mentioned. For example, home appliances can monitor and detect noteworthy conditions. For example, various devices in a home (e.g., a refrigerator, a cooling system, etc.) can monitor the status of the devices and provide an alert to the homeowner (or, for example, a maintenance facility) if a specific event is detected. Alternatively, a thermostat can monitor the temperature in a home and automatically adjust the heating / cooling system based on a history of the homeowner's responses to various conditions. Figure 8Also shown are applications of system 800 to various modes of transportation. For example, system 800 may be used for control and / or entertainment systems for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), and the like. In various cases, system 800 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, and the like. Any of these and many other embodiments are possible and contemplated. Note that Figure 8 The devices and applications shown are illustrative only and are not intended to be limiting. Other devices are possible and contemplated.

[0073] ***

[0074] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). An embodiment is different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a specific embodiment," etc., are not necessarily to the same embodiment. Numerous possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of this disclosure.

[0075] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are many reasons why an implementation falling within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular implementation may include additional circuitry outside the scope of this disclosure that, in combination with one of the disclosed embodiments, negates or mitigates one or more of the disclosed advantages. Furthermore, suboptimal design implementation of a particular implementation (e.g., a particular implementation technique or tool) may also negate or mitigate the disclosed advantages. Even assuming a specific implementation of the technique, the realization of an advantage may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more of the problems addressed by this disclosure from occurring in a particular situation, and as a result, the benefits of its solution may not be realized. In light of the possible existence of factors external to this disclosure, it is expressly stated that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from this disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantages often depends on technical realities of additional factors.

[0076] Unless otherwise stated, the embodiments are non-restrictive. That is, the disclosed embodiments are not intended to limit the scope of claims drafted based on this disclosure, even when only a single example is described with respect to a particular feature. The embodiments disclosed herein are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art knowing the beneficial effects of this disclosure.

[0077] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be formulated during the prosecution of this application (or an application claiming priority thereto) directed to any such combination of features. Specifically, with reference to the appended claims, features of dependent claims may, where appropriate, be combined with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may, where appropriate, be combined.

[0078] Thus, while the appended dependent claims can be drafted such that each dependent claim is dependent on a single other claim, additional dependencies are also contemplated. Any combination of dependent claims consistent with the present disclosure is contemplated and may be claimed in this or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0079] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0080] ***

[0081] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how claims drafted based on this disclosure are to be interpreted.

[0082] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim, without accompanying context, does not exclude additional instances of that item. A "plurality" of an item refers to a group of two or more items.

[0083] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0084] The terms "include" and "including" and their forms are open ended and mean "including, but not limited to."

[0085] When the term "or" is used in this disclosure with respect to a list of options, unless the context provides otherwise, it will generally be understood to be used in an inclusive sense. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0086] The expressions “w, x, y, or z, or any combination thereof” or “at least one of . . . w, x, y, and z” are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “at least one of . . . w, x, y, and z” thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in that list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0087] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0088] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on the specified factors or on the specified factors as well as other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover embodiments in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0089] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrases do not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with or independent of the specified factors. That is, the effect may be responsive only to these factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is the factor that triggers the performance of A or triggers a particular result of A. The phrase does not exclude that the performance of A may also be responsive to some other factor, such as C. The phrase also does not exclude that the performance of A may be performed in response to B and C in combination. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0090] ***

[0091] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0092] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0093] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA could be "configurable to" perform that function. After being appropriately programmed, the FPGA could then be considered "configured to" perform the particular function.

[0094] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0095] Different “circuits” may be described in this disclosure. These circuits or “circuits” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits can be custom designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits.

[0096] Thus, the disclosed circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an instruction's opcode and routing that instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible architectures for the circuit.

[0097] In various embodiments, as discussed in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to one another and the manner in which they interact form a microarchitectural definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, a microarchitectural definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitectural definition. That is, a person skilled in the art having a microarchitectural definition provided in accordance with the present disclosure can, without undue experimentation and with the application of ordinary skill, implement the structure by coding a description of the circuits / units / components in a hardware description language (HDL) such as Verilog or VHDL. HDL descriptions are often expressed in a manner that can be rendered as functional. However, for those skilled in the art, the HDL description is a means for transforming the structure of a circuit, unit, or component into the next level of implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce the integrated circuit. Some hardware circuits, or portions thereof, may also be custom designed in the schematic editor and captured into the integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to situations where the circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at a different stage in the circuit implementation process.

[0098] The fact that many different low-level combinations of circuit elements can be used to achieve the same specifications of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell libraries available for a particular project, and so on. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0099] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Consequently, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

[0100] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. A device, comprising: Memory; and a memory controller coupled to the memory, wherein the memory controller includes a calibration circuit configured to: performing horizontal memory calibration for some of the plurality of performance states during an initialization process; as well as determining information indicative of a set of differences between calibration results for pairs of performance states in the plurality of performance states and storing the information in a memory circuit; wherein the memory controller is further configured to, after the initialization process and in response to a change from a first performance state of the plurality of performance states to a second performance state of the plurality of performance states: setting initial memory parameters for the second performance state based on the set of differences; as well as Operation is initiated in the second performance state without performing an initial level calibration. 2 . The apparatus of claim 1 , wherein a given one of the plurality of performance states comprises a unique combination of operating voltage and clock frequency relative to other ones of the plurality of performance states.

3. The apparatus of claim 1 , wherein the calibration circuit is further configured to perform a margin check calibration after operating in the second performance state, wherein to perform the margin check calibration, the calibration circuit is further configured to: determining whether a calibration result at a first point provides a passing result, wherein the first point corresponds to a delay value that is less than a calibrated delay point; and A determination is made as to whether a calibration result at a second point provides a passing result, wherein the second point corresponds to a delay value greater than the calibrated delay point. 4 . The apparatus of claim 3 , wherein the calibration circuit is configured to skip performing a full-level calibration in the second performance state in response to determining that the calibration results at the first point and the second point are passing results.

5. The apparatus of claim 3 , wherein the calibration circuit is further configured to: performing a full level calibration in the second performance state in response to determining that at least one of the calibration results at the first point and the second point has failed; and The set of differences is updated based on results of the full horizontal calibration.

6. The apparatus of claim 3 , wherein the calibration circuit is further configured to limit the number of times the margin check calibration is performed after entering the second performance state to a threshold, and to perform a full level calibration instead of the margin check calibration in response to determining that the number of times the margin check calibration has been performed exceeds the threshold. 7 . The apparatus of claim 1 , wherein when performing horizontal calibration, the calibration circuit is configured to perform data writing to and reading from a memory at a specific reference voltage and at different delay values ​​applied to a data strobe signal.

8. The apparatus of claim 1 , wherein the memory comprises a multi-rank memory system having a first group of memory circuits and a second group of memory circuits, the first group of memory circuits and the second group of memory circuits sharing a set of common signal paths between the memory controller and the memory.

9. The apparatus of claim 1 , wherein the calibration circuit is further configured to perform one or more periodic horizontal calibrations during operation in the first of the multiple performance states after the initialization process and before changing to the second of the multiple performance states, and is further configured to set initial memory parameters for the second of the multiple performance states based on the most recent horizontal calibration performed in the first of the multiple performance states before transitioning to the second performance state.

10. The apparatus of claim 1, wherein the initialization process comprises system startup.

11. A method comprising: performing, by the memory controller, horizontal memory calibration for some of the plurality of performance states during an initialization process; determining, by the memory controller, a set of differences between calibration results for pairs of performance states in the plurality of performance states; storing, by the memory controller, information indicative of the set of differences; After the initialization process and in response to a change from a first performance state of the plurality of performance states to a second performance state of the plurality of performance states: setting initial memory parameters for the second performance state of the plurality of performance states, the initial memory parameters being based on the set of differences; as well as Operation is commenced in the second of the plurality of performance states using the initial memory parameters without performing an initial level memory calibration.

12. The method of claim 11 , further comprising performing a margin check calibration using a calibration circuit, wherein performing the margin check calibration comprises: determining whether a calibration result at a first point provides a passing result, wherein the first point corresponds to a delay value that is less than a calibrated delay point; as well as A determination is made as to whether a calibration result at a second point provides a passing result, wherein the second point corresponds to a delay value greater than the calibrated delay point. 13 . The method of claim 12 , further comprising skipping performing full-level calibration in the second performance state among the plurality of performance states in response to determining that the calibration results at the first point and the second point are passed results. 14 . The method of claim 13 , further comprising performing a full level calibration if at least one of the calibration results from one of the first point and the second point does not produce a passing result. 15 . The method of claim 11 , wherein a given one of the plurality of performance states comprises a unique combination of operating voltage and clock frequency relative to other ones of the plurality of performance states. The method of claim 11 , wherein the initialization process comprises a startup routine.

17. A system comprising: a memory subsystem having a memory controller coupled to a memory, wherein the memory controller includes calibration circuitry configured to perform horizontal memory calibration for some of a plurality of performance states during an initialization process, and storage circuitry configured to store information indicative of a set of differences between calibration results for pairs of performance states in the plurality of performance states; and power management circuitry configured to change operation of the memory subsystem from a first performance state of the plurality of performance states to a second performance state of the plurality of performance states; wherein the memory controller is further configured to, after the initialization process and in response to a change from a first performance state among the plurality of performance states to a second performance state among the plurality of performance states, set initial parameters for the second performance state based on the set of differences, and to begin operation in the second performance state without performing an initial level calibration.

18. The system of claim 17, wherein a given one of the plurality of performance states comprises a unique combination of operating voltage and clock frequency relative to other ones of the plurality of performance states.

19. The system of claim 17 , wherein the calibration circuit is configured to perform a tolerance check calibration, the tolerance check calibration comprising determining whether calibration results at a first point and a second point provide a passing result, wherein the first point corresponds to a delay value less than a calibrated delay point, and wherein the second point corresponds to a delay value greater than the calibrated delay point; and wherein the calibration circuit is further configured to skip performing a full level calibration in the second performance state in response to determining that the calibration results at the first point and the second point are passing results.

20. The system of claim 17, wherein the initialization process comprises a system startup routine.

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