Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor (1) in which the occurrence of insulation breakdown is further suppressed. A laminated ceramic capacitor (1) is provided with: a laminated body (2) including a plurality of laminated dielectric layers (4) and a plurality of internal electrode layers (10); and external electrodes (20) provided on the first end surface (62a) and the second end surface (62b), the internal electrode layer (10) being provided with a first internal electrode layer (10a) and a second internal electrode layer (10b), the first internal electrode layer (10a) being led out toward the first end surface (62a), the second internal electrode layer (10b) being led out toward the second end surface (62b), the external electrodes (20) including a first external electrode (20a) connected to the first internal electrode layer (10a) and a second external electrode (20b) connected to the second internal electrode layer (10b), a region in which the first internal electrode layers (10a) are arranged on the first end surface (62a) side and do not overlap each other in the lamination direction (T), and a region in which the second internal electrode layers (10b) are arranged on the second end surface (62b) side and do not overlap each other in the lamination direction (T) are defined as L spacer regions (51), and the L spacer regions (51) are provided with Si segregation layers (14).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] If the multilayer ceramic capacitor is miniaturized and has a larger capacitance, insulation breakdown is likely to occur in the multilayer ceramic capacitor. Patent document 1 describes a technique in which, in order to suppress the insulation breakdown, at least a portion of the region near the edge of the internal electrode of the dielectric layer is formed of a dielectric ceramic having a higher withstand voltage than other regions.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 11-317321 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] For the purpose of further miniaturization and high capacitance, the thickness of the dielectric layer of the stacked ceramic capacitor is gradually becoming thinner. As the thickness of the dielectric layer becomes thinner, the insulation resistance value decreases. In particular, in the area where the internal electrodes connected to the same external electrode on the end face side of the stack overlap each other, the internal electrodes are structurally easy to bend. Therefore, the thickness of the dielectric layer decreases locally, making it easier to produce insulation breakdown. Therefore, the subject of the present invention is to provide a stacked ceramic capacitor that further suppresses the occurrence of insulation breakdown.

[0008] Technical solutions to solve problems

[0009] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrode layers, the multilayer body including a first main surface and a second main surface opposite to each other in a stacking direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the stacking direction and the width direction; and external electrodes provided on the first end surface and the second end surface, the internal electrode layers including a first internal electrode layer and a second internal electrode layer, the first internal electrode layer being led out toward the first end surface, and the second internal electrode layer being led out toward the second end surface, the external electrodes including a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer, a region disposed on the first end surface side where the first internal electrode layers do not overlap with each other in the stacking direction, and a region disposed on the second end surface side where the second internal electrode layers do not overlap with each other in the stacking direction are set as an L spacer region, and the L spacer region includes a Si segregation layer.

[0010] Effects of the Invention

[0011] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the occurrence of dielectric breakdown is further suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a perspective view of a multilayer ceramic capacitor according to the present embodiment.

[0013] Figure 2 yes Figure 1 Line II cross-sectional view.

[0014] Figure 3 yes Figure 1 Sectional view along line II-II.

[0015] Figure 4 FIG. 1 is a diagram showing a part of the LT cross section of the multilayer ceramic capacitor according to the present embodiment.

[0016] Figure 5 FIG. 1 is a diagram showing a part of a WT cross section of the multilayer ceramic capacitor according to the present embodiment.

[0017] Figure 6 WT is a diagram showing a part of the cross section of another structure of the multilayer ceramic capacitor according to the present embodiment.

[0018] Figure 7 It is a top view of the ceramic green sheet in this embodiment.

[0019] Figure 8 It is a top view of a ceramic green sheet having another structure in this embodiment.

[0020] Fig. 9 (a) and (b) are diagrams showing LT cross sections of stacked ceramic green sheets.

[0021] Fig.10 It is a graph showing the results of the high temperature load reliability test.

[0022] Fig.11 It is a graph showing the results of dielectric constant and mean time to failure. DETAILED DESCRIPTION

[0023] Hereinafter, an example of an embodiment of a multilayer ceramic capacitor 1 according to the present invention will be described with reference to the drawings.

[0024] (Outline of a multilayer ceramic capacitor)

[0025] based on Figure 1 , an outline of the appearance of the multilayer ceramic capacitor 1 will be described. Figure 11 is a perspective view showing a multilayer ceramic capacitor 1 according to the present embodiment. The multilayer ceramic capacitor 1 includes a laminated body 2 and external electrodes 20 .

[0026] (Definition of direction)

[0027] In the figure, the L direction, the W direction, and the T direction are appropriately shown. The L direction is the length direction L of the laminated ceramic capacitor 1. The W direction is the width direction W of the laminated ceramic capacitor 1. The T direction is the stacking direction T of the laminated ceramic capacitor 1. Thus, Figure 2 The section shown is called the LT section. Figure 3 The cross section shown is referred to as a WT cross section. The length direction L, the width direction W, and the stacking direction T are not necessarily mutually orthogonal. The length direction L, the width direction W, and the stacking direction T may also be mutually intersecting.

[0028] (Outer shape of laminate)

[0029] The stack 2 has a substantially rectangular parallelepiped shape. The stack 2 has two main surfaces 61, two end surfaces 62, and two side surfaces 63. The main surfaces 61 are surfaces that are opposite to each other in the stacking direction T. The end surfaces 62 are surfaces that are opposite to each other in the length direction L. The side surfaces 63 are surfaces that are opposite to each other in the width direction W. One of the two main surfaces 61 is set as the first main surface 61a, and the other is set as the second main surface 61b. One of the two end surfaces 62 is set as the first end surface 62a, and the other is set as the second end surface 62b. One of the two side surfaces 63 is set as the first side surface 63a, and the other is set as the second side surface 63b. Figure 1 The second main surface 61 b ​​and the first side surface 63 a are shown.

[0030] It is preferable that the ridges and corners of the laminate 2 are rounded. The ridges are the portions where two surfaces of the laminate 2 intersect. The corners are the portions where three surfaces of the laminate 2 intersect. The size of the laminate 2 is not particularly limited.

[0031] (Structure of laminated body)

[0032] The laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. Hereinafter, the structure of the laminate 2 will be described with reference to a cross-sectional view of the laminate 2.

[0033] (Internal structure of the laminate (LT cross section))

[0034] based on Figure 2 , the internal structure of the stacked body 2 is described. Figure 2 yes Figure 1 A cross-sectional view of the multilayer ceramic capacitor 1 taken along line II is shown. Figure 2LT cross section of the laminated ceramic capacitor 1 is shown. The laminated body 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The plurality of dielectric layers 4 and the plurality of internal electrode layers 10 are laminated in the lamination direction T on one another.

[0035] (Inner and outer parts)

[0036] The laminate 2 is divided into an inner layer portion 53 and two outer layer portions 54 in the lamination direction T. The outer layer portion 54 includes a first outer layer portion 54a and a second outer layer portion 54b. The first outer layer portion 54a and the second outer layer portion 54b are located in the lamination direction T so as to sandwich the inner layer portion 53 therebetween.

[0037] The inner layer portion 53 is provided with a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. In the inner layer portion 53, the plurality of internal electrode layers 10 are opposed to each other via the dielectric layer 4. Therefore, an electrostatic capacitance is formed in the inner layer portion 53. Therefore, the inner layer portion 53 is a portion of the laminate 2 that substantially functions as a capacitor. Therefore, the inner layer portion 53 is also referred to as an effective portion.

[0038] The first outer layer portion 54a is a portion of the outer layer portion 54 located on the first main surface 61a side of the stack 2. The second outer layer portion 54b is a portion of the outer layer portion 54 located on the second main surface 61b side of the stack 2. Specifically, the first outer layer portion 54a is a portion between the first main surface 61a and the internal electrode layer 10 closest to the first main surface 61a among the plurality of internal electrode layers 10. The second outer layer portion 54b is a portion between the second main surface 61b and the internal electrode layer 10 closest to the second main surface 61b among the plurality of internal electrode layers 10. No internal electrode layer 10 is arranged in the first outer layer portion 54a and the second outer layer portion 54b. The remaining dielectric layers 4 of the plurality of dielectric layers 4 except for the dielectric layers 4 for the inner layer portion 53 are arranged in the first outer layer portion 54a and the second outer layer portion 54b. The first outer layer portion 54 a and the second outer layer portion 54 b function as protective layers for the inner layer portion 53 .

[0039] (Dielectric layer)

[0040] The dielectric layer 4 can be classified into the dielectric layer 4 arranged in the inner layer portion 53 and the dielectric layer 4 arranged in the outer layer portion 54. The dielectric layer 4 arranged in the inner layer portion 53 is referred to as the inner dielectric layer 4a, and the dielectric layer 4 arranged in the outer layer portion 54 is referred to as the outer dielectric layer 4b.

[0041] (Number of dielectric layers)

[0042] The number of dielectric layers 4 stacked in the stacked body 2 can be, for example, 5 or more and 2000 or less.

[0043] (Material of dielectric layer)

[0044] As the material of the dielectric layer 4, for example, dielectric ceramics containing BaTiO3, CaTiO3, SrTiO3, CaZrO3, etc. as main components can be used. In addition, materials containing Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc. as secondary components added to these main components can also be used.

[0045] (Thickness of dielectric layer)

[0046] The thickness of dielectric layer 4 can be set to, for example, 0.3 μm or more and 0.6 μm or less.

[0047] (Internal electrode layer)

[0048] The internal electrode layer 10 can be classified into a first internal electrode layer 10a and a second internal electrode layer 10b. The first internal electrode layer 10a is an internal electrode layer 10 connected to the first external electrode 20a. The second internal electrode layer 10b is an internal electrode layer 10 connected to the second external electrode 20b. The first internal electrode layer 10a extends from the first end face 62a toward the second end face 62b. The second internal electrode layer 10b extends from the second end face 62b toward the first end face 62a.

[0049] (Opposing part and lead-out part)

[0050] The first internal electrode layer 10 a and the second internal electrode layer 10 b each have a counter electrode portion 11 and a lead electrode portion 12 .

[0051] The opposing electrode portion 11 is a portion of the internal electrode layer 10 where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T. The lead electrode portion 12 is a portion of the internal electrode layer 10 extending from the opposing electrode portion 11 to the first end surface 62a or the second end surface 62b of the stacked body 2.

[0052] The counter electrode portion 11 of the first internal electrode layer 10a is referred to as a first counter electrode portion 11a. The lead electrode portion 12 of the first internal electrode layer 10a is referred to as a first lead electrode portion 12a. The first lead electrode portion 12a is a portion extending from the first counter electrode portion 11a to the first end surface 62a of the laminate 2.

[0053] Similarly, the counter electrode portion 11 of the second internal electrode layer 10b is referred to as a second counter electrode portion 11b. The lead electrode portion 12 of the second internal electrode layer 10b is referred to as a second lead electrode portion 12b. The second lead electrode portion 12b is a portion extending from the second counter electrode portion 11b to the second end surface 62b of the laminate 2.

[0054] (Number of internal electrode layers)

[0055] The number of the internal electrode layers 10 can be, for example, not less than 10 and not more than 2000. The number of the internal electrode layers 10 includes the number of the first internal electrode layers 10a and the number of the second internal electrode layers 10b.

[0056] (Thickness of internal electrode layer)

[0057] The thickness of the internal electrode layer 10 can be set to, for example, 0.1 μm to 5.0 μm, preferably 0.2 μm to 2.0 μm. When the thickness of the internal electrode layer 10 is 0.5 μm or more, a plated film is easily grown when forming the metal layer of the external electrode 20 by plating.

[0058] (Material of internal electrode layer)

[0059] The material of the internal electrode layer 10 can be, for example, metals such as Ni, Cu, Ag, Pd, and Au, alloys of Ni and Cu, alloys of Ag and Pd, etc. In addition, the material of the internal electrode layer 10 may further include dielectric particles of the same composition as the ceramic included in the dielectric layer 4.

[0060] (Electrode facing portion)

[0061] The division of the stacked body 2 in the longitudinal direction L is described. The stacked body 2 can be divided into an electrode opposing portion 50 and an L interval (L interval region) 51 in the longitudinal direction L. The electrode opposing portion 50 in the division in the longitudinal direction L is referred to as an L opposing portion 50a. In addition, the L interval 51 includes a first L interval 51a and a second L interval 51b.

[0062] The L opposing portion 50a corresponds to a portion where the first internal electrode layer 10a and the second internal electrode layer 10b are opposed to each other in the stacking direction T. Capacitance is formed in the L opposing portion 50a. Therefore, the L opposing portion 50a is also referred to as an effective portion.

[0063] (L interval)

[0064] The L interval 51 is a portion in which the first internal electrode layer 10a and the second internal electrode layer 10b are not opposed to each other in the stacking direction T in the longitudinal direction L of the stacked body 2. The first L interval 51a of the L interval 51 is between the L opposing portion 50a and the first end surface 62a. The second L interval 51b is between the L opposing portion 50a and the second end surface 62b.

[0065] In the 1st L interval 51a, the first internal electrode layer 10a is arranged but the second internal electrode layer 10b is not arranged in the stacking direction T. In the 2nd L interval 51b, the second internal electrode layer 10b is arranged in the stacking direction T but the first internal electrode layer 10a is not arranged.

[0066] The first L interval 51a functions as a lead-out portion of the first counter electrode portion 11a to the first end surface 62a, and the second L interval 51b functions as a lead-out portion of the second counter electrode portion 11b to the second end surface 62b.

[0067] The length of the L interval 51 in the longitudinal direction L can be, for example, 10% to 30% of the length of the laminate 2 in the longitudinal direction L. The length of the L interval 51 in the longitudinal direction L can be, for example, 5 μm to 30 μm.

[0068] (External Electrode)

[0069] The external electrode 20 includes a first external electrode 20 a and a second external electrode 20 b .

[0070] (1st external electrode)

[0071] The first external electrode 20a is an external electrode 20 disposed on the first end surface 62a of the stacked body 2. The first external electrode 20a is electrically connected to the first internal electrode layer 10a.

[0072] (Second external electrode)

[0073] The second external electrode 20b is an external electrode 20 disposed on the second end surface 62b of the stacked body 2. The second external electrode 20b is electrically connected to the second internal electrode layer 10b.

[0074] (External electrodes on each surface)

[0075] The external electrode 20 extends from one end surface 62 to a portion of the two main surfaces 61 and a portion of the two side surfaces 63 .

[0076] (Layer structure of external electrode)

[0077] based on Figure 2 , the layer structure of the external electrode 20 is described. The external electrode 20 includes a base electrode layer 21 and a plating layer 23. The plating layer 23 includes an inner plating layer 24 and a surface plating layer 25. These layers are arranged in the order of the base electrode layer 21, the inner plating layer 24, and the surface plating layer 25 from the end surface 62 of the laminate 2. In detail, the first external electrode 20a includes a first base electrode layer 21a and a first plating layer 23a. Furthermore, the first plating layer 23a includes a first inner plating layer 24a and a first surface plating layer 25a. Similarly, the second external electrode 20b includes a second base electrode layer 21b and a second plating layer 23b. Furthermore, the second plating layer 23b includes a second inner plating layer 24b and a second surface plating layer 25b.

[0078] (Base electrode layer)

[0079] The first foundation electrode layer 21a is arranged on and covers the first end surface 62a of the stacked body 2. The first foundation electrode layer 21a extends from the first end surface 62a to a portion of the first principal surface 61a, a portion of the second principal surface 61b, a portion of the first side surface 63a, and a portion of the second side surface 63b.

[0080] Similarly, the second base electrode layer 21b is arranged on and covers the second end face 62b of the stacked body 2. The second base electrode layer 21b extends from the second end face 62b to a portion of the first main face 61a, a portion of the second main face 61b, a portion of the first side face 63a, and a portion of the second side face 63b.

[0081] (burned layer)

[0082] The first base electrode layer 21a and the second base electrode layer 21b are formed as sintered layers. The sintered layers contain glass components and metals. As the glass component, at least one selected from B, Si, Ba, Mg, Al, Li, etc. is included. As the metal, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. is included. The sintered layer may also be a plurality of layers.

[0083] (Plating layer)

[0084] The plating layer 23 on the base electrode layer 21 is described. As described above, in the present embodiment, the plating layer 23 includes the inner plating layer 24 and the surface plating layer 25. When the plating layer 23 is formed into two layers, it is preferable to form a Ni plating layer and a Sn plating layer in the order from the bottom. That is, the inner plating layer 24 is a Ni plating layer, and the surface plating layer 25 is a Sn plating layer.

[0085] The Ni plating layer can prevent the base electrode layer 21 from being corroded by the solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer can improve the wettability of the solder when mounting the multilayer ceramic capacitor 1, making the mounting easier. Therefore, by setting the surface plating layer 25 as a Sn plating layer, the wettability of the solder to the external electrode 20 can be improved. The thickness of each plating layer is preferably 3 μm or more and 9 μm or less.

[0086] (Internal structure of the laminate (WT cross section))

[0087] based on Figure 3 , the internal structure of the stacked body 2 is described. Figure 3 yes Figure 1FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II. The multilayer body 2 is divided into an electrode facing portion 50 and a W interval 52 in the width direction W. The electrode facing portion 50 divided in the width direction W is referred to as a W facing portion 50b. The W interval 52 includes a first W interval 52a and a second W interval 52b.

[0088] The W opposing portion 50b is a portion where the internal electrode layers 10 are opposed in the stacking direction T. The W gap 52 is a portion in the width direction W where neither the first internal electrode layer 10a nor the second internal electrode layer 10b is arranged in the stacking direction T.

[0089] The first W interval 52a of the W intervals 52 is between the W facing portion 50b and the first side surface 63a in the width direction W of the stacked body 2. The second W interval 52b is between the W facing portion 50b and the second side surface 63b.

[0090] The first W interval 52 a and the second W interval 52 b are arranged so as to sandwich the W opposing portion 50 b . The first W interval 52 a and the second W interval 52 b function as a protective layer for the internal electrode layer 10 .

[0091] The length of the W space 52 in the width direction W can be, for example, 20% to 30% of the length of the laminate 2 in the width direction W. The length of the W space 52 in the width direction W can be, for example, 5 μm to 50 μm.

[0092] (Size of multilayer ceramic capacitors)

[0093] The size of the multilayer ceramic capacitor 1 is not particularly limited. The size of the multilayer ceramic capacitor 1 can be set, for example, as follows. The dimension in the length direction L of the multilayer ceramic capacitor 1 including the multilayer body 2 and the external electrode 20 is set to the L dimension. The L dimension is preferably greater than 0.25 mm and less than 1.0 mm. The dimension in the stacking direction T of the multilayer ceramic capacitor 1 including the multilayer body 2 and the external electrode 20 is set to the T dimension. The T dimension is preferably greater than 0.125 mm and less than 0.5 mm. The dimension in the width direction W of the multilayer ceramic capacitor 1 including the multilayer body 2 and the external electrode 20 is set to the W dimension. The W dimension is preferably greater than 0.125 mm and less than 0.5 mm. In addition, the length of each part of the multilayer body 2 and the external electrode 20 can be measured by a micrometer or an optical microscope.

[0094] (Terminal structure)

[0095] In this embodiment, the laminated ceramic capacitor 1 is described as a two-terminal laminated ceramic capacitor. However, the laminated ceramic capacitor 1 is not limited to a two-terminal laminated ceramic capacitor, but may be a multi-terminal laminated ceramic capacitor with three or more terminals.

[0096] (Si segregation layer)

[0097] The multilayer ceramic capacitor 1 of the present embodiment includes a Si segregation layer 14 in the L gap 51. The Si segregation layer 14 refers to a Si layer formed on the surface of the internal electrode layer 10 and the like.

[0098] based on Figure 4 , the Si segregation layer 14 is described. Figure 4 1 is a diagram showing a part of the LT cross section of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 4 Equivalent to Figure 2 The region R1 indicated by the middle dotted line is enlarged in the figure. Figure 4 The 1Lth interval 51 a and its vicinity are shown.

[0099] In the first L-th gap 51 a and its vicinity, a Si segregation layer 14 is formed on the surface of the internal electrode layer 10 .

[0100] (1st internal electrode layer)

[0101] The first internal electrode layer 10a has a Si segregation layer 14 formed on the entire surface of the first extraction electrode portion 12a and at least a portion of the first opposing electrode portion 11a. At least a portion of the first opposing electrode portion 11a corresponds to a portion of the first opposing electrode portion 11a close to the first L-space 51a.

[0102] (Second internal electrode layer)

[0103] Regarding the second internal electrode layer 10b, a Si segregation layer 14 is formed on the surface of at least a portion of the second opposing electrode portion 11b. At least a portion of the second opposing electrode portion 11b corresponds to a portion of the second opposing electrode portion 11b close to the 1L gap 51a.

[0104] Regarding the first internal electrode layer 10a and the second internal electrode layer 10b, the portion close to the first L-space 51a refers to a portion extending from the boundary between the first L-space 51a and the L-opposing portion 50a toward the L-opposing portion 50a by, for example, about 50 μm.

[0105] The end of the internal electrode layer 10 is referred to as an electrode end 10e. The end of the internal electrode layer 10 means an end surface of the internal electrode layer 10 parallel to the stacking direction T. Figure 4 FIG. 1 shows an electrode end portion 10e of the second internal electrode layer 10b. Figure 4 In the structure shown, a Si segregation layer 14 is formed over the entire electrode end portion 10 e in a direction parallel to the stacking direction T.

[0106] As described above, the Si segregation layer 14 is formed not only on the surface of the internal electrode layer 10 parallel to the longitudinal direction L, but also on the surface of the electrode end 10e parallel to the stacking direction T. In this way, the Si segregation layer 14 is formed on the surface of the internal electrode layer 10 in the first L interval 51a and its vicinity.

[0107] (Floating island electrode)

[0108] exist Figure 4 In the example shown, a floating island electrode 13 in the shape of a floating island is formed in the first L interval 51a. A Si segregation layer 14 is also formed on the surface of the floating island electrode 13. The floating island electrode 13 can be formed intentionally when forming the internal electrode layer 10. Alternatively, it may be formed accidentally when forming the internal electrode layer 10.

[0109] (2L interval)

[0110] In the above, the Si segregation layer 14 is described by taking the 1L interval 51a as an example. However, the 2L interval 51b also has the same structure. That is, the second extraction electrode portion 12b and the first opposing electrode portion 11a in the 2L interval 51b also form the same Si segregation layer 14 as the first extraction electrode portion 12a and the second opposing electrode portion 11b in the 1L interval 51a.

[0111] (Electrode end in width direction)

[0112] based on Figure 5 , the electrode end portion 10 e in the width direction W of the internal electrode layer 10 will be described. Figure 5 1 is a diagram showing a portion of the WT cross section of the multilayer ceramic capacitor 1 according to the embodiment of the present invention. Figure 5 This is a schematic diagram. Therefore, the number of patterns, etc. may not match other drawings, etc.

[0113] like Figure 5 As shown, the Si segregation layer 14 is also formed at the electrode end 10e in the width direction W. In detail, the Si segregation layer 14 is also formed across the entire direction parallel to the stacking direction T at the electrode end 10e in the width direction W. In addition, the Si segregation layer 14 is also formed on the surface of the internal electrode layer 10 parallel to the width direction W. However, the Si segregation layer 14 is not formed to cover the entire surface parallel to the width direction W. The Si segregation layer 14 is formed on the surface parallel to the width direction W from the electrode end 10e to a given distance. Figure 5In FIG. 1 , the predetermined distance is indicated by the distance d1. The distance d1 can be set to, for example, 1 μm or more and 50 μm or less.

[0114] (Other structures of Si segregation layer)

[0115] Figure 6 About Figure 5 Region R2 shows another structural diagram. Figure 5 The structure shown and Figure 6 In the structure shown, the position where the Si segregation layer 14 is formed on the surface of the internal electrode layer 10 is different. Figure 5 In the structure shown in FIG. 1 , as shown in region R2, the Si segregation layer 14 is formed over the entire electrode end 10e of the internal electrode layer 10 in the stacking direction T. Figure 6 In the illustrated structural example, the Si segregation layer 14 is not formed over the entire electrode end 10e in the stacking direction T. The Si segregation layer 14 is formed at both ends of the electrode end 10e in the stacking direction T. On the other hand, the Si segregation layer 14 is not formed in the central portion of the electrode end 10e in the stacking direction T. Therefore, the internal electrode layer 10 is exposed from the central portion of the electrode end 10e in the stacking direction T.

[0116] like Figure 5 as well as Figure 6 As shown, at the electrode end portion 10 e in the width direction W of the internal electrode layer 10 , the Si segregation layer 14 may be formed entirely in the stacking direction T thereof, or may be formed only in a portion in the stacking direction T thereof.

[0117] (Thickness of Si segregation layer)

[0118] The thickness of the Si segregation layer 14 can be set to, for example, 0.01 μm or more and 0.30 μm or less. The thickness of the Si segregation layer 14 can be determined by exposing a cross section of the stacked body 2, identifying dielectric particles and the Si segregation layer using a scanning electron microscope (SEM), and further performing elemental analysis of the surface using energy dispersive X-ray analysis (EDX).

[0119] (Method for manufacturing multilayer ceramic capacitor)

[0120] based on Figure 7 etc., a method for manufacturing the multilayer ceramic capacitor 1 will be described.

[0121] (Fabrication of stacked blocks)

[0122] Ceramic green sheets 30 , electrode paste 31 for the internal electrode layer 10 , and step paste 32 for the step layer 5 are prepared.

[0123] (Step layer)

[0124] First, the step layer 5 is described. It is preferable that the length of the stacking direction T of the stacked body 2 is less different between the electrode opposing portion 50 and the L interval 51. However, in the inner layer portion 53, the length in the stacking direction T is likely to be different between the electrode opposing portion 50 and the L interval 51. The dielectric layer 4 and the internal electrode layer 10 are stacked in the electrode opposing portion 50. In contrast, in the L interval 51, only the dielectric layer 4 and the internal electrode layer 10 connected to one external electrode 20 are stacked. Therefore, the length in the stacking direction T is likely to be different between the electrode opposing portion 50 and the L interval 51.

[0125] Therefore, in order to reduce the difference in length between the L gap 51 and the electrode opposing portion 50 in the stacking direction T, an additional dielectric layer 4 is arranged in the L gap 51. The additional dielectric layer 4 is set as a step layer 5. The step layer 5 preferably has the same composition as the dielectric layer 4. However, the composition of the dielectric layer 4 is not limited thereto.

[0126] exist Figure 4 The step layer 5 is shown. Figure 4 As shown, the step layer 5 is disposed between two first opposing electrode portions 11a facing each other in the stacking direction T in the first L interval 51a. The step layer 5 compensates for the thickness of the second internal electrode layer 10b, thereby reducing the difference in length in the stacking direction T between the first L interval 51a and the L opposing portion 50a.

[0127] In addition, in the present embodiment, a Si component is mixed in the step paste 32. This Si component will form the Si segregation layer 14 later. In addition, adding the Si component to the step paste 32 is an example of a method of forming the Si segregation layer 14.

[0128] (Application of ointment)

[0129] The outline of the stacking of the ceramic green sheets 30 in the case of forming the step layer 5 is described. In addition, the shape of the pattern of the electrode paste 31 and the step paste 32 will be described later. First, the aforementioned electrode paste 31 and the step paste 32 are applied to the ceramic green sheet 30 in a desired pattern. For example, the application of each paste to the ceramic green sheet 30 can be performed by a method such as screen printing or gravure printing. The electrode paste 31 and the step paste 32 are printed on the ceramic green sheet 30 in a given pattern by an arbitrary printing method. In this way, the ceramic green sheet 30 for the inner layer portion 53 printed with the paste is obtained.

[0130] (Cascade)

[0131] A predetermined number of ceramic green sheets 30 on which the pattern of the internal electrode layer 10 is not printed are stacked. Thus, a portion corresponding to the outer layer portion 54 is produced. The ceramic green sheets 30 for the inner layer portion 53 to which the paste is applied are sequentially stacked thereon. Thus, a portion corresponding to the inner layer portion 53 is stacked. Furthermore, a predetermined number of ceramic green sheets 30 for another outer layer portion 54 are stacked thereon. Thus, a laminated sheet is produced. The laminated sheet is pressed in the stacking direction by means such as isostatic pressing to produce a laminated block.

[0132] (pattern)

[0133] Figure 7 It is a plan view of the ceramic green sheet 30 to which the electrode paste 31 and the step paste 32 are applied. Figure 7 This is a diagram of the ceramic green sheet 30 as viewed from the stacking direction T. Figure 7 701 and 702 each represent a ceramic green sheet 30. By stacking these ceramic green sheets 30, a laminated sheet can be obtained. Figure 7 In the example shown, ten electrode patterns are formed on the ceramic green sheet 30 using the electrode paste 31. The electrode patterns are arranged in two columns in the longitudinal direction L and in five rows in the width direction W. In addition, a step paste 32 is applied between two electrode patterns arranged in the longitudinal direction L.

[0134] exist Figure 7 In the two ceramic green sheets 30 shown in 701 and 702 , the electrode paste 31 and the step paste 32 are applied in the same pattern.

[0135] (Cascade)

[0136] In the Figure 7 When the two ceramic green sheets 30 shown in 701 and 702 are stacked, they are stacked with an offset in the length direction L. Figure 7 In FIG. 1 , the distance of the offset is indicated by the distance d2. By stacking two ceramic green sheets 30 with the offset, it is possible to easily manufacture a laminated ceramic capacitor 1 in which the Si segregation layer 14 is formed in either the first L interval 51a or the second L interval 51b. This will be described later.

[0137] (Preparation of laminated sheets)

[0138] The stacked block is cut into a given size to cut out stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by roller grinding or the like.

[0139] (Firing)

[0140] Next, the stacked small pieces are fired to produce the stacked body 2. The firing temperature depends on the materials of the ceramic layer 4 and the internal electrode layer 10, but is preferably 900°C or higher and 1400°C or lower.

[0141] (External Electrode)

[0142] Next, the external electrodes 20 are formed.

[0143] (Base electrode layer)

[0144] A conductive paste that becomes the base electrode layer 21 is applied to both end surfaces 62 of the laminate 2 to form the base electrode layer 21. In order to form a sintered layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping. Then, a sintering treatment is performed to form the base electrode layer 21. The temperature of the sintering treatment is preferably 500° C. or higher and 900° C. or lower. In addition, the time of the sintering treatment is preferably 30 minutes or higher and two hours or lower. In addition, the atmosphere of the sintering treatment is preferably a reducing atmosphere to which H2O or H2 is added, for example.

[0145] Next, a plating layer 23 is formed on the surface of the base electrode layer 21. In the present embodiment, a Ni plating layer is formed on the sintered layer. The Ni plating layer becomes the inner plating layer 24. Next, a Sn plating layer is formed on the Ni plating layer. The Sn plating layer becomes the surface plating layer 25. The Ni plating layer and the Sn plating layer are sequentially formed by, for example, a barrel plating method. In this way, a laminated ceramic capacitor 1 is obtained.

[0146] (Lamination and cutting)

[0147] based on Figure 8 as well as Fig. 9 , stacking and cutting in the method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described in more detail. Figure 8 FIG. 3 is a top view of a ceramic green sheet 30 coated with an electrode paste 31 and a step paste 32. Figure 7 and Figure 8 In the embodiment, the electrode paste 31 and the step paste 32 applied to the ceramic green sheet 30 have different patterns. Figure 7 In the structure shown, the electrode patterns are arranged in two columns in the length direction L and in five rows in the width direction W. In addition, the step paste 32 is applied between the two electrode patterns arranged in the length direction L. Figure 8 In the structure shown, the electrode patterns are arranged in four columns in the length direction L and in five rows in the width direction W. In addition, the step paste 32 is applied between the first electrode pattern and the second electrode pattern and between the third electrode pattern and the fourth electrode pattern among the four electrode patterns arranged in the length direction L. In this way, the electrode paste 31 and the step paste 32 can be applied in various patterns in the ceramic green sheet 30 according to the type of the multilayer ceramic capacitor 1 to be manufactured.

[0148] (Cascade)

[0149] Will Figure 8 The ceramic green sheet 30 shown in 801 is set as the first ceramic green sheet 30a. Figure 8 The ceramic green sheet 30 shown in 802 is set as the second ceramic green sheet 30b. Figure 7 In the same manner as in the structure shown, the first ceramic green sheet 30a and the second ceramic green sheet 30b are stacked so as to be shifted. Specifically, they are stacked so as to be shifted in the longitudinal direction L by a distance d2.

[0150] (cut off)

[0151] based on Fig. 9 , the cutting of the stacked ceramic green sheets 30 will be described. Fig. 9 (a) and Fig. 9 (b) is a diagram showing a LT cross section of the stacked ceramic green sheets 30. Fig. 9 (a) and Fig. 9 In (b), in order to simplify the structure, a state where only two ceramic green sheets 30 are stacked is illustrated. In the following description, the stack of two ceramic green sheets 30 is referred to as a stack 40 . Fig. 9 The lines L1 and L2 shown in (a) indicate the cutting lines. The lines L1 and L2 correspond to Figure 8 Shown are line L1 and line L2. Fig. 9 (a) shows the laminated body 40 before being cut. Fig. 9 (b) shows the laminated body 40 after being cut at the line L1 and the line L2.

[0152] (Line L1)

[0153] like Fig. 9 As shown in (a) of FIG. 4 , the first ceramic green sheet 30a and the second ceramic green sheet 30b in the stack 40 are stacked with an offset in the length direction L. Therefore, the positions of the end 31b of the pattern of the electrode paste 31 in the second ceramic green sheet 30b in the length direction L and the center 32a of the pattern of the step paste 32 in the first ceramic green sheet 30a in the length direction L are aligned in the length direction L. That is, the end 31b of the pattern of the electrode paste 31 and the center 32a of the pattern of the step paste 32 are both located on the line L1.

[0154] (Line L2)

[0155] Similarly, the positions of the central portion 32b of the pattern of the step paste 32 in the second ceramic green sheet 30b in the long direction L and the end portion 31a of the pattern of the electrode paste 31 in the long direction L in the first ceramic green sheet 30a in the long direction L are aligned in the long direction L. That is, the central portion 32b of the pattern of the step paste 32 and the end portion 31a of the pattern of the electrode paste 31 are both located on the line L2.

[0156] (After cutting)

[0157] The cut laminate 40 is shown in FIG. Fig. 9 (b). The stacked product 40 cut at the line L1 and the line L2 has a step layer 5 formed at the L interval 51. This is because the ceramic green sheets 30 are stacked in a staggered manner so that the pattern applied to the first ceramic green sheet 30a and the pattern applied to the second ceramic green sheet 30b have the positional relationship as described above.

[0158] (Cut surface)

[0159] The cut surface produced by cutting at the line L1 is referred to as the first cut surface 41. In addition, the cut surface produced by cutting at the line L2 is referred to as the second cut surface 42. The first cut surface 41 corresponds to the first end surface 62a in the stacked body 2. In addition, the second cut surface 42 corresponds to the second end surface 62b in the stacked body 2. Here, the so-called corresponding means the portion of the stacked body 2 that corresponds when the stacked object 40 is fired to become the stacked body 2.

[0160] From the first cut surface 41 of the laminate 40, the first green sheet 30a corresponding to the inner dielectric layer 4a, the step paste 32 corresponding to the step layer 5, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the electrode paste 31 corresponding to the first internal electrode layer 10a are exposed in order in the lamination direction T. Similarly, from the second cut surface 42 of the laminate 40, the first green sheet 30a corresponding to the inner dielectric layer 4a, the electrode paste 31 corresponding to the second internal electrode layer 10b, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the step paste 32 corresponding to the step layer 5 are exposed in order in the lamination direction T. In addition, in the longitudinal direction L, the portions where the step paste 32 is arranged are the first L interval 51a and the second L interval 51b, respectively.

[0161] (Formation of Si segregation layer)

[0162] As described above, the step paste 32 contains a Si component for forming the Si segregation layer 14. The Si component migrates in the step paste 32 and adheres to the internal electrode layer 10. This is because the Si component is a liquid phase component, so the Si component can pass through the dielectric material and approach the internal electrode layer. Specifically, the Si component adheres to the surface of the lead-out electrode portion 12 and at least a portion of the end and surface of the opposing electrode portion 11. The Si component adhered to each internal electrode layer 10 forms the Si segregation layer 14.

[0163] (Other methods for forming Si segregation layers)

[0164] In addition, the method for forming the Si segregation layer 14 is not limited to the method of mixing the Si component in the step paste 32 as described above. As another method for forming the Si segregation layer 14, there is a method of applying the Si component to the L space 51. In this method, the Si component is applied in the coating pattern of the electrode paste 31 corresponding to the portion where the Si segregation layer 14 is to be formed by printing or the like. As another method for forming the Si segregation layer 14, there is a method of allowing the Si component to penetrate from the WT end face of the stacked small piece before firing (i.e., the face corresponding to the end face 62 of the stacked body 2).

[0165] (Effect of Si segregation layer)

[0166] The multilayer ceramic capacitor 1 of the present embodiment includes the Si segregation layer 14 in the L space 51 . Therefore, the reliability of the multilayer ceramic capacitor 1 can be improved. This is because the Si segregation layer 14 has a high IR (Insulation Resistance).

[0167] Evaluation results of the characteristics of the multilayer ceramic capacitor 1 are shown below.

[0168] (High temperature load reliability test)

[0169] based on Fig.10 , the results of the high temperature load reliability test are explained. Fig.10 It is a figure which shows the result of the high temperature load reliability test about the comparative example and the Example.

[0170] The method of the high temperature load reliability test is as follows. For the comparative example and Examples 1 to 8, 100 samples were prepared respectively. The sample was mounted on a glass epoxy substrate using eutectic solder. The thickness of the dielectric layer in the sample was set to 0.5μm. First, the initial insulation resistance value of each sample was measured. Next, the glass epoxy substrate was placed in a high temperature tank, and a voltage of 6.3V was applied to each sample at 150°C. Then, the insulation resistance value was measured after 200 hours and 500 hours. The initial insulation resistance value and the insulation resistance value after the passage of time were compared, and the sample whose insulation resistance value dropped by more than one order of magnitude was considered defective. Fig.10 As shown in FIG. 1 , in the sample having the Si segregation layer, no defect occurred at 200 hours, and the number of defectives was suppressed to 5 or less even at 500 hours.

[0171] In particular, in Examples 2 to 6 in which the thickness of the Si segregation layer was 0.03 μm or more and 0.15 μm or less, no defect occurred not only after the lapse of 200 hours but also after the lapse of 500 hours.

[0172] (Dielectric constant and mean time to failure)

[0173] based on Fig.11 , the evaluation results of the dielectric constant and the mean time to failure are explained. Fig.11 This is a graph showing the evaluation results of dielectric constant and mean failure time for comparative examples and examples. The thickness of the dielectric layer in the sample was set to 4 types, ranging from 0.3 μm to 0.6 μm. By making the thickness of the dielectric layer different, samples with different element thicknesses were produced. In addition, the thickness of the Si segregation layer was set to 0.07 μm and 0.08 μm.

[0174] Si has a low dielectric constant. Therefore, in the sample with the Si segregation layer formed, a decrease in the dielectric constant was observed. In addition, in the sample with the Si segregation layer formed, an improvement in MTTF (Mean Time To Failure) was observed.

[0175] In particular, in Examples B and C in which the thickness of the dielectric layer was 0.4 μm or more and 0.5 μm or less, a significant improvement in MTTF was observed.

[0176] As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, Various changes and deformation|transformation are possible.

[0177] <1>

[0178] A multilayer ceramic capacitor, characterized by comprising:

[0179] A laminate comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers, comprising a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction; and

[0180] external electrodes are provided on the first end surface and the second end surface,

[0181] The internal electrode layer includes a first internal electrode layer and a second internal electrode layer,

[0182] The first internal electrode layer is led out toward the first end surface,

[0183] The second internal electrode layer is led out toward the second end surface,

[0184] The external electrodes include a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer.

[0185] A region disposed on the first end surface side where the first internal electrode layers do not overlap each other in the stacking direction and a region disposed on the second end surface side where the second internal electrode layers do not overlap each other in the stacking direction are defined as an L spacing region.

[0186] The L spacer region includes a Si segregation layer.

[0187] <2>

[0188] The multilayer ceramic capacitor according to <1>,

[0189] The Si segregation layer has a thickness of 0.03 μm or more and 0.15 μm or less.

[0190] <3>

[0191] The multilayer ceramic capacitor according to <1> or <2>, wherein:

[0192] The Si segregation layer exists at an end portion of the first internal electrode layer in the width direction and an end portion of the second internal electrode in the width direction.

[0193] <4>

[0194] The multilayer ceramic capacitor according to any one of <1> to <3>,

[0195] The dielectric layer has a thickness of 0.4 μm or more and 0.5 μm or less.

[0196] Description of Reference Numerals

[0197] 1: Multilayer ceramic capacitor;

[0198] 2: laminate;

[0199] 4: Dielectric layer;

[0200] 5: step layer;

[0201] 10: internal electrode layer;

[0202] 11: Opposing electrode portion;

[0203] 12: Lead-out electrode portion;

[0204] 13: floating island electrode;

[0205] 14: Si segregation layer;

[0206] 20: external electrode;

[0207] 21: base electrode layer;

[0208] 23: plating layer;

[0209] 24: inner plating layer;

[0210] 25: surface plating layer;

[0211] 30: Ceramic green sheet;

[0212] 31: electrode paste;

[0213] 32: Step paste;

[0214] 40: laminated objects;

[0215] 41: 1st section;

[0216] 42: 2nd section;

[0217] 50: electrode opposing portion;

[0218] 51: L interval (L interval area);

[0219] 52: W interval;

[0220] 53: inner layer;

[0221] 54: outer part;

[0222] 61: Main side;

[0223] 62: end face;

[0224] 63: side;

[0225] R1: Region;

[0226] R2: Region;

[0227] T: stacking direction;

[0228] L: length direction;

[0229] W: width direction.

Claims

1. A laminated ceramic capacitor, characterized in that: have: A laminate comprising a plurality of laminated dielectric layers and a plurality of internal electrode layers, comprising a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction; and external electrodes are provided on the first end surface and the second end surface, The internal electrode layer includes a first internal electrode layer and a second internal electrode layer, The first internal electrode layer is led out toward the first end surface, The second internal electrode layer is led out toward the second end surface, The external electrodes include a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer. A region disposed on the first end surface side where the first internal electrode layers do not overlap each other in the stacking direction and a region disposed on the second end surface side where the second internal electrode layers do not overlap each other in the stacking direction are defined as an L spacing region. The L spacer region includes a Si segregation layer.

2. The multilayer ceramic capacitor according to claim 1, wherein: The Si segregation layer has a thickness of 0.03 μm or more and 0.15 μm or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The Si segregation layer exists at an end portion of the first internal electrode layer in the width direction and an end portion of the second internal electrode layer in the width direction.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, characterized in that: The dielectric layer has a thickness of 0.4 μm or more and 0.5 μm or less.

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