Method for forming interconnection structure

Abstract

A method of forming an interconnect structure includes providing a polymer solution, providing a dielectric material, spin-coating the polymer solution on the dielectric material, forming a dispersion of a conductive composition within a sacrificial polymer in a trench, baking the dielectric material such that the sacrificial polymer is removed, and forming a conductive layer on the dielectric material. The method includes depositing a conductive composition on a substrate to form an exposed surface of the conductive composition, sputtering a metal seed layer to the exposed surface of the conductive composition, electroplating a layer of a copper composition to the metal seed layer, and chemically mechanical polishing the layer of the copper composition. The polymer solution includes a conductive composition including at least one of graphene nanosheets and reduced graphene oxide nanosheets, a sacrificial polymer, and a solvent. The dielectric material includes a channel formed into a surface of the dielectric material.

Description

[0001] Claiming priority

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 399,551 (Agent Docket No. 1202216, filed on August 19, 2022), which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to interconnect structures, and methods of forming interconnect structures. Background Art

[0004] Downward scaling of integrated circuit (IC) technology improves transistor performance by increasing switching speed and reducing power consumption. However, due to the reduction in interconnect linewidth, size reduction may also reduce electrical performance and reliability. In addition, copper is widely used in interconnect structures. Downward scaling may lead to electromigration problems. In particular, when copper-based interconnects are heated due to their resistance and high current density, copper atoms therein may migrate within the interconnect channels and at the interface, which may eventually lead to interconnect failure (e.g., open circuit or short circuit). In addition, conventional processes (such as chemical vapor deposition (CVD)) for forming interconnect structures may be time-consuming and expensive.

[0005] Therefore, there continues to be a need for new and more cost-effective processes for forming interconnect structures that mitigate electromigration issues of copper-based interconnect structures while improving the reliability and performance of integrated circuit chips. Summary of the invention

[0006] Some embodiments of the present disclosure relate to a method for forming an interconnect structure, the method comprising a polymer solution comprising at least one of graphene nanosheets and reduced graphene oxide (rGO) nanosheets and a sacrificial polymer, and an interconnect structure, the interconnect structure being prepared using a polymer solution comprising at least one of graphene nanosheets and reduced graphene oxide (rGO) nanosheets. The interconnect structure can reduce the occurrence of interconnect line failures and improve the reliability and performance of integrated circuit chips. Compared with copper-only interconnect structures, the interconnect structure can have better reliability and / or lower resistance.

[0007] According to one or more embodiments, a method for forming the interconnect structure is provided. The method comprises: providing a polymer solution, providing a dielectric material, spin coating the polymer solution on the dielectric material, forming a dispersion of the conductive composition in the sacrificial polymer in a channel, baking the dielectric material so that the sacrificial polymer is removed to form an exposed surface of the conductive composition, optionally reducing the rGO nanosheets to graphene nanosheets by an annealing step, wherein the rGO nanosheets included in the conductive composition are reduced to graphene nanosheets, sputtering a metal seeding layer to the exposed surface of the conductive composition, electroplating a layer of a copper composition to the metal seeding layer, and chemically mechanically polishing the layer of the copper composition. The polymer solution comprises a conductive composition comprising at least one of graphene nanosheets and rGO nanosheets, a sacrificial polymer, and a solvent. The dielectric material comprises a channel formed into the surface of the dielectric material.

[0008] Additional features and advantages of the embodiments described herein will be set forth in the detailed description that follows, and in part will become apparent to those skilled in the art from the description, or will be recognized by those skilled in the art through practice of the embodiments described herein, including the detailed description that follows, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following detailed description of specific embodiments of the present disclosure may be best understood when read in conjunction with the following drawings, in which like structures are represented by like reference numerals, and in which:

[0010] Figure 1 Depicted is a flow chart of a method of forming an interconnect structure according to one or more embodiments shown and described in the present disclosure.

[0011] Figure 2A is a cross-sectional view of a step of forming an interconnect structure according to one or more embodiments shown and described herein, the interconnect structure comprising at least one of a graphene nanosheet and a rGO nanosheet, and the interconnect structure having a trench;

[0012] Figure 2B is a cross-sectional view of another step of forming an interconnect structure according to one or more embodiments shown and described herein, the interconnect structure comprising at least one of a graphene nanosheet and a rGO nanosheet, and the interconnect structure having a channel;

[0013] Figure 2C is a cross-sectional view of another step of forming an interconnect structure according to one or more embodiments shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets, and the interconnect structure having channels;

[0014] Figure 2D is a cross-sectional view of another step of forming an interconnect structure according to one or more embodiments shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets, and the interconnect structure having channels;

[0015] Figure 2E is a cross-sectional view of another step of forming an interconnect structure according to one or more embodiments shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets, and the interconnect structure having channels;

[0016] Figure 2F is a cross-sectional view of another step of forming an interconnect structure according to one or more embodiments shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets, and the interconnect structure having channels;

[0017] Figure 2G is a cross-sectional view of another step of forming an interconnect structure according to one or more embodiments shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets, and the interconnect structure having channels;

[0018] Figure 3A is a cross-sectional view of a step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of a graphene nanosheet and an rGO nanosheet, and the interconnect structure having trenches and vias;

[0019] Figure 3B is a cross-sectional view of another step of forming an interconnect structure including at least one of graphene nanosheets and rGO nanosheets, and having trenches and vias according to another embodiment shown and described herein;

[0020] Figure 3C is a cross-sectional view of another step of forming an interconnect structure including at least one of graphene nanosheets and rGO nanosheets, and having trenches and vias according to another embodiment shown and described herein;

[0021] Figure 3D is a cross-sectional view of another step of forming an interconnect structure including at least one of graphene nanosheets and rGO nanosheets, and having trenches and vias according to another embodiment shown and described herein;

[0022] Figure 3Eis a cross-sectional view of another step of forming an interconnect structure including at least one of graphene nanosheets and rGO nanosheets, and having trenches and vias according to another embodiment shown and described herein;

[0023] Figure 3F is a cross-sectional view of another step of forming an interconnect structure including at least one of graphene nanosheets and rGO nanosheets, and having trenches and vias according to another embodiment shown and described herein;

[0024] Figure 3G is a cross-sectional view of another step of forming an interconnect structure including at least one of graphene nanosheets and rGO nanosheets, and having trenches and vias according to another embodiment shown and described herein;

[0025] Figure 4A is a cross-sectional view of a step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0026] Figure 4B is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having trenches and vias;

[0027] Figure 4C is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0028] Figure 4D is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0029] Figure 4E is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0030] Figure 4Fis a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0031] Figure 4G is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0032] Figure 5A is a cross-sectional view of steps of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having trenches and vias, according to another embodiment shown and described herein;

[0033] Figure 5B is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having trenches and vias;

[0034] Figure 5C is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having trenches and vias;

[0035] Figure 5D is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having trenches and vias;

[0036] Figure 5E is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having trenches and vias;

[0037] Fig. 5F is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having trenches and vias;

[0038] Figure 5G is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having trenches and vias;

[0039] Fig. 6A is a cross-sectional view of a step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0040] Figure 6B is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0041] Figure 6C is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0042] Fig.6D is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0043] Fig. 6E is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0044] Fig. 6F is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0045] Figure 6G is a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure comprising at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels;

[0046] Figure 6His a cross-sectional view of another step of forming an interconnect structure according to another embodiment shown and described herein, the interconnect structure including at least one of graphene nanosheets and rGO nanosheets and metal nanoparticles, and the interconnect structure having channels.

[0047] Reference will now be made in more detail to various embodiments of the present disclosure, some of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts / components. DETAILED DESCRIPTION

[0048] Reference will now be made in detail to various embodiments of methods of forming an interconnect structure, and particularly to various embodiments of methods of forming an interconnect structure using at least one of graphene nanosheets and reduced graphene oxide (rGO) nanosheets and a sacrificial polymer.

[0049] The present disclosure should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure is thorough and complete and fully conveys the subject matter to those skilled in the art.

[0050] definition

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terms used in the disclosure herein are only used to describe specific embodiments and are not intended to be limiting.

[0052] Ranges may be expressed herein as from "about" one particular value, and / or to "about" another particular value. When such a range is expressed, another embodiment includes from the one particular value and / or to the other particular value. Similarly, when values ​​are expressed as approximations, by use of the antecedent "approximately," it will be understood that the particular value forms another embodiment. It will be further understood that the endpoints of each range are both significant relative to the other endpoint and independent of the other endpoint.

[0053] Unless otherwise expressly stated, it is not intended that any method described herein be interpreted as requiring that its steps be performed in a particular order, or that it be performed in any particular orientation of the apparatus. Thus, if a method claim does not in fact indicate an order in which its steps are to be followed, or if any apparatus claim does not in fact indicate an order or orientation of components, or if the claim or specification does not otherwise expressly state that the steps are limited to a particular order, or does not indicate a particular order or orientation of apparatus components, then it is not intended to imply an order or orientation in any way. This applies to any possible non-explicit basis for interpretation, including: logical issues regarding the arrangement of steps, operational flow, order of components, or orientation of components; plain interpretation arising from grammatical organization or punctuation, and; the number or type of embodiments described in the specification.

[0054] As used in the specification and the appended claims, the singular forms "a, an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Thus, for example, reference to "a component" includes aspects having two or more of the components, unless the context clearly indicates otherwise.

[0055] As used herein, the term "interconnect structure" refers to a structure that electrically connects two or more circuit elements (eg, transistors).

[0056] As used herein, the term "trench" refers to a region etched deeply in a dielectric material. Trench can be used to construct horizontal interconnects of a substrate (e.g., a wafer substrate). A trench layer can be a network of trenches in a horizontal direction in a single layer. Once the trench layer is filled with a conductive material, the horizontal interconnects in the layer are formed.

[0057] As used herein, the term "via" refers to an opening in a dielectric layer, wherein a riser, or a region thereof, is provided to provide an electrical path (usually a vertical path) from one metal layer to an upper or lower metal layer. The via may connect two trench layers formed in the layering direction or vertical direction of the device.

[0058] As used herein, the term "field area" refers to a surface area outside the area of ​​interconnection lines (trench, via or both) in a multi-level interconnection structure of an IC chip device. The field area may be a portion of the dielectric material.

[0059] As used herein, the terms "dielectric" and "dielectric material" refer to materials that serve as electrical insulators between interconnects (trench and vias). In some embodiments, the dielectric material is a material having a relative dielectric constant of 50 or less, 40 or less, 30 or less, 20 or less, 10 or less, or even 3 or less.

[0060] As used herein, the term "flake size" refers to the length of the longest lateral axis of an object (eg, graphene) as determined by transmission electron microscopy (TEM).

[0061] As used herein, the term "mean" refers to the arithmetic mean of a characteristic dimension or some other measure of central tendency.

[0062] As used herein, the term "lateral dimension" refers to a dimension extending in a direction substantially perpendicular to the thickness direction of a planar object (eg, a graphene nanosheet).

[0063] As used herein, the term "thickness" refers to the minimum distance between two surfaces of an object (eg, a graphene nanosheet).

[0064] As used herein, the term "width" refers to a characteristic dimension of a feature, generally along a substantially horizontal direction.

[0065] As used herein, the term "depth" refers to a characteristic dimension of a feature, generally along a substantially vertical direction.

[0066] As used herein, the term "diameter" refers to a straight line through the center of a feature in the form of a sphere or disk, from one side to the other.

[0067] As used herein, the term "graphene" refers to a single atomic layer of carbon atoms tightly bonded in a hexagonal lattice similar to a honeycomb and forming sp 2 However, the graphene material obtained by exfoliating graphite usually has multiple single-layer graphenes stacked together, and depending on the exfoliation process, the surface of the graphene material also has different degrees of imperfection or defect. Oxygen-containing groups are usually present on the surface of the multilayer graphene material.

[0068] As used herein, the term "graphene nanosheet" refers to graphene in the form of nano-sized sheets formed by stacking multiple layers of single-layer graphene together. The graphene nanosheet used in the present invention has less than 30 layers of graphene (i.e., single-layer graphene), or less than 20 layers, or less than 10 layers of graphene. The lateral dimension of the graphene nanosheet is 1000nm or less, 700nm or less, 500nm or less, or 100nm or less.

[0069] As used herein, the term "nanosheet" refers to a substantially two-dimensional structure having a thickness in the range of 1 nm to 100 nm. In some embodiments, the width and length dimensions of a nanosheet may be greater than the thickness dimension.

[0070] As used herein, the term "lateral dimension of a graphene nanosheet" refers to the lateral dimension of a hypothetical disk having an equivalent area to a graphene nanosheet in its lateral dimension, even if the graphene nanosheet has an irregular shape. The graphene nanosheets prepared in the present disclosure may have an area size distribution in its lateral dimension, which can be measured by transmission electron microscopy (TEM). The measured area size distribution can be converted to a distribution of "lateral dimensions of graphene nanosheets" using a simple geometric relationship between the area and the lateral dimension of a circle. This distribution of "lateral dimensions of graphene nanosheets" can be plotted in a histogram that shows the frequency counts (in %) of each size interval over the entire lateral dimension of the graphene nanosheet material.

[0071] As used herein, the term "D50 of graphene nanoplatelets" refers to the value of a lateral dimension below which 50% (by count) of the graphene nanoplatelets in the population (measured by their lateral dimension) exist. Similarly, as used herein, the term "D90 of graphene nanoplatelets" refers to the value of a lateral dimension below which 90% (by count) of the graphene nanoplatelets in the population (measured) exist.

[0072] As used herein, the term "reduced graphene oxide nanosheets" refers to graphene oxide having an oxygen content reduced by a reduction process.

[0073] As used herein, the term "lateral dimension of a reduced graphene oxide nanosheet" refers to the lateral dimension of a hypothetical disk having an equivalent area to the reduced graphene oxide nanosheet in its lateral dimension, even if the reduced graphene oxide nanosheet has an irregular shape. The reduced graphene oxide nanosheets prepared in the present disclosure may have an area size distribution in its lateral dimension, which can be measured by TEM. The measured area size distribution can be converted to a distribution of "lateral dimensions of reduced graphene oxide nanosheets" using a simple geometric relationship between the area of ​​a circle and the lateral dimension. This distribution of "lateral dimensions of reduced graphene oxide nanosheets" can be plotted in a histogram showing the frequency counts (in %) of each size bin over the entire lateral dimension of the reduced graphene oxide nanosheet.

[0074] Continuous downward scaling in integrated circuit (IC) technology improves transistor performance by increasing switching speed and reducing power consumption. However, size reduction may have an adverse effect on the interconnect structure due to reduced electrical performance and reliability. Downward scaling can lead to a reduction in interconnect line width, which can lead to a surge in resistance because the influence of grain boundaries and electron surface scattering in metal lines increases. In addition, due to the reduction in line width, the current density inside the interconnect structure can also increase and exceed the current carrying capacity of traditional interconnect metals (such as copper and tungsten). This can lead to electromigration problems. In particular, when copper-based interconnects are heated due to their resistance and the high current density passing through, the copper atoms therein can migrate within the interconnect channel and at the interface, which can ultimately lead to interconnect failure (e.g., open circuit or short circuit). In addition, conventional methods for forming interconnect structures (such as chemical vapor deposition (CVD)) can be time-consuming and expensive.

[0075] Disclosed herein are methods for producing interconnect structures that alleviate the above-mentioned problems. Specifically, by using graphene nanosheets and / or rGO nanosheets to partially or completely replace copper, the interconnect structures produced by the present disclosure can alleviate the electromigration problem of copper because the amount of copper is reduced, and the graphene nanosheets and / or rGO nanosheets have relatively large lateral dimensions compared to single copper atoms, and are less likely to migrate when high currents pass through the interconnects. In addition, the sacrificial polymer used in the present disclosure can minimize the agglomeration of graphene nanosheets and / or rGO nanosheets, and improve the initial adhesion of graphene nanosheets and / or rGO nanosheets to dielectric materials with channels and through holes. Therefore, the interconnect structures produced by the present disclosure reduce interconnect failures (e.g., open circuits or short circuits) and improve the reliability and performance of integrated circuit chips.

[0076] The methods disclosed herein for producing interconnect structures can generally be described as comprising a polymer solution comprising at least one of graphene nanosheets and rGO nanosheets and a sacrificial polymer.

[0077] Method A—The conductive composition includes at least one of graphene nanosheets and rGO nanosheets

[0078] Reference Figure 1 , a method of forming an interconnect structure is shown at 100. The method 100 begins at step 110 by providing a polymer solution. The polymer solution may include a conductive composition, a sacrificial polymer, and a solvent.

[0079] The conductive composition may include at least one of graphene nanosheets and rGO nanosheets. In some embodiments, the graphene nanosheets and / or rGO nanosheets may be produced by a process of exfoliation and simultaneous size reduction of graphite materials. For example, the graphene nanosheets and / or rGO nanosheets may be prepared from expanded graphite materials dispersed and exfoliated in polar solvents. Using expanded graphite as a starting material may help ensure that the resulting graphene nanosheets have a certain thickness and lateral dimensions as defined herein, because expanded graphite materials may be easier to exfoliate than ordinary graphite materials.

[0080] Expanded graphite can be formed by expandable graphite after an expansion process (e.g., heat-triggered) occurs. Expandable graphite can be a modified graphite material with a high proportion of intercalated layers. In some embodiments, sulfur or nitrogen compounds can be used as intercalating agents. Under the influence of heat, the layers can be separated like an accordion, and the graphite sheets can expand. Depending on the grade of the expandable graphite, the expansion can start at as low as 180°C and occur suddenly and rapidly. In the case of free expansion, the final volume can be hundreds of times larger than the initial volume. Compared with the initial expandable graphite material, the number of graphene layers of the expandable graphite can be significantly reduced (e.g., reduced by 10 times). Subsequently, the expandable graphite can be subjected to further exfoliation and lateral dimensional reduction by liquid-assisted exfoliation, which involves ultrasonic treatment of the dispersed expandable graphene in a selected solvent.

[0081] The selected solvent may be a polar liquid solvent with a strong electron-withdrawing or electron-donating functional group (e.g., carbonyl). Potentially suitable solvents for liquid-assisted exfoliation include, but are not limited to, cyrene (i.e., dihydro-levulinic acid ketone), triacetin, butyl lactate, cyclic aliphatic ketones, benzonitrile, N,N-dimethylacetamide, morpholine, N-methyl-2-pyrrolidone (NMP), and dimethylformamide (DMF). The preferred solvent should have a surface energy that matches the graphene surface, as well as molecular-level electronic interactions between the graphene layer and the solvent molecules. In some embodiments, the solvent for liquid-assisted exfoliation may include cyrene (i.e., dihydro-levulinic acid ketone), because cyrene is a non-toxic solvent, obtained from waste, and is a fully biodegradable solvent with the benefit of sustainability. In some embodiments, a solvent (e.g., cyrene) for producing a dispersion of graphene nanosheets by liquid-assisted exfoliation of expanded graphite may also be included in the polymer solution.

[0082] In some embodiments, the expanded graphite as a starting material may have a sheet size of less than or equal to 100 mesh, a sheet size of less than or equal to 50 mesh, or a sheet size of less than or equal to 30 mesh.

[0083] The D50 of at least one of the graphene nanosheet and the rGO nanosheet along its lateral dimension may be less than or equal to 700 nanometers (nm) to ensure that at least one of the graphene nanosheet and the rGO nanosheet can fill the channel and / or through hole. For example, in some embodiments, the D50 of at least one of the graphene nanosheet and the rGO nanosheet along its lateral dimension may be less than or equal to 700nm, less than or equal to 500nm, less than or equal to 200nm, or even less than or equal to 100nm. In some embodiments, the D50 of at least one of the graphene nanosheet and the rGO nanosheet along its lateral dimension may be greater than or equal to 5nm, greater than or equal to 10nm, greater than or equal to 15nm, or even greater than or equal to 20nm. In some embodiments, the D50 of at least one of the graphene nanosheets and the rGO nanosheets may be 5 nm to 700 nm, 5 nm to 500 nm, 5 nm to 200 nm, 5 nm to 100 nm, 10 nm to 700 nm, 10 nm to 500 nm, 10 nm to 200 nm, 10 nm to 100 nm, 15 nm to 700 nm, 15 nm to 500 nm, 15 nm to 200 nm, 15 nm to 100 nm, 20 nm to 700 nm, 20 nm to 500 nm, 20 nm to 200 nm, or even 20 nm to 100 nm, or any and all subranges formed by any of these endpoints.

[0084] In some embodiments, the average thickness of at least one of the graphene nanosheets and the rGO nanosheets may be less than or equal to 15 nm, less than or equal to 12.5 nm, or even less than or equal to 10 nm. In some embodiments, the average thickness of at least one of the graphene nanosheets and the rGO nanosheets may be greater than or equal to 0.1 nm, greater than or equal to 0.2 nm, greater than or equal to 0.3 nm, or greater than or equal to 0.35 nm. In some embodiments, at least one of the graphene nanosheets and the rGO nanosheets may have an average thickness of 0.1 nm to 15 nm, 0.1 nm to 12.5 nm, 0.1 nm to 10 nm, 0.2 nm to 15 nm, 0.2 nm to 12.5 nm, 0.2 nm to 10 nm, 0.3 nm to 15 nm, 0.3 nm to 12.5 nm, 0.3 nm to 10 nm, 0.35 nm to 15 nm, 0.35 nm to 12.5 nm, or even 0.35 nm to 10 nm, or any and all subranges formed by any of these endpoints.

[0085] The sacrificial polymer may help stabilize the graphene dispersion by preventing graphene nanosheets from self-agglomerating in the polymer solution.

[0086] In some embodiments, the sacrificial polymer may be polar. Due to the interaction between the polar groups of the sacrificial polymer and the polar groups present on the surface of the dielectric material, the polar sacrificial polymer may have good adhesion to common silicon-based dielectric materials (such as silicon, silicon dioxide, silicon carbide, silicon nitride, or a combination thereof). Various sacrificial polymers are considered to be suitable for polymer solutions of the present application. In some embodiments, the sacrificial polymer may be selected from: polypropylene carbonate (PPC), polymethyl methacrylate (PMMA), poly(phthalaldehyde), including cyclic poly(phthalaldehyde), polylactide, and polyhydroxyalkanoate, and combinations thereof. In some embodiments, the sacrificial polymer may not include cellulose acetate butyrate. In some embodiments, the polymer solution may not include cellulose acetate butyrate.

[0087] In some embodiments, the polymer solution can include an amount of sacrificial polymer in order to achieve a desired polymer solution viscosity (eg, 7 to 55 centipoise) for a spin coating process.

[0088] Various solvents are considered suitable for use in the polymer solutions of the present application. In some embodiments, the solvent may be a polar solvent. In some embodiments, the solvent may include one or more of the following: cyrene, triacetin, butyl lactate, cyclic aliphatic ketones, benzonitrile, N,N-dimethylacetamide, morpholine, N-methyl-2-pyrrolidone (NMP), dimethylformamide (DMF), and combinations thereof.

[0089] In some embodiments, the graphene nanosheets are the only conductive filler dispersed in the polymer solution.

[0090] Back to Figure 1 , method 100 continues at step 120, where a dielectric material is provided. Figure 2A , the dielectric material 11 may include a trench 151 formed into the surface of the dielectric material 11. In some embodiments, a first dielectric passivation layer 12 may be disposed on at least a portion of the dielectric material 11. In some embodiments, the first dielectric passivation layer 12 may not be disposed on the trench 151. In some embodiments, the first dielectric passivation layer 12 may include silicon oxide. In some embodiments, a barrier layer 13 may be disposed on the first dielectric passivation layer 12 and the trench 151. In some embodiments, the barrier layer 13 may include tantalum nitride.

[0091] Reference Figure 3A In an alternative embodiment, the dielectric material 21 may have a trench 151 and a through hole 152. The through hole 152 may be disposed in the trench 151. The dielectric material 21 may be disposed on the first dielectric passivation layer 24. In some embodiments, the first dielectric passivation layer 24 may include silicon nitride. In some embodiments, a second dielectric passivation layer 22 may be disposed on at least a portion of the dielectric material 21. In some embodiments, the second dielectric passivation layer 22 may not be disposed on the trench 151 and the through hole 152. In some embodiments, the second dielectric passivation layer 22 may include silicon oxide. In some embodiments, a barrier layer 23 may be disposed on the second dielectric passivation layer 22, the trench 151, and the through hole 152. In some embodiments, the barrier layer 23 may include tantalum nitride.

[0092] In some embodiments, the width of each of the trench 151 and the via 152 may be less than or equal to 1000 nm, less than or equal to 500 nm, or even less than or equal to 300 nm. In some embodiments, the width of each of the trench 151 and the via 152 may be greater than or equal to 5 nm, greater than or equal to 10 nm, greater than or equal to 15 nm, or even greater than or equal to 30 nm. In some embodiments, the width of each of the trench 151 and the via 152 may be 5 nm to 1000 nm, 5 nm to 500 nm, 5 nm to 300 nm, 10 nm to 1000 nm, 10 nm to 500 nm, 10 nm to 300 nm, 15 nm to 1000 nm, 15 nm to 500 nm, 15 nm to 300 nm, 30 nm to 1000 nm, 30 nm to 500 nm, or even 30 nm to 300 nm, or any and all sub-ranges formed by any of these endpoints. With these width ranges, the lateral dimensions of at least one of the graphene nanosheets and the rGO nanosheets 111 as described herein may be able to fill the trenches 151 and / or the through-holes 152 .

[0093] In some embodiments, the depth to width aspect ratio of the channel 151 can be greater than or equal to 0.5, greater than or equal to 1.0, or even greater than or equal to 1.5. In some embodiments, the depth to width aspect ratio of the channel 151 can be less than or equal to 4.0, less than or equal to 3.5, less than or equal to 3.0, or even less than or equal to 2.5. In some embodiments, the depth to width aspect ratio of the channel 151 can be 0.5 to 4.0, 1.0 to 4.0, 1.5 to 4.0, 0.5 to 3.5, 1.0 to 3.5, 1.5 to 3.5, 0.5 to 3.0, 1.0 to 3.0, 1.5 to 3.0, 0.5 to 2.5, 1.0 to 2.5, or even 1.5 to 2.5, or any and all sub-ranges formed by any of these endpoints.

[0094] In some embodiments, the depth to width aspect ratio of the through hole 152 may be greater than or equal to 0.5, greater than or equal to 1.0, or even greater than or equal to 1.5. In some embodiments, the depth to width aspect ratio of the through hole 152 may be less than or equal to 4.0, less than or equal to 3.5, less than or equal to 3.0, or even less than or equal to 2.5. In some embodiments, the depth to width aspect ratio of the through hole 152 may be 0.5 to 4.0, 1.0 to 4.0, 1.5 to 4.0, 0.5 to 3.5, 1.0 to 3.5, 1.5 to 3.5, 0.5 to 3.0, 1.0 to 3.0, 1.5 to 3.0, 0.5 to 2.5, 1.0 to 2.5, or even 1.5 to 2.5, or any and all sub-ranges formed by any of these endpoints.

[0095] Still refer to Figure 1 , 2A , and 3A, a polymer solution 101 may be provided on the dielectric material 11 , 21 , the polymer solution 101 comprising at least one of the graphene nanosheets and the rGO nanosheets 111 , a solvent 121 , and a sacrificial polymer 131 .

[0096] Back to Figure 1 , now refer to Figure 2B and Figure 3B The method 100 continues at step 130, where the polymer solution 101 is spin-coated on the dielectric material 11, 21 to form a dispersion in the channel 151 (eg, Figure 2B ), or forming a dispersion in the channel 151 and the through hole 152 (as shown in Figure 3B ). Compared with CVD, spin coating can be faster and consume less energy. In some embodiments, the polymer solution 101 on the dielectric material 11, 21 can be spin-coated onto a wafer substrate having a trench and field region 156 of interconnect lines. The polymer solution 101 can be spin-coated to form a polymer solution 101 coating on the dielectric material 11, 21. The polymer solution 101 coating after step 130 may include a sacrificial polymer 131, residual solvent 121, and at least one of graphene nanosheets and rGO nanosheets 111. The sacrificial polymer 131 can act as a binder in the polymer solution 101 coating layer. The sacrificial polymer has good adhesion to the barrier layer 13 disposed on the wall and bottom of the trench 151 and the field region 156.

[0097] Back to Figure 1 , now refer to Figure 2C and 3C The method 100 continues at step 140, wherein the dielectric material 11, 21 is baked to remove both the residual solvent 121 and the sacrificial polymer 131 of the coating layer of the polymer solution 101, thereby forming an exposed surface of the conductive composition including at least one of the graphene nanosheets and the rGO nanosheets 111. The dielectric material 11 can be baked to completely remove the sacrificial polymer 131 and the residual solvent 121 ( Figure 2B and 3B ).

[0098] In some embodiments, the dielectric material 11, 21 may be baked under an inert gas. In some embodiments, the dielectric material 11, 21 may be baked at a temperature greater than or equal to 350° C., greater than or equal to 400° C., greater than or equal to 450° C., or even greater than or equal to 500° C. In some embodiments, the dielectric material 11, 21 may be baked at a temperature less than or equal to 1000° C., less than or equal to 950° C., or even less than or equal to 900° C. In some embodiments, the dielectric material 11, 21 may be baked at a temperature of 350°C to 1000°C, 350°C to 950°C, 350°C to 900°C, 400°C to 1000°C, 400°C to 950°C, 400°C to 900°C, 450°C to 1000°C, 450°C to 950°C, 450°C to 900°C, 500°C to 1000°C, 500°C to 950°C, or even 500°C to 900°C, or any and all subranges formed by any of these endpoints. At these temperature ranges, the sacrificial polymer 131 may decompose in step 140. In some embodiments, at least 90%, at least 95%, at least 99%, or at least 99.9% of the sacrificial polymer 131 may decompose in step 140.

[0099] Back to Figure 1 In some embodiments, method 100 may optionally continue at step 145, wherein the rGO nanosheets are reduced to graphene nanosheets by an annealing step. In some embodiments, the oxygen content of the rGO nanosheets (typically between 10 wt % and 20 wt %) may be reduced to less than or equal to 3 wt % by the annealing step in order to convert the rGO into graphene nanosheets. The reduction step 145 may improve the electrical properties of the conductive composition comprising the rGO nanosheets. In some embodiments, the rGO nanosheets may be converted to graphene nanosheets by the annealing step in the presence of a reducing agent. The reducing agent may comprise hydrogen.

[0100] Back to Figure 1 In some embodiments, method 100 may optionally continue at step 150, where one or more of steps 130, 140, and 145 may be repeated until at least one of the graphene nanosheets and the rGO nanosheets fills the trenches 151 and / or the through-holes 152 to a depth such as Figure 2D and 3D By repeating steps 130, 140, and 145, the amount of copper composition electroplated can be reduced. In some embodiments, step 130 can be repeated one or more times before performing step 140 or performing steps 140 and 145. In some embodiments, steps 130 and 140 can be repeated one or more times. In some embodiments, all of steps 130, 140, and 145 can be repeated one or more times. Back Figure 1 , now refer to Figure 2D and Figure 3D , method 100 continues at step 160, where a metal seed layer 200 is sputtered onto the exposed surface of the conductive composition (including at least one of the graphene nanosheets and the rGO nanosheets 111). In some embodiments, the metal seed layer 200 can be selected from copper, copper alloys, and both. The metal seed layer 200 can be sputtered onto: at least one of the graphene nanosheets and the rGO nanosheets 111, the barrier layer 13 disposed on the first dielectric passivation layer 12, and the channel 151, such as Figure 2D or sputtered to at least one of the graphene nanosheets and the rGO nanosheets 111, a barrier layer 23, a channel 151, and a through hole 152 disposed on the second dielectric passivation layer 22, as shown; Figure 3D In some embodiments, after step 140, voids 105 may be formed below some graphene nanosheets and rGO nanosheets. Voids 105 may be formed as shown in FIG. Figure 2D and 3D That is maintained and may also be present in the final interconnect structure in the subsequent steps 170 and 180. This may be because the sputtering process (step 160) is a conformal coating process and may not fill those void 105 spaces under some graphene nanosheets and rGO nanosheets.

[0101] Back to Figure 1 , now refer to Figure 2E and 3E , the method 100 continues at step 170, where a layer of the copper composition 300 is electroplated to the metal seed layer 200. In some embodiments, the copper composition 300 may be selected from copper, a copper-dominated alloy, and both. In some embodiments, the copper composition 300 may be copper having a purity greater than 99%, or a purity greater than or equal to 99.5%. In some embodiments, the copper-dominated alloy may be an alloy having greater than or equal to 90 weight percent (wt%), 95 weight percent, 98 weight percent, 99 weight percent, or 99.5 weight percent copper, based on the total weight of the alloy. In step 170, a layer of the copper composition 300 may be electroplated to the metal seed layer 200 so as to fill the trench 151. In step 170, at least one of the graphene nanosheets and the rGO nanosheets 111 may be a filler at least partially embedded in the layer of the copper composition 300. The layer of copper composition 300 may be electroplated onto the metal seed layer 200 and fill the trench 151, as shown in FIG. Figure 2E or electroplated to the metal seed layer 200 and fill the channel 151 and the through hole 152, such as Figure 3E as shown in .

[0102] Back to Figure 1 , now refer to Figure 2F and Figure 3F , the method 100 continues at step 180, where the layer of the copper composition 300 is subjected to chemical mechanical polishing (CMP). In step 180, at least one of the top layers of the dielectric materials 11, 21 may be planarized. In step 180, the excess layer of the copper composition 300 above the level of the trench 151 may be polished away. In step 180, during the CMP process, a certain depth of the top surface of the dielectric material 11, 21 may be removed until the layer (e.g., the layer 111 comprising at least one of the graphene nanosheets and the rGO nanosheets) in the field region 156 is removed from the field region 156. Figure 2C , 2D , 2E, 3C, 3E and 3F). As required, the depth of removal can be up to 100 nm so as to remove the remaining layer including at least one of the graphene nanosheets and the rGO nanosheets 111 remaining in the field region 156. In step 180, some of the top layer of the copper composition 300 can be removed from the metal seed layer 200 and the trench 151 (e.g. Figure 2F ), or removed from the metal seed layer 200, the trench 151 and the via 152 (as shown in Figure 3F The barrier layer 13 disposed on the first dielectric passivation layer 12 may be removed, as shown in Figure 2F The barrier layer 23 disposed on the second dielectric passivation layer 22 may be removed, as shown in FIG. Figure 3F shown.

[0103] In some embodiments, in step 180, a portion of the copper in the layer of copper composition 300 may be oxidized in the presence of an oxidizing agent. In some embodiments, the oxidizing agent may be selected from: H2O2 (i.e., hydrogen peroxide), HNO4, and Fe +3 In step 180, a portion of the oxidized copper may be removed. In step 180, a portion of the layer of the copper composition 300 may be oxidized to form an oxide layer 400, and at least a portion of the oxide layer 400 may be removed from the layer of the copper composition 300 and the trench 151, as shown in FIG. Figure 2F or removed from the copper composition layer 300, the channel 151, and the through hole 152, as shown in Figure 3F Only shown. The conductivity of the oxidized copper may be lower than that of copper. In some embodiments, the oxidized copper may be reduced back to copper by an annealing step in the presence of a reducing agent. The reducing agent may include hydrogen.

[0104] In some embodiments, another dielectric passivation layer may be disposed on the trench to close the trench. In some embodiments, the another dielectric passivation layer may include silicon nitride. For example, a second dielectric passivation layer 14 may be disposed on the dielectric passivation layer 12, the layer of the copper composition 300, and the trench 151, such as Figure 2G A third dielectric passivation layer 25 may be disposed on the first dielectric passivation layer 22, the layer of the copper composition 300, the trench 151, and the through hole 152, as shown in FIG. Figure 3G as shown in .

[0105] Method B—The conductive composition includes metal nanoparticles and at least one of graphene nanosheets and rGO nanosheets

[0106] In some embodiments, the conductive composition may further include metal nanoparticles. During the formation of the interconnect structure, the metal nanoparticles may form a continuous melt phase that contacts the conductive barrier layer at the bottom surface and sidewalls of the trench and ensures good connection between the barrier layer and at least one of the graphene nanosheets and rGO nanosheets, thereby improving the overall conductivity of the interconnect structure. With respect to a polymer solution including at least graphene nanosheets and reduced rGO nanosheets, a sacrificial polymer, and a solvent, the method for forming an interconnect structure including a polymer solution having metal nanoparticles is similar to method A. For example, returning to Figure 1 , in step 110, a polymer solution is provided. The polymer solution may include a conductive composition, a sacrificial polymer and a solvent. The conductive composition may include at least one of graphene nanosheets, reduced graphene oxide (rGO) nanosheets, and metal nanoparticles. The sacrificial polymer and the solvent included in the polymer solution including the metal nanoparticles may be similar or identical to the sacrificial polymer and the solvent associated with method A described above. Various metal nanoparticles are considered suitable for the conductive composition of the present application. In some embodiments, the metal nanoparticles may be selected from: copper, cobalt, ruthenium, nickel, titanium, aluminum, silver, gold, tungsten, platinum, palladium, and combinations thereof.

[0107] In some embodiments, the average diameter of the metal nanoparticles may be less than the average lateral dimension of at least one of the graphene nanosheets and the rGO nanosheets. The smaller metal nanoparticles may go between at least one of the graphene nanosheets and the rGO nanosheets in the polymer coating layer. This may help reduce the probability of self-agglomeration of graphene nanosheets in the process. In some embodiments, the average diameter of the metal nanoparticles may be less than or equal to 25nm, less than or equal to 22.5nm, or even less than or equal to 20nm. In some embodiments, the average diameter of the metal nanoparticles may be greater than or equal to 2nm, greater than or equal to 3nm, greater than or equal to 4nm, or even greater than or equal to 5nm. In some embodiments, the average diameter of the metal nanoparticles may be 1 nm to 25 nm, 1 nm to 22.5 nm, 1 nm to 20 nm, 2 nm to 25 nm, 2 nm to 22.5 nm, 2 nm to 20 nm, 3 nm to 25 nm, 3 nm to 22.5 nm, 3 nm to 20 nm, 4 nm to 25 nm, 4 nm to 22.5 nm, 4 nm to 20 nm, 5 nm to 25 nm, 5 nm to 22.5 nm, or even 5 nm to 20 nm, or any and all subranges formed by any of these endpoints.

[0108] In some embodiments, the metal nanoparticles may be pretreated with a thiolate capping ligand before providing the metal nanoparticles in the polymer solution. The thiolate capping ligand may have at least a second polar terminal group selected from -COOH, -OH, -SH, and combinations thereof. This pretreatment step may improve the dispersion of the metal nanoparticles in the polymer solution. This pretreatment step may promote a stronger interaction between the metal nanoparticles and at least one of the graphene nanosheets and the rGO nanosheets, because hydrogen bonds may exist between the second polar terminal groups (hydrogen donors) on the surface of the metal nanoparticles and the oxygen-containing groups (e.g., carbonyl groups as hydrogen acceptors) on the surface of at least one of the graphene nanosheets and the rGO nanosheets. Stronger star-lake interactions between the metal nanoparticles and at least one of the graphene nanosheets and the rGO nanosheets may prevent self-agglomeration of at least one of the graphene nanosheets and the rGO nanosheets, which may reduce the conductivity of the resulting interconnects.

[0109] Back to Figure 1 , method 100 continues at step 120, where a dielectric material is provided. Figure 4A and 5A As shown in FIG. 1 , the dielectric materials 11 and 21 may be used in conjunction with the method A, as described in Figure 2A and 3A The dielectric materials shown in are the same or similar.

[0110] Back to Figure 1 , now refer to Figure 4B and 5B The method 100 continues at step 130 by spin coating the polymer solution 101 on the dielectric material 11, 21 to form a dispersion in the channel 151, such as Figure 4B As shown in , or a dispersion is formed in the channel 151 and the through hole 152, as shown in Figure 5B As shown in . A polymer solution 101 (which includes at least one of the graphene nanosheets and the rGO nanosheets 111, a solvent 121, a sacrificial polymer 131, and metal nanoparticles 141) may be provided in a spin coating step 130 and applied to the dielectric material 11, 21. After the spin coating step 130, a coating layer of the polymer solution 101 (which includes at least one of the graphene nanosheets and the rGO nanosheets 111, residual solvent 121, sacrificial polymer 131, and metal nanoparticles 141) may be present in the channel 151 and the surrounding field region 156, as shown in FIG. Figure 4B As shown in , or exists in the trench 151 and the through hole 152, and the surrounding field region 156, as shown in Figure 5B as shown in .

[0111] Back to Figure 1 , now refer to Figure 4C and 5C The method 100 continues at step 140 by baking the dielectric materials 11, 21 to remove the sacrificial polymer 131 and the residual solvent 121 ( Figure 4B and 5B ), forming an exposed surface of the conductive composition, the conductive composition comprising at least one of the graphene nanosheets and the rGO nanosheets 111 and metal nanoparticles 141. Step 140 may further include sintering the metal nanoparticles 141. In the sintering step, the metal nanoparticles 141 may be sintered to form a continuous metal phase 161. The sintering step may cause at least one of the graphene nanosheets and the rGO nanosheets 111 to be partially repelled from the continuous metal phase 161 (i.e., partially embedded in the continuous metal phase 161), while the at least one of the graphene nanosheets and the rGO nanosheets 111 may remain in full contact with the continuous melt phase 161. During the sintering process, the at least one of the graphene nanosheets and the rGO nanosheets 111 may move to the top portion of the continuous metal phase 161 because the density of graphene is lighter than that of metal. The continuous melt phase 161 ensures connection between the dielectric material 11 , 21 and at least one of the graphene nanosheets and the rGO nanosheets 111 , thereby resulting in improved conductivity.

[0112] Due to their nanometer size, the metal nanoparticles 141 may have a melting point lower than the corresponding bulk metal. In some embodiments, the melting point of the metal nanoparticles may be greater than or equal to 100° C., greater than or equal to 120° C., greater than or equal to 140° C., greater than or equal to 160° C., greater than or equal to 180° C., or even greater than or equal to 200° C. In some embodiments, the melting point of the metal nanoparticles 141 may be less than or equal to 400° C., less than or equal to 420° C., less than or equal to 440° C., less than or equal to 460° C., less than or equal to 480° C., or even less than or equal to 500° C. In some embodiments, the melting point of the metal nanoparticles 141 may be 100° C. to 400° C., 100° C. to 420° C., 100° C. to 440° C., 100° C. to 460° C., 100° C. to 480° C., 100° C. to 500° C., 120° C. to 400° C., 120° C. to 420° C., 120° C. to 440° C., 120° C. to 460° C., 120° C. to 480° C., 120° C. to 500° C., 140° C. to 400° C., 140° C. to 420° C., 140° C. to 440° C., 140° C. to 460° C., 140° C. to 480° C., 140° C. to 500° C., 1 ℃ to 60℃ to 400℃, 160℃ to 420℃, 160℃ to 440℃, 160℃ to 460℃, 160℃ to 480℃, 160℃ to 500℃, 180℃ to 400℃, 180℃ to 420℃, 180℃ to 440℃, 180℃ to 460℃, 180℃ to 480℃, 180℃ to 500℃, 200℃ to 400℃, 200℃ to 420℃, 200℃ to 440℃, 200℃ to 460℃, 200℃ to 480℃, and even 200℃ to 500℃, or any and all subranges formed by any of these endpoints.

[0113] Back to Figure 1 In some embodiments, method 100 may optionally continue at step 145, wherein the rGO nanosheets are reduced to graphene nanosheets by an annealing step. In some embodiments, the oxygen content of the rGO nanosheets (normally between 10 wt % and 20 wt %) may be reduced to less than or equal to 3 wt % by the annealing step, thereby converting the rGO into graphene nanosheets. The reduction step 145 may improve the electrical properties of the conductive composition comprising the rGO nanosheets. In some embodiments, the rGO nanosheets may be converted to graphene nanosheets by the annealing step in the presence of a reducing agent. The reducing agent may include hydrogen.

[0114] Back to Figure 1In some embodiments, method 100 may optionally continue at step 150, where steps 130, 140, and 145 may be repeated until at least one of the graphene nanosheets and the rGO nanosheets and the metal nanoparticles 141 fill the trenches 151 and / or through-holes 152 to a depth such as Figure 4C and 5C By repeating steps 130, 140, and 145, the amount of electroplating copper composition required can be reduced.

[0115] Back to Figure 1 , now refer to Figure 4D and 5D , method 100 continues at step 160, where a metal seed layer 200 is sputtered onto the exposed surface of the conductive composition, the conductive composition including the graphene nanosheets and the rGO nanosheets 111, and the continuous metal phase 161. In some embodiments, the metal seed layer 200 can be sputtered to cover at least one of the graphene nanosheets and the rGO nanosheets 111, the exposed surface of the continuous metal phase 161, or both. In some embodiments, the metal seed layer 200 can be selected from copper, copper alloys, and both. The metal seed layer 200 can be sputtered onto at least one of the graphene nanosheets and the rGO nanosheets 111, the continuous metal phase 161, the barrier layer 13 disposed on the dielectric passivation layer 12, and the channel 151, such as Figure 4D As shown in, or sputtered to at least one of the graphene nanosheets and the rGO nanosheets 111, the continuous metal phase 161, the barrier layer 23 disposed on the second dielectric passivation layer 22, the channel 151, and the through hole 152, as shown in Figure 5D as shown in . Figure 2D and 3D The gap 105 shown in FIG. 1 may not exist Figure 4D and 5D In the embodiment of the present invention, the continuous metal phase 161 may be able to fill the voids between the graphene nanosheets and the rGO nanosheets that would exist in the absence of the metal nanoparticles during the baking step. The absence of voids in the final interconnects may increase the electrical contact resistance of the deposited conductive composition in the interconnect trenches and vias.

[0116] Back to Figure 1 , now refer to Figure 4E and 5E , method 100 continues at step 170 where a layer of copper composition 300 is electroplated onto metal seed layer 200. Figure 4E and 5E As shown in FIG. 1 , step 170 of method B may be performed with Figure 2E

[0117] The same or similar to step 170 shown in 3E and described above with respect to method A.

[0118] Back to Figure 1 , now refer to Figure 4F and 5F The method 100 continues at step 180, wherein the copper composition 300

[0119] The layer is subjected to chemical mechanical polishing. Figure 4F and 5F As shown in FIG. 1 , step 180 of method B may be performed with Figure 2F and 3F The process may be the same or similar to step 180 as shown in FIG. 1 and described above with respect to method A.

[0120] Still for reference Figure 4G and 5G , another dielectric passivation layer 14, 25 may be connected with Figure 2G and 3G , or in a manner identical or similar to that described above with respect to method A.

[0121] Method C—Polymer solution includes photoinitiator and crosslinker

[0122] In some embodiments, the sacrificial polymer component of the polymer solution may further include a photoinitiator and a cross-linking agent to add a photoresistance function to the sacrificial polymer component. The photoresistance function of the sacrificial polymer component may allow the coated polymer layer (which includes the graphene nanosheets, rGO nanosheets, or both) to be selectively removed from the field area. Back Figure 1 , now refer to Fig. 6A , method 100 begins at step 110, wherein a polymer solution 101 is provided. The polymer solution 101 may include at least one of the graphene nanosheets and the rGO nanosheets 111, a solvent 121, a sacrificial polymer component 132, and metal nanoparticles 141. The sacrificial polymer component 132 may include the sacrificial polymer described in methods A and B, and further include a photoinitiator and a cross-linking agent.

[0123] In some embodiments, the photoinitiator may be selected from: azobisisobutyronitrile, benzoyl peroxide, camphorquinone, benzophenone, 2-phenylacetophenone, acetophenone derivatives (such as 2,2-dimethoxy-2-phenylacetophenone), and combinations thereof. In some embodiments, the crosslinking agent may be selected from: multifunctional acrylates, multifunctional methacrylates, and both. Multifunctional acrylates and multifunctional methacrylates may be selected from: trimethylolpropane triacrylate, trimethylolpropane trimethacrylate, pentaerythritol triacrylate, pentaerythritol tetraacrylate, dipentaerythritol pentaacrylate, 1,6-hexanediol diacrylate, polyethylene glycol diacrylate, and combinations thereof.

[0124] Still refer to Figure 1 and Fig. 6A The method continues at step 120 where a dielectric material is provided. Fig. 6A As shown in FIG. , the dielectric material 11 may be Figure 4A The dielectric material 100 may be the same or similar to the dielectric material shown in , with respect to method B. In the spin coating step 130 , a polymer solution 101 (which includes at least one of the graphene nanosheets and the rGO nanosheets 111 , a solvent 121 , a sacrificial polymer component 132 , and metal nanoparticles 141 ) may be provided and applied to the dielectric material 11 .

[0125] Back to Figure 1 , now refer to Figure 6B The method 100 continues at step 130 by spin coating the polymer solution 101 on the dielectric material 11 to form a dispersion in the channel 151, such as Figure 4B In the spin coating step 130 , a polymer solution 101 (which includes at least one of the graphene nanosheets and the rGO nanosheets 111 , a solvent 121 , a sacrificial polymer component 132 , and metal nanoparticles 141 ) may be provided and applied onto the dielectric material 11 , 21 .

[0126] Back to Figure 1 , now refer to Figure 6C , method 100 continues at step 135, where the polymer coating layer (spin-coated polymer solution) is exposed to a radiation source together with dielectric material 11 through a photomask. The radiation source can be selected from UV light, electron beam, gamma-irradiation, and combinations thereof. The masked area of ​​the photomask can overlap with field region 156. After step 135, the polymer coating layer (dispersion) in the channel region can be cross-linked, while the polymer coating layer in field region 156 can remain uncross-linked.

[0127] Back to Figure 1 , now refer to Fig.6D , method 100 continues at step 137, where the irradiated polymer coating (spin-coated polymer solution) is developed by a solvent, which is then used to remove the uncrosslinked polymer coating in field 156. In some embodiments, the solvent used in the development step 137 can be a good solvent for the sacrificial polymer. The solvent can be the same as or different from the solvent used to make the polymer solution.

[0128] Back to Figure 1 , now refer to Fig.6D The method 100 continues at step 140, where the dielectric material 11 is baked so that the sacrificial polymer 131 (eg, Figure 6C As shown in ) and residual solvent, thereby forming an exposed surface of the conductive composition. Fig.6D As shown in FIG. 1 , step 140 of method C may be performed with Figure 4C The step 140 shown in FIG. 1 is the same or similar to the step 140 described above with respect to method B.

[0129] Back to Figure 1 In some embodiments, method 100 may optionally continue at step 145, wherein the rGO nanosheets are reduced to graphene nanosheets by an annealing step. In some embodiments, the oxygen content of the rGO nanosheets (which is generally between 10 wt % and 20 wt %) may be reduced to less than or equal to 3 wt % by the annealing step, thereby converting the rGO into graphene nanosheets. The reduction step 145 may improve the electrical properties of the conductive composition comprising the rGO nanosheets. In some embodiments, the rGO nanosheets may be converted to graphene nanosheets by the annealing step in the presence of a reducing agent. The reducing agent may include hydrogen.

[0130] Back to Figure 1 In some embodiments, method 100 may optionally continue at step 150, where steps 130, 140, and 145 may be repeated until at least one of the graphene nanosheets and the rGO nanosheets and the metal nanoparticles 141 fill the channel 151 to a depth such as Fig.6D By repeating steps 130, 140, and 145, the amount of copper composition electroplated can be reduced. In some embodiments, step 130 can be repeated one or more times before proceeding to step 140 or steps 140 and 145. In some embodiments, steps 130 and 140 can be repeated one or more times. In some embodiments, all of 130, 140, and 145 can be repeated one or more times.

[0131] Back to Figure 1 , now refer to Fig. 6EThe method 100 continues at step 160 by sputtering a metal seed layer 200 onto the exposed surface of the conductive composition. Fig. 6E As shown in FIG. 1 , step 160 of method C may be performed with Figure 4F The step 160 shown in FIG. 1 is the same or similar to the step 160 described above with respect to method B.

[0132] Back to Figure 1 , now refer to Fig. 6F , method 100 continues at step 170 where a layer of copper composition 300 is electroplated onto metal seed layer 200. Fig. 6F As shown in FIG. 1 , step 170 of method C may be performed with Figure 4E The step 170 shown in FIG. 1 is the same or similar to the step 170 described above with respect to method B.

[0133] Back to Figure 1 , now refer to Figure 6G , method 100 continues at step 180, where the layer of copper composition 300 is subjected to chemical mechanical polishing. Figure 6G As shown in FIG. 1 , step 180 in method C can be performed with Figure 4F The step 180 shown in FIG. 1 is the same or similar to the step 180 described above with respect to method B.

[0134] Still for reference Figure 6H , can be compared with Figure 4G A further dielectric passivation layer 14, 25 is provided in the same or similar manner as described above with respect to method B as shown in FIG.

[0135] Interconnection structure

[0136] In some embodiments, the interconnect structure can be produced by at least one of method A, method B, and method C. Figure 2G , 4G , and 6H, the interconnect structure may be a single-layer interconnect structure having a trench 151. Figure 3G and 5G , the interconnect structure may be a dual-damascene interconnect structure having trenches 151 and vias 152. The conductivity filled in trenches 151 and vias 152 is substantially heterogeneous because the graphene nanosheet fillers are dispersed in a continuous copper matrix of trenches and vias.

[0137] The interconnect structure may be used in an integrated circuit (IC).

[0138] It will be apparent that modifications and variations may be made without departing from the scope of the disclosure as defined in the appended claims.More specifically, although some aspects of the present disclosure are identified herein as preferred or particularly advantageous, the present disclosure is not necessarily intended to be limited to these aspects.

Claims

1. A method for forming an interconnect structure, the method comprising: (i) providing a polymer solution, wherein the polymer solution comprises: a conductive composition comprising at least one of graphene nanosheets and reduced graphene oxide (rGO) nanosheets; Sacrificial polymers; and Solvents; (ii) providing a dielectric material, wherein the dielectric material comprises channels formed into a surface of the dielectric material; (iii) spin coating the polymer solution onto the dielectric material to form a dispersion of the conductive composition within the sacrificial polymer in the trench; (iv) baking the dielectric material to remove the sacrificial polymer, thereby forming an exposed surface of the conductive composition; (v) optionally, reducing the rGO nanosheets to the graphene nanosheets by an annealing step, wherein the rGO nanosheets included in the conductive composition are reduced to the graphene nanosheets; (vi) sputtering a metal seed layer onto the exposed surface of the conductive composition; (vii) electroplating a layer of a copper composition onto the metal seed layer; as well as (viii) subjecting the layer of the copper composition to chemical mechanical polishing. 2 . The method for forming the interconnect structure according to claim 1 , wherein the conductive composition further comprises metal nanoparticles.

3. The method of forming the interconnect structure of claim 2, wherein the step of baking the dielectric material sinters the metal nanoparticles to form a continuous metal phase.

4. The method of forming the interconnect structure as claimed in claim 3, wherein at least one of the graphene nanosheets and the rGO nanosheets is partially repelled by the continuous metal phase.

5. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the sacrificial polymer is polar.

6. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the sacrificial polymer is selected from the group consisting of polypropylene carbonate (PPC), polymethyl methacrylate (PMMA), poly(phthalaldehyde), including cyclic poly(phthalaldehyde), polylactide, polyhydroxyalkanoate, and combinations thereof.

7. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the solvent comprises one or more of cyrene, triacetin, butyl lactate, cyclic aliphatic ketones, benzonitrile, N,N-dimethylacetamide, morpholine, N-methyl-2-pyrrolidone (NMP), and dimethylformamide (DMF).

8. The method of forming the interconnect structure according to any one of the preceding claims, wherein at least one of the graphene nanosheets and the rGO nanosheets is prepared from an expanded graphite material dispersed and exfoliated in a polar solvent.

9. The method of forming the interconnect structure of any one of the preceding claims, wherein at least one of the graphene nanosheets and the rGO nanosheets has an average lateral dimension less than or equal to 1000 nanometers and an average thickness less than or equal to 10 nm.

10. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the metal nanoparticles are selected from the group consisting of copper, cobalt, ruthenium, nickel, titanium, aluminum, silver, gold, tungsten, platinum, palladium, and combinations thereof.

11. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the conductive composition is free of metal nanoparticles.

12. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the average diameter of the metal nanoparticles is less than 10 nm.

13. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the metal seed layer is selected from the group consisting of copper, copper alloys, and both.

14. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the copper composition is selected from the group consisting of copper, a copper-dominant alloy, and both.

15. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the step of chemically mechanically polishing the layer of copper composition oxidizes a portion of the copper in the layer of copper composition; and the method further comprises the step of reducing the oxidized copper.

16. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein at least one of the graphene nanosheets and the rGO nanosheets is a filler at least partially embedded in a copper matrix.

17. The method of forming the interconnect structure as claimed in any one of the preceding claims, wherein the polymer solution further comprises a photoinitiator and a cross-linking agent.

18. The method of forming the interconnect structure according to claim 17, further comprising: exposing the spin-coated polymer solution to a radiation source through a photomask; and The irradiated spin-coated polymer solution is developed.

19. An interconnect structure produced by the method of any preceding claim.

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