Wet etch process and method for forming air gap between metal interconnects

Abstract

Embodiments of improved process flows and methods for forming air gaps between metal interconnects are provided in the present disclosure. More specifically, the present disclosure provides improved process flows and methods that utilize a wet etch process to form recesses between metal interconnects formed on a patterned substrate. The method is different from a conventional air gap integration method. The improved process flows and methods described herein utilize a critical dimension (CD) dependent etch provided by a wet etch process to etch the intermetallic dielectric material formed between the metal interconnects at a faster rate than etching the intermetallic dielectric material in a surrounding region of the patterned substrate. This enables the improved process flows and methods described herein to form recesses (and subsequently air gaps) between metal interconnects without the use of a dry etch process.

Description

[0001] Cross-references to related patents and applications

[0002] This application claims priority to and the benefit of the filing date of U.S. non-provisional patent application No. 17 / 942,378, filed on September 12, 2022, which is incorporated herein by reference in its entirety. Background Art

[0003] The present disclosure relates to integrated circuit (IC) processing. In particular, the present disclosure provides improved processes and methods for forming air gaps between interconnects of IC chips.

[0004] The continued shrinking of integrated circuit (IC) chips has significantly increased parasitic resistance and capacitance in multi-layer interconnects. In order to reduce capacitance, enhance circuit performance and reduce power consumption, low-k dielectric materials are often used as intermetallic dielectrics (IMDs) and interlayer dielectrics (ILDs) between metal (e.g., copper or aluminum) interconnects. However, the use of low-k dielectric materials is challenging due to their mechanical strength and process immunity characteristics that typically deteriorate with decreasing k values.

[0005] As an alternative to low-k dielectrics, low-k values ​​can also be achieved by removing all material from the IMD to provide air gaps between metal interconnects. Different air gap integration techniques have been used to fabricate multi-layer metal interconnects. All air gap integration processes can be divided into the following categories: 1) partial or complete removal of IMD material between metal lines, followed by non-conformal CVD deposition and chemical mechanical polishing (CMP) planarization, and 2) inlaying integrated metal lines in sacrificial IMD layers that are selectively removed by permeable dielectric caps.

[0006] In a non-conformal CVD process, air gaps can be selectively formed between metal interconnects, leaving dielectric material elsewhere, which helps maintain the mechanical strength of the air gap interconnects. When using a sacrificial IMD approach to form air gaps in a multi-layer interconnect structure, a permeable dielectric cap enables the removal of all sacrificial IMD layers below the multiple metal layers after the stack is fully completed. However, the sacrificial IMD layers can also be removed after each metal layer is completed. In a sacrificial IMD process, a protective cap is typically placed on the metal lines to protect the metal lines when the sacrificial IMD layers are removed.

[0007] One of the biggest problems of air gap integration in multi-layer interconnects is the mechanical integrity of the entire IC stack. Due to the weaker mechanical properties of dielectric materials, subsequent packaging process steps (such as wire bonding and molding) may cause cracks inside the IC stack, which may cause electrical failures in the short or long term. Therefore, an IC stack with good mechanical properties is crucial for chip survival during packaging. When using a sacrificial IMD method to form air gaps, the mechanical strength of the stack is based only on metal lines and other cap / barrier dielectrics. It is very important to accurately place the air gap in a specific position at each metal level and will determine the mechanical integrity of the air gap interconnect. However, compared with the sacrificial IMD process, mechanical integrity is less problematic in the non-conformal CVD process because the CVD dielectric contributes to the mechanical strength of the stack in a wider space.

[0008] FIG9 (Prior Art) illustrates a conventional air gap integration process 10 that is typically used to form air gaps in multi-layer interconnects. As shown in FIG9(a), the conventional gap integration process 10 may typically begin after a plurality of copper interconnects 15 have been formed in a first intermetallic dielectric (IMD) layer 20 formed on one or more underlying layers 25 using a dual damascene (DD) process and a chemical mechanical polishing (CMP) process has been performed to planarize the first IMD layer 20 and form a planarized surface 30.

[0009] In the conventional air gap integration process 10 shown in FIG9 , a portion of the first IMD layer 20 sandwiched between two or more copper interconnects 15 is recessed using a combination of patterning, dry etching processes, and wet etching processes. As shown in FIG9( b), for example, the first IMD layer 20 is recessed using a hard mask (HM) 40 that is patterned by an additional photomask (not shown) for the subsequently formed air gap. The edge of the hard mask 40 is located on the two copper interconnects 15, forming an HM opening region covering one or more spaces between the two or more copper interconnects 15. In the recessing step shown in FIG9( b), the portion of the first IMD layer 20 within the HM opening region is etched away in a self-aligned manner to form a recessed portion 35 between the interconnects.

[0010] The portion of the first IMD layer 20 in the HM opening region is typically etched by exposing the substrate to a dry etching process, or a combination of a dry etching process and a wet etching process. In an exemplary process flow, a highly selective dry etching process may be initially used to minimize damage to the copper interconnect 15. However, because the dry etching process has an etch stop, it is difficult to recess deeply enough to achieve the target recess depth. Therefore, in some process flows, a variety of wet etching processes and / or thermal treatments may be performed after the initial dry etching process to compensate for the insufficient recess depth. In an exemplary process flow, a first hydrofluoric acid (HF) stripping may be performed after the dry etching to remove the high density layer at the bottom of the dry etched recess. After the first HF stripping, a partial pressure ammonia (pNH 3 ) and a second HF peeling to reach a target recess depth and form a recess 35, as shown in FIG. 9( b ).

[0011] Once the recess 35 is formed to the target recess depth, an air gap liner 50 and a second IMD layer 55 may be deposited using non-conformal CV deposition, as shown in FIG9( c). The air gap liner 50 covers the entire first metal layer (including the recess pattern), and a subsequent IMD deposition process closes the recess 35 via pinching off at the top of the IMD recess to form an air gap 45. After the second IMD layer 55 is deposited on the first metal layer, steps 9(a)-9(c) of the conventional air gap integration process 10 may be repeated to form an air gap 45 in the next metal layer, as shown in FIG9( d).

[0012] The conventional air gap integration process 10 shown in FIG9 utilizes multiple steps after CMP - hard mask patterning, dry etching and wet etching - to form air gaps 45 between copper interconnects 15. Although a high selectivity dry etching process is used in the recess step shown in FIG9(b), the dry etching process may still cause damage to the copper interconnects 15 (which leads to resistance degradation) and damage to the first IMD layer 20 (which causes capacitance degradation and defect generation). In order to avoid such damage, there is still a need for improved processes and methods for forming air gaps between interconnect structures. Summary of the invention

[0013] The present disclosure provides different embodiments of improved process flows and methods for forming air gaps between metal interconnects. More specifically, the present disclosure provides improved process flows and methods that utilize a wet etching process to form recesses between metal interconnects formed on a patterned substrate. Unlike conventional air gap integration methods, the improved process flows and methods described herein utilize critical dimension (CD)-dependent etching provided by a wet etching process to etch the intermetallic dielectric material formed between the metal interconnects at a faster rate than etching the intermetallic dielectric material in the surrounding area of ​​the patterned substrate. This enables the improved process flows and methods described herein to form recesses (and subsequently form air gaps) between metal interconnects without using a dry etching process.

[0014] According to one embodiment, a method for forming air gaps between metal interconnects is provided. Generally speaking, the method may include: providing a patterned substrate having a plurality of metal interconnects formed within a first dielectric material layer, wherein a critical dimension (CD) between the metal interconnects is small compared to a surrounding area of ​​the patterned substrate; and exposing the patterned substrate to an etching solution to etch the first dielectric material layer and form recesses between the plurality of metal interconnects, wherein the etching removes portions of the first dielectric material layer disposed between the plurality of metal interconnects at a faster etching rate than removing the first dielectric material layer in the surrounding area of ​​the patterned substrate. The method may continue to etch the first dielectric material layer with the etching solution until the recesses formed between the plurality of metal interconnects reach a target recess depth. After the recesses are formed to the target recess depth, the method may include depositing a second dielectric material layer on the patterned substrate, wherein the deposition closes the recesses formed between the plurality of metal interconnects to form air gaps between the plurality of metal interconnects.

[0015] In some embodiments, the method described above may include one or more planarization steps. For example, before exposing the patterned substrate to the etching solution, the method may further include planarizing the patterned substrate to expose the plurality of metal interconnects and provide the first dielectric material layer having a first planarized surface. After depositing the second dielectric material layer on the patterned substrate, the method may further include planarizing the second dielectric material layer to provide a second planarized surface and depositing an air gap liner on the second planarized surface.

[0016] In the methods described herein, a wide variety of etching solutions may be used to etch the first dielectric layer. However, the specific etching solution used to etch the first dielectric layer may generally depend on a variety of factors, including but not limited to the primary reactive species used within the etching solution, the surface potential of the wall material adjacent to the first dielectric material layer being etched when exposed to an aqueous solution of a certain pH, and the effectiveness of changing the surface potential of the wall material by adjusting the pH of the etching solution and / or by adding a surfactant.

[0017] In some embodiments, the wall material of the plurality of metal interconnects may exhibit a negative surface potential when exposed to an aqueous solution of a certain pH. In such embodiments, exposing the patterned substrate to the etching solution may sometimes include exposing the patterned substrate to a non-aqueous organic-based etching solution comprising an organic solvent and an etchant chemistry comprising anions as the primary reactive species. When the patterned substrate is exposed to a non-aqueous organic-based etching solution containing anions as the primary reactive species, the non-aqueous organic-based etching solution may increase the etching rate of the portion of the first dielectric material layer disposed between the plurality of metal interconnects compared to the etching rate of the first dielectric material layer in the surrounding area of ​​the patterned substrate.

[0018] In other embodiments, the wall material of the plurality of metal interconnects may exhibit a positive surface potential when exposed to an aqueous solution at a certain pH. In such embodiments, exposing the patterned substrate to the etching solution may include exposing the patterned substrate to an aqueous-based etching solution comprising an etchant chemistry and an aqueous solvent, or a non-aqueous organic-based etching solution comprising an etchant chemistry and an organic solvent, depending on the primary reactive species utilized within the etchant chemistry. For example, exposing the patterned substrate to the etching solution may include: (a) exposing the patterned substrate to the aqueous-based etching solution or the non-aqueous organic-based etching solution when the etchant chemistry comprises anions as the primary reactive species; and (b) exposing the patterned substrate to the aqueous-based etching solution when the etchant chemistry comprises cations as the primary reactive species. When the patterned substrate is exposed to the water-based etching solution or the non-aqueous organic-based etching solution, the water-based etching solution or the non-aqueous organic-based etching solution can increase the etching rate of the portion of the first dielectric material layer arranged between the plurality of metal interconnections compared to the etching rate of the first dielectric material layer in the surrounding area of ​​the patterned substrate.

[0019] In one embodiment, the etchant chemistry used in the non-aqueous organic-based etching solution may include one or more of the following: hydrofluoric acid (HF), ammonium hydroxide (NH 4 OH), hydrochloric acid (HCl), hydrogen peroxide (H 2O 2 ), nitric acid (HNO 3 ), phosphoric acid (H 3 PO 4 ), potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). The organic solvent used in the non-aqueous organic-based etching solution may include one or more of the following: methanol (CH 4 O), ethanol (C 2 H 6 O), isopropyl alcohol (C 3 H 8 O), benzyl alcohol (C 7 H 8 O), ethylene glycol (C 2 H 6 O 2 ), acetic acid (CH 3 COOH), acetone (C 3 H 6 O), propylene carbonate (C 4 H 6 O 3 ), n-hexane (C 6 H 14 ), cyclohexane (C 6 H 12 ), diethyl ether (C 4 H 10 O), tetrahydrofuran (C 4 H 8 O), benzene (C 6 H 6 ), toluene (C 7 H 8 ), dichloromethane (CH 2 Cl 2 ), trichloroethylene (C 2 HCl 3 )、1,1,1-trichloroethane (C 2 H 3 Cl 3 ), 1,2-dichloroethane (C 2 H 4 Cl 2 ), N-methyl-2-pyrrolidone (C 5 H 9 NO), dimethyl sulfoxide (C 2 H 6 OS), ethyl lactate (C 5 H 10 O 3 ), ethanolamine (C 2 H 7 NO) and propylene glycol methyl ether acetate (C 6 H12 O 3 ).

[0020] In other embodiments, exposing the patterned substrate to the etching solution may include exposing the patterned substrate to a water-based etching solution comprising an aqueous solvent and an etchant chemistry comprising cations as a primary reactive species. When the patterned substrate is exposed to the water-based etching solution containing cations as a primary reactive species, the water-based etching solution may increase an etching rate of a portion of the first dielectric material layer disposed between the plurality of metal interconnects compared to an etching rate of the first dielectric material layer in a surrounding area of ​​the patterned substrate.

[0021] According to another embodiment, another method for forming air gaps between metal interconnects is provided herein. Generally speaking, the method may include providing a patterned substrate having a plurality of metal interconnects formed within a first dielectric material layer, wherein the critical dimension (CD) between the metal interconnects is small compared to the surrounding area of ​​the patterned substrate, and exposing the patterned substrate to a non-aqueous organic-based etching solution to etch the first dielectric material layer and form recesses between the plurality of metal interconnects, wherein the non-aqueous organic-based etching solution etches the first dielectric material layer disposed between the plurality of metal interconnects faster than etching the first dielectric material layer in the surrounding area of ​​the patterned substrate. The method may continue to etch the first dielectric material layer with the non-aqueous organic-based etching solution until the recesses formed between the plurality of metal interconnects reach a target recess depth. After the recesses are formed to the target recess depth, the method may include depositing a second dielectric material layer on the patterned substrate, wherein the deposition seals the recesses formed between the plurality of metal interconnects to form air gaps between the plurality of metal interconnects.

[0022] In some embodiments, the non-aqueous organic-based etching solution for etching the first dielectric material layer may include an etchant chemical and an organic solvent. The etchant chemical may include one or more of the following: hydrofluoric acid (HF), ammonium hydroxide (NH 4 OH), hydrochloric acid (HCl), hydrogen peroxide (H 2 O 2 ), nitric acid (HNO 3 ), phosphoric acid (H 3 PO 4 ), potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). The organic solvent may include one or more of the following: methanol (CH 4 O), ethanol (C 2 H 6 O), isopropyl alcohol (C 3 H8 O), benzyl alcohol (C 7 H 8 O), ethylene glycol (C 2 H 6 O 2 ), acetic acid (CH 3 COOH), acetone (C 3 H 6 O), propylene carbonate (C 4 H 6 O 3 ), n-hexane (C 6 H 14 ), cyclohexane (C 6 H 12 ), diethyl ether (C 4 H 10 O), tetrahydrofuran (C 4 H 8 O), benzene (C 6 H 6 ), toluene (C 7 H 8 ), dichloromethane (CH 2 Cl 2 ), trichloroethylene (C 2 HCl 3 )、1,1,1-trichloroethane (C 2 H 3 Cl 3 ), 1,2-dichloroethane (C 2 H 4 Cl 2 ), N-methyl-2-pyrrolidone (C 5 H 9 NO), dimethyl sulfoxide (C 2 H 6 OS), ethyl lactate (C 5 H 10 O 3 ), ethanolamine (C 2 H 7 NO) and propylene glycol methyl ether acetate (C 6 H 12 O 3 ).

[0023] As noted above, the etching solution used to etch the first dielectric layer may depend at least in part on the primary reactive species used within the etching solution and the surface potential of the wall material adjacent to the first dielectric material layer being etched. In some embodiments, the wall material of the plurality of metal interconnects may exhibit a negative surface potential when exposed to an aqueous solution of a certain pH. When the wall material exhibits a negative surface potential and the etchant chemistry utilized within the non-aqueous organic-based etching solution contains anions as the primary reactive species, exposing the patterned substrate to the non-aqueous organic-based etching solution may increase the etching rate of portions of the first dielectric material layer disposed between the plurality of metal interconnects as compared to the etching rate of the first dielectric material layer in the surrounding areas of the patterned substrate.

[0024] The method described herein can provide multiple advantages over conventional methods for forming air gaps between metal interconnects. Unlike conventional methods, the method described herein uses a wet etching process to form these recesses between these metal interconnects. In the method described herein, the recesses formed between the multiple metal interconnects reach the target recess depth without using a dry etching process. This reduces the number of process steps required to form the recesses to the target recess depth, and avoids damaging the metal interconnects and the dielectric materials surrounding the recesses. In addition, the method described continues to etch the first dielectric material layer with the etching solution to completely remove the portion of the first dielectric material layer arranged between the multiple metal interconnects, while retaining a certain thickness of the first dielectric material layer in the surrounding area of ​​the patterned substrate. This enables the method described herein to maintain the mechanical integrity of the subsequently formed air gap interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A more complete understanding of the present invention and its advantages may be obtained by referring to the following description in conjunction with the accompanying drawings, in which like reference numerals indicate like features. It should be noted, however, that the drawings illustrate only exemplary embodiments of the disclosed concepts and are therefore not to be considered limiting of the scope, as the disclosed concepts may admit to other equally effective embodiments.

[0026] Figure 1A is a cross-sectional view through a substrate having features of different critical dimensions (CDs) illustrating CD-dependent etching of material within the features when the substrate is exposed to a non-aqueous organic-based etching solution;

[0027] Figure 1B is a cross-sectional view through a substrate having features with different critical dimensions (CDs) illustrating CD-dependent etching of material within the features when the substrate is exposed to a water-based etching solution;

[0028] Figure 2 is a graph showing normalized etch rate versus characteristic CD when a substrate is exposed to a non-aqueous organic-based etching solution and a water-based etching solution;

[0029] Figure 3 is a schematic diagram showing the zeta potential and the electrical double layer (EDL) existing between the charged wall surface and the etching solution;

[0030] Figure 4 is a graph showing the relationship between the zeta potential and pH for various wall materials;

[0031] Figure 5 is a graph showing the relationship between zeta potential and pH for various etching solutions and wall materials;

[0032] Figure 6 is a cross-sectional view through a patterned substrate having a plurality of metal interconnects formed within a dielectric material layer, illustrating one embodiment of an improved process for forming air gaps between the metal interconnects using the techniques described herein;

[0033] Figure 7 is a flow chart illustrating one embodiment of a method for forming air gaps between metal interconnects using the techniques described herein;

[0034] Figure 8 is a flow chart illustrating another embodiment of a method of forming air gaps between metal interconnects using the techniques described herein; and

[0035] FIG. 9 (Prior Art) illustrates a conventional non-conformal CVD process commonly used to form air gaps in multi-layer interconnects. DETAILED DESCRIPTION

[0036] The present disclosure provides different embodiments of improved process flows and methods for forming air gaps between metal interconnects. More specifically, the present disclosure provides improved process flows and methods that utilize a wet etching process to form recesses between metal interconnects formed on a patterned substrate. Unlike conventional air gap integration methods, the improved process flows and methods described herein utilize critical dimension (CD)-dependent etching provided by a wet etching process to etch the intermetallic dielectric material formed between the metal interconnects at a faster rate than etching the intermetallic dielectric material in the surrounding area of ​​the patterned substrate. This enables the improved process flows and methods described herein to form recesses (and subsequently form air gaps) between metal interconnects without using a dry etching process.

[0037] In an embodiment disclosed herein, a patterned substrate is provided, the patterned substrate having a plurality of metal interconnects formed within a first dielectric material layer, wherein the critical dimension (CD) between the metal interconnects is small compared to other areas of the patterned substrate surrounding the metal interconnects. A wet etching process is then used to form recesses within the first dielectric material layer between the plurality of metal interconnects. During the wet etching process, the patterned substrate is exposed to an etching solution that reacts with the first dielectric material layer and promotes dissolution of the reaction product to etch the first dielectric material layer and form recesses between the metal interconnects.

[0038] When etching the first dielectric material layer, the rate at which material is removed from the patterned substrate (i.e., the etch rate) may vary depending on a variety of factors, such as the CD of the recesses formed between the metal interconnects compared to the surrounding areas of the patterned substrate, the one or more etchant chemicals used in the etching solution, the solvent used in the etching solution, the ratio of the one or more etchant chemicals used in the etching solution to the solvent, the pH of the etching solution, and the wall material adjacent to the material being etched. The difference in etching rate is referred to in the art as CD-dependent etching.

[0039] Because the CD between the metal interconnects is small compared to the surrounding area of ​​the patterned substrate, the wet etching process described herein removes the portion of the first dielectric material layer arranged between the metal interconnects at a faster etching rate than removing the first dielectric material layer in the surrounding area of ​​the patterned substrate. The difference in etching rate enables the wet etching process described herein to completely remove the portion of the first dielectric material layer arranged between the metal interconnects, and thus form a recessed portion reaching a target recessed portion depth, while retaining at least a portion of the first dielectric material layer in the surrounding area of ​​the patterned substrate. After the recessed portion formed between the metal interconnects reaches the target recessed portion depth, a second dielectric material layer can be deposited on the patterned substrate to close (or pinch off) the recessed portion and form an air gap between the metal interconnects.

[0040] The improved process flows and methods described herein form recesses between metal interconnects (and subsequently form air gaps) without using a dry etching process by utilizing a CD-dependent wet etch, and continuing the wet etching process until the recesses formed between metal interconnects reach a target recess depth. In this way, the improved process flows and methods described herein reduce the number of process steps required to form recesses between metal interconnects (by eliminating the hard mask patterning and dry etching process steps used in conventional air gap integration methods) and avoid damage to metal interconnects and dielectric materials while maintaining the mechanical integrity of the air gap interconnects.

[0041] The wet etching process described herein can utilize a variety of etching solutions. For example, a non-aqueous organic-based etching solution or an aqueous-based etching solution can be used to etch the first dielectric material layer and form a recessed portion between the metal interconnects. The etching solution used to etch the first dielectric layer can depend on a variety of factors, including but not limited to the main reactive species used in the etching solution, the surface potential of the wall material when the wall material adjacent to the etched first dielectric material layer is exposed to an aqueous solution, and the effectiveness of changing the surface potential of the wall material by adjusting the pH of the etching solution or adding a surfactant. In some embodiments, the wall material adjacent to the etched first dielectric material layer can exhibit a negative surface potential when exposed to an aqueous solution. In such embodiments, the wet etching process disclosed herein can be used to etch the first dielectric material layer faster in the recessed portion and etch the first dielectric material layer more slowly in the surrounding area of ​​the substrate by using: (a) a non-aqueous organic-based etching solution containing an organic solvent and an etchant chemical containing anions as the main active species, or (b) a water-based etching solution containing an aqueous solvent and an etchant chemical containing cations as the main active species.

[0042] Figure 1A to Figure 1B and Figure 2 It is shown that when the substrate is exposed to a non-aqueous organic-based etching solution 130 ( Figure 1A and Figure 2 ) and water-based solution 140 ( Figure 1B and Figure 2 ), CD-dependent etching of materials deposited within features with different CDs and on flatter areas of the substrate. As used herein, water-based etching solution 140 is a solution comprising an aqueous solvent (e.g., water (H 2 On the other hand, the non-aqueous organic-based etching solution 130 is a solution containing one or more etchant chemicals mixed with an organic solvent. In some embodiments, the non-aqueous organic-based etching solution 130 may include an etchant chemical containing water (e.g., hydrofluoric acid (HF) containing, for example, 49% HF and 51% water, or containing, for example, 29% NH 4 OH and 71% aqueous ammonium hydroxide (NH 4 OH), in wt %), and can therefore contain a minimum amount of water.

[0043] Figure 1A to Figure 1B The substrate 100 shown in FIG. 1 is provided with a plurality of structures 105 (e.g., metal lines, fins, etc.) extending on the surface of the substrate. Each of the plurality of structures 105 is separated by features 115 (e.g., such as gaps, trenches, holes, etc.). The critical dimensions (CD) of the features 115 may be the same or may be different, such as Figure 1A to Figure 1B As shown in Figure 1A to Figure 1B In the example embodiment shown in FIG. 1 , substrate 100 is depicted as having a smaller CD (CD 1 ) and the first feature 115a having a larger CD (CD 2 ). Compared to the flatter region 120 of the substrate 100 surrounding the plurality of structures 105, the CD of the plurality of features 115 is relatively small (eg, less than 100 nm).

[0044] The material 125 to be etched is deposited on the surface of the substrate 100, on the plurality of structures 105, and in the features 115 formed between the plurality of structures 105. The material 125 may include a variety of semiconductor materials. For example, the material 125 may be an oxide, a dielectric material, silicon, or a metal. In one example, the material 125 may be silicon oxide (e.g., silicon dioxide SiO 2 Other oxides and dielectric materials (including low-k dielectric materials) may also be formed within the plurality of features 105 and etched.

[0045] exist Figure 1A In the embodiment shown in FIG. 1 , the substrate 100 is exposed to a non-aqueous organic-based etching solution 130 comprising one or more etchant chemicals and an organic solvent. Examples of etchant chemicals that may be included in the non-aqueous organic-based etching solution 130 include, but are not limited to, hydrofluoric acid (HF), ammonium hydroxide (NH 4 OH), hydrochloric acid (HCl), hydrogen peroxide (H 2 O 2 ), nitric acid (HNO 3 ), phosphoric acid (H 3 PO 4 ), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), and other etchant chemicals containing anions (negatively charged ions) as the primary reactive species.

[0046] A variety of organic solvents may be used in the non-aqueous organic-based etching solution 130 described herein. Examples of organic solvents that may be included in the non-aqueous organic-based etching solution 130 include, but are not limited to, various alcohols (e.g., methanol (CH 4 O), ethanol (C 2 H 6 O), isopropyl alcohol (C 3 H 8 O), benzyl alcohol (C 7 H 8 O) etc.), polyols (e.g., ethylene glycol (C 2 H 6 O 2 ) etc.), acetic acid (CH 3 COOH), ketones (e.g., acetone (C3 H 6 O), propylene carbonate (C 4 H 6 O 3 ) etc.), alkanes (e.g., n-hexane (C 6 H 14 ), cyclohexane (C 6 H 12 ) etc.), ethers (e.g., diethyl ether (C 4 H 10 O), tetrahydrofuran (C 4 H 8 O) etc.), aromatic hydrocarbons (e.g., benzene (C 6 H 6 ), toluene (C 7 H 8 ) etc.), halogen compounds (e.g., dichloromethane (CH 2 Cl 2 ), trichloroethylene (C 2 HCl 3 )、1,1,1-trichloroethane (C 2 H 3 Cl 3 ), 1,2-dichloroethane (C 2 H 4 Cl 2 ) etc.), nitrogen compounds (e.g., N-methyl-2-pyrrolidone (C 5 H 9 NO), sulfur-containing compounds (e.g., dimethyl sulfoxide (C 2 H 6 OS) and other volatile carbon-based solvents such as ethyl lactate (C 5 H 10 O 3 ), ethanolamine (C 2 H 7 NO) and propylene glycol methyl ether acetate (C 6 H 12 O 3 ).

[0047] In some embodiments, the non-aqueous organic-based etching solution 130 may include an etchant chemical (e.g., hydrofluoric acid, ammonium hydroxide, or hydrochloric acid) containing anions as the main reactive species mixed with an alcohol (e.g., isopropyl alcohol, IPA), a polyol (e.g., ethylene glycol, EG), acetic acid AA, or a ketone (e.g., propylene carbonate, PC). In at least one preferred embodiment, the non-aqueous organic-based etching solution 130 may include hydrofluoric acid mixed with IPA, AA, EG, or PC. Other organic solvents described herein may also be mixed with hydrofluoric acid or other etchant chemicals containing anions as the main reactive species (e.g., NH4 Although the etchant chemistries described herein can be mixed with many different organic solvents, the compatibility and solubility of the etchant chemistry and the organic solvent must be carefully considered.

[0048] When the substrate 100 is exposed to the non-aqueous organic-based etching solution 130 containing anions as the main reactive species, the portion of the feature 115 exposed to the non-aqueous organic-based etching solution 130 may exhibit a positive surface potential (e.g., Figure 1A ), which depends on the pH of the etching solution and the wall material 110 used to form the feature 115. For example, when the substrate 100 is exposed to a non-aqueous organic-based etching solution 130 containing hydrofluoric acid mixed with an organic solvent (e.g., IPA, AA, EG, or PC) and the wall material 110 includes a silicon-containing material (e.g., amorphous silicon (a-Si), polycrystalline silicon (poly-Si), silicon nitride (SiN), silicon carbonitride (SiCN), or silicon oxynitride (SiON)), the exposed portion of the feature 115 can exhibit a positive surface potential (e.g., Figure 1A In some cases, when the conductive wall material 110 (such as copper (Cu), aluminum (Al), etc.) is exposed to the non-aqueous organic-based etching solution 130, the exposed portion of the feature 115 can also exhibit a positive surface potential.

[0049] like Figure 1A As shown in and described above, when the substrate 100 is exposed to the non-aqueous organic-based etching solution 130, the anions within the etchant chemistry are attracted to the positively charged surface. This increases the local concentration of anions within the features 115, thereby increasing the etch rate of the material 125 deposited within the features 115 as compared to the flatter regions 120 of the substrate 100. As a result, the material 125 is etched faster within the plurality of features 115 and slower within the flatter regions 120 of the substrate 100 surrounding the plurality of structures 105. This Figure 1A is schematically shown in Figure 2 The curve diagram 200 shown in FIG. Figure 1A As shown in FIG. 1 , when features 115 of different CDs are formed within the plurality of structures 105, the increase in etch rate is more pronounced within features with smaller CDs (e.g., feature 115a) and less pronounced within features with larger CDs (e.g., feature 115b). However, the etch rate within feature 115 is significantly faster than the etch rate achieved on the flatter region 120 of the substrate 100.

[0050] exist Figure 1B In the embodiment shown in FIG. 1 , the substrate 100 is exposed to a water-based etching solution 140 comprising one or more etchant chemicals and an aqueous solvent. As noted above, the water-based etching solution 140 is a solution comprising an aqueous solvent (e.g., water (H2 Examples of etchant chemicals that may be included in the water-based etching solution 140 include, but are not limited to, hydrofluoric acid (HF), ammonium hydroxide (NH 4 OH), hydrochloric acid (HCl), hydrogen peroxide (H 2 O 2 ), nitric acid (HNO 3 ), phosphoric acid (H 3 PO 4 ), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), and other etchant chemicals containing anions (negatively charged ions) as the primary reactive species.

[0051] When the substrate 100 is exposed to the water-based etching solution 140 containing anions as the main reactive species, the portion of the feature 115 exposed to the water-based etching solution 140 may exhibit a negative surface potential (eg, Figure 1B ), which depends on the pH of the etching solution and the wall material 110 used to form the feature 115. For example, when the substrate 100 is exposed to an aqueous-based etching solution 140 containing hydrofluoric acid mixed with water and the wall material 110 includes a silicon-containing material (such as a-Si, poly-Si, SiCN, or SiON) or a conductive material (such as Cu or Al), the exposed portion of the feature 115 can exhibit a negative surface potential (such as Figure 1B However, other silicon-containing materials such as silicon nitride (SiN) may exhibit a positive surface potential (at Figure 1B This is not shown in Figure 5 and described in more detail below.

[0052] like Figure 1B As shown in and described above, when the substrate 100 is exposed to the water-based etching solution 140, the negative surface potential of the wall material 110 repels the anions within the etchant chemistry, thereby reducing their local concentration in the feature 115 and thus reducing the etch rate of the material 125 deposited in the feature 115. Figure 1B As shown in FIG. 1 , when features 115 of different CDs are formed within multiple structures 105, the reduction in etching rate is more pronounced in features with smaller CDs (such as feature 115a) and less pronounced in features with larger CDs (such as feature 115b). Therefore, material 125 is etched more slowly in features with smaller CDs (such as feature 105a) and more quickly in features with larger CDs (such as feature 105b). Figure 1B As shown in , the etch rate on the flatter regions 120 of the substrate is significantly faster than the etch rate within the features 115 .

[0053] When etching material 125 formed within plurality of features 115, the etch rate of material 125 may depend on a variety of factors, including the critical dimension (CD) of features 115, one or more specific etchant chemicals and / or reactive species used in the etching solution, a specific solvent used in the etching solution, a ratio of one or more etchant chemicals to solvent used in the etching solution, and / or the pH of the etching solution. In addition to these factors, the potential of wall material 110 adjacent to material 125 being etched may also affect the etch rate of material 125, depending on the etching solution used.

[0054] like Figure 1A to Figure 1B and Figure 2 As shown in , the non-aqueous organic-based etching solution 130 and the water-based etching solution 140 may sometimes have opposite effects on the etching rate. When the non-aqueous organic-based etching solution 130 is used to etch the material 125, the etching rate increases in the features of smaller CD (such as feature 115a) and decreases in the features of larger CD (such as feature 115b). However, when the water-based etching solution 140 is used to etch the material 125, the opposite is true. This may be due, at least in part, to the zeta potential and the electrical double layer (EDL) that exists between the wall material 110 and the etching solution.

[0055] Figure 3 is a schematic diagram showing the zeta potential and the double electrical layer that exists between the wall material and the etching solution. The etching solution contains cations (positively charged ions) and anions (negatively charged ions). Figure 3 As shown in , when the etching solution contacts the wall material with a negative surface potential, the cations in the etching solution are attracted and adsorbed to the wall material by electrostatic and / or van der Waals forces. When the etching solution contacts the wall material with a positive surface potential (i.e., the anions in the etching solution are attracted and adsorbed to the wall material), the situation is reversed. This attraction generates a double electrical layer (i.e., a layer that does not satisfy electrical neutrality) between the wall material and the etching solution.

[0056] According to the Stern model, the electric double layer (EDL) is divided into two parts separated by a plane called the Stern plane. The center of the adsorbed ions is located in the Stern layer between the wall surface and the Stern plane. The ions whose centers are located outside the Stern plane form the diffusion layer of the EDL. Figure 3 As shown in , the potential (Ψ) near the wall surface is 0 With δ (the potential at the Stern plane) varies linearly and varies from Ψ δThe zeta potential (ζ) is the potential at the shear interface between the charged wall surface and the etching solution. Depending on the wall material and the pH of the etching solution, the zeta potential (ζ) can be positive, zero, or negative.

[0057] Figure 4 A graph 400 showing the zeta potential (expressed in mV) of various wall materials versus pH is depicted. Figure 4 As shown in , the zeta potential generally increases with decreasing pH and decreases with increasing pH. In some embodiments, the zeta potential between the charged wall surface and the etching solution can be changed by changing the pH of the etching solution (e.g., by changing one or more etchant chemicals used in the etching solution, or by adding an acid or base to the etching solution), such as Figure 4 In other embodiments, the zeta potential between the charged wall surface and the etching solution can be changed by adding a surfactant to the etching solution. In still other embodiments, the zeta potential between the charged wall surface and the etching solution can be changed by utilizing an organic solvent rather than an aqueous solvent in the etching solution (which depends on the pH of the etching solution). Figure 5 This is shown in the graph 500 shown in FIG.

[0058] Figure 5 The graph 500 shown in shows the relationship between the zeta potential and pH of various etching solutions and wall materials (e.g., SiN, a-Si, and SiCN). When hydrofluoric acid (HF) is mixed with an aqueous solvent and used as an etching solution, the zeta potential (denoted by Δ) between the etching solution and the wall material is: (a) negative for a-Si and SiCN (resulting in negatively charged wall surfaces), and (b) positive for SiN (resulting in positively charged wall surfaces). When hydrofluoric acid is mixed with an organic solvent instead of an aqueous solvent, the zeta potential (denoted by ●) is positive for a-Si, SiCN, and SiN (resulting in positively charged wall surfaces). Figure 5 The graph 500 shown in shows that, although the organic solvent has little effect on the zeta potential between the etching solution and the already positively charged wall surface, by using an organic solvent instead of an aqueous solvent in the etching solution, the zeta potential between the etching solution and the negatively charged wall surface can (sometimes) be changed to a positive surface potential. This difference in zeta potential can at least partially explain the opposite effects that aqueous-based etching solutions and non-aqueous organic-based solutions have on etching rates when etching features with different CDs.

[0059] exist Figure 5In the curve graph 500 shown in, an organic solvent is used in the HF etching solution to change the zeta potential of the negatively charged a-Si or SiCN wall surface to a positive surface potential. However, the use of an organic solvent may not be enough to transfer the zeta potential of all wall surfaces from a negative surface potential to a positive surface potential. In some cases, the pH of the organic-based etching solution can be adjusted (for example, by changing one or more etchant chemicals used in the etching solution, or by adding acid or alkali to the etching solution) to further adjust the zeta potential, so as to achieve a positive surface potential and a desired CD-dependent etching result. If the pH cannot be changed (for example, due to compatibility considerations), a surfactant can be added to the organic-based etching solution to adjust the zeta potential and achieve the desired CD-dependent etching result. In some cases, all three methods (organic solvent, pH adjustment and surfactant addition) can be used to provide or enhance the CD-dependent trend.

[0060] In the description provided above, an organic-based etching solution (with or without pH adjustment and surfactant addition) is used to increase the etching rate of materials formed within features with smaller CDs when: (a) the organic-based etching solution contains anions as the main reactive species, and (b) the etched material is adjacent to a wall material that exhibits a negative surface potential in an aqueous solution. However, in all embodiments, the organic-based etching solution may not provide the desired CD-dependent etching results. In some embodiments, when cations are used as the main reactive species, a water-based etching solution may be used to increase the etching rate of materials formed within features with smaller CDs. In some embodiments, the pH may be adjusted and / or a surfactant may be added to the water-based etching solution containing cations as the main reactive species to provide the desired CD-dependent etching results.

[0061] As described herein, one mechanism that may cause the etch rate variation when using various etching solutions, various wall materials, and various CDs is a mechanism related to surface potential. However, the technology described herein is not strictly limited to such technology. Therefore, the CD-dependent etch rate described herein can be achieved by other mechanisms, and the etch rate advantages described and obtained with the technology provided herein are not limited to a specific surface potential mechanism. Instead, other mechanisms can also be used to obtain these advantages.

[0062] The present disclosure utilizes the difference in etching rate that occurs when a wet etching process is used to etch a material formed in a feature (e.g., a recess, a groove, a hole, a slit, etc.) with a relatively small CD compared to the surrounding area of ​​the substrate. In the present disclosure, a wet etching process is used to form a recess between a plurality of metal interconnects formed in a first dielectric material layer (e.g., a first IMD layer) of a patterned substrate. During the wet etching process, the patterned substrate is exposed to an etching solution that removes a portion of the first dielectric material layer arranged between the plurality of metal interconnects at an etching rate faster than that of the first dielectric material layer in the surrounding area of ​​the patterned substrate. The wet etching process disclosed herein continues to etch the first dielectric material layer with the etching solution until the recess formed between the metal interconnects reaches a target recess depth. Once the recess is formed to the target recess depth, a second dielectric material layer is deposited on the patterned substrate to close (or pinch off) the recess formed between the metal interconnects, thereby forming an air gap between the metal interconnects.

[0063] Unlike conventional air gap integration methods that utilize a combination of hard mask patterning, dry etching processes, and wet etching processes to form recesses between metal interconnects, the present disclosure provides an all-in-one wet etching process that completely removes dielectric materials formed between metal interconnects while retaining at least a portion of the dielectric material in the surrounding area of ​​the patterned substrate. This reduces the number of process steps required to form these recesses to a target recess depth and avoids damage to these metal interconnects and the dielectric material surrounding these recesses while maintaining the mechanical integrity of the subsequently formed air gap interconnects.

[0064] Figures 6 to 8 Various embodiments of an improved process 600 and methods 700 and 800 for forming air gaps between metal interconnects utilizing the techniques described herein are presented. It will be appreciated that Figures 6 to 8 The embodiments described herein are exemplary only, and additional processes and methods may also utilize the techniques described herein. Further, additional processing steps may be added to Figures 6 to 8 In the embodiment shown in the figure, the steps shown are not intended to be exclusive. In addition, the order of the steps is not limited to the order shown in the figure, because different orders may occur and / or various steps can be performed in combination or simultaneously.

[0065] like Figure 6 , Figure 7 and Figure 8 As shown in FIG. 6 , the improved process 600 and methods 700 , 800 may generally be performed by providing a patterned substrate (in a substrate having a plurality of metal interconnects 610 formed in a first dielectric material layer 620 (eg, a first IMD layer) Figure 6 (a) Chinese Figure 7Step 710 and Figure 8 Step 810) starts. Figure 6 As shown in (a), the critical dimension (CD) between the metal interconnects 610 1 ) and the surrounding area 650 (CD 2 ) may be smaller than

[0066] Figure 6 The metal interconnect 610 shown in (a) can be formed of a variety of conductive materials commonly used to form metal interconnects in integrated circuits, such as aluminum (Al), copper (Cu), etc. The metal interconnect 610 can generally include a conductive metal core (e.g., a Cu core) that can be surrounded by one or more layers, such as a barrier layer (which prevents metal diffusion into the dielectric layer) and a liner layer (which improves barrier adhesion to the metal core). In one embodiment, a copper interconnect can be formed within a patterned substrate by forming a tantalum nitride barrier, a tantalum liner, a copper seed layer (which initiates metal filling / plating), and finally a bulk (core conductive) copper metal.

[0067] Figure 6 The first dielectric material layer 620 shown in (a) may also include a variety of dielectric materials. For example, the first dielectric material layer 620 may include an oxide (e.g., silicon dioxide, SiO 2 ) or a low-k dielectric material having a dielectric constant (k) less than silicon dioxide (k=3.9). The first dielectric material layer 620 may be formed on one or more underlying layers 630, as is known in the art. Figure 6 As shown in (a), the first dielectric material layer 620 may be planarized to expose the plurality of metal interconnects 610 and provide a planarized surface 640 for the first dielectric material layer 620. In some embodiments, a chemical mechanical polishing (CMP) process may be used to planarize the surface.

[0068] Once Figure 6 As shown in (a), a patterned substrate is provided, and the improved process 600 and methods 700, 800 can expose the patterned substrate to an etching solution 660 to etch the first dielectric material layer 620 and form a recess 670 between the metal interconnects 610, as shown in FIG. Figure 6 (b) Figure 7 Step 720 and Figure 8As shown in step 820 of . In some embodiments, the patterned substrate can be exposed to a non-aqueous organic-based etching solution containing an organic solvent and an etchant chemistry containing anions (negatively charged ions) as the main reactive species. In other embodiments, the patterned substrate can be exposed to a water-based etching solution containing an aqueous solvent and an etchant chemistry containing cations (positively charged ions) as the main reactive species.

[0069] like Figure 6 (b) Figure 7 Step 720 and Figure 8 As shown in step 820 of , when the patterned substrate is exposed to the etching solution 660, the portion of the first dielectric material layer 620 disposed between the metal interconnects 610 is removed at a faster rate (i.e., a faster etching rate) than the first dielectric material layer 620 is removed in the surrounding area 650 of the patterned substrate. The increase in the etching rate between the metal interconnects 610 is at least partially due to the critical dimension (CD) of the metal interconnects 610 compared to the surrounding area 650 of the patterned substrate. 1 ).

[0070] like Figure 6 As shown in (a), for example, the critical dimension (CD) between the metal interconnects 610 1 ) and the surrounding area 650 (CD 2 ) may be relatively small compared to the CD between the metal interconnects 610. 1 ) is smaller than the surrounding area 650 of the patterned substrate, so the etching solution 660 removes the first dielectric material layer 620 faster between the metal interconnects 610 than in the surrounding area 650, as shown in FIG. Figure 6 The faster etching rate between the metal interconnects 610 forms a recessed portion 670 between the metal interconnects 610, which has an etching depth (D) greater than that achieved in the surrounding area 650. 1 ) of the concave portion (D 2 ).

[0071] The wet etching process continues to etch the first dielectric material layer 620 with the etching solution 660 until the recess 670 reaches the target recess depth (D T ),like Figure 6 (d) Figure 7 Step 730 and Figure 8 As used herein, the "target recess depth" is substantially equal to the height or thickness of the metal interconnect 610, such as Figure 6As shown in (d), due to the faster etching rate between the metal interconnects 610, the recess 670 reaches the target recess depth (D T By reaching the target recess depth (D T ), the improved process 600 and methods 700, 800 described herein completely remove the portion of the first dielectric material layer 620 arranged between the metal interconnects 610, while retaining a certain thickness (T) of the first dielectric material layer 620 in the surrounding area 650 of the patterned substrate.

[0072] Figure 6 (b) to Figure 6 The wet etching process shown in (d) can utilize a variety of etching solutions. For example, a non-aqueous organic-based etching solution or a water-based etching solution can be used to etch the first dielectric material layer 620 and form a recess 670 between the metal interconnects 610. The specific etching solution 660 used in the wet etching process can be selected based on a variety of factors, including but not limited to the desired etching rate of the first dielectric material layer 620, the critical dimension (CD) between the metal interconnects 610, and the thickness of the first dielectric material layer 620. 1 ) and the surface potential of the wall material adjacent to the etched dielectric material layer when the wall material is exposed to an aqueous solution of a certain pH.

[0073] As noted above, the metal interconnect 610 may include a conductive metal core (e.g., a Cu core) that may be surrounded by one or more layers (e.g., such as a barrier layer and / or a liner layer). In some embodiments, the wall material of the conductive metal core (or the barrier layer / liner layer surrounding the conductive metal core) may exhibit a negative surface potential when exposed to an aqueous solution at a certain pH. In some embodiments, the negative surface potential of the wall material may affect the etching rate of the etched dielectric material layer, depending on the etching solution used to etch the dielectric material layer.

[0074] In some embodiments, Figure 6 (b) to Figure 6The wet etching process shown in (d) can form a recessed portion 670 between the metal interconnects 610 by using a non-aqueous organic-based etching solution containing an organic solvent and an etchant chemical containing anions (negatively charged ions) as the main reactive species. Examples of organic solvents and etchant chemicals containing anions as the main reactive species are listed above. When the patterned substrate is exposed to a non-aqueous organic-based etching solution containing anions as the main reactive species, the non-aqueous organic-based etching solution may cause the exposed portion of the wall material to exhibit a positive surface potential, which attracts the anions in the etchant chemical. This attraction can increase the local concentration of anions in the recessed portion 670, which in turn can increase the etching rate of the portion of the first dielectric material layer 620 arranged between the metal interconnects 610 compared to the etching rate of the first dielectric material layer 620 in the surrounding area 650 of the patterned substrate.

[0075] In other embodiments, Figure 6 (b) to Figure 6 The wet etching process shown in (d) can use a water-based etching solution containing an aqueous solvent (i.e., water) and an etchant chemical containing cations (positively charged ions) as the main active species to form a recess 670 between the metal interconnects 610. When the patterned substrate is exposed to the water-based etching solution containing cations as the main reactive species, the water-based etching solution may cause the exposed portion of the wall material to exhibit a negative surface potential, which attracts the cations within the etchant chemical. This attraction can increase the local concentration of cations within the recess 670, which in turn can increase the etching rate of the portion of the first dielectric material layer 610 disposed between the metal interconnects 610 compared to the etching rate of the first dielectric material layer 620 in the surrounding area 660 of the patterned substrate.

[0076] Figure 6 (b) to Figure 6 The wet etching process shown in (d) utilizes an etching solution 660 (e.g., a non-aqueous organic-based etching solution containing anions as the main reactive species or a water-based etching solution containing cations as the main reactive species) that provides a faster etching rate between the metal interconnects 610 than the surrounding areas 650 of the patterned substrate. In doing so, Figure 6 (b) to Figure 6 The wet etching process shown in (d) enables the recess 670 to be formed to a target recess depth (D T ), while retaining a certain thickness (T) of the first dielectric material layer 620 in the peripheral area 650 of the patterned substrate.

[0077] When the etched material (e.g., the first dielectric material layer 620) is adjacent to a wall material that exhibits a negative surface charge when exposed to an aqueous solution at a certain pH, the above etching solution provides a faster etching rate between the metal interconnects 610 than the surrounding area 650 of the patterned substrate. However, the etching solution 660 is not strictly limited to the example etching solution described above. When the etched material (e.g., the first dielectric material layer 620) is adjacent to a wall material that exhibits a positive surface charge in an aqueous solution at a certain pH, an alternative etching solution 660 can be used to provide a faster etching rate between the metal interconnects 610 than the surrounding area 650 of the patterned substrate. For example, when the wall surface is positively charged in an aqueous solution, the etching solution 660 may alternatively include: (a) a water-based etching solution or a non-aqueous organic-based etching solution containing anions as the main reactive species, or (b) a water-based etching solution containing cations as the main reactive species. In some embodiments, the pH of the etching solution 660 may be adjusted and / or surfactants may be added to the etching solution 660 to change the surface potential of the wall material adjacent to the material being etched and provide a desired CD-dependent etching result.

[0078] In use Figure 6 (b) to Figure 6 The wet etching process shown in (d) forms a target recessed portion depth (D T ), the improved process 600 and methods 700, 800 may deposit a second dielectric material layer 680 on the patterned substrate to close (or pinch off) the recessed portion 670 and form an air gap 690 between the metal interconnects 610, as shown in FIG. Figure 6 (e) Figure 7 Step 740 and Figure 8 As shown in step 840 of . In some embodiments, it can be as follows Figure 6 As shown in (f), the second dielectric material layer 680 is planarized to provide a second planarized surface 685, and then Figure 6 As further shown in (g), an air gap liner 695 is deposited on the second planarized surface 685. Figure 6 In (e) and 6(g), various well-known deposition techniques can be used to deposit the second dielectric material layer 680 and the air gap liner 695. For example, the second dielectric material layer 680 and the air gap liner 695 can be deposited by spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0079] Figure 6 (a) to Figure 6 The process steps shown in (g) can generally be used to form an air gap 690 between two or more metal interconnects 610 formed in the first metal layer. Figure 6The process steps shown in (a) to 6(g) are repeated one or more times to form air gaps 690 between metal interconnects 610 formed in one or more subsequently formed metal layers overlying the first metal layer. Figure 6 (h) shows the formation of air gaps 690 between metal interconnects formed in a second metal layer overlying the first metal layer. Figure 6 (a) to Figure 6 The process steps shown in (g) are repeated multiple times to form air gaps 690 within multiple metal layers that are stacked on top of each other to form a multi-layer interconnect structure.

[0080] The improved process flow 600 and methods 700, 800 disclosed herein can generally be used to form air gaps 690 between metal interconnects 610 formed in one or more metal layers of a patterned substrate. Unlike conventional air gap integration techniques that use a combination of hard mask patterning, dry etching processes, and wet etching processes to form recesses between metal interconnects, the improved process 600 and methods 700, 800 described herein use a combination of hard mask patterning, dry etching processes, and wet etching processes to form recesses between metal interconnects. Figure 6 (b) to (d) an all-in-one wet etching process is used to form a recess 670 between the metal interconnects 610. As noted above, Figure 6 (b) to Figure 6 The wet etching process shown in (d) uses an etching solution 660 to completely remove the dielectric material disposed between the metal interconnects 610 while retaining at least a portion of the dielectric material in the surrounding area 650 of the patterned substrate. Figure 6 (b) to Figure 6 (d) shows a wet etching process, the improved process 600 and methods 700, 800 described herein form a recess 670 between the metal interconnects 610 without using a dry etching process. By avoiding a dry etching process, the improved process 600 and methods 700, 800: (a) reduce the number of process steps required to form the recess 670 between the metal interconnects 610, (b) avoid damage to the metal interconnects 610 and the dielectric material layers 620, 680, and (c) maintain the mechanical integrity of the air gap interconnects formed within the multi-layer interconnect structure. Therefore, the improved process 600 and methods 700, 800 described herein provide several advantages over conventional air gap integration techniques.

[0081] As used herein, the term "substrate" means and includes the base material or structure on which a material is formed. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device), and may be, for example, a base substrate structure (such as a semiconductor substrate), or a layer (such as a thin film) on or covering a base substrate structure. Therefore, the term "substrate" is not intended to be limited to any particular base structure, underlying layer or covering layer, patterned layer or unpatterned layer. Rather, it is intended that the term "substrate" includes any such layer or base structure, as well as any combination of layers and / or base structures.

[0082] It should be understood that the substrate described herein may include a single material, multiple layers of different materials, one or more layers of regions with different materials or different structures, etc. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, the substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, features, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrates including a semiconductor material layer. As used herein, the term "bulk substrate" refers not only to and includes silicon wafers, but also to and includes silicon on insulator ("SOI") substrates (e.g., silicon on sapphire ("SOS") substrates and silicon on glass ("SOG") substrates), silicon epitaxial layers on base semiconductor bottoms, and other semiconductor or optoelectronic materials (e.g., silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide). The substrate may be doped or undoped.

[0083] It should be noted that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, material, or characteristic described in conjunction with that embodiment is included in at least one embodiment of the invention, but does not imply that they are present in every embodiment. Thus, the appearance of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same embodiment of the invention. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. In other embodiments, various additional layers and / or structures may be included, and / or described features may be omitted.

[0084] Those skilled in the relevant art will recognize that the various embodiments described herein can be practiced without one or more of the specific details or with other replacements and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the aspects of the various embodiments of the present invention. Similarly, for the purpose of explanation, specific numbers, materials and configurations are set forth to provide a thorough understanding of the present invention. Nevertheless, the present invention can be practiced without the specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0085] In view of this description, further modifications and alternative embodiments of the processes and methods described herein will be apparent to those skilled in the art. Therefore, it will be appreciated that the processes and methods described are not limited by the examples described herein. It should be understood that the forms of the processes and methods described herein will be considered as example embodiments. Various changes can be made in the embodiments. Therefore, although the present invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention. Therefore, the description and the accompanying drawings will be viewed in an illustrative rather than a restrictive sense, and such modifications are intended to be included within the scope of the present invention. Further, any benefit, advantage, or solution to the problem described herein with respect to a specific embodiment is not intended to be interpreted as a key, required, or essential feature or element of any or all claims.

Claims

1. A method for forming an air gap between metal interconnects, the method comprising: providing a patterned substrate having a plurality of metal interconnects formed within a first dielectric material layer, wherein a critical dimension (CD) between the metal interconnects is small compared to surrounding areas of the patterned substrate; exposing the patterned substrate to an etching solution to etch the first dielectric material layer and form recesses between the plurality of metal interconnects, wherein the etching removes portions of the first dielectric material layer disposed between the plurality of metal interconnects at a faster etching rate than removing the first dielectric material layer in the surrounding areas of the patterned substrate; Continue etching the first dielectric material layer with the etching solution until the recesses formed between the plurality of metal interconnections reach a target recess depth; and A second dielectric material layer is deposited on the patterned substrate, wherein the deposition closes the recesses formed between the plurality of metal interconnects to form air gaps between the plurality of metal interconnects.

2. The method of claim 1, wherein: Prior to exposing the patterned substrate, the method further includes planarizing the patterned substrate to expose the plurality of metal interconnects and provide the first dielectric material layer having a planarized surface.

3. The method of claim 1, wherein: After depositing the second dielectric material layer on the patterned substrate, the method further includes planarizing the second dielectric material layer to provide a planarized surface and depositing an air gap liner on the planarized surface.

4. The method of claim 1, wherein: The etching of the first dielectric material layer by the etching solution is continued to completely remove the portion of the first dielectric material layer disposed between the plurality of metal interconnections, while retaining a certain thickness of the first dielectric material layer in the surrounding areas of the patterned substrate.

5. The method of claim 1, wherein: The etching solution is a non-aqueous organic-based etching solution comprising an etchant chemical and an organic solvent.

6. The method of claim 5, wherein: The etchant chemistry includes one or more of the following: hydrofluoric acid (HF), ammonium hydroxide (NH4OH), hydrochloric acid (HCl), hydrogen peroxide (H2O2), nitric acid (HNO3), phosphoric acid (H3PO4), potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH).

7. The method of claim 5, wherein: The organic solvent includes one or more of the following: methanol (CH4O), ethanol (C2H6O), isopropanol (C3H8O), benzyl alcohol (C7H8O), ethylene glycol (C2H6O2), acetic acid (CH3COOH), acetone (C3H6O), propylene carbonate (C4H6O3), n-hexane (C6H 14 ), cyclohexane (C6H 12 ), diethyl ether (C4H 10 O), tetrahydrofuran (C4H8O), benzene (C6H6), toluene (C7H8), dichloromethane (CH2Cl2), trichloroethylene (C2HCl3), 1,1,1-trichloroethane (C2H3Cl3), 1,2-dichloroethane (C2H4Cl2), N-methyl-2-pyrrolidone (C5H9NO), dimethyl sulfoxide (C2H6OS), ethyl lactate (C5H 10 O3), ethanolamine (C2H7NO) and propylene glycol methyl ether acetate (C6H 12 O3).

8. The method of claim 1, wherein: The wall material of the plurality of metal interconnects exhibits a negative surface potential when exposed to an aqueous solution at a certain pH.

9. The method of claim 8, wherein: Exposing the patterned substrate to the etching solution includes exposing the patterned substrate to a non-aqueous organic-based etching solution, the organic-based etching solution comprising an etchant chemistry and an organic solvent, and wherein the etchant chemistry comprises anions as a main reactive species.

10. The method of claim 9, wherein: Exposing the patterned substrate to the non-aqueous organic-based etching solution increases an etch rate of portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to an etch rate of the first dielectric material layer in the surrounding areas of the patterned substrate.

11. The method of claim 8, wherein: Exposing the patterned substrate to the etching solution includes exposing the patterned substrate to a water-based etching solution comprising an etchant chemistry and an aqueous solvent, and wherein the etchant chemistry comprises a cation as a main reactive species.

12. The method of claim 11, wherein: Exposing the patterned substrate to the water-based etching solution increases an etch rate of portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to an etch rate of the first dielectric material layer in the surrounding areas of the patterned substrate.

13. The method of claim 1, wherein: The wall material of the plurality of metal interconnects exhibits a positive surface potential when exposed to an aqueous solution at a certain pH.

14. The method of claim 13, wherein: Exposing the patterned substrate to the etching solution includes exposing the patterned substrate to a water-based etching solution comprising an etchant chemical and an aqueous solvent, or a non-aqueous organic-based etching solution comprising the etchant chemical and an organic solvent.

15. The method of claim 14, wherein: Exposing the patterned substrate to the etching solution comprises: When the etchant chemistry comprises anions as the main reactive species, exposing the patterned substrate to the water-based etching solution or the non-aqueous organic-based etching solution; and When the etchant chemistry contains cations as the primary reactive species, the patterned substrate is exposed to the water-based etching solution.

16. The method of claim 13, wherein: Exposing the patterned substrate to the water-based etching solution or the non-aqueous organic-based etching solution increases the etching rate of the portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to the etching rate of the first dielectric material layer in the surrounding areas of the patterned substrate.

17. The method of claim 1, wherein: The recesses formed between the plurality of metal interconnections reach the target recess depth without using a dry etching process.

18. A method for forming an air gap between metal interconnects, the method comprising: providing a patterned substrate having a plurality of metal interconnects formed within a first dielectric material layer, wherein a critical dimension (CD) between the metal interconnects is small compared to surrounding areas of the patterned substrate; exposing the patterned substrate to a non-aqueous organic-based etching solution to etch the first dielectric material layer and form recesses between the plurality of metal interconnects, wherein the non-aqueous organic-based etching solution etches portions of the first dielectric material layer disposed between the plurality of metal interconnects faster than it etches the first dielectric material layer in the surrounding areas of the patterned substrate; Continue etching the first dielectric material layer with the non-aqueous organic-based etching solution until the recesses formed between the plurality of metal interconnects reach a target recess depth; and A second dielectric material layer is deposited on the patterned substrate, wherein the deposition closes the recesses formed between the plurality of metal interconnects to form air gaps between the plurality of metal interconnects.

19. The method of claim 18, wherein: The continuing to etch the first dielectric material layer with the non-aqueous organic-based etching solution completely removes the portion of the first dielectric material layer disposed between the plurality of metal interconnects while retaining a certain thickness of the first dielectric material layer in the surrounding areas of the patterned substrate.

20. The method of claim 18, wherein: The non-aqueous organic-based etching solution comprises an etchant chemical and an organic solvent.

21. The method of claim 20, wherein: The etchant chemistry includes one or more of the following: hydrofluoric acid (HF), ammonium hydroxide (NH4OH), hydrochloric acid (HCl), hydrogen peroxide (H2O2), nitric acid (HNO3), phosphoric acid (H3PO4), potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH).

22. The method of claim 20, wherein: The organic solvent includes one or more of the following: methanol (CH4O), ethanol (C2H6O), isopropanol (C3H8O), benzyl alcohol (C7H8O), ethylene glycol (C2H6O2), acetic acid (CH3COOH), acetone (C3H6O), propylene carbonate (C4H6O3), n-hexane (C6H 14 ), cyclohexane (C6H 12 ), diethyl ether (C4H 10 O), tetrahydrofuran (C4H8O), benzene (C6H6), toluene (C7H8), dichloromethane (CH2Cl2), trichloroethylene (C2HCl3), 1,1,1-trichloroethane (C2H3Cl3), 1,2-dichloroethane (C2H4Cl2), N-methyl-2-pyrrolidone (C5H9NO), dimethyl sulfoxide (C2H6OS), ethyl lactate (C5H 10 O3), ethanolamine (C2H7NO) and propylene glycol methyl ether acetate (C6H 12 O3).

23. The method of claim 20, wherein: The wall material of the plurality of metal interconnects exhibits a negative surface potential when exposed to an aqueous solution at a pH, wherein the etchant chemistry comprises anions as primary reactive species, and wherein exposing the patterned substrate to the non-aqueous organic-based etching solution increases the etch rate of portions of the first dielectric material layer disposed between the plurality of metal interconnects as compared to the etch rate of the first dielectric material layer in the surrounding areas of the patterned substrate.

24. The method of claim 18, wherein: The recesses formed between the plurality of metal interconnections reach the target recess depth without using a dry etching process.

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