Vertical transistor with self-aligned backside contact

Abstract

A semiconductor structure includes a fin of a vertical transistor structure, a top source-drain region on a top side of the fin, a bottom source-drain region on a bottom side of the fin, and a backside contact below and in contact with the bottom source-drain region.

Description

Background Art

[0001] The present invention relates generally to semiconductor structures and more particularly to self-aligned backside contacts for vertical transistor structures. Vertical transistors are an attractive option for technology scaling to 5nm and beyond. Vertical transistors have channels oriented perpendicular to the substrate surface, as opposed to being positioned along the plane of the substrate surface in the case of lateral transistors. By using a vertical design, packing density can be increased. That is, by making the channel perpendicular to the substrate, vertical transistors improve scaling limitations over lateral transistors. Summary of the invention

[0002] According to an embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a fin of a vertical transistor structure, a top source and drain region on the top side of the fin, a bottom source and drain region on the bottom side of the fin, and a backside contact below the bottom source and drain region and in contact with the bottom source and drain region.

[0003] According to an embodiment of the present invention, the semiconductor structure further comprises a shallow trench isolation liner and a shallow trench isolation filler, wherein the backside contact portion and the sidewalls of the bottom source and drain directly contact the shallow trench isolation liner.

[0004] According to an embodiment of the present invention, the semiconductor structure further includes a backside interconnect via in electrical contact with a bottom surface of the backside contact.

[0005] According to an embodiment of the present invention, the semiconductor structure further includes a top spacer isolating the top source and drain region from the fin, and a bottom spacer isolating the bottom source and drain region from the fin.

[0006] According to an embodiment of the present invention, the width of the bottom source and drain region is equal to the width of the backside contact portion.

[0007] According to an embodiment of the present invention, the length of the bottom source and drain region is equal to the length of the back contact portion.

[0008] According to an embodiment of the present invention, the backside contact is self-aligned with an adjacent shallow trench isolation liner.

[0009] According to an embodiment of the present invention, the bottom source and drain region contacts a bottom surface of one or more additional fins adjacent to the fin.

[0010] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a fin of a vertical transistor structure, a top source and drain region on the top side of the fin, a bottom source and drain region on the bottom side of the fin, wherein the width of the bottom source and drain region is greater than the length of the fin, and a backside contact portion below the bottom source and drain region and in contact with the bottom source and drain region.

[0011] According to an embodiment of the present invention, the semiconductor structure further includes a top spacer isolating the top source and drain region from the fin, and a bottom spacer isolating the bottom source and drain region from the fin.

[0012] According to an embodiment of the present invention, the width of the bottom source and drain region is equal to the width of the backside contact portion.

[0013] According to an embodiment of the present invention, the length of the bottom source and drain region is equal to the length of the back contact portion.

[0014] According to an embodiment of the present invention, the backside contact is self-aligned with an adjacent shallow trench isolation liner.

[0015] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a fin of a vertical transistor structure, a top source and drain region on the top side of the fin, a bottom source and drain region on the bottom side of the fin, wherein the width of the bottom source and drain region is greater than the width of the fin, and a backside contact portion below the bottom source and drain region and contacting the bottom source and drain region.

[0016] According to an embodiment of the present invention, the semiconductor structure further includes a top spacer isolating the top source and drain region from the fin, and a bottom spacer isolating the bottom source and drain region from the fin.

[0017] According to an embodiment of the present invention, the width of the bottom source and drain region is equal to the width of the backside contact portion.

[0018] According to an embodiment of the present invention, the length of the bottom source and drain region is equal to the length of the back contact portion.

[0019] According to an embodiment of the present invention, the backside contact is self-aligned with an adjacent shallow trench isolation liner.

[0020] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a fin of a vertical transistor structure, a top source and drain region on a top surface of the fin, a bottom source and drain region on a bottom side of the fin, and a backside contact below and in contact with the bottom source and drain region, wherein the entire top source and drain region is above the fin, wherein the entire bottom source and drain region is below the fin, and wherein the entire backside contact is below the bottom source and drain region.

[0021] According to an embodiment of the present invention, the width of the bottom source and drain region is equal to the width of the backside contact portion.

[0022] According to an embodiment of the present invention, the length of the bottom source and drain region is equal to the length of the back contact portion.

[0023] According to an embodiment of the present invention, the backside contact is self-aligned with an adjacent shallow trench isolation liner.

[0024] According to an embodiment of the present invention, the width of the bottom source and drain region is greater than the width of the fin.

[0025] According to an embodiment of the present invention, the bottom source and drain region contacts a bottom surface of one or more additional fins adjacent to the fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following detailed description, which is given by way of example and is not intended to be limiting of the invention thereto, will be best understood in conjunction with the accompanying drawings, in which:

[0027] Figure 1 and Figure 2 is a cross-sectional view of a semiconductor structure during an intermediate step of a method of fabricating a vertical transistor having a self-aligned backside contact for the vertical transistor according to an exemplary embodiment;

[0028] Figure 3 and Figure 4 is a cross-sectional view of the semiconductor structure after forming sidewall spacers and recessing the second substrate layer according to an exemplary embodiment;

[0029] Figure 5 and Figure 6 is a cross-sectional view of a semiconductor structure after forming a bottom source and drain region according to an exemplary embodiment;

[0030] Figure 7 and Figure 8 is a cross-sectional view of a semiconductor structure after defining an active device region using an RX patterning mask according to an exemplary embodiment;

[0031] Fig. 9 and Fig.10 is a cross-sectional view of a semiconductor structure after forming a shallow trench isolation region according to an exemplary embodiment;

[0032] Fig.11 and Fig.12 is a cross-sectional view of a semiconductor structure after forming a bottom spacer, a metal gate, and an interlayer dielectric layer according to an exemplary embodiment;

[0033] Fig.13 and Fig.14 is a cross-sectional view of a semiconductor structure after forming a top spacer and a top source and drain region according to an exemplary embodiment;

[0034] Fig.15 and Fig.16 is a cross-sectional view of a semiconductor structure after forming a contact structure in a mid-stage process line, forming a back-end process line, and fixing a carrier wafer according to an exemplary embodiment;

[0035] Fig.17 and Fig.18 is a cross-sectional view of a semiconductor structure after flipping the assembly and removing the substrate according to an exemplary embodiment;

[0036] Fig.19 and Fig. 20 is a cross-sectional view of a semiconductor structure after removing an etch stop layer according to an exemplary embodiment;

[0037] Fig.21 and Fig. 22 is a cross-sectional view of the semiconductor structure after removing a remaining portion of the second substrate layer according to an exemplary embodiment;

[0038] Fig.23 and Fig.24 is a cross-sectional view of a semiconductor structure after forming a self-aligned backside contact according to an exemplary embodiment;

[0039] Fig.25 and Fig.26 is a cross-sectional view of a semiconductor structure after forming backside vias, backside metal lines, and backside wiring interconnect levels according to an exemplary embodiment;

[0040] Fig. 27 and Fig.28 is a cross-sectional view of a semiconductor structure during an intermediate step of a method of fabricating a vertical transistor having a self-aligned backside contact according to an alternative embodiment;

[0041] Fig.29 , Fig.30 and Fig.31 shows a number of design layouts according to exemplary embodiments;

[0042] The accompanying drawings are not necessarily to scale. The accompanying drawings are merely schematic representations and are not intended to depict specific parameters of the present invention. For clarity and ease of illustration, the proportions of the elements may be exaggerated. The accompanying drawings are intended to describe only typical embodiments of the present invention. In the accompanying drawings, similar reference numerals represent similar elements.

[0043] In addition, XYZ Cartesian coordinates may also be shown in each of the figures to provide additional spatial context. The terms "vertical" or "vertical direction" or "vertical height" as used herein refer to the Z direction of the Cartesian coordinates shown in the figures, and the terms "horizontal" or "horizontal direction" or "lateral direction" as used herein refer to the X direction and / or Y direction of the Cartesian coordinates shown in the figures. DETAILED DESCRIPTION

[0044] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be implemented in various forms. However, the present invention may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0045] References in the specification to "one embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, these terms do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0046] For the purposes of the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the disclosed structures and methods as oriented in the accompanying drawings. It should be understood that when an element as a layer, region or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can also be intermediate elements. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intermediate elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements. In addition, the term "sub-lithographic" may refer to a size or size that is smaller than the current size achievable by a photolithographic process, and the term "photolithographic" may refer to a size or size that is equal to or larger than the current size achievable by a photolithographic process. Sub-lithographic dimensions and photolithographic dimensions may be determined by a person of ordinary skill in the art at the time of filing an application.

[0047] The terms substantially, substantially similar, approximately, or any other term indicating functionally equivalent similarity refers to situations where differences in length, height, or orientation do not convey an actual difference between the explicit recitation (e.g., the term is not substantially similar) and the substantially similar variation. In one embodiment, substantially (and its derivatives) refers to differences within generally accepted engineering or manufacturing tolerances for similar devices, such as a 10% deviation in value or a 10° deviation in angle.

[0048] In order not to obscure the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for presentation and for illustration purposes, and may not be described in detail in some instances. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description is more focused on the distinguishing features or elements of various embodiments of the present invention.

[0049] Vertical transfer FETs (VTFETs) have known advantages over conventional FinFETs in terms of density, performance, power consumption, and integration. However, valuable layout area is consumed by the front-side contact structure to the bottom source-drain region. This contact structure is usually arranged adjacent to the main unit, thus requiring additional layout area. In addition, current process technology limits how much space can be saved by physically moving the bottom source-drain contact structure closer to the main unit.

[0050] The present invention relates generally to semiconductor structures and more particularly to self-aligned backside contacts for vertical transistor structures. More specifically, the self-aligned backside contacts are formed from the backside and are vertically aligned with the fins of the main cell. This reduces the "cell height", or reduces the cell footprint or design area. Figures 1 to 31 The drawings in the drawings describe in detail exemplary embodiments of self-aligned backside contacts for vertical transistor structures. Those skilled in the art will readily appreciate that the detailed description given herein with respect to these drawings is for illustrative purposes, as the invention extends beyond these limited embodiments.

[0051] Reference now Figure 1 and 2 , shows structure 100 during an intermediate step of a method for fabricating a vertical transistor with a self-aligned backside contact according to an embodiment of the present invention. Figure 1 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Figure 2 Depicted is a cross-sectional view of structure 100 taken along line YY parallel to the fin. Note that Figures 1 to 16 and its corresponding description for front-side processing, while Figures 17 to 26 and its corresponding description is for dorsal processing.

[0052] The structure 100 includes a first semiconductor substrate layer 102 (hereinafter referred to as “first substrate layer”), an etch stop layer 104 , a second semiconductor substrate layer 106 (hereinafter referred to as “second substrate layer”), a semiconductor fin 108 , and a mask 110 .

[0053] The substrate layers 102, 106 may be formed of any suitable material, including, for example, a bulk semiconductor or a semiconductor-on-insulator layered structure. Illustrative examples of suitable materials for the substrate layers 102, 106 include, but are not limited to, silicon, silicon germanium, carbon-doped silicon germanium, carbon-doped silicon, epitaxial silicon, and multilayers thereof. Although silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be employed, such as, but not limited to, gallium arsenide, indium phosphide, indium gallium arsenide, indium arsenide, gallium, cadmium telluride, and zinc selenide.

[0054] In the present embodiment, substrate layers 102, 106 are both bulk semiconductor substrate layers. "Body" means that substrate layers 102, 106 are completely composed of at least one of the above materials. In one embodiment, substrate layers 102, 106 may be completely composed of silicon. In other embodiments, substrate layers 102, 106 may include a multilayer semiconductor material stack, which includes at least two different semiconductor materials, as defined above. In another embodiment, the multilayer semiconductor material stack may include a stack of silicon and silicon-germanium alloys in any order. In another embodiment, substrate layers 102, 106 may include single crystal semiconductor materials. Such single crystal materials may have any well-known crystal orientation. For example, the crystal orientation of substrate layers 102, 106 may be {100}, {110} or {111}. Other crystal orientations other than those specifically mentioned may also be used in the present application.

[0055] In one embodiment, the first substrate layer 102 may have a thickness ranging from about 50 μm to about 1000 μm; however, other thicknesses less than or greater than the above thickness ranges may also be employed. As will be described in more detail below, the first substrate layer 102 is sacrificial and will be completely removed during subsequent processing. Therefore, the thickness of the first substrate layer 102 should be carefully selected to enable easy removal, but not to compromise the structural support as a carrier during manufacturing.

[0056] Unlike the first substrate layer 102, the second substrate layer 106 or a portion thereof remains an integral part of the final structure after fabrication. Therefore, the thickness of the second substrate layer 106 should be selected based on vertical transistor conventions. In one embodiment, the second substrate layer 106 can have a thickness ranging from about 50 nm to about 300 nm; however, other thicknesses less than or greater than the above thickness ranges can also be used.

[0057] The etch stop layer 104 is disposed between the first substrate layer 102 and the second substrate layer 106 and may be formed of any suitable material, including, for example, a known buried oxide layer or silicon germanium. In all cases, the substrate layers 102, 106 should be selectively etched or removed relative to the etch stop layer 104, and vice versa.

[0058] Semiconductor fins 108 are etched from second substrate layer 106 and form a channel region of the vertical transistor structure depicted by structure 100. First, a mask 110 is formed on or over second substrate layer 106. Mask 110 defines the area of ​​semiconductor fins 108. Using an anisotropic etch, such as reactive ion etching, second substrate layer 106 is etched or patterned to remove material not covered by mask 110, thereby forming semiconductor fins 108. Although the present application describes and illustrates the formation of three semiconductor fins 108, the same process can be used to form a single semiconductor fin or more than two semiconductor fins.

[0059] As used herein, "semiconductor fin" refers to a semiconductor material including a pair of vertical sidewalls that are parallel to each other. As used herein, a surface is "vertical" if there is a surface that deviates from a vertical plane by no more than three times the root mean square roughness of the surface. In an embodiment, each semiconductor fin 108 has a height ranging from about 20nm to about 200nm, and a width ranging from about 5nm to about 30nm. Other heights and / or widths that are less than or greater than the ranges mentioned herein may also be used in the present application. Each semiconductor fin 108 is spaced apart from its nearest adjacent semiconductor fin 108 by a spacing ranging from about 20nm to about 100nm; the spacing is measured from a point or reference surface on one semiconductor fin to the exact same point or reference surface on an adjacent semiconductor fin. In addition, the semiconductor fins 108 are generally oriented parallel to each other.

[0060] Reference now Figure 3 and 4 , shows the structure 100 after forming sidewall spacers 112 and recessing the second substrate layer 106 in accordance with an embodiment of the present invention. Figure 3 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Figure 4 A cross-sectional view of structure 100 taken along line YY parallel to the fin is depicted.

[0061] The sidewall spacers 112 may be formed by conformally depositing or growing a dielectric, followed by an anisotropic etch that removes the dielectric from horizontal surfaces of the structure 100. For example, the anisotropic etch is designed to substantially remove the conformal dielectric from the top surface of the mask 110 and the bottom surface of the opening between adjacent fins. After etching, the sidewall spacers 112 remain on the sidewalls of the semiconductor fins 108.

[0062] The sidewall spacers 112 may include any suitable dielectric material, such as a nitride or an oxide. In an embodiment, the sidewall spacers 112 may include silicon nitride. In another embodiment, the sidewall spacers 112 may have a horizontal width or thickness ranging from about 5 nm to about 10 nm. The sidewall spacers 112 may include a single layer; however, the sidewall spacers 112 may alternatively include multiple layers of dielectric material. In all cases, the sidewall spacers 112 should be made of a material composition having a thickness suitable for protecting the sidewalls of the semiconductor fins 108 during subsequent manufacturing techniques, as described in more detail below.

[0063] After forming the sidewall spacers 112, the second substrate layer 106 may be recessed using any suitable method, such as wet etching, dry etching, or a combination of sequential wet and / or dry etching. In an embodiment, anisotropic etching, such as reactive ion etching, is used to recess the second substrate layer 106. Alternatively, the second substrate layer 106 may be recessed using a wet etching technique.

[0064] The etch is designed to recess the exposed portion of the second substrate layer 106. Doing so will create an opening 114 or space between and below the semiconductor fin 108 and the sidewall spacer 112, as shown. In all cases, the etch stops before the etch stop layer 104 is exposed.

[0065] Reference now Figure 5 and 6 , shows the structure 100 after forming the bottom source and drain regions 116 according to an embodiment of the present invention. Figure 5 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Figure 6 A cross-sectional view of structure 100 taken along line YY parallel to the fin is depicted.

[0066] The bottom source and drain regions 116 are formed by first epitaxially growing epitaxial material on the exposed surface of the second substrate layer 106 at the bottom of the opening 114. Thereafter, the structure 100 may be annealed according to known techniques to diffuse the epitaxial material into the second substrate layer 106. Note that the sidewall spacers 112 are used to prevent the epitaxial material from growing on the surface of the semiconductor fin 108.

[0067] It should be understood that the bottom source and drain regions 116 can be either source or drain regions, as appropriate. Illustrative examples of suitable materials for the bottom source and drain regions 116 include, but are not limited to, silicon, silicon germanium, carbon-doped silicon germanium, and multilayers thereof.

[0068] In some embodiments, the bottom source and drain region 116 can be doped with dopant atoms as needed. The bottom source and drain region 116 can be doped in situ as it grows, or can be doped subsequently using known techniques (e.g., ion implantation). The dopant atoms can be n-type dopants or p-type dopants. Example N-type dopants include phosphorus, arsenic antimony for group IV semiconductors, and selenium, tellurium, silicon, and germanium for group III-V semiconductors. Example p-type dopants include beryllium, zinc, cadmium, silicon, germanium for group III-V semiconductors, and boron, aluminum, and gallium for group IV semiconductors. In an embodiment, for devices based on group IV semiconductors, the bottom source and drain region 116 is made of doped Si: (for N-type devices) or SiGe: B (for P-type devices), with a dopant concentration ranging from about 2×10 20 About 2.5×10 21 Atom / cm 2 , dopant concentrations range from about 4 × 10 20 About 1.5×10 21 Atom / cm 2 is more typical.

[0069] In another embodiment, the bottom source and drain region 116 can be formed of a III-V semiconductor. The term "III-V compound semiconductor" refers to a semiconductor material that includes at least one element from the III group of the periodic table and at least one element from the V group of the periodic table. Typically, the III-V compound semiconductor is a binary, ternary or quaternary alloy including III / V elements. Examples of III-V compound semiconductors that can be used in embodiments of the present invention include, but are not limited to, gallium arsenide, indium arsenide, indium antimonide, indium phosphide, aluminum arsenide, indium gallium arsenide, indium aluminum arsenide, indium antimonide aluminum, indium arsenide aluminum phosphide, indium gallium arsenide phosphide and alloys of combinations thereof. In one embodiment, the bottom source and drain region 116 is made of a doped III-V semiconductor material having a dopant concentration ranging from about 1×10 18 to about 1×10 20 Atom / cm 2 , more typically the dopant concentration ranges from about 5 × 10 18 to about 8×10 19 Atom / cm 2 .

[0070] Reference now Figure 7 and 8 , shows structure 100 after defining active device areas using an RX patterning mask according to an embodiment of the present invention. Figure 7 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Figure 8 A cross-sectional view of structure 100 taken along line YY parallel to the fin is depicted.

[0071] An RX patterning mask is applied, and active device areas are defined by etching exposed portions of the structure 100 according to known techniques. In doing so, as illustrated, bottom source and drain regions 116 and portions of the second substrate layer 106 are removed. According to an embodiment of the present invention, the etching during RX patterning is selective to both the mask 110 and the sidewall spacers 112, and continues at least until the etch stop layer 104 is exposed. In most cases, the etching will continue to a certain nominal depth in the etch stop layer 104.

[0072] Reference now Fig. 9 and 10 , shows the structure 100 after forming a shallow trench isolation region (hereinafter referred to as “STI region”) according to an embodiment of the present invention. Fig. 9 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Fig.10 A cross-sectional view of the structure 100 is shown, taken along line YY parallel to the fin.

[0073] According to an embodiment of the present invention, the STI region includes an STI liner 118 and an STI filler 120. First, according to known techniques, the STI liner 118 is conformally deposited directly on the exposed surface of the structure 100. Specifically, as shown in the figure, the STI liner 118 is conformally deposited directly on the exposed surfaces of the etch stop layer 104, the second substrate layer 106, and the source and drain regions 116. "Conformal" means that the material layer has a continuous thickness. For example, a continuous thickness generally means that a first thickness measured from the bottom surface to the topmost surface is the same as a second thickness measured from the inner sidewall surface to the outer sidewall surface. The STI liner 118 can be formed of any suitable dielectric, including, for example, silicon nitride (SixNy).

[0074] Next, according to known techniques, an STI filler 120 is blanket deposited over the entire structure 100, specifically, directly on top of the STI liner 118. The STI filler 120 may be formed of any suitable dielectric, including, for example, silicon oxide (SiOx).

[0075] Finally, as shown, the STI liner 118, the STI filler 120, and the sidewall spacer 112 are recessed. According to known techniques, the recess selectively removes portions of the STI liner 118, the STI filler 120, and the sidewall spacer 112 relative to the mask 110. After the recess, the sidewall spacer 112 is completely removed, and the uppermost surfaces of the STI liner 118 and the STI filler 120 are flush or substantially flush with the uppermost surfaces of the source and drain regions 116.

[0076] In this example, the STI region penetrates or extends from near the bottom of the semiconductor fin 108 to the etch stop layer 104 below the bottom source and drain region 116. Doing so ensures electrical isolation between adjacent active device regions and enables the formation of backside contacts.

[0077] Reference now Fig.11 and 12 , shows the structure 100 after forming a bottom spacer 122 , a metal gate 124 , and an interlayer dielectric layer 126 according to an embodiment of the present invention. Fig.11 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Fig.12 A cross-sectional view of structure 100 taken along line YY parallel to the fin is depicted.

[0078] Bottom spacers 122 are deposited on the top surfaces of bottom source and drain regions 116 and STI regions. It is particularly contemplated to deposit bottom spacers 122 in an anisotropic manner without accumulating on the sidewalls of semiconductor fins 108. This can be accomplished using, for example, gas cluster ion beam (GCIB) deposition, in which a surface is bombarded with high energy cluster ions. In alternative embodiments, other deposition techniques may be used to form bottom spacers 122 only on horizontal surfaces.

[0079] Alternatively, the bottom spacer 122 is formed by first depositing a blanket dielectric layer, followed by a recess etch to remove a portion of the blanket dielectric layer. The recess etch removes a portion of the blanket dielectric layer until the bottom spacer 122 remains. In this case, the selected dielectric material is etched to be selective to the mask 110 and the semiconductor fin 108.

[0080] Suitable spacer materials for forming the bottom spacer 122 include, but are not limited to, oxides, such as silicon oxide (SiOx); nitrides, such as silicon nitride (SixNy); and / or low-κ materials, such as carbon-doped oxide materials (SiCOH) or silicon boron carbon nitride (SiBCN) containing silicon (Si), carbon (C), oxygen (O), and hydrogen (H). As used herein, the term "low-κ" refers to a material having a relative dielectric constant κ lower than that of silicon dioxide.

[0081] Continue to refer Fig.11 and 12According to known techniques, before forming the metal gate 124, a gate dielectric (not shown) is first conformally deposited directly on the exposed surface of the structure 100. The gate dielectric is composed of a gate dielectric material. The gate dielectric can be an oxide, a nitride and / or an oxynitride. In one example, the gate dielectric can be a high-k material having a dielectric constant greater than that of silicon dioxide. Exemplary high-k dielectrics include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, silicates thereof, and alloys thereof. Each value of x is independently 0.5 to 3, and each value of y is independently 0 to 2. In some embodiments, a multi-layer gate dielectric structure including different gate dielectric materials (eg, silicon dioxide) and a high-k gate dielectric may be formed and used as the gate dielectric.

[0082] Next, according to known techniques, the metal gate 124 is directly conformally deposited on the gate dielectric. For example, the metal gate 124 can be formed by any deposition technique, including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering or atomic layer deposition. In an embodiment, the metal gate 124 can have a thickness ranging from about 1nm to about 10nm. Other thicknesses less than or greater than the above-mentioned thickness range can also be used to provide the metal gate 124. The key is to monitor and control the formation of the metal gate 124 to prevent pinching off between adjacent devices, especially in narrow spacing structures. As shown, the bottom spacer 122 separates the bottom source and drain region 116 from the metal gate 124.

[0083] In an embodiment, the metal gate 124 is composed of an N-type work function metal. As used herein, an "N-type work function metal" is a metal that realizes an N-type threshold voltage shift. As used herein, an "N-type threshold voltage shift" means the shift of the Fermi energy of an n-type semiconductor device toward the silicon conduction band in a silicon-containing substrate of an n-type semiconductor device. The "conduction band" is the lowest electronic energy band of a doped material that is not completely filled with electrons. In an embodiment, the work function of the N-type work function metal is in the range of 4.1eV to 4.3eV. In an embodiment, the N-type work function metal is composed of at least one of TiAl, TaN, TiN, HfN, HfSi, or a combination thereof. The N-type work function metal can be formed using chemical vapor deposition, atomic layer deposition, sputtering, or electroplating.

[0084] In another embodiment, the metal gate 124 can be a p-type work function metal. As used herein, a "p-type work function metal" is a metal that achieves a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is between 4.9 eV and 5.2 eV. As used herein, a "threshold voltage" is the lowest achievable gate voltage that will turn on a semiconductor device (e.g., a transistor) by turning on the channel of the device. The term "p-type threshold voltage shift" used herein means that the Fermi energy of a p-type semiconductor device is shifted toward the valence band of silicon in a silicon-containing substrate of the p-type semiconductor device. The "valence band" is the highest range of electron energy where electrons usually exist at absolute zero. In one embodiment, the p-type work function metal can be composed of titanium, titanium nitride, or titanium carbide. The p-type work function metal can also be composed of TiAlN, Ru, Pt, Mo, Co, and alloys and combinations thereof. In one embodiment, the p-type work function metal can be formed by a physical vapor deposition method, such as sputtering, chemical vapor deposition, or atomic layer deposition.

[0085] Next, portions of the gate dielectric and metal gate 124 are removed according to known techniques. Specifically, an anisotropic etch may be used to remove portions of the gate dielectric and metal gate 124 from horizontal surfaces of the structure 100. For example, the anisotropic etch is designed to substantially remove portions of the gate dielectric and metal gate 124 from the top surface of the mask 110 and the bottom spacers 122 in the unmasked areas, as shown. In the case of this embodiment, as shown in FIG. Fig.12 As shown, the gate dielectric and metal gate 124 are not removed from between the ends of the fin 108 .

[0086] Finally, in accordance with an embodiment of the present invention, an interlayer dielectric layer 126 is deposited across the structure 100 in accordance with known techniques. The interlayer dielectric layer 126 may be composed of, for example, silicon oxide (SiOx), undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-κ dielectric layer, a chemical vapor deposition (CVD) low-κ dielectric layer, or any combination thereof. As described above, the term "low-κ" as used herein refers to a material having a relative dielectric constant κ lower than the dielectric constant of silicon dioxide.

[0087] In one embodiment, the interlayer dielectric layer 126 may be formed using a deposition technique including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation, spin coating, or sputtering.

[0088] After deposition, a planarization technique such as chemical mechanical planarization (CMP) and / or grinding is applied. The planarization technique removes excess material of the interlayer dielectric layer 126 and continues polishing until the uppermost surface of the mask 110 and the metal gate 124 is exposed. After polishing, the uppermost surface of the mask 110 and the metal gate 124 is flush or substantially flush with the uppermost surface of the interlayer dielectric layer 126.

[0089] Reference now Fig.13 and 14 , shows the structure 100 after forming a top spacer 128 and a top source and drain region 130 according to an embodiment of the present invention. Fig.13 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Fig.14 A cross-sectional view of the structure 100 is shown, taken along line YY parallel to the fin.

[0090] First, the metal gate 124 is recessed according to known techniques. More specifically, the metal gate 124 and the gate dielectric are selectively recessed relative to the interlayer dielectric layer 126 and the mask 110 until the upper portion of the fin 108 is exposed.

[0091] The metal gate 124 and the gate dielectric may be recessed using any suitable method, such as wet etching, dry etching, or a combination of sequential wet and / or dry etching. In an embodiment, the metal gate 124 and the gate dielectric may be recessed using an anisotropic etch, such as reactive ion etching. Alternatively, the metal gate 124 and the gate dielectric may be recessed using a wet etching technique.

[0092] The etching will remove the top portions of the metal gate 124 and the gate dielectric and create an opening or space between the semiconductor fin 108 and the interlayer dielectric layer 126. After etching, the upper surfaces of the metal gate 124 and the gate dielectric will be below the uppermost surface of the semiconductor fin 108.

[0093] It is critical that the metal gate 124 and gate dielectric are recessed below the uppermost surface of the semiconductor fin 108 to ensure isolation between the gate metal and the top source and drain regions 130. If the metal gate 124 and gate dielectric are not recessed below the uppermost surface of the semiconductor fin 108, then the source and drain epitaxy formed later may contact the metal gate 124 and create a short circuit. Therefore, controlling the recess depth of the metal gate 124 and gate dielectric below the top of the semiconductor fin 108 will allow for precise top junction definition as well as defined channel length.

[0094] The top spacer 128 can be formed directly on top of the upper surface of the metal gate 124, and the gate dielectric is exposed after the recess. The top spacer 128 can be formed using a deposition technique followed by a spacer etch (anisotropic etch). For example, the techniques for depositing the top spacer 128 include, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation, spin coating, or sputtering. For example, the techniques for etching the top spacer 128 include dry etching techniques such as reactive ion etching, ion beam etching, plasma etching, or laser ablation. The top spacer 128 is composed of any dielectric material similar to the bottom spacer 122 described above in terms of composition and etching rate.

[0095] Next, the mask 110 is selectively removed according to known techniques. The mask 110 is removed using an etch selective to the top source and drain regions 130 and the semiconductor fins 108. In one embodiment, when the mask 110 is composed of silicon nitride (SixNy), a hot (about 150° C. to 180° C.) phosphoric acid solution may be used to selectively remove the mask 110 with respect to the top source and drain regions 130 and the semiconductor fins 108. Removing the mask 110 creates an opening and exposes the uppermost surface of the semiconductor fins 108.

[0096] After removing the mask 110, an optional ion implantation technique and thermal treatment are performed to form the junction. If used, the semiconductor fin 108 is doped with dopant atoms using an implantation technique in a manner similar to the formation of the bottom source and drain region 116 described above. As described above, the dopant atoms can be n-type dopants or p-type dopants. Exemplary n-type dopants include phosphorus, arsenic antimony, selenium, tellurium, silicon, and germanium. Exemplary p-type dopants include beryllium, zinc, cadmium, silicon, germanium, boron, aluminum, and gallium. Typically, the bottom source and drain region 116 and the junction will be doped with the same type of dopant.

[0097] Next, a thermal treatment is used to diffuse the implanted dopants into the semiconductor fin 108 or into the top of the channel to form a junction. In some cases, dopants from the top source and drain regions 130 may also diffuse into the semiconductor fin 108 and contribute to the formation of the junction. In at least one embodiment, the thermal treatment may include a high temperature spike anneal or a laser spike anneal.

[0098] Next, top source and drain regions 130 are formed in the openings between adjacent top spacers 128 . Thus, the top source and drain regions 130 directly contact the exposed uppermost surface of the semiconductor fin 108 , and the top spacers 128 separate and isolate the top source and drain regions 130 from the metal gate 124 .

[0099] The top source and drain regions 130 can be epitaxially grown from the exposed surface of the semiconductor fin 108 using conventional techniques similar to the bottom source and drain regions 116. In addition, the top source and drain regions 130 can be formed of similar materials and similar dopant concentrations as the bottom source and drain regions 116. In this embodiment, the top source and drain regions 130 should be grown to completely fill the opening. In some cases, the process can include overgrowing the top source and drain regions 130 above the top surface of the interlayer dielectric layer 126, after which any excess material will be removed by subsequent chemical mechanical planarization techniques. At this stage of manufacturing, the top source and drain regions 130 do not undergo high temperature annealing in order to maintain the integrity of the metal gate 124.

[0100] Reference now Fig.15 and 16 , shows the structure 100 after forming contact structures 132 in a mid-stage process line, forming a back-end-of-stage process line 134, and securing a carrier wafer 136 according to an embodiment of the present invention. Fig.15 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Fig.16 A cross-sectional view of the structure 100 is shown, taken along line YY parallel to the fin.

[0101] First, a contact structure 132 is formed in the middle process line according to known techniques. For example, an additional layer of interlayer dielectric material is deposited, shown as a portion of interlayer dielectric layer 126, and a contact structure 132 is formed in interlayer dielectric layer 126 using conventional damascene techniques. Contact structure 132 may include typical source-drain contacts and gate contacts. For example, contact structure 132 may include source-drain contacts and gate contacts formed in an additional layer of interlayer dielectric material, as shown.

[0102] The contact structure 132 may include any suitable conductive material, such as copper, aluminum, tungsten, cobalt, or alloys thereof. Examples of deposition techniques that may be used to provide the spacer material include, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). In some cases, electroplating techniques may be used to form the contact structure 132.

[0103] In a typical manner, a planarization technique, such as chemical mechanical planarization (CMP) and / or grinding, is applied after depositing the contact structure 132. The planarization technique removes excess conductive material of the contact structure 132 from above the interlayer dielectric layer 126. After polishing, the uppermost surface of the contact structure 132 is flush or substantially flush with the upper surface of the interlayer dielectric layer 126. After forming the mid-stage process line including the contact structure 132, the back-end process line 134 is formed on top of the mid-stage process line according to known techniques.

[0104] Finally, a carrier wafer 136 is attached or removably secured to the backing tray 134. Typically, and not depicted, the carrier wafer 136 may be thicker than the other layers. Temporarily bonding the structure 100 to a thicker carrier provides improved handling and additional support for backside processing of the thin wafer. After the backside processing described below, the structure may be debonded or removed from the carrier wafer 134 according to known techniques.

[0105] Reference now Fig.17 and 18 , shows the structure 100 after flipping the assembly and removing the first substrate layer 102 in accordance with an embodiment of the present invention. Fig.17 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Fig.18 A cross-sectional view of the structure 100 is shown, taken along line YY parallel to the fin.

[0106] First, the structure 100 is flipped 180 degrees to prepare for backside processing. Generally, backside processing includes the fabrication or processing of the structure 100 opposite the active devices and wiring layers. Next, the first substrate layer 102 is selectively removed relative to the etch stop layer 104 according to known techniques.

[0107] Reference now Fig.19 and 20 , shows structure 100 after removal of etch stop layer 104 in accordance with an embodiment of the present invention. Fig.19 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Fig. 20 A cross-sectional view of the structure 100 is shown, taken along line YY parallel to the fin.

[0108] The etch stop layer 104 is selectively removed according to known techniques. For example, a wet etching technique may be used to selectively remove the etch stop layer 104 to the second substrate layer 106 and the STI region (specifically, the STI liner 118), as shown.

[0109] Reference now Fig.21 and 22 , shows the structure 100 after removing the remaining portion of the second substrate layer 106 according to an embodiment of the present invention. Fig.21 Depicted is a cross-sectional view of the structure 100 taken along line XX perpendicular to the fin. Fig. 22 A cross-sectional view of structure 100 taken along line YY parallel to the fin is depicted.

[0110] The second substrate layer 106 is selectively removed according to known techniques. For example, a wet etching technique may be used to selectively remove the second substrate layer 106 to the bottom source and drain regions 116, as shown. After removal, the trench 138 remains.

[0111] Reference now Fig.23 and 24 , shows the structure 100 after forming a self-aligned backside contact 140 according to an embodiment of the present invention. Fig.23 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Fig.24 A cross-sectional view of structure 100 taken along line YY parallel to the fin is depicted.

[0112] The backside contact 140 is formed in the trench 138. Specifically, the trench 138 is filled with a conductive material to form the backside contact 140. Thus, in at least one embodiment, as shown, the conductive material of the backside contact 140 is deposited directly on the exposed upper surface of the STI liner 118 and the bottom source and drain region 116. In addition, it is noted that the backside contact 140 is self-aligned and can be alternatively referred to as a self-aligned backside contact. Most notably, the backside contact 140 completely covers the entire source and drain epitaxy (116) without the risk of contact-to-contact shorting. This is achieved by the presence of the STI region, which includes the STI liner 118 and the STI filler 120. As previously described, the STI region is initially created deeper than the thickness of the second substrate layer 106, and is specifically created into the etch stop layer 104 to accommodate the formation of the backside contact 140, as shown.

[0113] The back contact 140 may include any suitable conductive material, such as copper, aluminum, tungsten, cobalt, or alloys thereof. Examples of deposition techniques that can be used to provide the spacer material include, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). In some cases, electroplating techniques may be used to form the back contact 140.

[0114] After deposition, a planarization technique such as chemical mechanical planarization (CMP) and / or grinding is applied. The planarization technique removes excess conductive material of backside contact 140 from above STI liner 118. After polishing, the upper surface of backside contact 140 is flush or substantially flush with the upper surface of STI liner 118.

[0115] Reference now Fig.25 and 26 , shows structure 100 after forming backside vias 142 , backside metal lines 144 , and backside wiring interconnect levels 146 , in accordance with an embodiment of the present invention. Fig.25 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Fig.26 A cross-sectional view of structure 100 is depicted, taken along line YY parallel to the fin.Backside vias 142, backside metal lines 144, and backside wiring interconnect levels 146 are formed in the backside dielectric layer according to known techniques.

[0116] like Fig.25 and 26 As shown, the vertical transistor structure represented by structure 100 in this example has some significant salient features. For example, structure 100 includes a self-aligned backside contact (140). Conventional contact structures for the bottom source and drain regions of vertical transistor devices are made on or from the front side, are arranged adjacent to the main cell, and require additional space. Unlike conventional contact structures, the backside contact (140) disclosed herein is vertically aligned with the bottom source and drain regions and is stacked directly below the bottom source and drain regions. Doing so eliminates the need for additional space, thereby reducing the "cell height" or footprint of the device.

[0117] Similar to a conventional vertical transistor structure, the bottom spacer 122 isolates the bottom source and drain regions 116 from the fins 108, and the top spacer 128 isolates the top source and drain regions 130 from the fins 108. In the present embodiment, the bottom spacer 122 is substantially horizontal and extends between adjacent fins 108, and the top spacer 128 is substantially vertical and surrounds the top source and drain regions 130.

[0118] Continue to refer Fig.25 and 26 , note that the width (x-direction) of the bottom source and drain region 116 is equal to the width of the backside contact 140, and the length (y-direction) of the bottom source and drain region 116 is equal to the length of the backside contact 140. In addition, the width (x-direction) of the bottom source and drain region 116 is greater than the width of the fin 108.

[0119] Reference now Fig. 27 and 28 , shows a structure 200 according to an alternative embodiment of the present invention. Fig. 27 A cross-sectional view of the structure 100 taken along line XX perpendicular to the fin is depicted. Fig.28 A cross-sectional view of structure 100 taken along line YY parallel to the fin is depicted. Structure 200 is substantially similar to structure 100 described above, except that it benefits from a shared bottom source and drain region 216 and a shared backside contact 240. Unlike structure 100, the shared bottom source and drain region 216 and shared backside contact 240 of structure 200 contact the fins 108 of multiple adjacent vertical devices, as shown.

[0120] Similar to the structure 100, the length (y-direction) of the shared bottom source and drain region 216 is equal to the length of the shared backside contact 240. In addition, similar to the structure 100, the width (x-direction) of the shared bottom source and drain region 216 is greater than the width of the fin 108. Unlike the structure 100, the width (x-direction) of the shared bottom source and drain region 216 is greater than the cumulative width of the plurality of fins 108. In this way, the shared bottom source and drain region 216 contacts the bottom surfaces of the plurality of fins 108.

[0121] Reference now Fig.29 , 30 and 31, depicting a plurality of design layouts according to embodiments of the present invention. Fig.29 Design layout A representing a typical configuration is depicted. Fig.30 A design layout B corresponding to the structure 100 described above is depicted. Fig.31 A design layout C corresponding to structure 200 described above is depicted.

[0122] Design layout A shows the relative positions of the fins, gate contacts (CB), top source-drain contacts (CA), and bottom source-drain contacts (CR) shown in each of the depicted design layouts. In addition, a representative "cell height" for each is depicted. Most relevantly, the bottom source-drain contact (CR) is typically adjacent to or close to the main cell or fin. In the example shown, the bottom source-drain contact (CR) is arranged at opposite ends of the fin. In some cases, the bottom source-drain contact (CR) separates one end of the first fin from one end of the second fin, as described. This configuration has a relatively large cell height, where the cell height is typically a measurement from one end of the transistor device to the other end of the transistor device parallel to the fin. In this example, the cell height of a single vertical device is measured from one bottom source-drain contact (CR) to another.

[0123] In contrast, according to an embodiment of the present invention, the cell height of the vertical transistor device of design layout B is less than the cell height of the vertical transistor device of design layout A. As previously described, embodiments of the present invention enable the manufacture of vertical transistor devices with reduced cell heights. Doing so saves valuable layout area.

[0124] Similar to design layout B, design layout C also benefits from reduced cell height, but shows an alternative configuration where bottom source and drain contacts (CR) are merged across adjacent fins or cells. This configuration may or may not have shared source and drain regions, such as structure 200 .

[0125] It should be noted that since the top source and drain regions and the bottom source and drain regions are both vertically aligned with the top source and drain contacts (CA) and the bottom source and drain contacts (CR), and are between the top source and drain contacts (CA) and the bottom source and drain contacts (CR), they are omitted from design layout B and design layout C in other cases.

[0126] Furthermore, according to an embodiment of the present application, in design layout B and design layout C, the bottom source-drain contact (CR) may be relatively larger than the top source-drain contact (CA), as previously discussed with respect to structure 100 and structure 200. More specifically, the size difference between the bottom source-drain contact (CR) and the top source-drain contact (CA) is proportional to the thickness of sidewall spacer 112 (see FIG. Figure 7-10 ).

[0127] The description of various embodiments of the present invention has been given for the purpose of illustration, but it is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: Fins with vertical transistor structures; a top source and drain region located on a top side of the fin; a bottom source and drain region on a bottom side of the fin; as well as A backside contact portion is below the bottom source and drain region and contacts the bottom source and drain region.

2. The semiconductor structure according to claim 1, further comprising: Shallow trench isolation liner; as well as A shallow trench isolation filling, wherein the sidewalls of both the backside contact and the bottom source and drain directly contact the shallow trench isolation liner.

3. The semiconductor structure according to claim 1, further comprising: A backside interconnect via is in electrical contact with a bottom surface of the backside contact.

4. The semiconductor structure according to claim 1, further comprising: a top spacer isolating the top source and drain region from the fin; as well as A bottom spacer is used to isolate the bottom source and drain region from the fin. The semiconductor structure according to claim 1 , wherein a width of the bottom source and drain region is equal to a width of the backside contact. The semiconductor structure according to claim 1 , wherein a length of the bottom source and drain region is equal to a length of the backside contact portion.

7. The semiconductor structure of claim 1, wherein the backside contact is self-aligned to an adjacent shallow trench isolation liner. 8 . The semiconductor structure of claim 1 , wherein the bottom source and drain regions contact bottom surfaces of one or more additional fins adjacent to the fin. 9 . The semiconductor structure according to claim 1 , wherein a width of the bottom source and drain region is greater than a length of the fin.

10. The semiconductor structure according to claim 9, further comprising: a top spacer isolating the top source and drain region from the fin; as well as A bottom spacer is used to isolate the bottom source and drain region from the fin. The semiconductor structure according to claim 9 , wherein a width of the bottom source and drain region is equal to a width of the backside contact. 12 . The semiconductor structure according to claim 9 , wherein a length of the bottom source and drain region is equal to a length of the backside contact portion.

13. The semiconductor structure of claim 9, wherein the backside contact is self-aligned to an adjacent shallow trench isolation liner. 14 . The semiconductor structure of claim 1 , wherein the entire top source and drain region is above the fin, wherein the entire bottom source and drain region is below the fin, and wherein the entire backside contact is below the bottom source and drain region.

15. The semiconductor structure of claim 14, further comprising: a top spacer isolating the top source and drain region from the fin; as well as A bottom spacer is used to isolate the bottom source and drain region from the fin. The semiconductor structure according to claim 14 , wherein a width of the bottom source and drain region is equal to a width of the backside contact. The semiconductor structure according to claim 14 , wherein the length of the bottom source and drain region is equal to the length of the backside contact.

18. The semiconductor structure of claim 14, wherein the backside contact is self-aligned to an adjacent shallow trench isolation liner. The semiconductor structure of claim 14 , wherein a width of the bottom source and drain region is greater than a width of the fin.

20. The semiconductor structure of claim 14, wherein the bottom source and drain regions contact bottom surfaces of one or more additional fins adjacent to the fin.

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