Test circuit and test method
By designing a test circuit with parallel structures of PMOS and NMOS transistors, the impact of MOSFET parasitic junction capacitor on circuit efficiency in high-frequency applications is solved, and the accurate measurement of parasitic capacitance value and the signal-to-noise ratio are improved.
Patent Information
- Application Number
- CN202311329505.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-13
- Publication Date
- 2025-04-15
AI Technical Summary
In high-frequency applications, the parasitic junction capacitance of MOSFET has a great impact on the circuit working efficiency and is difficult to accurately measure, resulting in a reduced signal-to-noise ratio.
A test circuit is designed, including a reference circuit unit and a circuit unit to be tested. Through the alternating output of the charging signal and the discharge signal, the parallel structure of the PMOS and NMOS transistors is used to reduce the charge injection effect, thereby accurately obtaining the parasitic capacitance value.
Improves the accuracy of obtaining parasitic capacitance values, reduces the charge injection effect, and improves the signal-to-noise ratio of MOSFETs in high-frequency applications.
Smart Images
Figure CN119827934A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a test circuit and a test method. Background Art
[0002] Integrated circuits are increasingly being used in high-frequency applications. In the future, with the rapid development of communication technology and the rise of 5G technology, the demand for high-frequency integrated circuits will grow further. MOSFET has the characteristics of low noise, low power consumption, fast switching, high voltage, and high frequency, and has been widely used in high-frequency power amplifiers, wireless communications, radio frequency identification, and other fields. In high-frequency applications, the superior performance of MOSFET provides a large market space for it and also promotes the continuous development and innovation of MOSFET technology.
[0003] In a MOS tube, a PN junction is formed between the source-drain doped region and the substrate. Therefore, there is a parasitic junction capacitance in the MOS tube. When the source-drain voltage changes, the parasitic capacitance will be charged or discharged. When the operating frequency of the MOS tube is high, the charging and discharging of the parasitic junction capacitance will have a significant impact on the working efficiency of the circuit. Therefore, the parasitic junction capacitance has a great influence on the high-frequency characteristics of the MOS tube. At the same time, the substrate noise can be transmitted to the MOS tube through the parasitic junction capacitance, which will reduce the signal-to-noise ratio of the MOS tube.
[0004] Currently, accurate measurement of parasitic junction capacitance of MOS tubes is an important consideration in MOS tube design. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a test circuit and a test method to improve the accuracy of obtaining parasitic capacitance values.
[0006] To solve the above problems, an embodiment of the present invention provides a test circuit, including: a reference circuit unit, including a first charging branch and a reference capacitor branch coupled to the first charging branch, the reference circuit unit is suitable for responding to a charging signal and obtaining a first charging current value through the first charging branch; a circuit unit to be tested, including a second charging branch and a capacitor branch to be tested coupled to the second charging branch, the circuit unit to be tested is suitable for responding to a charging signal and obtaining a second charging current value through the second charging branch, the first charging branch and the second charging branch both include a first logic device, the first logic device includes a PMOS transistor and an NMOS transistor connected in parallel with each other; a control unit, suitable for outputting the charging signal.
[0007] Optionally, the first charging branch and the second charging branch both include a first inverter coupled to the first logic device, and the first charging branch and the second charging branch share one first inverter.
[0008] Optionally, the first logic device has a first signal input terminal, a second signal input terminal, a first voltage input terminal and a first voltage output terminal; the first signal input terminal of the first logic device of the first charging branch is coupled to the first signal input terminal of the first logic device of the second charging branch, and the second signal input terminal of the first logic device of the first charging branch is coupled to the second signal input terminal of the first logic device of the second charging branch; the first voltage output terminal of the first logic device of the first charging branch is coupled to the reference capacitor branch, and the first voltage output terminal of the first logic device of the second charging branch is coupled to the capacitor branch to be measured.
[0009] Optionally, the first inverter has a third signal input terminal and a first signal output terminal; the third signal input terminal of the first inverter is coupled to the first signal input terminal of the first logic device, and the first signal output terminal of the first inverter is coupled to the second signal input terminal of the first logic device.
[0010] Optionally, the first charging branch and the second charging branch further include an ammeter coupled to the first voltage input terminal of the first logic device, and the ammeter is used to obtain the first charging current value and the second charging current value.
[0011] Optionally, the charging signal output terminal of the control unit is coupled to the first signal input terminal of the first logic device.
[0012] Optionally, the reference circuit unit also includes a first discharge branch coupled to the first charging branch and the reference capacitor branch, and the first discharge branch is suitable for responding to a discharge signal; the circuit unit to be tested also includes a second discharge branch coupled to the second charging branch and the capacitor branch to be tested, and the second discharge branch is suitable for responding to a discharge signal; the control unit is also suitable for outputting the discharge signal, and the discharge signal has the same frequency as the charging signal.
[0013] Optionally, both the first discharge branch and the second discharge branch include a second logic device, and the second logic device includes a PMOS transistor and an NMOS transistor connected in parallel with each other; or, the second logic device is a PMOS transistor; or, the second logic device is an NMOS transistor.
[0014] Optionally, the first discharge branch and the second discharge branch each further include a second inverter coupled to the second logic device, and the first discharge branch and the second discharge branch share a second inverter.
[0015] Optionally, the second logic device has a fourth signal input terminal, a fifth signal input terminal, a second voltage input terminal and a second voltage output terminal; the third signal input terminal of the second logic device of the first discharge branch is coupled to the third signal input terminal of the second logic device of the second discharge branch, and the fifth signal input terminal of the second logic device of the first discharge branch is coupled to the fifth signal input terminal of the second logic device of the second discharge branch; the second voltage input terminal of the second logic device of the first discharge branch is coupled to the reference capacitor branch, and the second voltage input terminal of the second logic device of the second discharge branch is coupled to the capacitor branch to be measured; the second voltage output terminal of the second logic device is used as a ground terminal.
[0016] Optionally, the second inverter has a fifth signal input terminal and a second signal output terminal; the fifth signal input terminal of the second inverter is coupled to the fourth signal input terminal of the second logic device, and the second signal output terminal of the second inverter is coupled to the fifth signal input terminal of the second logic device.
[0017] Optionally, the test circuit further includes: a voltage applying unit, which is coupled to the first charging branch and the second charging branch respectively and is used to provide a power supply voltage to the first charging branch and the second charging branch.
[0018] Optionally, the capacitor branch to be measured includes a MOS tube parasitic junction capacitance branch and a back-end metal connection parasitic capacitance branch coupled to the MOS tube parasitic junction capacitance branch; the reference capacitor branch includes a back-end metal connection parasitic capacitance branch, and the back-end metal connection parasitic capacitance branch in the reference capacitor branch is the same as the back-end metal connection parasitic capacitance branch in the capacitor branch to be measured.
[0019] Optionally, the capacitor branch to be tested is provided by the device to be tested, and the reference capacitor branch is provided by the reference device. The device to be tested and the reference device both include a gate, a drain and a source, and the drain and source of the device to be tested are respectively electrically connected to the back-end metal connection, and the source and drain of the reference device are electrically isolated from the back-end metal connection.
[0020] Correspondingly, an embodiment of the present invention also provides a testing method, including: providing a test circuit provided by an embodiment of the present invention; applying a power supply voltage to the test circuit; outputting a charging signal to the reference circuit unit and the circuit unit to be tested through the control unit; obtaining a first charging current value of the reference circuit unit within a signal cycle; obtaining a second charging current value of the circuit unit to be tested within a signal cycle; and obtaining a parasitic capacitance value of the capacitor branch to be tested based on the first charging current value and the second charging current value.
[0021] Optionally, the parasitic capacitance value of the capacitor branch to be measured is obtained according to the first charging current value and the second charging current value. Wherein, Idut represents the second charging current value, Iref represents the first charging current value, Vdd represents the power supply voltage applied to the test circuit, and f represents the frequency of the charging signal.
[0022] Optionally, the reference circuit unit also includes a first discharge branch coupled to the first charging branch and the reference capacitor branch, and the first discharge branch is suitable for responding to a discharge signal; the circuit unit to be tested also includes a second discharge branch coupled to the second charging branch and the capacitor branch to be tested, and the second discharge branch is suitable for responding to a discharge signal; after the control unit outputs a charging signal to the reference circuit unit and the circuit unit to be tested, it also includes: outputting a discharge signal to the reference circuit unit and the circuit unit to be tested, and the frequency of the discharge signal is the same as that of the charging signal.
[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0024] In a test circuit provided by an embodiment of the present invention, a reference circuit unit comprises a first charging branch and a reference capacitor branch coupled to the first charging branch, the reference circuit unit is adapted to respond to a charging signal and obtain a first charging current value through the first charging branch, a circuit unit to be tested comprises a second charging branch and a capacitor branch to be tested coupled to the second charging branch, the circuit unit to be tested is adapted to respond to a charging signal and obtain a second charging current value through the second charging branch, the first charging branch and the second charging branch both comprise a first logic device, the first logic device comprises a PMOS transistor and an NMOS transistor connected in parallel with each other, a control unit is adapted to output the charging signal, and the The first charging branch and the second charging branch both include a first logic device, and the first logic device includes a PMOS transistor and an NMOS transistor connected in parallel with each other. In the process of the control unit outputting a charging signal, the first logic devices in the first charging branch and the second charging branch will be in an on or off state, and at the moment when the first logic device is in the on or off state, the first logic device has the function of reducing the probability of channel charge flowing into or out of the channel region, thereby reducing the charge injection effect. Accordingly, in the process of obtaining the parasitic capacitance of the capacitance branch to be measured through the first charging current value and the second charging current value, the parasitic capacitance value can be accurately obtained, thereby improving the accuracy of obtaining the parasitic capacitance value. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a circuit diagram of an embodiment of a test circuit of the present invention;
[0026] Figure 2is a top view of the structure of the reference device and the device under test of the present invention;
[0027] Figure 3 It is a flow chart of the steps of an embodiment of the testing method of the present invention. DETAILED DESCRIPTION
[0028] As the characteristic size of MOS tubes continues to decrease, the order of magnitude of parasitic junction capacitance is also decreasing. Limited by the accuracy of the AC method, the error of the measured capacitance value is getting larger and larger. At the same time, the miniaturization of device size has made the metal connection spacing smaller and smaller, and the parasitic capacitance caused by this has an increasingly greater impact on the test results.
[0029] In order to solve the above technical problems, an embodiment of the present invention provides a test circuit, including: a reference circuit unit, including a first charging branch and a reference capacitor branch coupled to the first charging branch, the reference circuit unit is suitable for responding to a charging signal and obtaining a first charging current value through the first charging branch; a circuit unit to be tested, including a second charging branch and a capacitor branch to be tested coupled to the second charging branch, the circuit unit to be tested is suitable for responding to the charging signal and obtaining a second charging current value through the second charging branch, the first charging branch and the second charging branch both include a first logic device, the first logic device includes a PMOS transistor and an NMOS transistor connected in parallel with each other; a control unit, suitable for outputting the charging signal.
[0030] In the test circuit provided by the embodiment of the present invention, the first charging branch and the second charging branch both include a first logic device, and the first logic device includes a PMOS transistor and an NMOS transistor connected in parallel with each other. In the process of the control unit outputting a charging signal, the first logic devices in the first charging branch and the second charging branch will be in an on or off state, and at the moment when the first logic device is in the on or off state, the first logic device has the function of reducing the probability of channel charge flowing into or out of the channel region, thereby reducing the charge injection effect. Accordingly, in the process of obtaining the parasitic capacitance of the capacitance branch to be measured through the first charging current value and the second charging current value, the parasitic capacitance value can be accurately obtained, thereby improving the accuracy of obtaining the parasitic capacitance value.
[0031] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0032] Figure 1 is a circuit diagram of an embodiment of a test circuit of the present invention; Figure 2 It is a top view of the structure of the reference device and the device to be tested of the present invention.
[0033] The test circuit includes: a reference circuit unit 100, including a first charging branch 102 and a reference capacitor branch 106 coupled to the first charging branch 102, the reference circuit unit 100 is suitable for responding to a charging signal and obtaining a first charging current value through the first charging branch 102; a circuit unit to be tested 101, including a second charging branch 108 and a capacitor branch to be tested 116 coupled to the second charging branch 108, the circuit unit to be tested 101 is suitable for responding to a charging signal and obtaining a second charging current value through the second charging branch 108, the first charging branch 102 and the second charging branch 108 both include a first logic device 130, the first logic device 130 includes a PMOS transistor and an NMOS transistor connected in parallel with each other; a control unit, suitable for outputting the charging signal.
[0034] It should be noted that the first logic device 130 includes a PMOS transistor and an NMOS transistor connected in parallel with each other. When the control unit outputs a charging signal, the first logic device 130 in the first charging branch 102 and the second charging branch 108 will be in an on or off state, and at the moment when the first logic device 130 is in the on or off state, the first logic device 130 has the function of reducing the probability of channel charge flowing into or out of the channel region, thereby reducing the charge injection effect. Accordingly, in the process of obtaining the parasitic capacitance of the capacitor branch 116 to be measured through the first charging current value and the second charging current value, the parasitic capacitance value can be accurately obtained, thereby improving the accuracy of obtaining the parasitic capacitance value.
[0035] Specifically, the reference circuit unit 100 is used to obtain the charging current of the reference device 170 .
[0036] In this embodiment, the reference circuit unit 100 includes a first charging branch 102 and a reference capacitor branch 106 coupled thereto. The first charging branch 102 is used to charge the reference capacitor branch 106 .
[0037] Specifically, as an example, the reference capacitor branch 106 includes a back-end metal wiring parasitic capacitor branch.
[0038] It should be noted that the back-end metal connection parasitic capacitance branch refers to the back-end metal connection 165 in the reference device 170 being electrically connected to other circuit structures in the reference device 170, and the parasitic capacitance generated between the back-end metal connection 165 and other circuit structures.
[0039] It should be noted that the parasitic capacitance generated between the back-end metal connection 165 and other circuit structures is only the back-end metal connection parasitic capacitance.
[0040] In this embodiment, the reference capacitor branch 106 is provided by a reference device 170 , and the reference device 170 includes a gate 163 , a drain 162 , and a source 161 , and the source 161 and the drain 162 of the reference device 170 are both electrically isolated from the back-end metal connection 165 .
[0041] It should be noted that a PN junction is formed between the source 161 and the drain 162 and the substrate in the MOS transistor, that is, there is a parasitic junction capacitance in the MOS transistor. When an operating voltage is applied to the source 161 and the drain 162, the parasitic capacitance will be charged or discharged. Therefore, by electrically isolating the source 161 and the drain 162 of the reference device 170 from the rear metal connection 165, the parasitic capacitance in the MOS transistor is not in a charging or discharging state. Correspondingly, this means that the total capacitance in the reference capacitor branch 106 does not include the parasitic junction capacitance, but only includes the subsequent metal connection parasitic capacitance.
[0042] It should also be noted that the source 161 and the drain 162 of the reference device 170 are electrically isolated from the back-end metal connection 165, and the gate 163 of the reference device 170 is electrically connected to the back-end metal connection 165, thereby providing the reference device 170 with a gate 163 turn-on voltage.
[0043] As an example, the first charging branch 102 includes a first logic device 130 , and the first logic device 130 includes a PMOS transistor and an NMOS transistor connected in parallel.
[0044] The PMOS transistor and the NMOS transistor connected in parallel can neutralize holes and electrons, so that the first logic device 130 has a lower probability of channel charges flowing into or out of the channel region, thereby reducing the charge injection effect.
[0045] In this embodiment, the first logic device 130 has a first signal input terminal a, a second signal input terminal b, a first voltage input terminal c and a first voltage output terminal d.
[0046] It should be noted that the first signal input terminal a and the second signal input terminal b are used as input terminals of the clock signal output by the control unit. The clock signal is used to control the conduction and cutoff of the PMOS transistor in the first logic device 130 through the first signal input terminal a, and the second signal input terminal b is used to control the conduction and cutoff of the NMOS transistor in the first logic device 130.
[0047] The first voltage input terminal c is used as an input terminal for providing a power supply voltage to the first logic device 130 , and the power supply voltage is also a start-up voltage of the first logic device 130 . The first voltage output terminal d is used as an output terminal of the power supply voltage output from the first logic device 130 .
[0048] As an example, the first signal input terminal a of the first logic device 130 of the first charging branch 102 is coupled to the first signal input terminal a of the first logic device 130 of the second charging branch 108, and the second signal input terminal b of the first logic device 130 of the first charging branch 102 is coupled to the second signal input terminal b of the first logic device 130 of the second charging branch 108.
[0049] In this embodiment, the first voltage output terminal d of the first logic device 130 of the first charging branch 102 is coupled to the reference capacitor branch 106 , and the first voltage output terminal d of the first logic device 130 of the second charging branch 108 is coupled to the measured capacitor branch 116 .
[0050] Specifically, the first voltage output terminal d of the first logic device 130 of the first charging branch 102 is coupled to the reference capacitor branch 106. When the input clock signal causes the first logic device 130 of the first charging branch 102 to be in an on state, the subsequent metal connection parasitic capacitance in the reference capacitor branch 106 can be charged through the first charging branch 102; the first voltage output terminal d of the first logic device 130 of the second charging branch 108 is coupled to the capacitor branch 116 to be tested. When the input clock signal causes the first logic device 130 of the second charging branch 108 to be in an on state, the subsequent metal connection parasitic capacitance in the reference capacitor branch 106 can be charged through the second charging branch 108.
[0051] As an example, the first charging branch 102 further includes a first inverter coupled to the first logic device 130 .
[0052] Specifically, the first inverter has the function of inverting the phase of the input signal by 180 degrees. In this embodiment, the first inverter is coupled to the first logic device 130. When the clock signal output by the control unit is at a low level, the PMOS transistor in the first logic device 130 is turned on. At the same time, the first inverter can change the clock signal output by the control unit from a low level to a high level, so that the NMOS transistor in the first logic device 130 is also turned on, so that the first logic device 130 can start charging the reference capacitor branch 106; when the clock signal output by the control unit is at a high level, the PMOS transistor in the first logic device 130 is turned off. At the same time, the first inverter can change the clock signal output by the control unit from a high level to a low level, so that the NMOS transistor in the first logic device 130 is also turned off, so that the first logic device 130 is turned off.
[0053] In this embodiment, the first inverter has a third signal input terminal e and a first signal output terminal f. The third signal input terminal e is used as the input terminal of the clock signal output by the control unit, and the first signal output terminal f is used as the output terminal of the clock signal after the phase of the input clock signal is reversed by 180 degrees.
[0054] As an example, the third signal input terminal e of the first inverter is coupled to the first signal input terminal a of the first logic device 130 , and the first signal output terminal f of the first inverter is coupled to the second signal input terminal b of the first logic device 130 .
[0055] Specifically, when the clock signal output by the control unit is at a low level, the clock signal is input through the first signal input terminal a of the first logic device 130, so that the PMOS transistor in the first logic device 130 is turned on. At the same time, the clock signal is also input through the third signal input terminal e of the first inverter. The first inverter converts the clock signal from a low level to a high level, and outputs the high-level clock signal through the first signal output terminal f of the first inverter. Since the first signal output terminal f of the first inverter is coupled to the second signal input terminal b of the first logic device 130, the NMOS transistor in the first logic device 130 can be changed from a cut-off state to a conductive state, thereby putting the first logic device 130 in an on state.
[0056] In this embodiment, the first charging branch 102 further includes an ammeter coupled to the first voltage input terminal c of the first logic device 130 , and the ammeter is used to obtain a first charging current value.
[0057] It should be noted that the first charging current here is the charging current of the subsequent metal connection parasitic capacitance.
[0058] In this embodiment, the reference circuit unit 100 further includes a first discharge branch 105 coupled to the first charging branch 102 and the reference capacitor branch 106 , and the first discharge branch 105 is adapted to respond to a discharge signal.
[0059] Specifically, the first discharge branch 105 is used to discharge the capacitor voltage in the reference capacitor branch 106 .
[0060] It should be noted that the first discharge branch 105 is adapted to respond to the discharge signal so as to turn on the first logic device 130 in the first discharge branch 105 , thereby achieving the effect of releasing the capacitor voltage in the reference capacitor branch 106 .
[0061] In this embodiment, the first discharge branch 105 includes a second logic device 130, and the second logic device 130 includes a PMOS transistor and an NMOS transistor connected in parallel.
[0062] Specifically, the PMOS transistor and the NMOS transistor connected in parallel can neutralize the holes and the electrons, so that the capacitor voltage in the reference capacitor branch 106 can be fully released.
[0063] In other embodiments, the second logic device 130 may also be a PMOS transistor.
[0064] In some other embodiments, the second logic device 130 may also be an NMOS transistor.
[0065] In this embodiment, the second logic device 130 has a fourth signal input terminal A, a fifth signal input terminal B, a second voltage input terminal C and a second voltage output terminal D.
[0066] It should be noted that the fourth signal input terminal A is used as the input terminal of the clock signal output by the control unit. The clock signal is used through the fourth signal input terminal A to control the conduction and cutoff of the PMOS transistor in the second logic device 130 and the conduction and cutoff of the NMOS transistor.
[0067] The fifth signal input terminal B is used to output a clock signal.
[0068] The second voltage input terminal C is used as an input terminal for providing a power supply voltage to the second logic device 130 , and the power supply voltage is also a start-up voltage of the second logic device 130 . The second voltage output terminal D is used as an output terminal of the power supply voltage output from the second logic device 130 .
[0069] As an example, the second voltage input terminal C of the second logic device 130 of the first discharge branch 105 is coupled to the reference capacitor branch 106 .
[0070] In this embodiment, the first discharge branch 105 further includes a second inverter coupled to the second logic device 130 .
[0071] In this embodiment, the second voltage output terminal D of the second logic device 130 is used as a ground terminal.
[0072] Specifically, the second inverter has the function of inverting the phase of the input signal by 180 degrees. In this embodiment, the second inverter is coupled to the second logic device 130. When the clock signal output by the control unit is at a high level, the NMOS transistor in the second logic device 130 is turned on. At the same time, the second inverter can change the clock signal output by the control unit from a high level to a low level, so that the PMOS transistor in the second logic device 130 is also turned on, so that the second logic device 130 can start discharging the reference capacitor branch 106; when the clock signal output by the control unit is at a low level, the NMOS transistor in the second logic device 130 is turned off. At the same time, the second inverter can change the clock signal output by the control unit from a high level to a low level, so that the PMOS transistor in the second logic device 130 is also turned off, so that the second logic device 130 is turned off.
[0073] In this embodiment, the second inverter has a fifth signal input terminal E and a first signal output terminal f. The fifth signal input terminal E is used as the input terminal of the clock signal output by the control unit, and the first signal output terminal f is used as the output terminal of the clock signal after the phase of the input clock signal is reversed by 180 degrees.
[0074] As an example, the fifth signal input terminal E of the second inverter is coupled to the fourth signal input terminal A of the second logic device 130 , and the first signal output terminal f of the second inverter is coupled to the fifth signal input terminal B of the second logic device 130 .
[0075] Specifically, when the clock signal output by the control unit is at a high level, the clock signal is input through the fourth signal input terminal A of the second logic device 130, so that the NMOS transistor in the second logic device 130 is turned on. At the same time, the clock signal is also input through the fifth signal input terminal E of the second inverter. The second inverter converts the clock signal from a high level to a low level, and outputs the low-level clock signal through the first signal output terminal f of the second inverter. Since the first signal output terminal f of the second inverter is coupled to the fifth signal output terminal B of the second logic device 130, the PMOS transistor in the second logic device 130 can be changed from a cut-off state to a conductive state, thereby putting the second logic device 130 in an on state.
[0076] Specifically, the circuit unit under test 101 is used to obtain the charging current of the device under test 160 .
[0077] In this embodiment, the circuit unit to be tested 101 includes a second charging branch 108 and a capacitor branch to be tested 116 coupled thereto. The second charging branch 108 is used to charge the capacitor branch to be tested 116 .
[0078] Specifically, as an example, the capacitance branch 116 to be measured includes a MOS tube parasitic junction capacitance branch and a back-end metal connection parasitic capacitance branch coupled to the MOS tube parasitic junction capacitance branch.
[0079] The parasitic junction capacitance branch refers to the parasitic junction capacitance generated by the electrical connection between the rear-end metal connection 165 in the device under test 160 and the source 161 and the drain 162 in the device under test 160, and between the subsequent metal connection and the source 161 and the drain 162; the rear-end metal connection parasitic capacitance branch refers to the parasitic capacitance generated by the electrical connection between the rear-end metal connection 165 in the device under test 160 and other circuit structures in the device under test 160, and between the subsequent metal connection and the other circuit structures.
[0080] It should also be noted that the back-end metal connection parasitic capacitance branch in the reference capacitor branch 106 is the same as the back-end metal connection parasitic capacitance branch in the capacitor branch 116 to be tested, thereby facilitating the subsequent calculation of the parasitic junction capacitance in the device under test 160 through the test circuit.
[0081] In this embodiment, the capacitor branch 116 is provided by a device under test 160 , which includes a gate 163 , a drain 162 and a source 161 , and the drain 162 and the source 161 of the device under test 160 are electrically connected to the back-end metal connection 165 , respectively.
[0082] It should be noted that a PN junction is formed between the source 161 and the drain 162 and the substrate in the MOS transistor, that is, there is a parasitic junction capacitance in the MOS transistor. When an operating voltage is applied to the source 161 and the drain 162, the parasitic capacitance will be charged or discharged. Therefore, by electrically connecting the source 161 and the drain 162 of the device under test 160 to the back-end metal connection 165, the parasitic capacitance in the MOS transistor is in a charging or discharging state. Correspondingly, it means that the total capacitance in the capacitor branch 116 to be tested includes the parasitic junction capacitance and the subsequent metal connection parasitic capacitance.
[0083] It should also be noted that the gate 163 of the device under test 160 is electrically connected to the back-end metal connection 165 , thereby providing a gate 163 turn-on voltage for the reference device 170 .
[0084] As an example, the second charging branch 108 includes a first logic device 130 , and the first logic device 130 includes a PMOS transistor and an NMOS transistor connected in parallel.
[0085] The PMOS transistor and the NMOS transistor connected in parallel can neutralize holes and electrons, so that the first logic device 130 has a lower probability of channel charges flowing into or out of the channel region, thereby reducing the charge injection effect.
[0086] As an example, the second charging branch 108 further includes a first inverter coupled to the first logic device 130 , and the first charging branch 102 and the second charging branch 108 share a first inverter.
[0087] Specifically, the first inverter has the function of inverting the phase of the input signal by 180 degrees. In this embodiment, the first inverter is coupled to the first logic device 130. When the clock signal output by the control unit is at a low level, the PMOS transistor in the first logic device 130 is turned on. At the same time, the first inverter can change the clock signal output by the control unit from a low level to a high level, so that the NMOS transistor in the first logic device 130 is also turned on, so that the first logic device 130 can start charging the reference capacitor branch 106; when the clock signal output by the control unit is at a high level, the PMOS transistor in the first logic device 130 is turned off. At the same time, the first inverter can change the clock signal output by the control unit from a high level to a low level, so that the NMOS transistor in the first logic device 130 is also turned off, so that the first logic device 130 is turned off.
[0088] It should be noted that the first charging branch 102 and the second charging branch 108 share a first inverter, which is beneficial to reduce the area occupied by the test circuit.
[0089] In this embodiment, the second charging branch 108 further includes an ammeter coupled to the first voltage input terminal c of the first logic device 130 , and the ammeter is used to obtain the second charging current value.
[0090] It should be noted that the second charging current here is the charging current of the parasitic junction capacitance and the subsequent metal connection parasitic capacitance.
[0091] In this embodiment, the circuit unit to be tested 101 further includes a second discharge branch 110 coupled to the second charging branch 108 and the capacitor branch to be tested 116 , and the second discharge branch 110 is adapted to respond to a discharge signal.
[0092] Specifically, the second discharge branch 110 is used to discharge the capacitor voltage in the capacitor branch 116 to be measured.
[0093] It should be noted that the second discharge branch 110 is adapted to respond to the discharge signal to turn on the first logic device 130 in the second discharge branch 110 , thereby achieving the effect of releasing the capacitor voltage in the capacitor branch 116 to be tested.
[0094] In this embodiment, the second discharge branch 110 includes a second logic device 130, and the second logic device 130 includes a PMOS transistor and an NMOS transistor connected in parallel.
[0095] Specifically, the PMOS transistor and the NMOS transistor connected in parallel can neutralize the holes and the electrons, so that the capacitor voltage in the capacitor branch 116 to be measured can be fully released.
[0096] In other embodiments, the second logic device 130 may also be a PMOS transistor.
[0097] In some other embodiments, the second logic device 130 may also be an NMOS transistor.
[0098] As an example, the second voltage input terminal C of the second logic device 130 of the second discharge branch 110 is coupled to the measured capacitance branch 116 .
[0099] In this embodiment, the second discharge branch 110 further includes a second inverter coupled to the second logic device 130 , and the first discharge branch 105 and the second discharge branch 110 share a second inverter, which helps to reduce the area occupied by the test circuit.
[0100] As an example, the fourth signal input terminal A of the second logic device 130 of the first discharge branch 105 is coupled to the fourth signal input terminal A of the second logic device 130 of the second discharge branch 110, and the fifth signal input terminal B of the second logic device 130 of the first discharge branch 105 is coupled to the fifth signal input terminal B of the second logic device 130 of the second discharge branch 110.
[0101] The control unit is used to output a charging signal to control the on and off of the first logic device 130 , so that the first charging branch 102 can charge the reference capacitor branch 106 , and the second charging branch 108 can charge the capacitor branch 116 to be tested.
[0102] As an example, the charging signal output terminal of the control unit is coupled to the first signal input terminal a of the first logic device 130 , so that the charging signal output by the control unit can enter the first logic device 130 to control the conduction and cutoff of the first logic device 130 .
[0103] In this embodiment, the control unit is further adapted to output the discharge signal, and the discharge signal has the same frequency as the charge signal.
[0104] The control unit outputs a discharge signal to control the on and off of the first logic device 130 , so that the first discharge branch 105 can discharge the reference capacitor branch 106 , and the second discharge branch 110 can discharge the capacitor branch 116 to be tested.
[0105] When the charging signal and the discharging signal of the control unit are at a low level, the first logic device 130 in the first charging branch 102 and the second charging branch 108 is turned on, and the first discharging branch 105 and the second discharging branch 110 are turned off. At this time, the reference capacitor branch 106 and the capacitor to be measured 116 are charged. When the charging signal and the discharging signal of the control unit are at a high level, the first logic device 130 in the first charging branch 102 and the second charging branch 108 is turned off, and the first discharging branch 105 and the second discharging branch 110 are turned on. At this time, the reference capacitor branch 106 and the capacitor to be measured 116 are discharged. The discharge signal has the same frequency as the charging signal, which ensures that the charging branch and the discharging branch will not be turned on at the same time.
[0106] In this embodiment, the test circuit further includes: a voltage applying unit (not shown), which is coupled to the first charging branch 102 and the second charging branch 108 respectively and is used to provide a power supply voltage Vdd to the first charging branch 102 and the second charging branch 108 .
[0107] Specifically, the voltage applying unit is used to be coupled to the first voltage input terminal c of the first logic device 130 .
[0108] The power supply voltage Vdd is a constant voltage, and the constant voltage value is greater than or equal to a turn-on voltage value of the first logic device 130 .
[0109] Accordingly, the embodiment of the present invention also provides a testing method. To make the above-mentioned purpose, features and advantages of the embodiment of the present invention more obvious and easy to understand, the following is combined with Figures 1 to 3 The specific embodiments of the present invention are described in detail. Figure 3 It is a flow chart of the steps of an embodiment of the testing method of the present invention.
[0110] refer to Figure 3 , execute step S1: provide a test circuit provided by an embodiment of the present invention.
[0111] For a detailed description of the test circuit provided in the embodiment of the present invention, please refer to the above description, which will not be repeated here.
[0112] In this embodiment, the reference circuit unit also includes a first discharge branch coupled to the first charging branch and the reference capacitor branch, and the first discharge branch is suitable for responding to a discharge signal; the circuit unit to be tested also includes a second discharge branch coupled to the second charging branch and the capacitor branch to be tested, and the second discharge branch is suitable for responding to a discharge signal.
[0113] The first discharge branch is adapted to respond to the discharge signal so as to release the capacitor voltage in the reference capacitor branch, and the second discharge branch is adapted to respond to the discharge signal so as to release the capacitor voltage in the capacitor branch to be measured.
[0114] refer to Figure 3 , execute step S2: apply a power supply voltage to the test circuit.
[0115] Specifically, by applying a power supply voltage to the first charging branch and the second charging branch, the first charging branch can charge the reference capacitor branch, the second charging branch can charge the capacitor branch to be measured, and the first charging current value and the second charging current value are obtained, and the parasitic capacitance of the capacitor branch to be measured is obtained based on the obtained first charging current value and the second charging current value.
[0116] It should be noted that the power supply voltage is a constant voltage, and the constant voltage value is greater than or equal to the turn-on voltage value of the first logic device.
[0117] refer to Figure 3 , executing step S3: outputting a charging signal to the reference circuit unit and the circuit unit to be tested through the control unit.
[0118] Specifically, the control unit outputs a charging signal to the reference circuit unit and the circuit unit to be tested, and the first logic device in the first charging branch and the second charging branch will be in an on or off state, and at the moment when the first logic device is in the on or off state, the first logic device has the effect of reducing the probability of channel charge flowing into or out of the channel region, thereby reducing the charge injection effect, and accordingly, in the subsequent process of obtaining the parasitic capacitance of the capacitor branch to be tested through the first charging current value and the second charging current value, the parasitic capacitance value can be accurately obtained, thereby improving the accuracy of obtaining the parasitic capacitance value.
[0119] It should be noted that after the control unit outputs a charging signal to the reference circuit unit and the circuit unit to be tested, the method further includes: outputting a discharging signal to the reference circuit unit and the circuit unit to be tested, and the frequency of the discharging signal is the same as that of the charging signal.
[0120] When the charging signal and the discharging signal of the control unit are at a low level, the first logic device 130 in the first charging branch 102 and the second charging branch 108 is turned on, and the first discharging branch 105 and the second discharging branch 110 are turned off. At this time, the reference capacitor branch 106 and the capacitor to be measured 116 are charged. When the charging signal and the discharging signal of the control unit are at a high level, the first logic device 130 in the first charging branch 102 and the second charging branch 108 is turned off, and the first discharging branch 105 and the second discharging branch 110 are turned on. At this time, the reference capacitor branch 106 and the capacitor to be measured 116 are discharged. The discharge signal has the same frequency as the charging signal, which ensures that the charging branch and the discharging branch will not be turned on at the same time.
[0121] refer to Figure 3, execute step S4: obtain a first charging current value of the reference circuit unit within a signal cycle.
[0122] It should be noted that a PN junction is formed between the source and drain and the substrate in a MOS transistor, that is, there is a parasitic junction capacitance in the MOS transistor. When an operating voltage is applied to the source and drain, the parasitic capacitance will be charged or discharged. Therefore, by electrically isolating the source and drain of the reference device from the back-end metal connection, the parasitic capacitance in the MOS transistor is not in a charging or discharging state. Correspondingly, this means that the total capacitance in the reference capacitor branch does not include the parasitic junction capacitance, but only includes the subsequent metal connection parasitic capacitance.
[0123] It should also be noted that the first charging current here is the charging current of the subsequent metal connection parasitic capacitance.
[0124] refer to Figure 3 , execute step S5: obtain a second charging current value of the circuit unit to be tested within a signal cycle.
[0125] It should be noted that a PN junction is formed between the source and drain and the substrate in a MOS transistor, that is, there is a parasitic junction capacitance in the MOS transistor. When an operating voltage is applied to the source and drain, the parasitic capacitance will be charged or discharged. Therefore, by electrically connecting the source and drain of the device to be tested to the back-end metal connection, the parasitic capacitance in the MOS transistor is in a charging or discharging state. Correspondingly, it means that the total capacitance in the capacitor branch to be tested includes the parasitic junction capacitance and the subsequent metal connection parasitic capacitance.
[0126] It should also be noted that the second charging current here is the charging current of the parasitic junction capacitance and the subsequent metal connection parasitic capacitance.
[0127] refer to Figure 3 , execute step S6: obtain the parasitic capacitance value of the capacitor branch to be measured according to the first charging current value and the second charging current value.
[0128] Specifically, the first logic device includes a PMOS transistor and an NMOS transistor connected in parallel with each other. During the process of the control unit outputting a charging signal, the first logic device in the first charging branch and the second charging branch will be in an on or off state, and at the moment when the first logic device is in the on or off state, the first logic device has the function of reducing the probability of channel charge flowing into or out of the channel region, thereby reducing the charge injection effect. Accordingly, in the process of obtaining the parasitic capacitance of the capacitor branch to be measured through the first charging current value and the second charging current value, the parasitic capacitance value can be accurately obtained, thereby improving the accuracy of obtaining the parasitic capacitance value.
[0129] In this embodiment, the parasitic capacitance value of the capacitor branch to be measured is obtained according to the first charging current value and the second charging current value. Among them, I dut Represents the second charging current value, I ref represents the first charging current value, Vdd represents the power supply voltage applied to the test circuit, and f represents the frequency of the charging signal.
[0130] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A test circuit, characterized in that: include: a reference circuit unit, comprising a first charging branch and a reference capacitor branch coupled to the first charging branch, wherein the reference circuit unit is adapted to respond to a charging signal and obtain a first charging current value through the first charging branch; a circuit unit to be tested, comprising a second charging branch and a capacitance branch to be tested coupled to the second charging branch, the circuit unit to be tested being adapted to respond to a charging signal and obtain a second charging current value through the second charging branch, the first charging branch and the second charging branch both comprising a first logic device, the first logic device comprising a PMOS transistor and an NMOS transistor connected in parallel with each other; The control unit is adapted to output the charging signal.
2. The test circuit according to claim 1, characterized in that: The first charging branch and the second charging branch each include a first inverter coupled to the first logic device, and the first charging branch and the second charging branch share a first inverter.
3. The test circuit according to claim 1, characterized in that: The first logic device has a first signal input terminal, a second signal input terminal, a first voltage input terminal and a first voltage output terminal; The first signal input terminal of the first logic device of the first charging branch is coupled to the first signal input terminal of the first logic device of the second charging branch, and the second signal input terminal of the first logic device of the first charging branch is coupled to the second signal input terminal of the first logic device of the second charging branch; The first voltage output terminal of the first logic device of the first charging branch is coupled to the reference capacitor branch, and the first voltage output terminal of the first logic device of the second charging branch is coupled to the capacitor branch to be measured.
4. The test circuit according to claim 3, characterized in that: The first inverter has a third signal input terminal and a first signal output terminal; The third signal input terminal of the first inverter is coupled to the first signal input terminal of the first logic device, and the first signal output terminal of the first inverter is coupled to the second signal input terminal of the first logic device.
5. The test circuit according to claim 3, characterized in that: The first charging branch and the second charging branch further include an ammeter coupled to the first voltage input terminal of the first logic device, and the ammeter is used to obtain the first charging current value and the second charging current value.
6. The test circuit according to claim 3, characterized in that: The charging signal output terminal of the control unit is coupled to the first signal input terminal of the first logic device.
7. The test circuit according to claim 1, characterized in that: The reference circuit unit further comprises a first discharge branch coupled to the first charging branch and the reference capacitor branch, wherein the first discharge branch is adapted to respond to a discharge signal; The circuit unit to be tested further comprises a second discharge branch coupled to the second charging branch and the capacitance branch to be tested, wherein the second discharge branch is adapted to respond to a discharge signal; The control unit is further adapted to output the discharge signal, and the discharge signal has the same frequency as the charge signal.
8. The test circuit according to claim 7, characterized in that: The first discharge branch and the second discharge branch both include a second logic device, and the second logic device includes a PMOS transistor and an NMOS transistor connected in parallel with each other; Alternatively, the second logic device is a PMOS transistor; Alternatively, the second logic device is an NMOS transistor.
9. The test circuit according to claim 8, characterized in that: The first discharge branch and the second discharge branch each further include a second inverter coupled to the second logic device, and the first discharge branch and the second discharge branch share a second inverter.
10. The test circuit according to claim 8, characterized in that: The second logic device has a fourth signal input terminal, a fifth signal input terminal, a second voltage input terminal, and a second voltage output terminal; The third signal input terminal of the second logic device of the first discharge branch is coupled to the third signal input terminal of the second logic device of the second discharge branch, and the fifth signal input terminal of the second logic device of the first discharge branch is coupled to the fifth signal input terminal of the second logic device of the second discharge branch; The second voltage input terminal of the second logic device of the first discharge branch is coupled to the reference capacitor branch, and the second voltage input terminal of the second logic device of the second discharge branch is coupled to the capacitor branch to be measured; The second voltage output terminal of the second logic device is used as a ground terminal.
11. The test circuit according to claim 10, characterized in that: The second inverter has a fifth signal input terminal and a second signal output terminal; The fifth signal input terminal of the second inverter is coupled to the fourth signal input terminal of the second logic device, and the second signal output terminal of the second inverter is coupled to the fifth signal input terminal of the second logic device.
12. The test circuit according to claim 1, characterized in that: The test circuit further includes: a voltage applying unit, which is coupled to the first charging branch and the second charging branch respectively and is used to provide a power supply voltage to the first charging branch and the second charging branch.
13. The test circuit according to claim 1, characterized in that: The capacitance branch to be measured includes a MOS tube parasitic junction capacitance branch and a rear-stage metal connection parasitic capacitance branch coupled to the MOS tube parasitic junction capacitance branch; The reference capacitor branch includes a rear metal connection parasitic capacitor branch, and the rear metal connection parasitic capacitor branch in the reference capacitor branch is the same as the rear metal connection parasitic capacitor branch in the capacitor branch to be measured.
14. The test circuit according to claim 13, characterized in that: The capacitor branch to be tested is provided by the device to be tested, and the reference capacitor branch is provided by the reference device. The device to be tested and the reference device both include a gate, a drain and a source. The drain and source of the device to be tested are electrically connected to the back-end metal wiring, respectively, and the source and drain of the reference device are electrically isolated from the back-end metal wiring.
15. A testing method, characterized in that: include: Providing a test circuit as claimed in any one of claims 1 to 14; applying a power supply voltage to the test circuit; Outputting a charging signal to the reference circuit unit and the circuit unit to be tested by the control unit; Acquire a first charging current value of the reference circuit unit within a signal cycle; Acquire a second charging current value of the circuit unit to be tested within a signal cycle; The parasitic capacitance value of the capacitor branch to be measured is obtained according to the first charging current value and the second charging current value.
16. The testing method according to claim 15, characterized in that: Obtaining the parasitic capacitance value of the capacitor branch to be measured according to the first charging current value and the second charging current value Wherein, Idut represents the second charging current value, Iref represents the first charging current value, Vdd represents the power supply voltage applied to the test circuit, and f represents the frequency of the charging signal.
17. The testing method according to claim 15, characterized in that: The reference circuit unit further comprises a first discharge branch coupled to the first charging branch and the reference capacitor branch, wherein the first discharge branch is adapted to respond to a discharge signal; The circuit unit to be tested further comprises a second discharge branch coupled to the second charging branch and the capacitance branch to be tested, wherein the second discharge branch is adapted to respond to a discharge signal; After the control unit outputs a charging signal to the reference circuit unit and the circuit unit to be tested, the method further includes: outputting a discharging signal to the reference circuit unit and the circuit unit to be tested, and the frequency of the discharging signal is the same as that of the charging signal.