Method for controlling thickness uniformity of large-area surface silicon oxide

Abstract

The invention provides a method for controlling the thickness uniformity of large-area surface silicon oxide, which comprises the following steps of: etching a waveguide substrate to form a metal deposition groove, forming a metal electrode in the metal deposition groove, and filling a silicon oxide cladding in the metal deposition groove so as to cover the metal electrode through the silicon oxide cladding; forming a first photoresist layer on a concave-convex surface jointly formed by the surface of the waveguide substrate and the surface of the silicon oxide cladding, and performing patterning processing on the first photoresist layer to enable the patterned first photoresist layer to form a protection structure above a gap between the metal electrode and the groove wall of the metal deposition groove; patterning the concave-convex surface through etching by taking the protection structure as a mask so as to carry out first-time planarization treatment on the concave-convex surface; and removing the protection structure, and carrying out second-time planarization processing on the concave-convex surface to obtain the processed waveguide device. According to the method, the thickness uniformity of the large-area surface silicon oxide can be accurately controlled, so that the device performance and the product yield are improved.

Description

Technical Field

[0001] The invention relates to the technical field of electro-optic modulators, and in particular to a method for controlling the uniformity of silicon oxide thickness on a large surface area. Background Art

[0002] At present, the development of fields such as autonomous driving, remote interactive applications, and 3D virtual games has led to a rapid increase in the demand for high-bandwidth optical communications. Electro-optic modulators are key components in optical communications, which modulate optical signals through electric current to load information. Lithium niobate materials have been widely used due to their excellent electro-optical effect and high optical transparency. Lithium niobate materials and waveguide substrates can be heterogeneously integrated through bonding and other processes. In order to achieve good modulation performance, the silicon oxide thickness (i.e., spacing) between lithium niobate and the waveguide needs to be precisely controlled to 100nm±10nm. How to control the uniformity of silicon oxide thickness in a large modulation area (mm level) is a key issue.

[0003] In the prior art, after silicon oxide is grown on the waveguide substrate with the metal electrode prepared by slotting, the waveguide substrate is subjected to chemical mechanical polishing (CMP) to flatten the waveguide substrate and reach the required thickness requirement (100±10nm). However, due to the metal structure grown by slotting and the large modulation area (mm level), the silicon oxide surface obtained by chemical mechanical polishing of the waveguide substrate surface has large fluctuations, so the thickness uniformity of silicon oxide in the large modulation area (mm level) cannot be accurately controlled, and the current device design requirements cannot be met. In addition, the subsequent heterogeneous integration yield of lithium niobate material and waveguide substrate will be reduced, affecting device performance. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a method for controlling the uniformity of silicon oxide thickness on a large surface area, so as to achieve precise control of the uniformity of silicon oxide thickness on a large surface area, thereby improving device performance and product yield.

[0005] The embodiment of the present application provides the following technical solution: a method for controlling the uniformity of silicon oxide thickness on a large surface area, comprising:

[0006] Etching a metal deposition groove on a waveguide substrate, forming a metal electrode in the metal deposition groove, and filling the metal deposition groove with a silicon oxide cladding layer so as to cover the metal electrode with the silicon oxide cladding layer;

[0007] forming a first photoresist layer on the concave-convex surface formed by the surface of the waveguide substrate and the surface of the silicon oxide cladding layer, and patterning the first photoresist layer so that the patterned first photoresist layer forms a protective structure above the gap between the metal electrode and the wall of the metal deposition groove;

[0008] Using the protection structure as a mask, the concave-convex surface is patterned by etching to perform a first planarization process on the concave-convex surface;

[0009] The protective structure is removed, and the concave-convex surface is subjected to a second flattening treatment to obtain a processed waveguide device.

[0010] According to an embodiment of the present application, the method further includes: forming a first silicon oxide layer on a silicon substrate, forming a patterned waveguide structure on the first silicon oxide layer, and covering the waveguide structure with a second silicon oxide layer to obtain the waveguide substrate.

[0011] According to an embodiment of the present application, the first silicon oxide layer is prepared by thermal oxidation, and the second silicon oxide layer is prepared by chemical vapor deposition.

[0012] According to an embodiment of the present application, forming a metal electrode in the metal deposition tank includes:

[0013] forming a metal electrode layer to cover the surface of the metal deposition tank and the surface of the waveguide substrate through the metal electrode layer, and forming a patterned second photoresist layer on the metal electrode layer in the metal deposition tank;

[0014] The metal electrode layer is patterned by dry etching using the second photoresist layer as a mask, and then the second photoresist layer is removed to form the metal electrode in the metal deposition tank.

[0015] According to an embodiment of the present application, the outermost width of the protective structure is greater than the width of the gap between the metal electrode and the wall of the metal deposition tank, so that the protective structure completely covers the gap.

[0016] According to an embodiment of the present application, the upper surface of the protection structure is a plane, and the lower surface of the protection structure is adapted to the corresponding position of the concave-convex surface.

[0017] According to an embodiment of the present application, the second planarization process adopts chemical mechanical polishing.

[0018] According to an embodiment of the present application, the metal deposition grooves are located on both sides of the waveguide structure, and the bottoms of the metal deposition grooves extend into the first silicon oxide layer.

[0019] According to an embodiment of the present application, the thickness of the metal electrode does not exceed the groove depth of the metal deposition groove, and the top of the metal electrode is not higher than the top of the waveguide structure.

[0020] According to an embodiment of the present application, the thickness of the metal electrode is 0.8-1 μm, and the groove depth of the metal deposition groove is 1.5-2 μm.

[0021] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of this specification include at least: the embodiments of the present invention form a metal deposition groove by etching on the waveguide substrate, form a metal electrode in the metal deposition groove, and fill the metal deposition groove with a silicon oxide cladding layer to cover the metal electrode with the silicon oxide cladding layer; form a first photoresist layer on the concave-convex surface formed by the surface of the waveguide substrate and the surface of the silicon oxide cladding layer, and perform a patterning process on the first photoresist layer so that the patterned first photoresist layer forms a protective structure above the gap between the metal electrode and the groove wall of the metal deposition groove; use the protective structure as a mask to pattern the concave-convex surface by etching to perform a first flattening process on the concave-convex surface; remove the protective structure, and then perform a second flattening process on the concave-convex surface to obtain a processed waveguide device. By adding a mask etching process, the large height difference of the non-uniform surface is reduced, so that the large-range modulation area reaches a preliminary flat state, and then a chemical mechanical polishing process is performed so that the silicon oxide thickness on the substrate surface meets the device requirements. The embodiment of the present invention adopts a chemical mechanical polishing treatment scheme after mask etching, which can enable a large-area modulation area (mm level) to obtain a flat surface that meets the design requirements (100±10nm), so that the modulation performance of the silicon photonic platform can achieve the best effect, while providing a uniform surface for subsequent processes and improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 1 is a schematic flow chart of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;

[0024] Figure 2 This is a first structural schematic diagram of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;

[0025] Figure 3 2 is a schematic diagram of the second structure of the method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;

[0026] Figure 4It is a third structural schematic diagram of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;

[0027] Figure 5 It is a fourth structural schematic diagram of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;

[0028] Figure 6 It is a fifth structural schematic diagram of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;

[0029] Among them, 10 is a silicon substrate, 11 is a thermal oxide silicon layer, 12 is a silicon nitride waveguide layer, 13 is a chemical vapor deposition silicon oxide layer, 14 is a metal deposition groove, 15 is a metal electrode, and 16 is a protection structure. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0032] like Figure 1 As shown, an embodiment of the present invention provides a method for controlling the uniformity of silicon oxide thickness on a large surface area, comprising:

[0033] 101. Etching a metal deposition groove on a waveguide substrate, forming a metal electrode in the metal deposition groove, and filling the metal deposition groove with a silicon oxide cladding layer so that the metal electrode is covered by the silicon oxide cladding layer;

[0034] 102. Forming a first photoresist layer on the concave-convex surface formed by the surface of the waveguide substrate and the surface of the silicon oxide cladding layer, and patterning the first photoresist layer so that the patterned first photoresist layer forms a protection structure above the gap between the metal electrode and the wall of the metal deposition groove;

[0035] 103. Using the protection structure as a mask, the concave-convex surface is patterned by etching to perform a first planarization process on the concave-convex surface;

[0036] 104. Remove the protective structure, and then perform a second flattening treatment on the concave-convex surface to obtain a processed waveguide device.

[0037] In order to make the large-area modulation area (mm level) obtain a flat surface that meets the design requirements (100±10nm) and to accurately control the uniformity of silicon oxide thickness on the large-area surface, the embodiment of the present invention spin-coats the first photoresist layer on the surface of the waveguide substrate that has not been flattened, and after mask exposure, forms the required protection structure to protect the relatively low trench area between the metal electrode and the metal deposition groove; then etches the concave and convex surface of the unprotected area to reduce the height difference between the steps of the concave and convex surface, and at the same time reduce the amount of subsequent chemical mechanical polishing, so that the surface is initially flat, that is, the first flattening treatment is performed, and finally chemical mechanical polishing is performed after removing the protective structure, that is, the second flattening treatment is performed to obtain a flat surface that meets the design requirements (100±10nm). The embodiment of the present invention reduces the large height difference of the non-uniform surface by adding a mask etching process, so that the large-range modulation area reaches a preliminary flat state, and then chemical mechanical polishing is performed so that the silicon oxide thickness on the substrate surface meets the device requirements. The embodiment of the present invention adopts two planarization processes, namely, chemical mechanical polishing after mask etching, so that a large-area modulation area (mm level) can obtain a flat surface that meets the design requirements (100±10nm), so that the modulation performance of the silicon photonic platform can achieve the best effect, and at the same time provide a uniform surface for subsequent processes, thereby improving product yield.

[0038] In some embodiments of the present invention, the method further includes: forming a first silicon oxide layer on a silicon substrate, forming a patterned waveguide structure on the first silicon oxide layer, and covering the waveguide structure with a second silicon oxide layer to obtain the waveguide substrate. The first silicon oxide layer is a silicon oxide layer prepared by thermal oxidation, and the second silicon oxide layer is a silicon oxide layer prepared by chemical vapor deposition. The two layers of silicon oxide are non-same-layer thin film structures, and there is a silicon nitride waveguide structure in the middle: the first silicon oxide layer is prepared by thermal oxidation, which has the best density and the best film quality, and can be used as a lower silicon oxide layer to grow a silicon nitride thin film layer with good crystal quality to optimize the optical performance; after the silicon nitride thin film layer is grown, it is impossible to continue to prepare silicon oxide by thermal oxidation, so the upper cladding silicon oxide is prepared by chemical vapor deposition to form a second silicon oxide layer, the film quality is slightly worse than the first silicon oxide layer, but it can be used as a cladding to protect the silicon nitride waveguide structure.

[0039] In specific implementation, the thickness of the first silicon oxide layer is 3-8 μm, the thickness of the silicon nitride waveguide structure layer is 50-450 nm, and the thickness of the second silicon oxide layer is 500 nm-1 um. The specific dimensions of the three are determined according to current design conditions and process windows.

[0040] In some embodiments of the present invention, a metal electrode is formed in the metal deposition tank, including: forming a metal electrode layer to cover the surface of the metal deposition tank and the surface of the waveguide substrate with the metal electrode layer, and forming a patterned second photoresist layer on the metal electrode layer in the metal deposition tank; using the second photoresist layer as a mask, patterning the metal electrode layer by dry etching, and then removing the second photoresist layer to form the metal electrode in the metal deposition tank.

[0041] In some embodiments of the present invention, the outermost width of the protection structure is greater than the gap width between the metal electrode and the wall of the metal deposition tank, so that the protection structure completely covers the gap. In addition, the upper surface of the protection structure is a plane, and the lower surface of the protection structure is adapted to the corresponding position of the concave-convex surface.

[0042] In specific implementation, the shape and size of the protection structure are determined according to the groove size of the metal deposition groove and the size of the metal electrode. The protection structure uses a layer of photoresist to protect the trench structure between the metal electrode and the metal deposition groove, that is, in the subsequent etching process, the lowest position of the silicon oxide on the concave and convex surface is protected. By controlling the etching depth, the entire concave and convex surface is made as flat as possible and then the CMP process is used to further polish the wafer surface to improve the flattening effect of the silicon oxide surface.

[0043] In some embodiments of the present invention, the metal deposition groove is located on both sides of the waveguide structure, and the bottom of the metal deposition groove extends into the first silicon oxide layer. In specific implementation, the metal electrode layer can be made of materials such as Al and Cu, the thickness of the metal electrode does not exceed the groove depth of the metal deposition groove, and the top of the metal electrode needs to be no higher than the top of the waveguide structure, and the gap between the top of the metal electrode and the top of the waveguide structure is controlled to be 0-100nm. The reason is that after the metal electrode structure is prepared, it is necessary to cover the silicon oxide cladding layer and perform two flattening processes to control the second silicon oxide layer to be 100nm higher than the silicon nitride waveguide layer, optimize the optical performance and prepare for the subsequent bonding process; if the metal electrode is higher than the waveguide structure layer, there is not enough process window to control the requirement of 100nm silicon oxide thickness on the silicon nitride waveguide layer, thereby affecting the optical performance, and it may also cause damage to the metal electrode during the flattening process, thereby affecting the electrical performance.

[0044] In specific implementation, the groove depth of the metal deposition groove is 1.5-2μm, which is determined by the final thickness of the second silicon oxide layer; the thickness of the metal electrode is 0.8-1μm, so that the top of the metal electrode is lower than the top of the silicon nitride waveguide structure to prevent subsequent CMP process and bonding process from causing electrode damage.

[0045] like Figure 2-Figure 6 As shown, this embodiment proposes a solution of first performing mask etching on a large area of ​​uneven surface and then performing chemical mechanical polishing to obtain the required thickness uniformity and precision. 3 N 4 The process steps of the embodiment of the present invention are specifically described by taking the waveguide substrate as an example (unless otherwise specified, all schematic diagrams are cross-sectional diagrams):

[0046] First, a silicon nitride waveguide substrate is prepared, including a waveguide structure and a metal electrode structure, and the substrate is not planarized. Figure 2 As shown, the silicon nitride waveguide substrate includes a silicon substrate 10, a thermal oxide silicon layer 11, a silicon nitride waveguide layer 12, and a chemical vapor deposited silicon oxide layer 13 which are formed in sequence from bottom to top; a metal deposition groove 14 is formed by etching on the silicon nitride waveguide substrate, a metal electrode 15 is formed in the metal deposition groove 14, and a silicon oxide cladding is filled in the metal deposition groove 14 to cover the metal electrode 15.

[0047] Secondly, a photoresist is spin-coated on the concave-convex surface formed by the surface of the silicon nitride waveguide substrate and the surface of the silicon oxide cladding layer, and then a mask is exposed to form a desired protection structure 16 to protect the relatively low trench area between the metal electrode and the deep trench, such as Figure 3 shown.

[0048] Again, the protective structure 16 is used as a mask to etch the concave-convex surface of the unprotected area, that is, the silicon oxide layer, to reduce the height difference between the steps of the concave-convex surface and reduce the amount of subsequent chemical mechanical polishing, so that the surface is initially flat. Figure 4 As shown. Again, remove the photoresist, as shown Figure 5 shown.

[0049] Finally, the silicon nitride waveguide substrate is subjected to chemical mechanical polishing to flatten the surface to meet device performance requirements.

[0050] The embodiment of the present invention adopts two planarization processes, namely, first performing a mask etching process to reduce the large height difference of the non-uniform surface, so that the large-area modulation area reaches a preliminary flat state, and then performing chemical mechanical polishing. This can enable the large-area modulation area (mm level) to obtain a flat surface that meets the design requirements (100±10nm), so that the modulation performance of the silicon photonic platform can achieve the best effect, and at the same time provide a uniform surface for subsequent processes, thereby improving product yield.

[0051] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for controlling the uniformity of silicon oxide thickness on a large surface area, characterized in that: include: Etching a metal deposition groove on a waveguide substrate, forming a metal electrode in the metal deposition groove, and filling the metal deposition groove with a silicon oxide cladding layer so as to cover the metal electrode with the silicon oxide cladding layer; forming a first photoresist layer on the concave-convex surface formed by the surface of the waveguide substrate and the surface of the silicon oxide cladding layer, and patterning the first photoresist layer so that the patterned first photoresist layer forms a protection structure above the gap between the metal electrode and the wall of the metal deposition groove; Using the protection structure as a mask, the concave-convex surface is patterned by etching to perform a first planarization process on the concave-convex surface; The protective structure is removed, and the concave-convex surface is subjected to a second flattening treatment to obtain a processed waveguide device.

2. The method for controlling the uniformity of silicon oxide thickness on a large surface area according to claim 1, characterized in that: The method further comprises: forming a first silicon oxide layer on the silicon substrate, forming a patterned waveguide structure on the first silicon oxide layer, and covering the waveguide structure with a second silicon oxide layer to obtain the waveguide substrate.

3. The method for controlling the uniformity of silicon oxide thickness on a large surface area according to claim 2, characterized in that: The first silicon oxide layer is prepared by thermal oxidation, and the second silicon oxide layer is prepared by chemical vapor deposition.

4. The method for controlling the uniformity of silicon oxide thickness on a large surface area according to claim 1, characterized in that: Forming a metal electrode in the metal deposition tank, comprising: forming a metal electrode layer to cover the surface of the metal deposition tank and the surface of the waveguide substrate through the metal electrode layer, and forming a patterned second photoresist layer on the metal electrode layer in the metal deposition tank; The metal electrode layer is patterned by dry etching using the second photoresist layer as a mask, and then the second photoresist layer is removed to form the metal electrode in the metal deposition tank.

5. The method for controlling the uniformity of silicon oxide thickness on a large surface area according to claim 1, characterized in that: The outermost width of the protection structure is greater than the width of the gap between the metal electrode and the wall of the metal deposition groove, so that the protection structure completely covers the gap.

6. The method for controlling the uniformity of silicon oxide thickness on a large surface area according to claim 1, characterized in that: The upper surface of the protection structure is a plane, and the lower surface of the protection structure is adapted to the corresponding position of the concave-convex surface.

7. The method for controlling the uniformity of silicon oxide thickness on a large surface area according to claim 1, characterized in that: The second planarization process adopts chemical mechanical polishing.

8. The method for controlling the uniformity of silicon oxide thickness on a large surface area according to claim 2, characterized in that: The metal deposition grooves are located at two sides of the waveguide structure, and the bottoms of the metal deposition grooves extend into the first silicon oxide layer.

9. The method for controlling the uniformity of silicon oxide thickness on a large surface area according to claim 2, characterized in that: The thickness of the metal electrode does not exceed the groove depth of the metal deposition groove, and the top of the metal electrode is not higher than the top of the waveguide structure.

10. The method for controlling the uniformity of silicon oxide thickness on a large surface area according to claim 1, characterized in that: The thickness of the metal electrode is 0.8-1 μm, and the groove depth of the metal deposition groove is 1.5-2 μm.

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