Array substrate and display device

Abstract

An array substrate and a display device, the array substrate comprising a first substrate and a sub-pixel, the sub-pixel comprising a transistor and a pixel electrode connected to each other; the pixel electrode comprising a main conductive part, the main conductive part comprising at least one first group of sub-conductive parts and at least one second group of sub-conductive parts, the first group of sub-conductive parts and the second group of sub-conductive parts being arranged alternately in a first direction; the first group of sub-conductive parts comprising a first connecting strip extending in the first direction, the first group of sub-conductive parts being located at an open end of the first connecting strip; the second group of sub-conductive parts comprising a second connecting strip extending in the first direction, the second group of sub-conductive parts being located at an open end of the second connecting strip; in a second direction, the first connecting strip is closer to the transistor than the second connecting strip; wherein the sum of the lengths of the first connecting strips in the at least one first group of sub-conductive parts is less than the sum of the lengths of the second connecting strips in the at least one second group of sub-conductive parts; the first direction intersects the second direction.

Description

[0001] This application is a divisional application of the application with the application date of April 6, 2021, the Chinese application number of 202180000716.X, and the invention name of "Pixel electrode, array substrate and display device". TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, in particular, to an array substrate and a display device. BACKGROUND

[0003] With the continuous development of liquid crystal panels, high-resolution products are being developed. However, for high-resolution pixels such as 8K, the pixel pitch (i.e., Dot pitch) is small, and the storage capacitance (i.e., Cst) is small. Therefore, the pixel voltage is more easily pulled by the data voltage, which easily causes the pull on both sides of the pixel to be asymmetric, thereby making the phenomenon of V-Crosstalk (i.e., V-type crosstalk) of gray scale more serious, affecting the display effect.

[0004] DISCLOSURE

[0005] The purpose of the present disclosure is to provide a pixel electrode, an array substrate and a display device, thereby at least partially overcoming one or more problems caused by the limitations and defects of the related art.

[0006] The first aspect of the present disclosure provides a pixel electrode, comprising: a first edge conductive part and a second edge conductive part arranged at intervals in a first direction, and a main conductive part located at least partially between the first edge conductive part and the second edge conductive part, the main conductive part being connected to the first edge conductive part and the second edge conductive part respectively, the main conductive part comprising at least one first group of sub-conductive parts and at least one second group of sub-conductive parts, the first group of sub-conductive parts and the second group of sub-conductive parts being arranged alternately in the first direction;

[0007] The first group of sub-conductive parts comprises a first connecting strip, the first connecting strip extending in the first direction and having a first face and a second face opposite in a second direction; the first group of sub-conductive parts has a first gap located on the side of the first face away from the second face, and the end of the first gap away from the first connecting strip is an open end;

[0008] The second group of sub-conductive parts includes a second connecting strip located on a side of the first slit away from the first connecting strip and connected with the first group of sub-conductive parts, the second connecting strip extends in the first direction and has a third face and a fourth face opposite in the second direction, the third face is located on a side of the fourth face close to the first face; and the second group of sub-conductive parts has a second slit located on a side of the third face away from the fourth face, the second slit has an open end away from an end of the second connecting strip;

[0009] In the second direction, the pixel electrode is configured such that the first connecting strip is closer to the transistor than the second connecting strip; and an end of the first edge conductive part or the second edge conductive part away from the second connecting strip is configured to be connected with the transistor.

[0010] The sum of the lengths of the first connecting strips in the at least one first group of sub-conductive parts is less than the sum of the lengths of the second connecting strips in the at least one second group of sub-conductive parts.

[0011] The first direction intersects the second direction.

[0012] In an exemplary embodiment of the present disclosure,

[0013] The first group of sub-conductive parts further includes a plurality of first electrode strips arranged at intervals in the first direction, the plurality of first electrode strips are located on a side of the first face away from the second face and connected with the first face; and the first slit is between two adjacent first electrode strips.

[0014] The second group of sub-conductive parts further includes a plurality of second electrode strips arranged at intervals in the first direction, the plurality of second electrode strips are located on a side of the third face away from the fourth face and connected with the third face; and the second slit is between two adjacent second electrode strips.

[0015] The third face of the second connecting strip is connected with an end of the first electrode strip closest to the second group of sub-conductive parts away from the first connecting strip.

[0016] In an exemplary embodiment of the present disclosure, the length of the first connecting strip is less than the length of the second connecting strip.

[0017] In an exemplary embodiment of the present disclosure, the main conductive part includes one first group of sub-conductive parts and one second group of sub-conductive parts,

[0018] The first edge conductive part is located on a side of the plurality of first electrode strips away from the second group of sub-conductive parts and on a position of the first face of the first connecting strip away from the second face; the first edge conductive part is connected with the first face and has a third gap with the first electrode strip adjacent thereto, and an end of the third gap away from the first connecting strip is an open end;

[0019] The second edge conductive part is located on a side of the plurality of second electrode strips away from the first group of sub-conductive parts and on a position of the third face of the second connecting strip away from the fourth face; the second edge conductive part is connected with the third face and has a fourth gap with the second electrode strip adjacent thereto, and an end of the fourth gap away from the second connecting strip is an open end.

[0020] In an exemplary embodiment of the present disclosure, the first electrode strip, the first gap and the third gap have the same extension direction and intersect with the first direction and the second direction; and the second electrode strip, the second gap and the fourth gap have the same extension direction and intersect with the first direction and the second direction.

[0021] In an exemplary embodiment of the present disclosure, the first electrode strip, the second electrode strip, the first gap, the second gap, the third gap and the fourth gap have equal widths.

[0022] In an exemplary embodiment of the present disclosure, the first electrode strip and the second electrode strip have the same extension direction, and the second gap is between the first electrode strip and the second electrode strip adjacent thereto.

[0023] In an exemplary embodiment of the present disclosure, the extension direction of the first electrode strip and the extension direction of the second electrode strip are mirror image arranged about the second direction.

[0024] In an exemplary embodiment of the present disclosure, the second group of sub-conductive parts further comprises an adjustment part, the adjustment part is located on a side of the plurality of second electrode strips close to the first group of sub-conductive parts and on a position of the third face of the second connecting strip away from the fourth face, and the adjustment part is connected with the third face of the second connecting strip; wherein,

[0025] The adjustment part and the first electrode strip adjacent thereto form a fifth gap therebetween, and the adjustment part and the second electrode strip adjacent thereto form a sixth gap therebetween;

[0026] The fifth gap and the sixth gap have open ends away from the second connecting strip;

[0027] The fifth slit has the same extension direction and equal width as the first slit, and the sixth slit has the same extension direction and equal width as the second slit.

[0028] In an exemplary embodiment of the present disclosure, the adjusting portion comprises a first adjusting strip and a second adjusting strip, the fifth slit is formed between the first adjusting strip and the first electrode strip, and the sixth slit is formed between the second adjusting strip and the second electrode strip; wherein,

[0029] The first adjusting strip has the same extension direction and equal width as the first electrode strip, and the second adjusting strip has the same extension direction and equal width as the second electrode strip.

[0030] One end of the first adjusting strip and the second adjusting strip in the extension direction thereof is connected to the third surface of the second connecting strip, and the other end thereof is connected to each other.

[0031] In an exemplary embodiment of the present disclosure, the ratio of the sum of the lengths of the first connecting strips in the at least one first group of sub-conductive portions to the sum of the lengths of the second connecting strips in the at least one second group of sub-conductive portions is 0.1 to 0.9.

[0032] The second aspect of the present disclosure provides an array substrate comprising a first substrate and sub-pixels arranged in an array on the first substrate along a first direction and a second direction, wherein the sub-pixels comprise a transistor and a pixel electrode according to any one of the preceding aspects, and the first edge conductive portion or the second edge conductive portion of the pixel electrode away from the end of the second connecting strip is connected to the transistor.

[0033] In the second direction, the transistor is arranged closer to the first connecting strip than to the second connecting strip of the pixel electrode.

[0034] In an exemplary embodiment of the present disclosure, the orthogonal projection of the transistor on the first substrate is arranged opposite to the orthogonal projection of the first connecting strip of the pixel electrode on the first substrate in the first direction.

[0035] In an exemplary embodiment of the present disclosure, in two adjacent pixel electrodes in the second direction:

[0036] The first edge conductive portion of one pixel electrode away from the end of the second connecting strip is connected to the transistor, and is closer to the transistor connected thereto than the second edge conductive portion thereof.

[0037] The second edge conductive portion of the other pixel electrode away from the end of the second connecting strip is connected to the transistor, and is closer to the transistor connected thereto than the first edge conductive portion thereof.

[0038] In an exemplary embodiment of the present disclosure, the array substrate further comprises a plurality of data lines formed on the first substrate, the data lines extending in the first direction, and the data lines and the sub-pixels are arranged alternately in the second direction;

[0039] In the pixel electrode of the sub-pixel, the distance between the first connecting strip and the data line closest to it is a first distance, the distance between the second connecting strip and the data line closest to it is a second distance, and the first distance and the second distance are equal.

[0040] In an exemplary embodiment of the present disclosure, each data line and the transistors of the sub-pixels located on the same side of the data line in the second direction are connected;

[0041] In an exemplary embodiment of the present disclosure, the first electrode and the second electrode of the transistor are arranged in the same layer as the data line and are located on the side of the pixel electrode close to the first substrate; the first electrode of the transistor is connected to the data line, and the second electrode of the transistor is connected to the second edge conductive part or the first edge conductive part of the pixel electrode through a transfer via hole.

[0042] In an exemplary embodiment of the present disclosure, the first electrode and the second electrode of the transistor are arranged at intervals in the first direction, and the distance between the first electrode and the second electrode in the first direction is a third distance;

[0043] In an exemplary embodiment of the present disclosure, the ratio of the sum of the lengths of the first connecting strips in the at least one first group of sub-conductive parts to the third distance is 2 to 20.

[0044] In an exemplary embodiment of the present disclosure, the sub-pixel further comprises a common electrode arranged on the side of the pixel electrode close to the first substrate and insulated from the pixel electrode;

[0045] The orthogonal projection of the common electrode on the first substrate and the orthogonal projection of the pixel electrode on the first substrate overlap, and the orthogonal projection of the common electrode on the first substrate does not overlap with the orthogonal projection of the data line on the first substrate.

[0046] In an exemplary embodiment of the present disclosure, the array substrate further comprises a plurality of scan lines and a plurality of common lines formed on the first substrate and extending in the second direction, the scan lines and the common lines are arranged alternately in the first direction, and the orthogonal projection of the scan lines on the first substrate does not overlap with the orthogonal projection of the common lines on the first substrate;

[0047] The scan lines are arranged in the same layer as the common lines, and the scan lines and the common lines are arranged on the side of the data lines close to the first substrate and are insulated from the data lines.

[0048] The sub-pixels are adjacent to the common lines on one side in the first direction and adjacent to the scan lines on the other side.

[0049] Each scan line is connected to the gate of the transistor of each sub-pixel located on the same side in the first direction and adjacent to the scan line.

[0050] Each common line is connected to the common electrode of each sub-pixel located on the same side in the first direction and adjacent to the common line.

[0051] In an exemplary embodiment of the present disclosure, part of the scan line constitutes the gate of the transistor, and the common electrode is in contact with the common line.

[0052] The third aspect of the present disclosure provides a display device, comprising the array substrate of any one of the above and an opposite substrate arranged opposite to the array substrate.

[0053] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0054] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0055] The drawings herein are incorporated into the specification and form a part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0056] Figure 1 A structural schematic diagram of a pixel electrode according to an embodiment of the present disclosure is shown;

[0057] Figure 2 A structural schematic diagram of a pixel electrode according to another embodiment of the present disclosure is shown;

[0058] Figure 3 A structural schematic diagram of a pixel electrode according to the related art is shown;

[0059] Figure 4 A structural schematic diagram of a minimum repeating unit of an array substrate according to an embodiment of the present disclosure is shown;

[0060] Figure 5 A schematic diagram of the structure of the smallest repeating unit of the array substrate according to another embodiment of the present disclosure is shown;

[0061] Figure 6 A schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure is shown. Detailed Implementation

[0062] The technical solutions of this disclosure will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of this disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of this disclosure and should not be construed as a limitation thereof.

[0063] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details.

[0064] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0065] It should be noted that while terms such as "first," "second," etc., may be used herein to describe various regions, layers, and / or portions, these regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one region, layer, and / or portion from another.

[0066] like Figure 1 and Figure 2 As shown, one embodiment of this disclosure provides a pixel electrode 10, which can be applied to liquid crystal display products, but is not limited thereto. Specifically, the pixel electrode 10 may include a first edge conductive portion 101 and a second edge conductive portion 102 arranged at intervals in a first direction Y, and a main conductive portion located at least partially between the first edge conductive portion 101 and the second edge conductive portion 102. The main conductive portion is connected to the first edge conductive portion 101 and the second edge conductive portion 102 respectively, and the main conductive portion may include at least one first group of sub-conductive portions and at least one second group of sub-conductive portions, which are alternately arranged in the first direction Y.

[0067] like Figure 1 and Figure 2As shown, the first group of sub-conductive parts mentioned above can include a first connecting strip 103 and a plurality of first electrode strips 104 arranged at intervals in the first direction Y. The first connecting strip 103 extends in the first direction Y (i.e., the length direction of the first connecting strip 103 is the first direction Y). The first connecting strip 103 can have a first surface 103a and a second surface 103b opposite to each other in the second direction X. It should be noted that the first direction Y can intersect the second direction X, and preferably, the first direction Y can be perpendicular to the second direction X. The plurality of first electrode strips 104 can be located at a position away from the second surface 103b of the first connecting strip 103 and connected to the first surface 103a. A gap between two adjacent first electrode strips 104 can be defined as a first gap S1, and the two adjacent first electrode strips 104 away from one end of the first connecting strip 103 are in a disconnected state, i.e., the first gap S1 away from one end of the first connecting strip 103 is in an open state. For the convenience of description, the end of the first gap S1 away from the first connecting strip 103 can be defined as an open end.

[0068] As shown, Figure 1 and Figure 2 As shown, the second group of sub-conductive parts mentioned above includes a second connecting strip 105 and a plurality of second electrode strips 106 arranged at intervals in the first direction Y. The second connecting strip 105 extends in the first direction Y (i.e., the length direction of the second connecting strip 105 is the first direction Y). The second connecting strip 105 can have a third surface 105a and a fourth surface 105b opposite to each other in the second direction X. In the second direction X, the third surface 105a of the second connecting strip 105 can be located on the side of the fourth surface 105b close to the first surface 103a of the first connecting strip 103. The third surface 105a of the second connecting strip 105 can be connected to the first electrode strip 104 close to the second group of sub-conductive parts, specifically, the end of the first electrode strip 104 away from the first connecting strip 103. It should be understood that the first electrode strip 104 close to the second group of sub-conductive parts mentioned here refers to the first electrode strip 104 closest to the second group of sub-conductive parts in the first group of sub-conductive parts. The plurality of second electrode strips 106 can be located at a position away from the fourth surface 105b of the second connecting strip 105 and connected to the third surface 105a of the second connecting strip 105. A gap between two adjacent second electrode strips 106 can be defined as a second gap S2, and the two adjacent second electrode strips 106 away from one end of the second connecting strip 105 are in a disconnected state, i.e., the second gap S2 away from one end of the second connecting strip 105 is in an open state. For the convenience of description, the end of the second gap S2 away from the second connecting strip 105 can be defined as an open end.

[0069] In the embodiments of the present disclosure, the pixel electrode 10 can be connected to the transistor 20 (such as the transistor 20a) through the first edge conductive part 101 or the second edge conductive part 102 mentioned above.Figure 4 and Figure 5 As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1). Figure 4 and Figure 5 As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1).

[0070] As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1). Figure 4 and Figure 5 As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1). Figure 3 As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1).

[0071] As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1). Figure 4 and Figure 5 As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1). Figure 4 and Figure 5 As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1). Figure 4 and Figure 5 As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1). Figure 4 and Figure 5 As shown in FIG. 1, the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively, and the first edge conductive part 101 and the second edge conductive part 102 are connected to the first connecting strip 103 and the second connecting strip 105 respectively. In the second direction X, the pixel electrode 10 is configured such that the first connecting strip 103 is closer to the transistor 20 than the second connecting strip 105, and it should be understood that the transistor 20 can be connected to the data line 40 adjacent thereto (as shown in FIG. 1).

[0072] If the sum of the lengths of the first connecting strips 103 of each first group of sub-conductive parts in the pixel electrode 10 is designed to be greater than or equal to the sum of the lengths of the second connecting strips 105 of each second group of sub-conductive parts, that is, the sum of the capacitances generated between each first connecting strip 103 of the pixel electrode 10 and the adjacent data line 40 is greater than or equal to the sum of the capacitances generated between each second connecting strip 105 and the adjacent data line 40, because the side where the first connecting strips 103 of the pixel electrode 10 are located will have more lateral capacitances generated between the first pole 201 and the second pole 202 of the transistor 20 than the side where the second connecting strips 105 of the pixel electrode 10 are located, the total capacitance on the side where the first connecting strips 103 of the pixel electrode 10 are located will be greater than the total capacitance on the side where the second connecting strips 105 of the pixel electrode 10 are located, which makes the pulling of the pixel electrode 10 by the data voltage different on both sides, resulting in a more serious phenomenon of gray scale V-Crosstalk in the display product. Based on this, in order to improve the phenomenon of gray scale V-Crosstalk in the product, in the embodiments of the present disclosure, the sum of the lengths of the first connecting strips 103 of each first group of sub-conductive parts in the pixel electrode 10 can be designed to be less than the sum of the lengths of the second connecting strips 105 of each second group of sub-conductive parts. It should be noted that the length mentioned here refers to the length in the extension direction thereof.

[0073] Alternatively, the ratio of the sum of the lengths of the first connecting strips 103 of each first group of sub-conductive parts in the pixel electrode 10 to the sum of the lengths of the second connecting strips 105 of each second group of sub-conductive parts can be 0.1 to 0.9, such as 0.1, 0.3, 0.5, 0.7, 0.9, and the like, but is not limited thereto. For example, the sum of the lengths of the first connecting strips 103 of each first group of sub-conductive parts in the pixel electrode 10 can be 30 μm to 90 μm, such as 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, and the like, but is not limited thereto. The sum of the lengths of the second connecting strips 105 of each second group of sub-conductive parts in the pixel electrode 10 can be 60 μm to 120 μm, such as 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 110 μm, and the like, but is not limited thereto.

[0074] It should be noted that the ratio of the sum of the lengths of the first connecting strips 103 of each first group of sub-conductive parts in the pixel electrode 10 to the sum of the lengths of the second connecting strips 105 of each second group of sub-conductive parts in the pixel electrode 10, the sum of the lengths of the first connecting strips 103 of each first group of sub-conductive parts in the pixel electrode 10, and the sum of the lengths of the second connecting strips 105 of each first group of sub-conductive parts in the pixel electrode 10 is not limited to the aforementioned numerical range, and can be determined according to the size of the transistor 20; that is, when designing the product, the size of the transistor 20 in the product can be determined first, so that the lateral capacitance generated between the first pole 201 and the second pole 202 of the transistor 20 can be determined first, and then the lengths of the first connecting strips 103 and the second connecting strips 105 of the pixel electrode 10 are designed and adjusted, so that the total capacitance on the side of the first connecting strips 103 of the pixel electrode 10 is equal to or substantially equal to (i.e., within an error range) the total capacitance on the side of the second connecting strips 105 of the pixel electrode 10, thereby improving the gray scale V-Crosstalk phenomenon of the product.

[0075] In addition, it should be understood that the number of the first group of sub-conductive parts and the second group of sub-conductive parts in the main conductive part of the pixel electrode 10 of the present embodiment can be the same, for example, one, two, etc.; but not limited to this, the number of the first group of sub-conductive parts and the second group of sub-conductive parts in the main conductive part of the pixel electrode 10 can also be different, that is, the number of the first group of sub-conductive parts in the main conductive part of the pixel electrode 10 is greater than or less than the number of the second group of sub-conductive parts, etc.

[0076] Wherein, when the number of the first group of sub-conductive parts and the second group of sub-conductive parts in the pixel electrode 10 is the same, the sum of the lengths of the first connecting strips 103 of each first group of sub-conductive parts in the pixel electrode 10 is designed to be less than the sum of the lengths of the second connecting strips 105 of each second group of sub-conductive parts, which can be understood as that the length of the first connecting strip 103 of the first group of sub-conductive parts in the pixel electrode 10 is less than the length of the second connecting strip 105 of the second group of sub-conductive parts.

[0077] As Figure 1 and Figure 2As shown, the main conductive part of the pixel electrode 10 can include a first group of sub-conductive parts and a second group of sub-conductive parts. At this time, the first edge conductive part 101 of the pixel electrode 10 is located on the side of the plurality of first electrode strips 104 away from the second group of sub-conductive parts and is located at the position of the first face 103a of the first connecting strip 103 away from the second face 103b. The first edge conductive part 101 can be connected with the first face 103a and has a third gap S3 between the first edge conductive part 101 and the first electrode strip 104 adjacent thereto. The end of the first edge conductive part 101 and the end of the first electrode strip 104 away from the first connecting strip 103 are in a disconnected state, that is, the end of the third gap S3 away from the first connecting strip 103 is in an open state. For the convenience of description, the end of the third gap S3 away from the first connecting strip 103 can be defined as an open end. The second edge conductive part 102 is located on the side of the plurality of second electrode strips 106 away from the first group of sub-conductive parts and is located at the position of the third face 105a of the second connecting strip 105 away from the fourth face 105b. The second edge conductive part 102 is connected with the third face 105a and has a fourth gap S4 between the second edge conductive part 102 and the second electrode strip 106 adjacent thereto. The end of the second edge conductive part 102 and the end of the second electrode strip 106 away from the second connecting strip 105 are in a disconnected state, that is, the end of the fourth gap S4 away from the second connecting strip 105 is in an open state. For the convenience of description, the end of the fourth gap S4 away from the second connecting strip 105 can be defined as an open end.

[0078] Optionally, the first electrode strip 104, the first gap S1 and the third gap S3 have the same extension direction to ensure the display uniformity at the first group of sub-conductive parts of the pixel electrode 10. The extension direction of the first electrode strip 104, the first gap S1 and the third gap S3 intersects the first direction Y and the second direction X to reduce color cast. Similarly, the second electrode strip 106, the second gap S2 and the fourth gap S4 have the same extension direction to ensure the display uniformity at the second group of sub-conductive parts of the pixel electrode 10. The extension direction of the second electrode strip 106, the second gap S2 and the fourth gap S4 intersects the first direction Y and the second direction X to reduce color cast.

[0079] Further, the first electrode strip 104, the second electrode strip 106, the first gap S1, the second gap S2, the third gap S3 and the fourth gap S4 have the same width to better ensure the display uniformity of the product. It should be noted that the width mentioned here is the size in the direction perpendicular to the extension direction.

[0080] In an optional embodiment of the present disclosure, as shown in Figure 1As shown, the aforementioned first electrode strip 104 and second electrode strip 106 can extend in the same direction, that is, the first electrode strip 104 and second electrode strip 106 can extend in the same direction. In other words, the pixel electrode 10 of this disclosure can be a single-domain structure, which can reduce the design difficulty. It should be noted that, in this embodiment, the gap between adjacent first electrode strip 104 and second electrode strip 106 can be the aforementioned second gap S2.

[0081] In another alternative embodiment of this disclosure, such as Figure 2 As shown, the extension direction of the first electrode strip 104 can be mirrored with the extension direction of the second electrode strip 106 about the second direction X. That is, the pixel electrode 10 of this disclosure can be a dual-domain structure, which can expand the viewing angle of the product. It should be noted that in the embodiments of this disclosure, the angle between the extension direction of the first electrode strip 104 and the extension direction of the second electrode strip 106 can be an acute angle.

[0082] When the pixel electrode 10 has a dual-domain structure, such as Figure 2 As shown, the second set of sub-conductive portions of the pixel electrode 10 may further include an adjustment portion 107. This adjustment portion 107 may be located on the side of the plurality of second electrode strips 106 near the first set of sub-conductive portions, and located on the third surface 105a of the second connecting strip 105 away from the fourth surface 105b. This adjustment portion 107 may be connected to the third surface 105a of the second connecting strip 105.

[0083] Specifically, such as Figure 2 As shown, a fifth gap S5 is formed between the adjustment part 107 and the adjacent first electrode strip 104, and a sixth gap S6 is formed between the adjustment part 107 and the adjacent second electrode strip 106. The ends of the adjacent adjustment parts 107 and the first electrode strip 104 away from the second connecting strip 105 are disconnected from each other, and the ends of the adjacent adjustment parts 107 and the second electrode strip 106 away from the second connecting strip 105 are also disconnected from each other. That is, the ends of the fifth gap S5 and the sixth gap S6 away from the second connecting strip 105 are open. For ease of description, the ends of the fifth gap S5 and the sixth gap S6 away from the second connecting strip 105 can both be defined as open ends. The fifth gap S5 can have the same extension direction and the same width as the aforementioned first gap S1, and the sixth gap S6 can have the same extension direction and the same width as the second gap S2. This design ensures that the electric field at the junction of the first group of sub-conductive parts and the second group of sub-conductive parts in the pixel electrode 10 is closer to the electric field at other parts of the pixel electrode 10, thereby ensuring display uniformity.

[0084] For example, such as Figure 2As shown, the adjusting portion 107 can include a first adjusting strip 107a and a second adjusting strip 107b, the first adjusting strip 107a and the first electrode strip 104 form the fifth gap S5 mentioned above, and the second adjusting strip 107b and the second electrode strip 106 form the sixth gap S6 mentioned above; wherein the extending direction of the first adjusting strip 107a can be the same as the extending direction of the first electrode strip 104 and the width is equal, and the extending direction of the second adjusting strip 107b can be the same as the extending direction of the second electrode strip 106 and the width is equal, so as to further ensure the uniformity of the electric field, thereby ensuring the display uniformity.

[0085] It should be noted that one end of the first adjusting strip 107a and the second adjusting strip 107b in the extending direction is connected with the third surface 105a of the second connecting strip 105, and the other end can be connected with each other, and it should be understood that the first adjusting strip 107a and the second adjusting strip 107b of the embodiment of the present disclosure form a gap pattern, and such design can reduce the dark field area.

[0086] Wherein, if the gap pattern formed between the first adjusting strip 107a and the second adjusting strip 107b has a larger width, a spacing portion (not shown in the figure) connected with the third surface 105a of the second connecting strip 105 can be further arranged in the gap pattern, so as to divide the gap pattern into a gap having the same and equal extending direction as the first gap S1, and another gap having the same and equal extending direction as the second gap S2; if the gap pattern formed between the first adjusting strip 107a and the second adjusting strip 107b has a smaller width, the spacing portion can also not be arranged.

[0087] In addition, it should be understood that when the area of the adjusting portion 107 of the embodiment of the present disclosure is small, the first adjusting strip 107a, the second adjusting strip 107b and the gap pattern mentioned above are also not arranged, that is, the adjusting portion 107 can be a whole structure, which does not have a gap pattern, depending on the specific circumstances.

[0088] In summary, the pixel electrode 10 of the embodiment of the present disclosure can be a one-piece structure. For example, the pixel electrode 10 of the embodiment of the present disclosure can be a transparent electrode, and the material thereof can be ITO (indium tin oxide) material, but is not limited thereto, and can also be made of transparent materials such as indium zinc oxide (IZO) and zinc oxide (ZnO).

[0089] The present disclosure also provides an array substrate, which can be used in a liquid crystal display device, but is not limited thereto. In combination with the above description of the pixel electrode 10, the array substrate will not be described in detail herein. Figure 1 、 Figure 2 and Figures 4 to 6As shown, the array substrate of this disclosure may further include a first substrate 30, sub-pixels located on the first substrate 30 and arranged in an array along the first direction Y and the second direction X, multiple data lines 40 formed on the first substrate 30, multiple scan lines 60 formed on the first substrate 30, and multiple common lines 70; it should be noted that the first direction Y mentioned in the embodiments of this disclosure may be referred to as the column direction, and the second direction X may be referred to as the row direction.

[0090] The array substrate of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0091] like Figure 6 As shown, the first substrate 30 may be a single-layer structure, but is not limited to this; the first substrate 30 may also include a multi-layer structure. For example, the material of the first substrate 30 may be glass, but is not limited to this; the material of the first substrate 30 may also be other materials, such as polyimide (PI), depending on the specific circumstances.

[0092] like Figure 4 and Figure 5 As shown, data lines 40 can extend in the first direction Y (i.e., column direction), and data lines 40 can be arranged alternately with sub-pixels in the second direction X (i.e., row direction). In embodiments of this disclosure, each data line 40 is connected to each sub-pixel located on the same side in the second direction X and adjacent to it, that is, each column of data lines 40 is connected to each sub-pixel adjacent to it and located in the same column, so as to provide data signals to the sub-pixels in the same column.

[0093] For example, the data cable 40 may include metallic or alloy materials, such as a single-layer or multi-layer structure of metal formed from molybdenum, aluminum and titanium, for example, the multi-layer structure is a multi-metal stack, such as a titanium, aluminum and titanium three-layer metal stack (Ti / Al / Ti) etc.

[0094] like Figure 4 and Figure 5 As shown, the scan line 60 and the common line 70 can extend in the second direction X, and the scan line 60 and the common line 70 are arranged alternately in the first direction Y. It should be understood that the orthogonal projection of the scan line 60 on the first substrate 30 does not overlap with the orthogonal projection of the common line 70 on the first substrate 30.

[0095] For example, the scan lines 60 and the common lines 70 are arranged in the same layer. In the present disclosure, "arranged in the same layer" refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form by one patterning process. That is, one patterning process corresponds to one mask plate (also referred to as a photomask). According to different specific patterns, one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and the specific patterns can also be at different heights or have different thicknesses. Thus, the manufacturing process is simplified, the manufacturing cost is saved, and the production efficiency is improved.

[0096] In combination with Figures 4 to 6 As shown in FIG. 1, the scan lines 60 and the common lines 70 can be arranged on the side of the data lines 40 close to the first substrate 30 and insulated from the data lines 40, that is, the scan lines 60 and the common lines 70 are both provided with a gate insulating layer 80 between the scan lines 60 and the data lines 40. It should be understood that the gate insulating layer 80 is arranged in the same layer.

[0097] In the embodiments of the present disclosure, as shown in FIG. 1, Figure 4 and Figure 5 As shown in FIG. 1, one row of scan lines 60 and one row of common lines 70 can form a group and be arranged corresponding to one row of sub-pixels, that is, one side of each row of sub-pixels in the first direction Y is adjacent to one row of common lines 70, and the other side is adjacent to one row of scan lines 60; wherein each scan line 60 is connected to each sub-pixel located on the same side of the scan line 60 in the first direction Y and adjacent to the scan line 60, that is, each row of scan lines 60 can be connected to the sub-pixels adjacent to the scan lines 60 and located in the same row to provide scan signals for the sub-pixels in the same row; and each common line 70 is connected to each sub-pixel located on the same side of the common line 70 in the first direction Y and adjacent to the common line 70, that is, each row of common lines 70 can be connected to the sub-pixels adjacent to the common lines 70 and located in the same row to provide common signals for the sub-pixels in the same row.

[0098] For example, the scan lines 60 and the common lines 70 can include a metal material or an alloy material, such as a single-layer or multi-layer structure formed by molybdenum, aluminum, titanium and the like.

[0099] In the embodiments of the present disclosure, as shown in FIG. 1, Figure 4 and Figure 5 As shown in FIG. 1, the sub-pixels can include a pixel electrode 10, a transistor 20 and a common electrode 50; wherein:

[0100] The structure of the pixel electrode 10 can refer to the description in any of the foregoing embodiments, and the specific structure can refer to the description in Figure 1 and Figure 2 The structure of the pixel electrode 10 can refer to the description in any of the foregoing embodiments, and the specific structure can refer to the description in

[0101] As shown in FIG. 1, Figure 4 and Figure 5As shown, in the pixel electrode 10 of the sub-pixel, the distance between the first connecting strip 103 and the data line 40 closest to it is the first distance h1, and the distance between the second connecting strip 105 and the data line 40 closest to it is the second distance h2. The first distance h1 can be equal to the second distance h2, which facilitates the subsequent design of the size of the first connecting strip 103 and the second connecting strip 105 and reduces the manufacturing difficulty. However, it should be understood that the first distance h1 can also be different from the second distance h2, depending on the specific situation.

[0102] Combination Figures 4 to 6 As shown, transistor 20 may include an active layer 203, a gate, and a first electrode 201 and a second electrode 202 disposed on the same layer. For example, the first electrode 201 and the second electrode 202 may be disposed on the same layer as the aforementioned data line 102. A gate insulating layer 80 may also be disposed between the gate of transistor 20 and the active layer 203 to insulate the gate from the active layer 203. This gate insulating layer 80 may be made of inorganic materials, such as silicon oxide, silicon nitride, etc.

[0103] It should be noted that the gate can be disposed on the same layer as the aforementioned scan line 60. This gate can be a part of the aforementioned scan line 60. That is, a part of the structure of the scan line 60 can be used as the gate of the transistor 20 to realize the connection between the scan line 60 and the transistor 20. The first electrode 201 and the second electrode 202 can be connected to the two doped regions (i.e., the source doped region and the drain doped region) of the active layer 203, respectively. The first electrode 201 can also be connected to the data line 40 to realize the connection between the data line 40 and the transistor 20. The second electrode 202 can be connected to the pixel electrode 10. Specifically, the end of the first edge conductive portion 101 or the second edge conductive portion 102 of the pixel electrode 10 away from the second connecting strip 105 can be connected to the second electrode 202 of the transistor 20 to realize the connection between the transistor 20 and the pixel electrode 10.

[0104] Among them, such as Figure 4 and Figure 5 As shown, in the second direction X, the transistor 20 of each sub-pixel is positioned closer to the first connecting strip 103 than the second connecting strip 105 of its pixel electrode 10. This makes the total capacitance on the side where the first connecting strip 103 of the pixel electrode 10 is located equal to or substantially equal to the total capacitance on the side where the second connecting strip 105 is located, thereby improving the V-Crosstalk phenomenon in the grayscale of the product.

[0105] Furthermore, the orthographic projection of the transistor 20 on the first substrate 30 and the orthographic projection of the first connecting strip 103 of the pixel electrode 10 on the first substrate 30 are positioned opposite each other in the first direction Y.

[0106] Optionally, such as Figure 4 and Figure 5As shown, the two adjacent sub-pixels in the second direction X are taken as the minimum repeating unit, wherein in the two adjacent pixel electrodes 10 in the second direction X: the first edge conductive part 101 of one is connected with the transistor 20 away from the end of the second connecting strip 105 and is closer to the transistor 20 connected therewith than the second edge conductive part 102 thereof; the second edge conductive part 102 of the other is connected with the transistor 20 away from the end of the second connecting strip 105 and is closer to the transistor 20 connected therewith than the first edge conductive part 101 thereof; that is, as shown Figure 5 As shown, the second connecting strip 105 of one and the first connecting strip 103 of the other are adjacent to the data line 40 therebetween, and the first connecting strip 103 of one and the second connecting strip 105 of the other are away from the data line 40 therebetween, in short, one of the two adjacent pixel electrodes 10 in the second direction X can be obtained by vertically flipping (i.e., mirroring about the second direction X) the other, and such design can expand the product viewing angle while reducing and balancing the dark field area, but is not limited thereto; or the connection relationship of the two adjacent pixel electrodes 10 in the second direction X and the transistor 20 can be the same, depending on the specific circumstances.

[0107] It should be noted that the first edge conductive part 101 or the second edge conductive part 102 of one of the two adjacent pixel electrodes 10 in the second direction X can be designed to be completely the same as the first edge conductive part 101 or the second edge conductive part 102 of the other, but is not limited thereto, and can be slightly adjusted according to the actual situation, as long as the total capacitance on the side of the first connecting strip 103 of the pixel electrode 10 is equal to or substantially equal to the total capacitance on the side of the second connecting strip 105 thereof, so as to improve the product gray scale V-Crosstalk phenomenon.

[0108] For example, the transistor 20 of the embodiment of the present disclosure can be a bottom gate type, that is, the gate can be formed on the first substrate 30 first, and the gate can include a metal material or an alloy material, such as molybdenum, aluminum, titanium, etc., to ensure good conductivity; then, the gate insulating layer 80 is formed on the first substrate 30, as shown Figure 6As shown, the gate electrode can be covered by the gate insulating layer 80; then the active layer 203 is formed on the side of the gate insulating layer 80 away from the first substrate 30, that is, the active layer 203 is located on the side of the gate electrode away from the first substrate 30, and the active layer 203 overlaps the orthogonal projection of the gate electrode on the first substrate 30, for example, the orthogonal projection of the active layer 203 on the first substrate 30 can be located in the orthogonal projection of the gate electrode on the first substrate; the first electrode 201 and the second electrode 202 can be formed after the formation of the active layer 203, wherein part of the first electrode 201 can be located on the side of the active layer 203 away from the first substrate 30 and in contact with the source doped region of the active layer 203, and part of the second electrode 202 can be located on the side of the active layer 203 away from the first substrate 30 and in contact with the drain doped region of the active layer 203.

[0109] It should be noted that the contact mentioned in the embodiments of the present disclosure means that two components are directly attached together without other film layers, that is, the two components do not need to be connected through other structures (for example, a through-hole).

[0110] In the embodiments of the present disclosure, as shown in Figure 4 and Figure 5 The first electrode 201 and the second electrode 202 of the transistor 20 can be arranged at intervals in the first direction Y, and the interval of the first electrode 201 and the second electrode 202 in the first direction Y can be a third interval h3; wherein the length design of the first connecting strip 103 and the second connecting strip 105 in each first group of sub-conductive parts of the pixel electrode 10 is related to the size selection of the transistor 20, specifically, the ratio of the sum of the lengths of the first connecting strips 103 in each first group of sub-conductive parts of the pixel electrode 10 to the third interval h3 can be 2 to 20, such as 2, 5, 8, 11, 14, 17, 20, etc., for example, the third interval h3 can be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, etc., but is not limited thereto, and can also be other values.

[0111] It should be noted that the sum of the lengths of the first connecting strips 103 in each first group of sub-conductive parts of the pixel electrode 10 is not only related to the third interval S3 mentioned above, but also related to the thickness and length of the first electrode 201 and the second electrode 202, wherein the thickness, length of the first electrode 201 and the second electrode 202 and the third interval h3 are all the keys to determine the size of the lateral capacitance generated between the first electrode 201 and the second electrode 202 in the transistor 20, that is, the length design of the first connecting strip 103 and the second connecting strip 105 in the pixel electrode 10 mainly depends on the lateral capacitance generated between the first electrode 201 and the second electrode 202 in the transistor 20.

[0112] For example, the thickness of the first electrode 201 and the second electrode 202 in the transistor 20 can be To For example: and the like, but are not limited thereto, and can be other values; and the lengths of the first electrode 201 and the second electrode 202 of the transistor 20 can be 5 μm to 50 μm, for example, 5 μm, 15 μm, 25 μm, 35 μm, 45 μm, 50 μm, and the like, but are not limited thereto, and can be other values.

[0113] It should be understood that the first electrode 201 and the second electrode 202 of the transistor 20 are not limited to being arranged at intervals in the first direction Y, but can also be arranged at intervals in the second direction X. It should be noted that when the first electrode 201 and the second electrode 202 of the transistor 20 are arranged at intervals in the second direction X, the third interval h3 mentioned above can be understood as the interval of the first electrode 201 and the second electrode 202 in the second direction X.

[0114] In addition, it should be noted that the length of the first electrode 201 and the second electrode 202 of the transistor 20 refers to the size in the direction perpendicular to the arrangement direction of the first electrode 201 and the second electrode 202.

[0115] In an embodiment of the present disclosure, as shown in Figure 6 The first electrode 201 and the second electrode 202 of the transistor 20 can be located on the side of the pixel electrode 10 close to the first substrate 30, that is, when manufacturing the array substrate, the first electrode 201 and the second electrode 202 of the transistor 20 can be manufactured first, and then the pixel electrode 10 is manufactured.

[0116] As shown in Figure 6 The first electrode 201 and the second electrode 202 of the transistor 20 and the pixel electrode 10 can also be provided with a passivation layer 90, which can be an inorganic film layer such as silicon nitride, but is not limited thereto, and can also be an organic film layer. It should be noted that at this time, the first edge conductive part 101 or the second edge conductive part 202 of the pixel electrode 10 mentioned above can be connected to the second electrode 202 of the transistor 20 through a transfer via hole P.

[0117] In an embodiment of the present disclosure, as shown in Figure 6 The common electrode 50 can be located on the side of the pixel electrode 10 close to the first substrate 30 and insulated from the pixel electrode 10. For example, the common electrode 50 can be formed on the first substrate 30 before the formation of the margin layer 203, that is, the common electrode 50 and the pixel electrode 10 can be insulated by the gate insulating layer 80 and the passivation layer 90 arranged in layers.

[0118] As shown in Figure 4 and Figure 6As shown, the orthogonal projection of the common electrode 50 on the first substrate 30 can overlap with the orthogonal projection of the common line 70 on the first substrate 30, wherein the common electrode 50 can be in contact with the aforementioned common line 70, specifically, the common electrode 50 can be formed on the first substrate 30 prior to the common line 70, but is not limited thereto, and can also be formed on the first substrate 30 after the common line 70 is formed on the first substrate 30.

[0119] It should be understood that the orthogonal projection of the common electrode 50 on the first substrate 30 overlaps with the orthogonal projection of the pixel electrode 10 on the first substrate 30, and does not overlap with the orthogonal projection of the data line 40 on the first substrate 30.

[0120] For example, the material of the common electrode 50 can be the same as the material of the pixel electrode 10, and the common electrode 50 can be a transparent electrode, and the material thereof can be an ITO (indium tin oxide) material, but is not limited thereto, and can also be made of transparent materials such as indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0121] In the embodiments of the present disclosure, the common electrode 50 can be a plate-shaped electrode, that is, no slits are formed on the common electrode 50, but is not limited thereto, and slits can also be formed, depending on the specific case.

[0122] The embodiments of the present disclosure also provide a display device, which can be a liquid crystal display device, but is not limited thereto. The display device of the embodiments of the present disclosure can include the array substrate described in any of the foregoing embodiments, which will not be repeated here.

[0123] The display device can also include a counter substrate (not shown in the figure) arranged opposite to the array substrate and a liquid crystal layer (not shown in the figure) between the array substrate and the counter substrate, and the liquid crystal molecules of the liquid crystal layer can be negative liquid crystals to improve the transmittance, but are not limited thereto, and can also be positive liquid crystals.

[0124] In the embodiments of the present disclosure, the display device can also include a spacer, which can be integrated on the counter substrate, but is not limited thereto, and can also be integrated on the array substrate, depending on the specific case.

[0125] The counter substrate of the present disclosure can include a second substrate (not shown in the figure) and a black matrix layer (not shown in the figure) on the side of the second substrate close to the array substrate, and the black matrix layer can have a shielding area and a light-transmitting area, the orthogonal projection of the shielding area on the first substrate 30 can completely cover the aforementioned data line 40, scan line 60, common line 70, transistor 20 of the sub-pixel, spacer, etc., and the shielding area can also cover the edges of the common electrode 50 and the pixel electrode 10; and the orthogonal projection of the light-transmitting area on the first substrate 30 can be located within the orthogonal projection of the common electrode 50 and the pixel electrode 10 on the first substrate 30.

[0126] In addition, the counter substrate of the present disclosure can further include a color filter layer, which can include red filter blocks, green filter blocks, blue filter blocks, and the like.

[0127] It should be noted that the color filter layer is not limited to being integrated in the counter substrate, but can also be integrated in the array substrate, depending on the specific case.

[0128] According to embodiments of the present disclosure, the specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as a television, a vehicle-mounted display, and the like. Those skilled in the art can select the display device according to the specific use of the display device, and thus the specific type of the display device is not described herein.

[0129] It should be noted that the display device, in addition to the array substrate, the counter substrate, and the liquid crystal layer mentioned above, further includes other necessary components and compositions. For example, the display device can further include a backlight module, a housing, a main circuit board, a power line, and the like. Those skilled in the art can supplement the display device according to the specific use requirements of the display device, and thus the specific type of the display device is not described herein.

[0130] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the specification and practice of the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following the general principles thereof and including any other modifications or implementations within the scope of the present disclosure. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein, It includes a first substrate (30) and sub-pixels located on the first substrate (30) and arranged in an array along a first direction (Y) and a second direction (X), wherein the sub-pixels include transistors (20) and pixel electrodes (10) connected to the transistors (20). The pixel electrode (10) includes a main conductive portion, which includes at least one first group of sub-conductive portions and at least one second group of sub-conductive portions, wherein the first group of sub-conductive portions and the second group of sub-conductive portions are alternately arranged in the first direction (Y). The first set of sub-conductive parts includes a first connecting strip (103), which extends in the first direction (Y) and has a first surface (103a) and a second surface (103b) opposite to each other in the second direction (X); the first set of sub-conductive parts has a first gap (S1) located on the side of the first surface (103a) away from the second surface (103b), and the end of the first gap (S1) away from the first connecting strip (103) is an open end; The second set of sub-conductive parts includes a second connecting strip (105) extending in the first direction (Y). The second connecting strip (105) is at least partially connected to one side of the first set of sub-conductive parts in the first direction (Y). The second connecting strip (105) has a third surface (105a) and a fourth surface (105b) opposite each other in the second direction (X). In the second direction (X), the third surface (105a) is located between the fourth surface (105b) and the first surface (103a). The second set of sub-conductive parts has a second gap (S2) located on the side of the third surface (105a) away from the fourth surface (105b). The end of the second gap (S2) away from the second connecting strip (105) is an open end. In the second direction (X), the pixel electrode (10) is configured such that its first connecting strip (103) is closer to the transistor (20) than its second connecting strip (105). Wherein, the sum of the lengths of the first connecting strips (103) in the at least one first group of sub-conductive parts is less than the sum of the lengths of the second connecting strips (105) in the at least one second group of sub-conductive parts; Wherein, the first direction (Y) intersects with the second direction (X); The ratio of the sum of the lengths of the first connecting strips (103) in at least one first group of sub-conductive parts to the sum of the lengths of the second connecting strips (105) in at least one second group of sub-conductive parts is 0.3 to 0.9; In at least one pixel electrode (10), the orthographic projection of the transistor (20) on the first substrate (30) and the orthographic projection of the first connecting strip (103) of the pixel electrode (10) on the first substrate (30) are arranged opposite to each other in the first direction (Y); The pixel electrode (10) further includes: a first edge conductive portion (101) and a second edge conductive portion (102) arranged at intervals in a first direction (Y), the main conductive portion being at least partially located between the first edge conductive portion (101) and the second edge conductive portion (102), and the main conductive portion being connected to the first edge conductive portion (101) and the second edge conductive portion (102) respectively; In the second direction (X), between two adjacent pixel electrodes (10): In one of the pixel electrodes (10): the first edge conductive portion (101) is connected to the transistor (20) at the end away from the second connecting strip (105) in the second direction (X), and the first edge conductive portion (101) is closer to the transistor (20) connected to the pixel electrode (10) than the second edge conductive portion (102). In another pixel electrode (10): the second edge conductive portion (102) is connected to the transistor (20) at the end away from the second connecting strip (105) in the second direction (X), and the second edge conductive portion (102) is closer to the transistor (20) connected to the pixel electrode (10) than the first edge conductive portion (101).

2. The array substrate according to claim 1, wherein, The first group of sub-conductive parts further includes a plurality of first electrode strips (104) arranged at intervals in the first direction (Y). The plurality of first electrode strips (104) are located on the first surface (103a) away from the second surface (103b) and are connected to the first surface (103a). There is a first gap (S1) between two adjacent first electrode strips (104). The second group of sub-conductive parts further includes a plurality of second electrode strips (106) spaced apart in the first direction (Y), the plurality of second electrode strips (106) being located on the third surface (105a) away from the fourth surface (105b) and connected to the third surface (105a); a second gap (S2) is provided between two adjacent second electrode strips (106). The third side (105a) of the second connecting strip (105) is connected to the end of the first electrode strip (104) closest to the second group of sub-conductive parts away from the first connecting strip (103).

3. The array substrate according to claim 2, wherein, The length of the first connecting strip (103) is less than the length of the second connecting strip (105).

4. The array substrate according to claim 3, wherein, The pixel electrode (10) further includes: a first edge conductive portion (101) and a second edge conductive portion (102) arranged at intervals in a first direction (Y), the main conductive portion being at least partially located between the first edge conductive portion (101) and the second edge conductive portion (102), and the main conductive portion being connected to the first edge conductive portion (101) and the second edge conductive portion (102) respectively; The main conductive part includes a first group of sub-conductive parts and a second group of conductive parts. The first edge conductive portion (101) is located on the side of the plurality of first electrode strips (104) away from the second group of sub-conductive portions, and is located on the first surface (103a) of the first connecting strip (103) away from the second surface (103b); the first edge conductive portion (101) is connected to the first surface (103a), and has a third gap (S3) with the adjacent first electrode strip (104), the end of the third gap (S3) away from the first connecting strip (103) being an open end; The second edge conductive portion (102) is located on the side of the plurality of second electrode strips (106) away from the first group of sub-conductive portions, and is located on the third surface (105a) of the second connecting strip (105) away from the fourth surface (105b); the second edge conductive portion (102) is connected to the third surface (105a), and has a fourth gap (S4) with the adjacent second electrode strip (106), the end of the fourth gap (S4) away from the second connecting strip (105) being an open end.

5. The array substrate according to claim 4, wherein, The first electrode strip (104), the first slit (S1), and the third slit (S3) extend in the same direction and intersect the first direction (Y) and the second direction (X); Furthermore, the second electrode strip (106), the second gap (S2), and the fourth gap (S4) extend in the same direction and intersect the first direction (Y) and the second direction (X).

6. The array substrate according to claim 5, wherein, The widths of the first electrode strip (104), the second electrode strip (106), the first gap (S1), the second gap (S2), the third gap (S3), and the fourth gap (S4) are equal.

7. The array substrate according to claim 6, wherein, The first electrode strip (104) and the second electrode strip (106) extend in the same direction, and there is a second gap (S2) between adjacent first electrode strips (104) and second electrode strips (106).

8. The array substrate according to claim 6, wherein, The extension direction of the first electrode strip (104) and the extension direction of the second electrode strip (106) are mirror images of each other about the second direction (X).

9. The array substrate according to claim 8, wherein, The second group of sub-conductive parts further includes an adjustment part (107), which is located on the side of the plurality of second electrode strips (106) near the first group of sub-conductive parts, and at a position on the third surface (105a) of the second connecting strip (105) away from the fourth surface (105b). The adjustment part (107) is connected to the third surface (105a) of the second connecting strip (105). A fifth gap (S5) is formed between the adjustment part (107) and the adjacent first electrode strip (104), and a sixth gap (S6) is formed between the adjustment part (107) and the adjacent second electrode strip (106). The fifth gap (S5) and the sixth gap (S6) are both open ends away from the second connecting strip (105); The fifth gap (S5) extends in the same direction as the first gap (S1) and has the same width. The sixth gap (S6) extends in the same direction as the second gap (S2) and has the same width.

10. The array substrate according to claim 9, wherein, The adjustment section (107) includes a first adjustment strip (107a) and a second adjustment strip (107b), wherein the first adjustment strip (107a) forms a fifth gap (S5) with the first electrode strip (104), and the second adjustment strip (107b) forms a sixth gap (S6) with the second electrode strip (106); wherein, The first adjustment strip (107a) extends in the same direction as the first electrode strip (104) and has the same width. The second adjustment strip (107b) extends in the same direction as the second electrode strip (106) and has the same width. The first adjustment bar (107a) and the second adjustment bar (107b) are connected at one end of their extension direction to the third surface (105a) of the second connecting bar (105), and the other ends are connected to each other.

11. The array substrate according to claim 1, wherein, It also includes multiple data lines (40) formed on the first substrate (30), the data lines (40) extending in the first direction (Y), and the data lines (40) and the sub-pixels are arranged alternately in the second direction (X); In the pixel electrode (10) of the sub-pixel, the distance between the first connecting strip (103) and the data line (40) closest to it is the first distance (h1), and the distance between the second connecting strip (105) and the data line (40) closest to it is the second distance (h2). The first distance (h1) and the second distance (h2) are equal.

12. The array substrate according to claim 11, wherein, The pixel electrode (10) further includes: a first edge conductive portion (101) and a second edge conductive portion (102) arranged at intervals in a first direction (Y), the main conductive portion being at least partially located between the first edge conductive portion (101) and the second edge conductive portion (102), and the main conductive portion being connected to the first edge conductive portion (101) and the second edge conductive portion (102) respectively; Each of the data lines (40) is connected to a transistor (20) on the same side of it in the second direction (X) and adjacent to each of the sub-pixels; The first electrode (201) and the second electrode (202) of the transistor (20) are disposed on the same layer as the data line (40) and are located on the side of the pixel electrode (10) close to the first substrate (30); the first electrode (201) of the transistor (20) is connected to the data line (40), and the second electrode (202) of the transistor (20) is connected to the second edge conductive part (102) or the first edge conductive part (101) of the pixel electrode (10) through a via (P).

13. The array substrate according to claim 12, wherein, The first electrode (201) and the second electrode (202) of the transistor (20) are arranged at intervals in the first direction (Y), and the distance between the first electrode (201) and the second electrode (202) in the first direction (Y) is a third distance (h3). The ratio of the sum of the lengths of the first connecting strips (103) in the at least one first group of conductive parts to the third spacing (h3) is 2 to 20.

14. The array substrate according to claim 12, wherein, The sub-pixel also includes a common electrode (50), located on the side of the pixel electrode (10) close to the first substrate (30) and insulated from the pixel electrode (10); Furthermore, the orthographic projection of the common electrode (50) on the first substrate (30) overlaps with the orthographic projection of the pixel electrode (10) on the first substrate (30), but does not overlap with the orthographic projection of the data line (40) on the first substrate (30).

15. The array substrate according to claim 14, wherein, The array substrate further includes a plurality of scan lines (60) and a plurality of common lines (70) formed on the first substrate (30) and extending in the second direction (X). The scan lines (60) and the common lines (70) are arranged alternately in the first direction (Y), and the orthographic projection of the scan lines (60) on the first substrate (30) does not overlap with the orthographic projection of the common lines (70) on the first substrate (30). The scan line (60) and the common line (70) are disposed on the same layer, and the scan line (60) and the common line (70) are located on the side of the data line (40) close to the first substrate (30) and are insulated from each other. Wherein, the sub-pixel is adjacent to the common line (70) on one side in the first direction (Y), and adjacent to the scan line (60) on the other side; Each scan line (60) is connected to the gate of a transistor (20) of each of the sub-pixels located on the same side of it in the first direction (Y) and adjacent thereto; Each of the common lines (70) is connected to a common electrode (50) of each of the sub-pixels located on the same side of it in the first direction (Y) and adjacent to it.

16. The array substrate according to claim 15, wherein, A portion of the scan line (60) forms the gate of the transistor (20), and the common electrode (50) is in contact with the common line (70).

17. A display device, wherein, It includes the array substrate as described in any one of claims 1 to 16 and the opposing substrate disposed opposite to the array substrate.

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