Mask layout, generation method thereof, related equipment and semiconductor structure

Abstract

The invention relates to a mask layout, a generation method thereof, related equipment and a semiconductor structure, the generation method of the mask layout comprises the following steps: providing an initial photoresist layout layer, the initial photoresist layout layer comprising a plurality of photoresist patterns arranged at intervals; and respectively setting corresponding auxiliary opening patterns in the plurality of photoresist patterns to form a target photoresist pattern layer. According to the generation method of the mask layout provided by the embodiment of the invention, the auxiliary opening pattern is arranged in the photoresist pattern of the initial photoresist layout layer so as to form the target photoresist pattern layer; according to the auxiliary opening pattern, the shrinkage amount of a photoresist layer formed by adopting a mask layout with a target photoresist layout layer subsequently in a target process can be reduced, the precision of the formed photoresist pattern is favorably improved, and the performance of a formed semiconductor structure is correspondingly favorably improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor integrated circuit manufacturing, and in particular to a mask layout and a generation method thereof, and related equipment and a semiconductor structure. Background Art

[0002] Photolithography is a crucial technology in semiconductor manufacturing. It can transfer patterns from the mask to the surface of the silicon wafer to form a semiconductor product that meets the design requirements.

[0003] The photolithography process includes an exposure step and a development step after the exposure step. In the exposure step, light is irradiated onto the silicon wafer coated with photoresist through the light-transmitting area of ​​the mask, and the photoresist undergoes a chemical reaction under the irradiation of light; in the development step, the photolithography pattern is formed by utilizing the different degrees of solubility of the photosensitive and non-photosensitive photoresists in the developer, and the mask pattern is transferred to the photoresist.

[0004] However, the photoresist layer formed by the photoresist plate layer generated by the existing method will shrink significantly in the subsequent target process, which affects the effect of the target process and reduces the performance of the formed semiconductor structure. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a mask pattern and a generation method thereof and related equipment and a semiconductor structure, which can reduce the shrinkage of the formed photoresist layer in the target process, improve the effect of the target process, and correspondingly improve the performance of the formed semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for generating a mask layout, comprising:

[0007] Providing an initial photoresist layer, wherein the initial photoresist layer includes a plurality of photoresist patterns arranged at intervals;

[0008] Corresponding auxiliary opening patterns are respectively arranged in the plurality of photoresist patterns to form a target photoresist layer.

[0009] Optionally, the step of respectively providing corresponding auxiliary opening patterns in the plurality of photoresist patterns comprises:

[0010] Acquire a non-exposed area within the photoresist pattern;

[0011] Based on the photoresist pattern and the non-exposed area, acquiring at least one exposeable area located in the photoresist pattern;

[0012] Based on the shrinkage rate of the photoresist layer and a preset photolithography process resolution limit, an auxiliary opening pattern located on the exposable area is arranged in the photoresist pattern.

[0013] Optionally, based on the shrinkage rate of the photoresist layer and a preset photolithography process resolution limit, the step of providing an auxiliary opening pattern located on the exposable area in the photoresist pattern includes:

[0014] Obtaining the size of the exposable area;

[0015] If the size of the exposable area meets the resolution limit of the photolithography process, an initial opening pattern smaller than the exposable area is arranged on the exposable area according to the shrinkage rate of the photoresist layer, so that the initial opening formed by the initial opening pattern and located in the photoresist layer exposes at most the exposable area in the target process;

[0016] If it is determined that the initial opening pattern meets the resolution limit of the photolithography process, using the initial opening pattern as the auxiliary opening pattern;

[0017] If it is determined that the initial opening pattern does not meet the photolithography process resolution limit, the portion of the initial opening pattern that does not meet the photolithography process resolution limit is deleted, and only the portion of the initial opening pattern that meets the photolithography process resolution limit is retained as the auxiliary opening pattern.

[0018] Optionally, after determining that the initial opening pattern meets the photolithography process resolution limit or deleting a portion of the initial opening pattern that does not meet the photolithography process resolution limit and retaining only a portion of the initial opening pattern that meets the photolithography process resolution limit, the step of providing an auxiliary opening pattern located on the exposable area in the photoresist pattern based on the shrinkage rate of the photoresist layer and the photolithography process resolution limit further includes:

[0019] Obtaining the center line of the initial opening pattern;

[0020] The center line is taken as the center line and expanded outward along both sides of the center line respectively, and a minimum opening pattern that meets the resolution limit of the photolithography process is obtained in the initial opening pattern as the final auxiliary opening pattern.

[0021] Optionally, the shrinkage rate of the photoresist layer is related to the material of the photoresist layer and the target process using the photoresist layer.

[0022] Optionally, the target process includes an ion implantation process and a drying process.

[0023] Optionally, after respectively setting corresponding auxiliary opening patterns in the plurality of photoresist patterns, the method for generating a mask pattern further includes: deleting part of the auxiliary opening patterns so that the design layout of the target photoresist layer meets preset requirements.

[0024] Optionally, the auxiliary opening pattern is a polygon.

[0025] Accordingly, an embodiment of the present invention further provides a device for generating a mask pattern, comprising:

[0026] A layer providing unit, adapted to provide an initial photoresist layer, wherein the initial photoresist layer comprises a plurality of photoresist patterns arranged at intervals;

[0027] The setting unit is adapted to respectively set corresponding auxiliary opening patterns in the plurality of photoresist patterns to form a target photoresist layer.

[0028] Optionally, the setting unit is suitable for obtaining a non-exposed area located within the photoresist pattern; based on the photoresist pattern and the non-exposed area, obtaining at least one exposeable area located within the photoresist pattern; and based on the shrinkage rate of the photoresist layer and a preset photolithography process resolution limit, setting an auxiliary opening pattern located on the exposeable area within the photoresist pattern.

[0029] Optionally, the setting unit is suitable for obtaining the size of the exposeable area; if the size of the exposeable area meets the resolution limit of the photolithography process, an initial opening pattern smaller than the exposeable area is set on the exposeable area according to the shrinkage rate of the photoresist layer, so that the initial opening formed in the photoresist layer using the initial opening pattern exposes at most the exposeable area in the target process; if the initial opening pattern meets the resolution limit of the photolithography process, the initial opening pattern is used as the auxiliary opening pattern; if it is determined that the initial opening pattern does not meet the resolution limit of the photolithography process, the part of the initial opening pattern that does not meet the resolution limit of the photolithography process is deleted, and only the part of the initial opening pattern that meets the resolution limit of the photolithography process is retained as the auxiliary opening pattern.

[0030] Optionally, the setting unit is also suitable for obtaining the center line of the initial opening pattern after determining that the initial opening pattern meets the resolution limit of the photolithography process or deleting the part of the initial opening pattern that does not meet the resolution limit of the photolithography process and only retaining the part of the initial opening pattern that meets the resolution limit of the photolithography process; taking the center line as the center line and expanding outward along both sides of the center line respectively, to obtain the minimum opening pattern that meets the resolution limit of the photolithography process within the initial opening pattern as the final auxiliary opening pattern.

[0031] Optionally, the shrinkage rate of the photoresist layer is related to the material of the photoresist layer and the target process using the photoresist layer.

[0032] Optionally, the target process includes an ion implantation process and a drying process.

[0033] Optionally, the mask plate pattern generating device further comprises: a deleting unit adapted to delete part of the auxiliary opening patterns after respectively setting corresponding auxiliary opening patterns in the plurality of photoresist patterns, so that the design layout of the target photoresist plate layer meets preset requirements.

[0034] Optionally, the auxiliary opening pattern is a polygon.

[0035] Correspondingly, an embodiment of the present invention further provides a mask pattern, comprising a target photoresist layer generated by using any of the mask pattern generation methods described above.

[0036] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including a photoresist pattern formed by using the mask pattern as described above.

[0037] Correspondingly, an embodiment of the present invention also provides a device, comprising at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method for generating a mask plate pattern as described in any one of the above items.

[0038] Correspondingly, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the method for generating a mask layout as described in any one of the above items.

[0039] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0040] An embodiment of the present invention provides a method for generating a mask pattern, comprising: providing an initial photoresist layer, the initial photoresist layer comprising a plurality of spaced photoresist patterns; and setting corresponding auxiliary opening patterns in the plurality of photoresist patterns to form a target photoresist layer.

[0041] The method for generating a mask pattern provided in an embodiment of the present invention forms a target photoresist pattern layer by setting an auxiliary opening pattern in the photoresist pattern of the initial photoresist layer. The auxiliary opening pattern can reduce the shrinkage of the photoresist layer subsequently formed using the mask pattern having the target photoresist layer in the target process, which helps to improve the accuracy of the formed photoresist pattern and correspondingly helps to improve the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a flow chart of an embodiment of a method for generating a mask layout provided by the technical solution of the present invention;

[0043] Figure 2 is a schematic diagram of a photoresist pattern in an initial photoresist layer and a photoresist layer formed by using the photoresist pattern in an embodiment of the present invention;

[0044] Figure 3 is a schematic diagram of a photoresist pattern and an auxiliary opening pattern arranged therein;

[0045] Figure 4 is a schematic diagram of a process of respectively setting corresponding auxiliary opening patterns in the plurality of photoresist patterns in an embodiment of the present invention;

[0046] Figure 5 It is a structural schematic diagram of a mask pattern generating device in an embodiment of the present invention;

[0047] Figure 6 It is a schematic diagram of an optional hardware structure of a terminal device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] As can be seen from the background art, the photoresist pattern formed by the current process has a large shrinkage in the target process, which correspondingly reduces the execution accuracy of the target process and reduces the performance of the formed semiconductor structure.

[0049] In order to solve the technical problem, an embodiment of the present invention provides a method for generating a mask pattern, including: providing an initial photoresist layer, the initial photoresist layer including a plurality of spaced-apart photoresist patterns; and respectively setting corresponding auxiliary opening patterns in the plurality of photoresist patterns to form a target photoresist layer.

[0050] The method for generating a mask pattern provided in an embodiment of the present invention forms a target photoresist pattern layer by setting an auxiliary opening pattern in the photoresist pattern of the initial photoresist layer. The auxiliary opening pattern can reduce the shrinkage of the photoresist layer subsequently formed using the mask pattern having the target photoresist layer in the target process, which helps to improve the accuracy of the formed photoresist pattern and correspondingly helps to improve the performance of the formed semiconductor structure.

[0051] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0052] Figure 1 The flowchart of an embodiment of a method for generating a mask layout provided by the technical solution of the present invention is shown. Figure 1 , a method for generating a mask layout, which may specifically include:

[0053] Step S110: providing an initial photoresist layer, wherein the initial photoresist layer comprises a plurality of photoresist patterns arranged at intervals;

[0054] Step S120: respectively setting corresponding auxiliary opening patterns in the plurality of photoresist patterns to form a target photoresist layer.

[0055] Figure 2 FIG. 1 is a schematic diagram showing a photoresist pattern in an initial photoresist layer and a photoresist layer formed by using the photoresist pattern in an embodiment of the present invention. Figure 1 to Figure 2 , executing step S110, providing an initial photoresist layer (not shown), wherein the initial photoresist layer includes a plurality of photoresist patterns 200 arranged at intervals.

[0056] In this embodiment, the photoresist pattern 200 provides a basis for subsequently setting an auxiliary opening pattern therein to form a target photoresist layer.

[0057] The photoresist pattern 200 is used to form an initial photoresist layer on the target film layer of the formed semiconductor structure. The initial photoresist layer is located on the target film layer, and accordingly, the initial photoresist layer can cover a portion of the target film layer located therebelow, while exposing the rest of the target film layer.

[0058] In the subsequent process of performing the target process on the target film layer, the initial photoresist layer can shield the target film layer it covers, thereby protecting the portion of the target film layer located underneath it, so that the target process is only applied to the area of ​​the target film layer exposed by the photoresist layer.

[0059] However, in the process of executing the target process on the target film layer, the initial photoresist layer will be affected by the target process and shrink, so that part of the target film layer that should have been shielded by the initial photoresist layer is exposed to the target process, thereby affecting the effect of the target process and reducing the performance of the formed semiconductor structure.

[0060] To this end, corresponding auxiliary graphic openings are subsequently set in each photoresist graphic 200 in the initial photoresist layer to reduce the shrinkage of the target photoresist layer finally formed in the target process, so that the formed target photoresist layer can play a good shielding role on the partial area of ​​the target film layer that should not be exposed in the target process, which correspondingly helps to improve the effect of the target process, thereby helping to improve the performance of the formed semiconductor structure.

[0061] In this embodiment, in the initial photoresist layer, a plurality of photoresist patterns 200 are arranged at intervals. In other words, in the initial photoresist layer, a plurality of photoresist patterns 200 are independent of each other, and there is an interval between adjacent photoresist patterns 200 in the plurality of photoresist patterns 200.

[0062] The spacing distance between adjacent photoresist patterns 200 can be set according to actual process requirements. Specifically, the spacing distance between adjacent photoresist patterns 200 can be set according to the shielding requirements of the target film layer.

[0063] Figure 3 A schematic diagram showing a photoresist pattern and an auxiliary opening pattern arranged therein; Figure 4 FIG. 1 is a schematic diagram showing a process of respectively setting corresponding auxiliary opening patterns in the plurality of photoresist patterns in an embodiment of the present invention. Figures 1 to 4 , executing step S120, respectively setting corresponding auxiliary opening patterns 210 in the plurality of photoresist patterns 200 to form a target photoresist layer.

[0064] In this embodiment, corresponding auxiliary opening patterns 210 are respectively set in the multiple photoresist patterns 200. The auxiliary opening patterns 210 can reduce the shrinkage of the photoresist patterns 200 in the target process, thereby improving the effect of the target process and correspondingly improving the performance of the formed semiconductor structure.

[0065] Specifically, for a photoresist layer with a specific area (or volume), its total shrinkage can be calculated by the shrinkage of its edge segments. Specifically, it can be calculated using the following formula:

[0066]

[0067] And the constraints are:

[0068]

[0069] Where ΔA shrikage Indicates the shrinkage of the photoresist layer, l i represents the length of the i-th edge segment of the photoresist layer, Δω i represents the shrinkage of the ith edge segment of the photoresist layer, represents the average shrinkage of the edge segments in the photoresist layer, and n represents the number of edge segments included in the photoresist layer.

[0070] It should be pointed out that the constraint condition represented by the above formula (2) indicates that the average shrinkage of the edge segment in the photoresist layer should be much smaller than the perimeter of the photoresist layer. Accordingly, the influence of tangential shrinkage and corners can be ignored to simplify the calculation formula of the shrinkage of the photoresist layer.

[0071] It can be seen from the above formula (1) and formula (2) that the shrinkage amount of each edge segment in the photoresist layer is relatively uniform. In other words, the variation between the shrinkage amounts of each edge segment in the photoresist layer is small.

[0072] When the shrinkage amount of each edge segment in the photoresist layer is relatively consistent, by setting the auxiliary opening pattern 210 in the photoresist pattern 200, the area of ​​the auxiliary opening pattern 210 is much smaller than the area of ​​the corresponding photoresist pattern 200, so that the shrinkage amount related to the area (or volume) of the auxiliary opening pattern 210 in the photoresist pattern 200 will not be affected.

[0073] Combined with reference Figure 3 From a local perspective, before the auxiliary opening pattern 210 is provided, the edge segment l of the photoresist pattern 200 i The corresponding shrinkage is the shrinkage amount corresponding to the edge segment l in the photoresist pattern 200. i After setting the auxiliary opening pattern 210, the edge segment of the photoresist pattern 200 l i The corresponding shrinkage is the shrinkage amount corresponding to the edge segment l in the photoresist pattern 200. i The shrinkage of region S2 is smaller than that of region S1. i The number of edge segments remains unchanged. i The corresponding area of ​​the photoresist pattern 200 is reduced, and accordingly each edge segment l i When the shrinkage amount is reduced, the photoresist pattern 200 has a smaller shrinkage amount.

[0074] On the other hand, according to the above formula (1), the setting of the auxiliary opening pattern 210 increases the total edge length of the corresponding light blocking pattern 200, and accordingly increases the length of each edge segment l of the corresponding light blocking pattern 200. i The average shrinkage The shrinkage amount of the photoresist pattern 200 is reduced.

[0075] In summary, by respectively setting corresponding auxiliary opening patterns 210 in the multiple photoresist patterns 200 of the initial photoresist layer, it is possible to reduce the shrinkage of the photoresist layer subsequently formed by using a mask pattern having a target photoresist layer in the target process, thereby helping to improve the accuracy of the formed photoresist layer pattern, and correspondingly helping to improve the performance of the formed semiconductor structure.

[0076] It should be noted that setting the corresponding auxiliary opening pattern 210 in the photoresist pattern 200 will lead to a change in the design layout of the target photoresist layer that is finally formed. At the same time, after the corresponding photoresist layer is formed, a portion of the target film layer corresponding to the auxiliary opening pattern 210 will be located outside the coverage area of ​​the formed photoresist layer, that is, a portion of the target film layer corresponding to the auxiliary opening pattern 210 will be exposed to the subsequent target process. Therefore, it is necessary to determine a suitable position for setting the auxiliary opening pattern 210 in the photoresist pattern 200.

[0077] See also Figure 4 In this embodiment, the step of setting the corresponding auxiliary opening pattern 210 in the photoresist pattern 200 includes: Figure 4 As shown in (a), a non-exposed area 201 located in the photoresist pattern 200 is obtained; Figure 4 As shown in (b), based on the photoresist pattern 200 and the non-exposed area 201, an exposable area 202 located in the photoresist pattern is obtained; Figure 4 As shown in (c) and 4(d), based on the shrinkage rate of the photoresist layer and the preset photolithography process resolution limit, a corresponding auxiliary opening pattern 210 is set on the exposable area 202 within the photoresist pattern 200.

[0078] The non-exposed area 201 in the photoresist pattern 200 is the non-active area of ​​the target process when the target process is subsequently performed on the target film layer. Correspondingly, the exposed area 202 in the photoresist pattern 200 is the active area of ​​the target process when the target process is subsequently performed on the target film layer.

[0079] In this embodiment, based on the photoresist pattern 200 and the non-exposed area 201, a Boolean operation is used to obtain the exposeable area 202 located in the photoresist pattern. Specifically, the Boolean operation is a logical negation operation.

[0080] It should be noted that there may be one or more non-exposed areas 201 in the photoresist pattern 200. When there are multiple non-exposed areas 201, the multiple non-exposed areas 201 are arranged at intervals.

[0081] Similarly, there may be one or more exposable regions 202 in the photoresist pattern 200. When there are multiple exposable regions 202, the multiple exposable regions 202 are arranged at intervals.

[0082] In this embodiment, the target process is an ion implantation process. Accordingly, the non-exposed area 201 in the photoresist pattern 200 is a non-ion implantation area, and the exposed area 202 in the photoresist pattern 200 is an ion implantation area.

[0083] For example, when the source-drain injection process is performed on the substrate on both sides of the gate structure, if the initial photoresist layer is used as the photoresist layer of the mask for the source-drain injection process, the photoresist layer also covers part of the gate structure. In fact, the existence of the gate structure can protect the substrate area below the gate structure from the influence of the source-drain injection process, that is, the gate structure can be used as a mask for performing the source-drain injection process. At this time, in the initial photoresist layer, the area in the photoresist pattern corresponding to the photoresist layer covering part of the gate structure is the exposed area in the photoresist pattern.

[0084] In other embodiments, the target process may also be a baking process or other process that can cause the photoresist layer to shrink.

[0085] In this embodiment, based on the shrinkage rate of the photoresist layer and the preset photolithography process resolution limit, the step of setting the corresponding auxiliary opening pattern 210 on the exposeable area 202 in the photoresist pattern 200 includes: obtaining the size of the exposeable area 202; if the size of the exposeable area 202 meets the photolithography process resolution limit, setting an initial opening pattern 210' smaller than the exposeable area 202 on the exposeable area 202 according to the shrinkage rate of the photoresist layer, so that the initial opening formed in the photoresist layer using the initial opening pattern 210' exposes at most the exposeable area 202 in the target process; if it is determined that the initial opening pattern 210' meets the photolithography process resolution limit, using the initial opening pattern 210' as the auxiliary opening pattern 210; if it is determined that the initial opening pattern 210' does not meet the photolithography process resolution limit, deleting the portion of the initial opening pattern 210' that does not meet the photolithography process resolution limit, and only retaining the portion of the initial opening pattern 210' that meets the photolithography process resolution limit as the auxiliary opening pattern 210.

[0086] The size of the exposeable area 202 is obtained, so that it can be determined whether a corresponding auxiliary opening pattern 210 can be set on the exposeable area 202 according to the size of the exposeable area 202.

[0087] Specifically, if an auxiliary pattern opening is set on the exposable region 202, after the photoresist layer is formed, the photoresist layer will shrink to a certain extent in the target process, so that the initial opening formed by the auxiliary pattern opening on the exposable region 202 expands outward, that is, the size of the initial opening increases. Therefore, the size of the initial opening pattern 210' needs to be smaller than the size of the corresponding exposable region 202, so that the initial opening formed by the initial opening pattern 210' in the photoresist layer can at most expose the exposable region 202 in the target process.

[0088] Accordingly, since the initial opening pattern 210' needs to be smaller than the size of the exposable area 202, when the size of the exposable area 202 is smaller than the resolution limit of the photolithography process, the initial opening pattern 210' will also be smaller than the resolution limit of the photolithography process, so that when the photoresist pattern is subsequently formed using the photoresist plate layer, the initial opening pattern 210' cannot meet the resolution limit of the photolithography process, resulting in the initial opening pattern 210' being unable to form a corresponding initial opening in the photoresist layer. Therefore, when the size of the exposable area 202 is smaller than the resolution limit of the photolithography process, the corresponding initial opening pattern 210' is not set on the exposable area 202.

[0089] See also Figure 4 (b) and Figure 4 (c) One of the exposed regions 202 is smaller than the resolution limit of the photolithography process, and therefore no initial opening pattern 210 ′ is correspondingly disposed on the exposed region 202 .

[0090] When the size of the exposeable area 202 is larger than the resolution limit of the photolithography process and the shrinkage rate of the photoresist layer is taken into consideration, if an initial opening pattern 210' is set on the exposeable area 202, the set initial opening pattern 210' may meet the resolution limit of the photolithography process, or at least part of the initial opening pattern 210' may not meet the resolution limit of the photolithography process.

[0091] Therefore, when the size of the exposeable area 202 is larger than the resolution limit of the photolithography process and taking into account the shrinkage rate of the photoresist layer, if after setting the corresponding initial opening pattern 210' on the exposeable area 202, the size of the initial opening pattern 210' cannot meet the resolution limit of the photolithography process, the portion of the initial opening pattern 210' that cannot meet the resolution limit of the photolithography process is deleted, and only the portion of the initial opening pattern 210' that meets the resolution limit of the photolithography process is retained; if the size of the initial opening pattern 210' can meet the resolution limit of the photolithography process, the corresponding initial opening pattern 210' is set on the exposeable area 202.

[0092] In this embodiment, after determining that the initial opening pattern 210' meets the resolution limit of the photolithography process or deleting the portion of the initial opening pattern 210' that does not meet the resolution limit of the photolithography process and retaining only the portion of the initial opening pattern 210' that meets the resolution limit of the photolithography process, based on the shrinkage rate of the photoresist layer and the preset photolithography process resolution limit, the step of setting the corresponding auxiliary opening pattern 210 on the exposeable area 202 in the photoresist pattern 200 also includes: obtaining the center line C of the initial opening pattern 210'; taking the center line C as the center line and expanding outward along both sides of the center line C, respectively, to obtain the minimum opening pattern that meets the resolution limit of the photolithography process in the initial opening pattern 210' as the final auxiliary opening pattern 210.

[0093] After the initial opening pattern 210' is set in the photoresist pattern 200, the initial opening pattern 210' may split the photoresist pattern 200 into multiple parts, which accordingly changes the design layout of the target photoresist layer. The design layout of the target photoresist layer includes at least one of the pattern shape, pattern spacing and pattern density.

[0094] Taking the center line C of the initial opening pattern 210' as the center line, the pattern is expanded outward along both sides of the center line C, and the minimum opening pattern that meets the resolution limit of the photolithography process is obtained within the initial opening pattern 210' as the final auxiliary opening pattern 210. This can make the size of the set auxiliary opening pattern 210 as small as possible, thereby minimizing the impact of the set auxiliary opening pattern 210 on the design layout of the target photoresist layer.

[0095] In this embodiment, after the corresponding auxiliary opening patterns 210 are respectively provided in the plurality of photoresist patterns, the method for generating the mask pattern further includes:

[0096] Step S130 is executed to delete part of the auxiliary opening patterns in the target photoresist layer so that the design layout in the target photoresist layer meets the preset requirements.

[0097] As mentioned above, after the initial opening pattern 210 ′ is set in the photoresist pattern 200 , the initial opening pattern 210 ′ may split one photoresist pattern 200 into multiple parts, which accordingly changes the design layout of the formed target photoresist layer.

[0098] Therefore, after the corresponding auxiliary opening patterns 210 are set in the plurality of photoresist patterns 200, part of the auxiliary opening patterns 210 in the target photoresist layer is deleted so that the design layout in the target photoresist layer meets the preset requirements.

[0099] Specifically, after the corresponding auxiliary opening patterns 210 are arranged in the plurality of photoresist patterns 200 , at least one of the pattern shape, pattern spacing and pattern density in the formed target photoresist layer may fail to meet the photolithography resolution limit.

[0100] Accordingly, the preset requirements include preset requirements for photolithography resolution limits.

[0101] It should be noted that the photolithography resolution limit refers to the patterns that can be distinguished by the exposure process in the photolithography process, the minimum spacing between patterns, and the minimum density of patterns.

[0102] Accordingly, in a specific process, the photolithography resolution limit is determined based on actual photolithography process equipment, process conditions, etc., and the specific value of the photolithography resolution limit is not limited in this embodiment.

[0103] Correspondingly, an embodiment of the present invention further provides a device for generating a mask pattern.

[0104] Figure 5 FIG. 1 is a schematic diagram showing the structure of a device for generating a mask pattern in an embodiment of the present invention. Figure 5 A mask plate pattern generating device 50 may include: a layer providing unit 501, adapted to provide an initial photoresist plate layer, the initial photoresist plate layer comprising a plurality of spaced photoresist patterns; a setting unit 502, adapted to respectively set corresponding auxiliary opening patterns in the plurality of photoresist patterns to form a target photoresist plate layer.

[0105] In this embodiment, the setting unit 502 is suitable for obtaining a non-exposed area located in the photoresist pattern; based on the photoresist pattern and the non-exposed area, obtaining at least one exposeable area located in the photoresist pattern; based on the shrinkage rate of the photoresist layer and the preset photolithography process resolution limit, setting an auxiliary opening pattern located on the exposeable area in the photoresist pattern.

[0106] In this embodiment, the setting unit 502 is suitable for obtaining the size of the exposeable area; if the size of the exposeable area is larger than the resolution limit of the photolithography process, a corresponding initial opening pattern is set on the exposeable area according to the shrinkage rate of the photoresist layer, so that the initial opening pattern in the shrunk photoresist pattern exposes at most the entire exposeable area; if the initial opening pattern meets the resolution limit of the photolithography process, the initial opening pattern is used as the auxiliary opening pattern; if it is determined that the initial opening pattern does not meet the resolution limit of the photolithography process, the portion of the initial opening pattern that does not meet the resolution limit of the photolithography process is deleted, and only the portion of the initial opening pattern that meets the resolution limit of the photolithography process is retained as the auxiliary opening pattern.

[0107] In this embodiment, the setting unit 502 is also suitable for obtaining the center line of the initial opening pattern after determining that the initial opening pattern meets the resolution limit of the photolithography process or deleting the part of the initial opening pattern that does not meet the resolution limit of the photolithography process and only retaining the part of the initial opening pattern that meets the resolution limit of the photolithography process; expanding outward along both sides of the center line with the center line as the center, and obtaining the minimum opening pattern that meets the resolution limit of the photolithography process within the initial opening pattern as the final auxiliary opening pattern.

[0108] In this embodiment, the shrinkage rate of the photoresist layer is related to the material of the photoresist layer and the target process using the photoresist layer.

[0109] In this embodiment, the target process includes an ion implantation process and a drying process.

[0110] In this embodiment, the auxiliary opening pattern is a polygon or a ring.

[0111] In this embodiment, the mask plate pattern generating device 50 also includes: a deleting unit 503, which is suitable for deleting part of the auxiliary opening patterns after setting corresponding auxiliary opening patterns in the multiple photoresist patterns respectively, so that the design layout of the target photoresist plate layer meets the preset requirements.

[0112] The mask generation device in the embodiment of the present invention can be used to execute the aforementioned mask generation method, or other devices can be used to execute the aforementioned mask generation method. For the mask generation method, please refer to the detailed description of the aforementioned part, which will not be repeated here.

[0113] Correspondingly, an embodiment of the present invention further provides a mask pattern, including a target photoresist layer generated by the mask pattern generation method. The mask pattern generation method is described in detail in the above part and will not be described again.

[0114] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including a photoresist pattern formed by using the mask pattern as described above. The mask pattern is described in detail in the above part and will not be described in detail again.

[0115] An embodiment of the present invention further provides a device, which can execute the above-mentioned method for generating a mask layout in the form of a loading program.

[0116] An optional hardware structure of the terminal device provided by the embodiment of the present invention can be as follows Figure 6 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.

[0117] In the embodiment of the present invention, the number of the processor 01 , the communication interface 02 , the memory 03 , and the communication bus 04 is at least one, and the processor 01 , the communication interface 02 , and the memory 03 communicate with each other through the communication bus 04 .

[0118] The communication interface 02 may be an interface of a communication module for network communication, such as an interface of a GSM module.

[0119] The processor 01 may be a central processing unit CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0120] The memory 03 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0121] The memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the method for generating a mask layout according to an embodiment of the present invention.

[0122] It should be noted that the above-mentioned terminal device may also include other devices (not shown) that may not be necessary for understanding the contents disclosed in the embodiments of the present invention; given that these other devices may not be necessary for understanding the contents disclosed in the embodiments of the present invention, the embodiments of the present invention will not introduce them one by one.

[0123] An embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the method for generating a mask layout provided by the embodiment of the present invention.

[0124] The above-mentioned embodiments of the present invention are combinations of elements and features of the present invention. Unless otherwise mentioned, the elements or features may be considered as optional. Each element or feature may be put into practice without being combined with other elements or features. In addition, the embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some constructions of any one embodiment may be included in another embodiment, and may be replaced by the corresponding construction of another embodiment. It is obvious to those skilled in the art that claims that do not have a clear reference relationship to each other in the attached claims may be combined into embodiments of the present invention, or may be included as new claims in the amendment after submitting this application.

[0125] The embodiments of the present invention can be implemented by various means such as hardware, firmware, software or a combination thereof. In a hardware configuration, the method according to the exemplary embodiment of the present invention can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0126] In a firmware or software configuration, the embodiments of the present invention may be implemented in the form of modules, procedures, functions, etc. The software code may be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and may send data to and receive data from the processor via various known means.

[0127] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0128] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for generating a mask layout, characterized in that: include: Providing an initial photoresist layer, wherein the initial photoresist layer includes a plurality of photoresist patterns arranged at intervals; Corresponding auxiliary opening patterns are respectively arranged in the plurality of photoresist patterns to form a target photoresist layer.

2. The method for generating a mask layout according to claim 1, characterized in that: The steps of respectively setting corresponding auxiliary opening patterns in the plurality of photoresist patterns include: Acquire a non-exposed area within the photoresist pattern; Based on the photoresist pattern and the non-exposed area, acquiring at least one exposeable area located in the photoresist pattern; Based on the shrinkage rate of the photoresist layer and a preset photolithography process resolution limit, an auxiliary opening pattern located on the exposable area is arranged in the photoresist pattern.

3. The method for generating a mask pattern according to claim 2, characterized in that: Based on the shrinkage rate of the photoresist layer and the preset photolithography process resolution limit, the step of providing an auxiliary opening pattern located on the exposable area in the photoresist pattern comprises: Obtaining the size of the exposable area; If the size of the exposable area meets the resolution limit of the photolithography process, an initial opening pattern smaller than the exposable area is arranged on the exposable area according to the shrinkage rate of the photoresist layer, so that the initial opening formed by the initial opening pattern and located in the photoresist layer exposes at most the exposable area in the target process; If it is determined that the initial opening pattern meets the resolution limit of the photolithography process, using the initial opening pattern as the auxiliary opening pattern; If it is determined that the initial opening pattern does not meet the photolithography process resolution limit, the portion of the initial opening pattern that does not meet the photolithography process resolution limit is deleted, and only the portion of the initial opening pattern that meets the photolithography process resolution limit is retained as the auxiliary opening pattern.

4. The method for generating a mask layout according to claim 3, characterized in that: After determining that the initial opening pattern meets the photolithography process resolution limit or deleting a portion of the initial opening pattern that does not meet the photolithography process resolution limit and retaining only a portion of the initial opening pattern that meets the photolithography process resolution limit, the step of providing an auxiliary opening pattern located on the exposable area in the photoresist pattern based on the shrinkage rate of the photoresist layer and the photolithography process resolution limit further includes: Obtaining the center line of the initial opening pattern; The center line is taken as the center line and expanded outward along both sides of the center line respectively, and a minimum opening pattern that meets the resolution limit of the photolithography process is obtained in the initial opening pattern as the final auxiliary opening pattern.

5. The method for generating a mask pattern according to claim 3, characterized in that: The shrinkage rate of the photoresist layer is related to the material of the photoresist layer and the target process using the photoresist layer.

6. The method for generating a mask layout according to claim 3, characterized in that: The target process includes an ion implantation process and a drying process.

7. The method for generating a mask pattern according to any one of claims 1 to 6, characterized in that: After respectively setting corresponding auxiliary opening patterns in the plurality of photoresist patterns, the method further includes: deleting part of the auxiliary opening patterns so that the design layout of the target photoresist layer meets preset requirements.

8. The method for generating a mask layout according to claim 1, characterized in that: The auxiliary opening pattern is a polygon.

9. A device for generating a mask pattern, characterized in that: include: A layer providing unit, adapted to provide an initial photoresist layer, wherein the initial photoresist layer comprises a plurality of photoresist patterns arranged at intervals; The setting unit is adapted to respectively set corresponding auxiliary opening patterns in the plurality of photoresist patterns to form a target photoresist layer.

10. The device for generating a mask pattern according to claim 9, characterized in that: The setting unit is adapted to obtain a non-exposed area located in the photoresist pattern; based on the photoresist pattern and the non-exposed area, obtain at least one exposable area located in the photoresist pattern; Based on the shrinkage rate of the photoresist layer and a preset photolithography process resolution limit, an auxiliary opening pattern located on the exposable area is arranged in the photoresist pattern.

11. The device for generating a mask pattern according to claim 10, characterized in that: The setting unit is adapted to obtain the size of the exposeable area; if the size of the exposeable area meets the resolution limit of the photolithography process, an initial opening pattern smaller than the exposeable area is set on the exposeable area according to the shrinkage rate of the photoresist layer, so that the initial opening formed by the initial opening pattern and located in the photoresist layer exposes at most the exposeable area in the target process; If the initial opening pattern meets the photolithography process resolution limit, using the initial opening pattern as the auxiliary opening pattern; If it is determined that the initial opening pattern does not meet the photolithography process resolution limit, the portion of the initial opening pattern that does not meet the photolithography process resolution limit is deleted, and only the portion of the initial opening pattern that meets the photolithography process resolution limit is retained as the auxiliary opening pattern.

12. The device for generating a mask pattern according to claim 10, characterized in that: The setting unit is also suitable for obtaining the center line of the initial opening pattern after determining that the initial opening pattern meets the resolution limit of the photolithography process or deleting the part of the initial opening pattern that does not meet the resolution limit of the photolithography process and only retaining the part of the initial opening pattern that meets the resolution limit of the photolithography process; taking the center line as the center line and expanding outward along both sides of the center line respectively, to obtain the minimum opening pattern that meets the resolution limit of the photolithography process in the initial opening pattern as the final auxiliary opening pattern.

13. The device for generating a mask pattern according to claim 10, characterized in that: The shrinkage rate of the photoresist layer is related to the material of the photoresist layer and the target process using the photoresist layer.

14. The device for generating a mask pattern according to claim 10, characterized in that: The target process includes an ion implantation process and a drying process.

15. The device for generating a mask pattern according to any one of claims 9 to 14, characterized in that: Also includes: The deleting unit is adapted to delete part of the auxiliary opening patterns after the corresponding auxiliary opening patterns are respectively set in the plurality of photoresist patterns, so that the design layout of the target photoresist layer meets the preset requirements.

16. The device for generating a mask pattern according to claim 9, characterized in that: The auxiliary opening pattern is a polygon.

17. A mask layout, characterized in that: It comprises a target photoresist layer generated by the mask pattern generation method according to any one of claims 1 to 8.

18. A semiconductor structure, characterized in that: It includes a photoresist pattern formed using the mask pattern as claimed in claim 17.

19. A device, characterized in that The method comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method for generating a mask layout according to any one of claims 1 to 8.

20. A storage medium, characterized in that: The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the method for generating a mask pattern as described in any one of claims 1-8.

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