Regulator, electronic system including regulator and method of operating regulator

Abstract

The invention provides a voltage regulator, an operation method of the voltage regulator, and an electronic system. The regulator configured to generate an output voltage includes: a comparison unit configured to generate a second voltage based on a reference voltage and a first voltage generated by feedback of the output voltage; a power supply noise copy buffer unit configured to generate a third voltage including power supply noise copied based on the second voltage; and a pass transistor configured to generate an output voltage in response to the third voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0136274 filed on October 12, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to elements for power management of a device, and more particularly, to a voltage regulator, an electronic system including the voltage regulator, and an operating method of the voltage regulator. Background Art

[0004] A power management integrated circuit (PMIC) can generate a supply voltage to provide power to electronic components. The level of the supply voltage can be determined based on the performance of each electronic component. The power management integrated circuit may include a regulator that generates various levels of supply voltage. A regulator refers to a circuit that converts power input from the outside of the PMIC into direct current (DC) power used by the system by using a power switch. The regulator may include a DC-DC converter for stepping up or down the input DC power as a power regulator. Depending on the operating mode of the regulator, the regulator can be classified as a linear regulator or a switching regulator. Summary of the invention

[0005] Embodiments of the present disclosure provide a voltage regulator having a simple structure while supporting a high power supply rejection ratio (PSRR) characteristic.

[0006] According to an embodiment, a voltage regulator that generates an output voltage includes: a comparison unit that generates a second voltage based on a reference voltage and a first voltage generated by feedback of the output voltage; a power supply noise replication buffer unit that generates a third voltage including power supply noise replicated based on the second voltage; and a pass transistor that generates the output voltage in response to the third voltage.

[0007] The power supply noise replica buffer unit includes: a zeroth transistor connected between a ground node and a zeroth node and operating in response to a second voltage; a first transistor connected between the zeroth node and a power supply node and including a gate node connected to the second node; a high-pass filter connected between the second node and a third node; a second transistor connected between the power supply node and a first node connected to the third node and including a gate node connected to the third node; and a current source connected between the first node and the ground node, wherein the power supply noise replica buffer unit provides a third voltage through the zeroth node.

[0008] According to an embodiment, a voltage regulator that generates an output voltage includes: a comparison unit that generates a second voltage based on a reference voltage and a first voltage generated by feedback of the output voltage; a power supply noise replication buffer unit that generates a bias signal including noise of the power supply voltage; a first buffer that generates a third voltage based on the bias signal and the second voltage; a second buffer that buffers a fourth voltage based on the third voltage; and a pass transistor that is configured to generate the output voltage in response to the fourth voltage.

[0009] According to an embodiment, an operating method of a regulator includes: generating a first voltage by comparing a reference voltage and a feedback voltage of an output voltage; generating a second voltage based on the first voltage and a bias signal including a high frequency component of a power supply voltage of the regulator; and generating an output voltage based on the second voltage.

[0010] According to an embodiment, an electronic system includes: a plurality of electronic devices; and a power management integrated circuit including a voltage regulator that provides an output voltage to the electronic devices. The voltage regulator includes: a comparison unit that generates a second voltage based on a reference voltage and a first voltage that is a feedback voltage of the output voltage; and a power supply noise replica buffer unit that generates a bias signal based on a high frequency component of the power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram illustrating a voltage regulator according to an embodiment of the present disclosure.

[0013] Figure 2 is shown on a logarithmic scale Figure 1 Bode plot of the regulator’s open-loop gain and power supply rejection ratio (PSRR) response over the frequency spectrum.

[0014] Figure 3 is a block diagram illustrating a voltage regulator according to an embodiment of the present disclosure.

[0015] Figure 4 is a block diagram illustrating a voltage regulator according to an embodiment of the present disclosure.

[0016] Figure 5 The embodiment according to the present disclosure is shown in detail. Figure 3 and Figure 4 Block diagram of a bias current generating unit.

[0017] Figure 6 According to the embodiment of the present disclosure Figure 3 Detailed block diagram of the power supply rejection (PSR) compensation circuit.

[0018] Figure 7The present invention is a diagram showing an embodiment of the present invention. Figure 3 and Figure 4 A circuit diagram of a power supply noise replica buffer unit including a PSR compensation circuit and a buffer.

[0019] Figure 8 The present invention is a diagram showing an embodiment of the present invention. Figure 3 and Figure 4 A circuit diagram of a power supply noise replica buffer unit including a PSR compensation circuit and a buffer.

[0020] Fig. 9 is shown in a logarithmic scale within the spectrum according to an embodiment of the present disclosure Figure 3 and Figure 4 Bode plot of the gain and PSRR of the regulator's input voltage and intermediate voltage.

[0021] Fig.10 is shown in a logarithmic scale within the spectrum according to an embodiment of the present disclosure Figure 2 The PSRR of the regulator and Figure 3 and Figure 4 Bode plot of the PSRR of the regulator.

[0022] Fig.11 The use of the embodiments according to the present disclosure Figure 5 The bias current generator current Figure 3 and Figure 4 Bode plot of the PSRR of the regulator.

[0023] Fig.12 is a diagram showing the frequency spectrum in a logarithmic scale according to an embodiment of the present disclosure. Figure 8 The size ratio of the zeroth MOSFET and the first MOSFET is Figure 3 and Figure 4 Bode plot of the PSRR of the regulator.

[0024] Fig.13 is shown in a logarithmic scale within the spectrum according to an embodiment of the present disclosure Figure 3 and Figure 4 Bode plot of the PSRR of a regulator depending on the magnitude of the load current.

[0025] Fig.14 The present invention is a diagram showing an embodiment of the present invention. Figure 3 and Figure 4 A flow chart of the operating method of the voltage regulator.

[0026] Fig.15 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure.

[0027] Fig.16is a block diagram illustrating an electronic system according to an embodiment of the present disclosure.

[0028] Fig.17 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.Throughout the drawings, like reference numerals may represent like elements.

[0030] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an embodiment may be described as the "second" element in another embodiment.

[0031] It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly dictates otherwise.

[0032] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0033] Figure 1 is a block diagram illustrating a voltage regulator according to an embodiment of the present disclosure.

[0034] Reference Figure 1 The voltage regulator 10 (also referred to as a voltage regulator circuit) may include a bias current generating unit 11 (also referred to as a bias current generating circuit), a reference voltage generating unit 12 (also referred to as a reference voltage generating circuit), a comparison unit 13 (also referred to as a comparison circuit), a buffer unit 14 (also referred to as a buffer circuit), a transmission transistor unit 15 (also referred to as a transmission transistor circuit), and a feedback unit 16 (also referred to as a feedback circuit). Figure 1 The power supply voltage VDD of each circuit may be a voltage supplied from an external power supply, or may be a voltage generated by a DC-DC converter based on a voltage of an external power supply. In an embodiment, the external power supply may include a power storage device such as a battery or a capacitor.

[0035] The bias current generating unit 11 may generate a bias current for operation of the voltage regulator 10. In an embodiment, the bias current generating unit 11 may generate a current that is not affected by an external environment (e.g., temperature). The bias current generating unit 11 may provide a bias current to various circuits in the voltage regulator 10 (e.g., the comparison unit 13 or the buffer unit 14).

[0036] The reference voltage generating unit 12 may generate a reference voltage VREF, which is used as a reference in the process of generating the output voltage Vo. In an embodiment, the reference voltage generating unit 12 may be implemented using one of various voltage generators. For example, the reference voltage generating unit 12 may include a bandgap reference voltage generator. The reference voltage generating unit 12 may provide the reference voltage VREF to the comparison unit 13.

[0037] The comparison unit 13 may compensate for the variation of the output voltage Vo. In an embodiment, the comparison unit 13 may be provided with a power supply voltage VDD and may compensate for the variation of the output voltage Vo. The comparison unit 13 may receive a reference voltage VREF and a feedback signal FS as inputs, and may generate a first voltage V1 as an output based on a result of comparing the voltages of the reference voltage VREF and the feedback signal FS.

[0038] The buffer unit 14 may receive the first voltage V1 and may provide the gate voltage VG to the pass transistor unit 15. The buffer unit 14 may operate based on the power supply voltage VDD provided thereby and may be provided with the bias current generated by the bias current generating unit 11. The buffer unit 14 may buffer the first voltage V1 to generate the gate voltage VG. The gate voltage VG may include power supply noise replicated based on the first voltage V1.

[0039] The transmission transistor unit 15 may be provided with a gate voltage VG, and may generate an output voltage Vo and a load current IL. In an embodiment, the transmission transistor unit 15 may include a metal oxide semiconductor field effect transistor (MOSFET) (hereinafter referred to as a "MOS transistor"). For example, the transmission transistor unit 15 may include a p-type MOSFET (hereinafter referred to as a "PMOS transistor"), which is connected between the power supply voltage VDD and the output node No, and generates an output in response to the gate voltage VG. In an embodiment, the first end of the transmission transistor unit 15 may be connected to the power supply voltage VDD, and the second end thereof may be connected to various circuits. For example, the second end of the transmission transistor unit 15 may be connected to the output capacitor Co, the feedback unit 16, and the load device 17. The output voltage Vo and the load current IL generated by the transmission transistor unit 15 may be provided to the load device 17.

[0040] The feedback unit 16 can sense the output voltage Vo and provide feedback to the comparison unit 13. The feedback unit 16 can receive the output voltage Vo and generate a feedback signal FS according to a given ratio. The feedback unit 16 can provide the feedback signal FS to one of the inputs of the comparison unit 13.

[0041] Figure 2 Shows Figure 1A graph of the frequency response characteristics of the regulator.

[0042] In an embodiment, Figure 2 The top graph is a Bode plot, with the horizontal axis representing frequency and the vertical axis representing the open-loop gain of the regulator on a logarithmic scale. Figure 2 The bottom graph of is a Bode plot, the horizontal axis represents frequency, and the vertical axis represents the power supply rejection ratio (PSRR) of the regulator in a logarithmic scale. The open-loop gain may represent the magnitude of the small signal gain of the output voltage Vo relative to the reference voltage VREF when the feedback unit 16 is removed from the regulator 10. The PSRR may represent how much the output voltage Vo changes according to the power supply voltage VDD.

[0043] Reference Figure 2 , three open-loop gains are shown. The first open-loop gain P11 may have a first gain A1 as a direct current (DC) gain, and may decrease at a rate of approximately 20 dB / dec when passing through a first pole frequency PF1. The second open-loop gain P21 may have a first gain A1 as a DC gain, and may decrease at a rate of approximately 20 dB / dec when passing through a second pole frequency PF2. In this article, the second pole frequency PF2 may be higher than the first pole frequency PF1. The third open-loop gain P31 may have a second gain A2 greater than the first gain A1 as a DC gain, and may decrease at a rate of approximately 20 dB / dec after the first pole frequency PF1. The pole frequencies PF1 and PF2 may be based on Figure 1 The output capacitor Co is based on Figure 1 The output impedance of the output node No and the characteristics of the reference voltage VREF are formed.

[0044] Reference Figure 2 , three PSRRs corresponding to three open-loop gains are shown, respectively. The first PSRR P12 may have a first ratio P1 as the PSRR at the DC point, and may increase at a rate of about 20dB / dec from the first pole frequency PF1. The second PSRR P22 may have a first ratio P1 as the PSRR at the DC point, and may increase at a rate of about 20dB / dec from the second pole frequency PF2. The third PSRR P32 may have a second ratio P2 as the PSRR at the DC point, and may increase at a rate of about 20dB / dec from the first pole frequency PF1. In this article, the first ratio P1 and the second ratio P2 may have negative values, and the absolute value of the second ratio P2 may be greater than the absolute value of the first ratio P1.

[0045] In the case of comparing the three PSRRs at the reference frequency (RF) point, the absolute value of the third PSRR P32 may be the largest, the absolute value of the first PSRR P12 may be the smallest, and the absolute value of the second PSRR P22 may be smaller than the absolute value of the third PSRR P32 and greater than the absolute value of the first PSRR P12. That is, as the DC gain increases, the absolute value of the PSRR may increase (or the PSRR characteristics may become better). Alternatively, when the pole frequency becomes higher, the absolute value of the PSRR may increase (or the PSRR characteristics may become better).

[0046] As from Figure 2 As understood, the PSRR performance of the regulator can be improved in the following two ways: 1) by increasing the DC gain of the output voltage, or 2) by moving the position of the pole frequency to a higher frequency. However, the above method may be difficult to increase the drive current of the regulator or improve the stability of the loop formed with the feedback circuit. In addition, even if the above method is applied to a regulator that provides high-frequency power, the effect of improving the PSRR may be minimal or reduced. Therefore, the structure, device and operation that can improve the PSRR even if the regulator supplies high-frequency output power will be described in detail with reference to the following drawings.

[0047] Hereinafter, for ease of explanation, the regulator 100 according to an embodiment of the present disclosure is described as a low dropout regulator. However, the present disclosure is not limited thereto. It should be understood that the technical ideas described in detail with respect to improving PSRR can be applied to various semiconductor elements, semiconductor circuits, semiconductor devices or electronic devices.

[0048] Figure 3 is a block diagram illustrating a voltage regulator 100 according to an embodiment of the present disclosure.

[0049] Reference Figure 3 , the voltage regulator 100 (also referred to as a voltage regulator circuit) may include a bias current generating unit 110 (also referred to as a bias current generating circuit), a reference voltage generating unit 120 (also referred to as a reference voltage generating circuit), a comparing unit 130 (also referred to as a comparing circuit), a power supply noise replica buffer unit PNR (also referred to as a power supply noise replica buffer circuit), a transmission transistor unit 160 (also referred to as a transmission transistor circuit), and a feedback unit 170 (also referred to as a feedback circuit). The power supply noise replica buffer unit PNR may include a power supply rejection (PSR) compensation circuit 140 and a buffer 150 (also referred to as a buffer circuit). Figure 3 The structure and operation of the regulator 100 according to the embodiment of the present disclosure are described in detail.

[0050] The bias current generating unit 110 may generate a bias current for operation of the voltage regulator 100. In an embodiment, the bias current generating unit 110 may be connected to Figure 1 The bias current generating unit 11 is the same or similar. Figure 3 , the bias current generating unit 110 is included in the voltage regulator 100, but the present disclosure is not limited thereto. For example, in an embodiment, the bias current generating unit 110 may be provided outside the voltage regulator 100. Figure 5 The bias current generating unit 110 is described in detail.

[0051] The reference voltage generating unit 120 may generate a reference voltage VREF, which is used as a reference in the process of generating an output voltage of the voltage regulator 100. In an embodiment, the reference voltage generating unit 120 may be connected to Figure 1 The reference voltage generating unit 12 is the same or similar. Figure 3 2 shows an example in which the reference voltage generating unit 120 is placed inside the voltage regulator 100 . However, the present disclosure is not limited thereto. For example, in an embodiment, the reference voltage generating unit 120 may be disposed outside the voltage regulator 100 .

[0052] The comparison unit 130 may receive feedback of the output voltage Vo and may apply the feedback to the generation of the output voltage Vo. The comparison unit 130 may operate based on the power supply voltage VDD. In an embodiment, the comparison unit 130 may generate a first voltage V1 based on a comparison of a reference voltage VREF with a feedback signal FS. For example, the comparison unit 130 may include an operational amplifier (OP-AMP) that outputs the first voltage V1 by using the reference voltage VREF as a non-inverting input and the feedback signal FS as an inverting input.

[0053] The above disclosure is provided as an example, and the present disclosure is not limited thereto. For example, according to an embodiment of the present disclosure, a circuit capable of comparing a reference voltage VREF with a feedback signal FS (e.g., amplifying the difference between the reference voltage VREF and the feedback signal FS) and outputting a first voltage V1 may be provided, and the circuit is included in the comparison unit 130. In the above example, the feedback signal FS is described as a voltage signal. However, the present disclosure is not limited thereto. For example, according to an embodiment of the present disclosure, the feedback signal FS may be in the form of a current.

[0054] The PSR compensation circuit 140 may extract a specific signal from the power supply voltage VDD. For example, the specific signal may include at least one or more of a low frequency component of the power supply voltage VDD, a high frequency component of the power supply voltage VDD, and a noise component of the power supply voltage VDD. In an embodiment, the PSR compensation circuit 140 may extract a noise component of the power supply voltage VDD. For example, the PSR compensation circuit 140 may extract a noise component such as ripple noise and thermal noise of the power supply voltage VDD. The PSR compensation circuit 140 may provide the extracted noise component to the buffer 150 in the form of a bias signal BS. Figure 6 , Figure 7 and Figure 8 The structure and operation of the PSR compensation circuit 140 are described in detail.

[0055] The buffer 150 may generate a gate voltage VG to be provided to the pass transistor unit 160 from the first voltage V1. In an embodiment, the buffer 150 may generate the gate voltage VG based on the first voltage V1 and the bias signal BS. For example, the buffer 150 may generate the gate voltage VG by buffering the first voltage V1 based on the bias signal BS. For example, the buffer 150 may generate the gate voltage VG including power supply noise replicated based on the first voltage V1. The buffer 150 may provide the gate voltage VG thus generated to the pass transistor unit 160. Figure 7 and Figure 8 The structure and operation of the buffer 150 are described in detail.

[0056] The transmission transistor unit 160 may receive a gate voltage VG to generate an output voltage Vo and a load current IL. In an embodiment, the transmission transistor unit 160 may include a circuit capable of generating an output voltage Vo and a load current IL in response to the gate voltage VG. For example, the transmission transistor unit 160 may include a PMOS transistor connected between the output node No and the power supply voltage VDD and operating in response to the gate voltage VG. In this case, the transmission transistor unit 160 may include a PMOS transistor of a common source (CS) structure, wherein the gate voltage VG is used as an input.

[0057] The above description is provided as an example and is not intended to limit the scope and spirit of the present disclosure. For example, according to an embodiment of the present disclosure, the transmission transistor unit 160 may include an element capable of generating an output voltage Vo or a load current IL in response to a gate voltage VG (or receiving a gate voltage VG to generate an output voltage Vo or a load current IL), or a circuit capable of generating an output voltage Vo or a load current IL in response to a gate voltage VG (or receiving a gate voltage VG to generate an output voltage Vo or a load current IL). For example, in an embodiment, the transmission transistor unit 160 may include an n-type metal oxide semiconductor field effect transistor (N-type MOSFET) (hereinafter referred to as an "NMOS transistor"), which is capable of generating an output voltage Vo or a load current IL in response to a gate voltage VG. For example, in an embodiment, the transmission transistor unit 160 may include a circuit implemented by a plurality of MOS transistors capable of generating an output voltage Vo or a load current IL in response to a gate voltage VG.

[0058] The feedback unit 170 may generate feedback of the output voltage Vo. The feedback unit 170 may generate a feedback signal FS from the output voltage Vo so as to provide it to the comparison unit 130. In an embodiment, the feedback signal FS may be a voltage signal. For example, the feedback unit 170 may generate a feedback voltage from the output voltage Vo, and may provide the feedback voltage to the inverting input of the comparison unit 130.

[0059] In an embodiment, the feedback unit 170 may include a circuit that generates a feedback signal FS having a magnitude of 1 / N (N is a real number of 1 or greater) of the output voltage Vo. Figure 3 , the feedback unit 170 may include a first resistor 171 (whose resistance value is "R1") connected between the ground node and the feedback node Nf and a second resistor 172 (whose resistance value is "R2") connected between the output node No and the feedback node Nf. In this case, the feedback signal FS provided to the comparison unit 130 through the feedback node Nf may have a value obtained by multiplying the output voltage Vo by a value (R1 / (R1+R2)). The detailed structure of the above-mentioned feedback unit 170 is provided as an example, and the present disclosure is not limited thereto.

[0060] The output capacitor Co may be connected between the output node No and the ground node. In an embodiment, the output capacitor Co may determine the characteristics of the output voltage Vo. For example, the capacitance of the output capacitor Co may determine the gain and frequency characteristics of the output voltage Vo together with the output impedance of the feedback unit 170 and the load device 17.

[0061] Figure 4 is a block diagram illustrating a regulator 200 according to an embodiment of the present disclosure.

[0062] Reference Figure 4 , the regulator 200 (also referred to as a regulator circuit) may include a bias current generating unit 210 (also referred to as a bias current generating circuit), a reference voltage generating unit 220 (also referred to as a reference voltage generating circuit), a comparing unit 230 (also referred to as a comparing circuit), a power supply noise replica buffer unit PNR (also referred to as a power supply noise replica buffer circuit), a transmission transistor unit 260 (also referred to as a transmission transistor circuit), a feedback unit 270 (also referred to as a feedback circuit), a post-buffer unit 280 (also referred to as a post-buffer circuit), and an output capacitor Co. The power supply noise replica buffer unit PNR may include a PSR compensation circuit 240 and a buffer 250 (also referred to as a buffer circuit). In an embodiment, Figure 3 Similar to the regulator 100, the regulator 200 may generate a first voltage V1 through the comparison unit 230, may buffer the first voltage V1 through the power supply noise replica buffer unit PNR, and may generate an output voltage Vo and a load current IL through the pass transistor unit 260. Hereinafter, the operation of the regulator 200 including the post-buffer unit 280 will be described in detail.

[0063] and Figure 3 Similar to the bias current generating unit 110 of FIG. 1 , the bias current generating unit 210 may generate a bias current for operation of the regulator 200. Figure 3 Similar to the reference voltage generating unit 120 of FIG. 1 , the reference voltage generating unit 220 may generate a reference voltage VREF to be provided to the comparing unit 230. Figure 3 Similarly, according to an embodiment of the present disclosure, the bias current generating unit 210 or the reference voltage generating unit 220 may be disposed outside the regulator 200 .

[0064] The PSR compensation circuit 240 can be Figure 3 The PSR compensation circuit 240 operates in the same manner as the PSR compensation circuit 140 of the embodiment. In an embodiment, the PSR compensation circuit 240 can extract a specific component of the power supply voltage VDD. For example, the PSR compensation circuit 240 can extract a noise component of the power supply voltage VDD. The PSR compensation circuit 240 can provide a bias signal BS including the extracted specific component to the buffer 250. For example, the PSR compensation circuit 240 can provide a bias signal BS including the noise component of the power supply voltage VDD to the buffer 250. Figure 3 Similar to the PSR compensation circuit 140 , the above disclosure is provided as an example, and the present disclosure is not limited thereto.

[0065] The buffer 250 may generate the second voltage V2 based on the first voltage V1 and the bias signal BS. For example, the buffer 250 may generate the second voltage V2 by buffering the first voltage V1 based on the bias signal BS. The buffer 250 may provide the second voltage V2 to the post-buffer unit 280. The remaining operations of the buffer 250 may be similar to those of FIG. Figure 3 The operation of the buffer 150 is the same or similar. Figure 7 and Figure 8 The structure of the buffer 250 is described in detail.

[0066] The transmission transistor unit 260 may generate an output voltage Vo and a load current IL in response to a gate voltage VG received from the post-buffer unit 280. In an embodiment, the transmission transistor unit 260 may include a PMOS transistor. For example, the transmission transistor unit 260 may include a PMOS transistor connected between a power supply voltage VDD and an output node No, and operated in response to a gate voltage VG. The above description is provided as an example and is not intended to limit the scope and spirit of the present disclosure. For example, according to an embodiment of the present disclosure, the transmission transistor unit 260 may include an element capable of generating an output voltage Vo or a load current IL in response to a gate voltage VG (or receiving a gate voltage VG to generate an output voltage Vo or a load current IL), or a circuit capable of generating an output voltage VO or a load current IL in response to a gate voltage VG (or receiving a gate voltage VG to generate an output voltage Vo or a load current IL).

[0067] The post-buffer unit 280 may generate a gate voltage VG based on the second voltage V2. For example, the post-buffer unit 280 may buffer the second voltage V2 to generate the gate voltage VG. In an embodiment, the post-buffer unit 280 may separate the power noise replica buffer unit PNR from the transmission transistor unit 260, and may reduce the mutual influence between the power noise replica buffer unit PNR and the transmission transistor unit 260. For example, even if the size of the transmission transistor unit 260 (for example, the width / length ratio of the MOSFET) is changed due to a change in the level of the output voltage Vo, the post-buffer unit 280 may be based on the reference to the power noise replica buffer unit PNR without making a separate design modification to the power noise replica buffer unit PNR. Figure 8 The described changes in the sizes of the zeroth MOSFET M0 and the first MOSFET M1 allow the regulator 200 to maintain the same PSRR performance.

[0068] Figure 3 The voltage regulator 100 and Figure 4The voltage regulator 200 can have a simpler structure while still providing high PSRR performance. Because the voltage regulator 100 or 200 has a structure that does not include an auxiliary amplifier, the voltage regulator 100 or 200 can be more easily designed to reduce the circuit area of ​​the voltage regulator 100 or 200 and reduce the cost of manufacturing the voltage regulator 100 or 200.

[0069] The voltage regulator 100 or 200 according to the embodiment of the present disclosure can provide improved PSRR performance in the high frequency range. Moreover, since the voltage regulator 100 or 200 has the characteristic of improving the PSRR performance without deteriorating the load transient response characteristics, the voltage regulator 100 or 200 can provide the load device 17 with an appropriate output voltage Vo and an appropriate load current IL.

[0070] Figure 4 The regulator 200 may have a structure including a post-buffer unit 280, and thus may make it easier to change the pass transistor than a conventional regulator. When the pass transistor is changed, conventional regulators undergo considerable design changes in the circuit for improving the PSRR performance. However, even if the size of the transistor included in the pass transistor unit 260 changes as the output voltage Vo or the load current IL increases (for example, even if the size W / L of the transistor increases or a plurality of transistors connected in parallel between the output node No and the power supply voltage VDD are included or added), the regulator 200 may more easily cope with the PSRR performance utilized by the load device 17 without changing the design of the power supply noise replica buffer unit PNR (or with minimal or reduced design changes). This may mean a reduction in the cost of changing the design of the regulator. Below, the details will be described. Figure 3 or Figure 4 The structure of the PSR compensation circuit 140 or 240, the power supply noise replica buffer unit PNR and the bias current generating unit 110 or 210.

[0071] Figure 5 is a detailed illustration of an embodiment of the present disclosure Figure 3 The bias current generating unit 110 and Figure 4 1 is a block diagram of the bias current generating unit 210.

[0072] Although in Figure 5 It is shown in Figure 3 The bias current generating unit 110, but it should be understood that Figure 4 The bias current generating unit 210 may also be the same as the bias current generating unit 110. Figure 5The bias current generating unit 110 (also referred to as a bias current generating circuit) may include a current generator 111 (also referred to as a current generator circuit) and a low-pass filter 112 (also referred to as a low-pass filter circuit). Figure 5 The bias current generating unit 110 according to an embodiment of the present disclosure is described in detail.

[0073] The current generator 111 may generate an initial current IC based on the power supply voltage VDD. In an embodiment, the current generator 111 may generate an initial current IC that is not affected by the external environment. For example, the current generator 111 may generate an initial current IC having a uniform size that is not affected by temperature changes. In an embodiment, the current generator 111 may provide the initial current IC to the low-pass filter 112.

[0074] The low-pass filter 112 may filter the high-frequency component of the initial current IC. In an embodiment, the low-pass filter 112 may remove noise included in the high-frequency component of the initial current IC. For example, the low-pass filter 112 may remove the thermal noise of the initial current IC or the noise component of the power supply voltage VDD. The low-pass filter 112 may filter the high-frequency component of the initial current IC to generate a bias current BC. In an embodiment, the low-pass filter 112 may provide the bias current BC to an internal circuit of the regulator 100 or 200. For example, the low-pass filter 112 may provide the bias current BC to the buffer 150.

[0075] Figure 6 According to the embodiment of the present disclosure Figure 3 Detailed block diagram of the PSR compensation circuit 140.

[0076] Although in Figure 6 It is shown in Figure 3 The PSR compensation circuit 140 is a PSR compensation circuit 240, but the present disclosure is not limited thereto. For example, the PSR compensation circuit 240 may also be implemented as the same as the PSR compensation circuit 140. Figure 6 , the PSR compensation circuit 140 may include a high-pass filter 141 (also referred to as a high-pass filter circuit) and an amplifier 142 (also referred to as an amplifier circuit). Figure 6 The PSR compensation circuit 140 according to an embodiment of the present disclosure is described in detail.

[0077] The high pass filter 141 may filter the low frequency component of the power supply voltage VDD. In an embodiment, the high pass filter 141 may remove noise included in the low frequency component of the power supply voltage VDD. For example, the high pass filter 141 may extract the noise component of the power supply voltage VDD by passing a signal of any frequency or higher frequency. In an embodiment, the high pass filter 141 may generate a high pass voltage Vh so as to be provided to the amplifier 142. Figure 8An example of the high-pass filter 141 is described in detail.

[0078] The amplifier 142 may amplify the high-pass voltage Vh. In an embodiment, the amplifier 142 may amplify the high-pass voltage Vh at a given ratio. For example, the amplifier 142 may amplify the high-pass voltage Vh by k times (k is a positive integer). The amplifier 142 may amplify the high-pass voltage Vh to generate a bias signal BS. The amplifier 142 may provide the bias signal BS to the buffer 150 or 250. Figure 8 An example of the amplifier 142 is described in detail.

[0079] Figure 7 The present invention is a diagram showing an embodiment of the present invention. Figure 3 and Figure 4 A circuit diagram of a power supply noise replica buffer unit PNR circuit.

[0080] Reference Figure 7 , the power supply noise replica buffer unit PNR may include a high-band bias current source HBC and a zeroth metal oxide semiconductor field effect transistor (MOSFET) M0. Figure 7 It is shown in Figure 3 The power supply noise replica buffer unit PNR receives the first voltage V1 to generate the gate voltage VG, but it can be applied to Figure 4 The power supply noise replica buffer unit PNR receives the first voltage V1 to generate the second voltage V2. Figure 7 The operation of the power supply noise replica buffer unit PNR according to an embodiment of the present disclosure is described in detail.

[0081] The high-band bias current source HBC may be connected between the power supply voltage VDD and the zeroth node N0. The high-band bias current source HBC may provide a high-frequency component of the power supply voltage VDD to the zeroth MOSFET M0. For example, the high-band bias current source HBC may provide a high-frequency component (e.g., a noise component) of the power supply voltage VDD to the zeroth MOSFET M0 in the form of a bias current. In an embodiment, the magnitude of the current generated by the high-band bias current source HBC may be controlled by Figure 3 The bias current generating unit 110 or Figure 4 The bias current generating unit 210 generates the current, but the present disclosure is not limited thereto.

[0082] In an embodiment, the high-band bias current source HBC may provide a signal obtained by amplifying the high-frequency component of the power supply voltage VDD to the zeroth MOSFET M0 in the form of a bias current. For example, the high-band bias current source HBC may extract the high-frequency component of the power supply voltage VDD in the form of a current so as to provide it to the zeroth MOSFET M0. Figure 8The structure of the high-band bias current source HBC is described in detail. Figure 7 2 shows that the high-band bias current source HBC flows from the power supply voltage VDD to the zeroth node N0. However, the present disclosure is not limited thereto.

[0083] The zeroth MOSFET M0 may be connected between the ground node and the zeroth node N0 and may operate in response to the first voltage V1. In an embodiment, the zeroth MOSFET M0 may operate as a source follower. For example, the zeroth MOSFET M0 may include a source connected to the zeroth node N0 and a drain connected to the ground node, and may generate a gate voltage VG as an output at the zeroth node N0 to be provided to the pass transistor unit 160. Figure 3 The regulator 100 is described, however, in Figure 4 In the case of the regulator 200, the zeroth MOSFET M0 can generate a second voltage V2 at the zeroth node N0 to provide Figure 4 According to the above operation of the zeroth MOSFET M0, a gate voltage VG (or a second voltage V2) in which the first voltage V1 is combined with a noise component of the power supply voltage VDD may be generated.

[0084] Figure 8 It is shown in detail Figure 3 , Figure 4 and Figure 7 Circuit diagram of the power supply noise replica buffer unit PNR.

[0085] Reference Figure 8 The power supply noise replica buffer unit PNR may include a zeroth MOSFET M0, a first MOSFET M1, a second MOSFET M2, a bias current source BCS, a filter resistor FR, and a filter capacitor FC. Figure 3 , Figure 4 , Figure 7 and Figure 8 A power supply noise replica buffer unit PNR according to an embodiment of the present disclosure is described.

[0086] The bias current source BCS may be connected between the ground node and the first node N1. In an embodiment, the bias current source BCS may generate Figure 3 or Figure 4 The bias current source BCS may be a duplicate of the current generated by the bias current generating unit 110 or 210. Figure 3 or Figure 4 The bias current source BCS may be a current mirror that copies the current of the bias current generating unit 110 or 210 and provides the current to the first node N1.

[0087] The second MOSFET M2 may be connected between the power supply voltage VDD and the first node N1, and the gate node of the second MOSFET M2 may be connected to the second node N2. The second MOSFET M2 may have a second size s2 (hereinafter, the size of the MOSFET refers to the width / length (W / L) of the MOSFET). In an embodiment, the first node N1 and the second node N2 may be connected. That is, the drain node and the gate node of the second MOSFET M2 may be connected to each other. The second MOSFET M2 may be a MOSFET placed on the current source side in the current mirror.

[0088] The high-frequency filter HF may be placed between the gate node of the first MOSFET M1 and the gate node of the second MOSFET M2. In an embodiment, the high-frequency filter HF may include a filter resistor FR and a filter capacitor FC. For example, the filter resistor FR may be connected between the second node N2 and the third node N3, and the filter capacitor FC may be connected between the third node N3 and the ground node. The above-mentioned high-frequency filter HF is provided as an example, but the present disclosure is not limited thereto. For example, according to an embodiment of the present disclosure, a circuit capable of providing a high-frequency component to the input signal of the first MOSFET M1 may be provided.

[0089] The first MOSFET M1 may be connected between the power supply voltage VDD and the zeroth node N0, and a gate node of the first MOSFET M1 may be connected to the third node N3. The first MOSFET M1 may have a first size s1. The first MOSFET M1 may provide a high frequency component (or a noise component) of the power supply voltage VDD to the zeroth node N0 in the form of current.

[0090] The zeroth MOSFET M0 can correspond to Figure 7 The zeroth MOSFET M0 may have a zeroth size s0. Figure 8 , the second MOSFET M2 and the first MOSFET M1 may have a current mirror structure. In an embodiment, the high frequency filter HF may be disposed between the current mirrors. For example, the high frequency filter HF may be disposed between the second node N2 and the third node N3. In an embodiment, the amount of amplification of the high frequency component may be determined based on the size ratio s1 / s0 of the zeroth MOSFET M0 and the first MOSFET M1. For example, the amount of amplification of the high frequency component may be increased by increasing the first size s1 when the zeroth size s0 is fixed. Fig.12 Results of comparing PSRR performance according to adjustments of the zeroth size s0 and the first size s1 are described.

[0091] Through the current mirror structure, the power supply noise replication buffer unit PNR can be simpler than the power supply noise replication buffer unit of the conventional regulator. For example, the power supply noise replication buffer unit PNR according to the embodiment of the present disclosure does not include an auxiliary amplifier. Even in the high frequency band, the power supply noise replication buffer unit PNR can more effectively improve the PSRR performance, and through a simple structure, the power supply noise replication buffer unit PNR according to the embodiment of the present disclosure can provide a more convenient design and a more convenient design change.

[0092] Although the above description refers to Figure 7 and Figure 8 The zeroth MOSFET M0, the first MOSFET M1, and the second MOSFET M2 are examples of PMOS transistors, but the present disclosure is not limited thereto. For example, according to an embodiment of the present disclosure, the zeroth MOSFET M0, the first MOSFET M1, and the second MOSFET M2 may be implemented using NMOS transistors that can provide the same effect and operation, or the zeroth MOSFET M0, the first MOSFET M1, and the second MOSFET M2 may be implemented using a circuit including a plurality of MOS transistors.

[0093] Figures 9 to 13 The present invention is a diagram showing an embodiment of the present invention. Figure 3 or Figure 4 A graph of the frequency response characteristics of the regulator 100 or 200 is shown.

[0094] In an embodiment, Figures 9 to 13 In the graph of , the horizontal axis represents frequency, and the vertical axis represents gain or PSRR characteristics. In an embodiment, Figures 9 to 13 A Bode plot is shown in logarithmic scale. Figures 9 to 13 , a to g of the horizontal axis may be sequentially increasing positive integers, and A to G of the vertical axis may be sequentially increasing negative integers by units of 10.

[0095] Fig. 9 It is shown that when a small signal (eg, noise) of the power supply voltage VDD is applied, Figure 4 The power supply voltage VDD, the first voltage V1, the second voltage V2 and the gain of the gate voltage VG of the regulator 200 and the PSRR characteristics of the regulator 200 are shown in FIG. Fig. 9 , showing the first response P91 of the power supply voltage VDD, Figure 4 A second response P92 of the first voltage V1, Figure 4 The third response P93 of the second voltage V2 and the gate voltage VG, and the fourth response P94 as the PSRR characteristic of the regulator 200. Fig. 9 Describe the improved PSRR characteristics.

[0096] Reference Fig. 9 , the first response P91 may indicate a response of 0 dB across the frequency spectrum. Since this indicates a gain according to a change in the signal of the power supply voltage VDD, the gain is 1.

[0097] Because the second response P92 is close to about 20 dB / dec in a specific frequency band, the gain may be reduced. For example, in the second response P92, the gain may be reduced by 10 c and 10 d For example, "a" may be 1, and therefore, in the second response P92, the gain may be reduced starting from about 2 kHz. The reason is that Figure 4 The gain provided in the comparison unit 230 decreases after an arbitrary frequency (eg, approximately 2 kHz).

[0098] The third response P93 may maintain a gain of about G across the spectrum. For example, when "A" is about -70, the third response P93 may indicate a response of about 0 dB. The third response P93 shows aspects that are different from those of the second response P92. The reason is that the power supply noise replica buffer unit PNR operates according to an embodiment of the present disclosure. For example, the reason is that the operation of the power supply noise replica buffer unit PNR offsets the reduction in the gain of the comparison unit 130 or 230.

[0099] The fourth response P94 may indicate a PSRR response characteristic. Figure 2 and Fig. 9 ,and Figure 2 The PSRR response characteristics are different. Figure 4 The fourth response P94 can maintain a uniform level across the spectrum. For example, when "A" is about -70 and "a" is about 0, the PSRR characteristic from the fourth response P94 can have a performance of about -60dB in the 1MHz band. The above characteristics of the fourth response P94 can come from the operation according to an embodiment of the present disclosure, which suppresses the noise signal to produce the third response P93.

[0100] Fig.10 The conventional voltage regulator 10 (refer to Figure 2 ) and the PSRR characteristics of the regulator 100 or 200 according to the embodiment of the present disclosure (refer to Figure 3 or Figure 4 ) is a Bode plot of the PSRR characteristics. Figures 2 to 4 and Fig.10 An improved PSRR characteristic of the regulator 100 or 200 according to an embodiment of the present disclosure is described.

[0101] Reference Fig.10 , the first response P101 can be Figure 3 or Figure 4 The second response P102 may be Figure 2 In an embodiment, the first response P101 may show a more improved PSRR performance than the second response P102 in a relatively high frequency range. For example, the PSRR performance of the first response P101 may be improved by 10 c and 10 d When "A" is about -80 and "a" is about 0, the regulator 100 or 200 having the first response P101 can be improved at 1 MHz (10 g ) shows a PSRR performance of about -70dB. Figure 2 Unlike the PSRR shown in , in the case of the regulator 100 or 200 according to the embodiment of the present disclosure, the PSRR may not increase even if the gain of the reference voltage VREF is reduced.

[0102] Fig.11 The Bode diagram of the voltage regulator 100 or 200 (refer to Figure 3 or Figure 4 ) depends on whether the PSRR characteristics are applied Figure 5 The frequency spectrum is represented by a logarithmic scale. Figures 3 to 5 and Fig.11 The PSRR characteristics measured when the bias current generating unit 110 is applied are described.

[0103] Reference Fig.11 , the first response P111 shows that it includes Figure 5 The PSRR characteristic of the regulator 100 or 200 of the bias current generating unit 110 is shown in FIG. 1 , and the second response P112 indicates that the bias current generating unit 110 does not include Figure 5 1. The first response P111 may show a more improved PSRR performance than the second response P112 in a relatively high frequency range. For example, when "A" is about -80 and "a" is about 0, compared with the case where the bias current generating unit 110 is not included. Figure 5 The bias current generating unit 110 of the voltage regulator 100 or 200 includes Figure 5 The voltage regulator 100 or 200 including the bias current generating unit 110 may exhibit a PSRR performance improved by up to about 20 dB at 1 MHz. That is, when the bias current generating unit 110 is appropriately selected, the voltage regulator 100 or 200 may have an appropriate PSRR performance.

[0104] Fig.12The Bode diagram of the voltage regulator 100 or 200 (refer to Figure 3 or Figure 4 )'s PSRR characteristics according to Figure 8 The ratio of the size of the zeroth MOSFET M0 to the first MOSFET M1 changes, and is represented in a logarithmic scale within the spectrum. Figure 3 , Figure 4 , Figure 8 and Fig.12 The manner in which the PSRR characteristic changes according to the size ratio of the zeroth MOSFET M0 and the first MOSFET M1 is described.

[0105] Reference Figure 8 and Fig.12 , a first response P121 indicates a PSRR characteristic of the regulator 100 or 200, wherein the zeroth MOSFET M0 and the first MOSFET M1 have a first size ratio s1 / s0, a second response P122 indicates a PSRR characteristic of the regulator 100 or 200, wherein the zeroth MOSFET M0 and the first MOSFET M1 have a second size ratio, and a third response P123 indicates a PSRR characteristic of the regulator 100 or 200, wherein the zeroth MOSFET M0 and the first MOSFET M1 have a third size ratio. In this article, the second size ratio may be about 90% of the first size ratio, and the third size ratio may be about 110% of the first size ratio. For example, when "A" is about -80 and "a" is about 0, at 1 MHz, the first response P121 may have improved PSRR performance compared to the second response P122 and the third response P123. For example, the first size ratio may be about 2.19, but the present disclosure is not limited thereto. That is, the target PSRR performance can be achieved by appropriately setting the size ratio of the zeroth MOSFET M0 to the first MOSFET M1.

[0106] Fig.13 The Bode diagram of FIG. 1 shows how the PSRR characteristic is based on the voltage regulator 100 or 200 (refer to FIG. 1 ) according to an embodiment of the present disclosure. Figure 3 or Figure 4 ) changes with the change of the load current IL. Figure 3 , Figure 4 and Fig.13 Describes the PSRR characteristics measured when the magnitude of the load current IL changes.

[0107] Reference Fig.13, the first response P131 indicates the response of the regulator 100 or 200 having a first load current, the second response P132 indicates the response of the regulator 100 or 200 having a second load current, and the third response P133 indicates the response of the regulator 100 or 200 having a third load current. The magnitude of the second load current may be approximately 50% of the magnitude of the first load current, and the magnitude of the third load current may be approximately 50% of the magnitude of the second load current. For example, when "A" is approximately -80 and "a" is approximately 0, at 1 MHz, the first response P131, the second response P132, and the third response P133 may have a PSRR of approximately -70 dB. That is, the regulator 100 or 200 according to an embodiment of the present disclosure may maintain the PSRR characteristics even when the magnitude of the load current IL changes.

[0108] Reference Figures 9 to 13 The PSRR characteristics of the regulator of the embodiment of the present disclosure described are provided as examples. However, the present disclosure is not limited thereto. For example, for better understanding, the above numerical values ​​are provided as examples, and the present disclosure is not limited thereto. For example, the above numerical values ​​may be changed differently according to design modifications. For example, the numerical values ​​may be changed according to the power level used and the characteristics of the device to which the regulator 100 or 200 according to the embodiment of the present disclosure supplies power.

[0109] Fig.14 The present invention is a diagram showing an embodiment of the present invention. Figure 3 or Figure 4 Flow chart of a method of operating the regulator 100 or 200.

[0110] Will refer to Figure 3 , Figure 4 and Fig.14 The operation process of the voltage regulator 100 or 200 is described below. Figure 3 However, it should be understood that Figure 4 The operation of the regulator 200 is similar to the operation of the regulator 100 .

[0111] Reference Figure 3 and Fig.14 In operation S110, the voltage regulator 100 may generate a first voltage V1 based on a reference voltage VREF and a feedback signal FS. In an embodiment, the voltage regulator 100 may generate the first voltage V1 through a comparison unit 130. For example, the voltage regulator 100 may generate the first voltage V1 by comparing the reference voltage VREF and the feedback signal FS through the comparison unit 130 and amplifying a difference between the reference voltage VREF and the feedback signal FS.

[0112] In operation S120, the voltage regulator 100 may generate a high frequency component of the power supply voltage VDD. In an embodiment, the voltage regulator 100 may generate a high frequency component (or a noise component) of the power supply voltage VDD through the PSR compensation circuit 140. For example, the voltage regulator 100 may generate a high frequency component (or a noise component) of the power supply voltage VDD through the PSR compensation circuit 140. Figure 6 The high-pass filter 141 generates a high-frequency component of the power supply voltage VDD.

[0113] In operation S130, the voltage regulator 100 may generate a second voltage based on the high frequency component of the power supply voltage VDD and the first voltage V1. In an embodiment, the voltage regulator 100 may generate the second voltage through the buffer 150. For example, the voltage regulator 100 may generate the second voltage by buffering the first voltage V1 based on the high frequency component of the power supply voltage VDD through the buffer 150. The second voltage may be Figure 3 The gate voltage VG.

[0114] In operation S140, the voltage regulator 100 may generate an output voltage based on the second voltage. In an embodiment, the voltage regulator 100 may generate the output voltage through the transmission transistor unit 160. For example, the voltage regulator 100 may operate in response to the second voltage and may generate the output voltage at the second end of the transmission transistor unit 160, the first end of which is connected to the power supply voltage VDD. Figure 4 In an embodiment of the voltage regulator 200, the voltage regulator 200 may generate an output voltage through the post-buffer unit 280 and the pass transistor unit 260. For example, the voltage regulator 200 may generate a third voltage by buffering the second voltage through the post-buffer unit 280, and may generate the output voltage Vo through the pass transistor unit 260 based on the third voltage.

[0115] The above description is provided as an example, and the present disclosure is not limited thereto.

[0116] Fig.15 is a block diagram illustrating an electronic system to which a voltage regulator according to an embodiment of the present disclosure is applied.

[0117] Reference Fig.15 , the electronic system 1000 may include a power management integrated circuit (PMIC) 1100 and a plurality of devices 1210, 1220, 1230, and 1240. In an embodiment, the electronic system 1000 may be one of various electronic devices, such as, for example, a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smart phone, a tablet computer, a laptop computer, and a wearable device. Alternatively, the electronic system 1000 may be implemented using, for example, a system on chip (SOC) or a system-in-package (SoP).

[0118] The power management integrated circuit 1100 may receive external power PWR and may generate a plurality of output voltages VOUT1, VOUT2, and VOUT3 based on the external power PWR. For example, the power management integrated circuit 1100 may include a first regulator 1110 configured to generate a first output voltage VOUT1, a second regulator 1120 configured to generate a second output voltage VOUT2, and a third regulator 1130 configured to generate a third output voltage VOUT3.

[0119] In an embodiment, each of the first regulator 1110 to the third regulator 1130 may be a reference Figures 3 to 14 One of the regulators 100 and 200 described above, or a combination of two or more thereof, or may be based on reference Figures 3 to 14 Describe the method of operation to operate.

[0120] The plurality of devices 1210 to 1240 may include, for example, electronic circuits, logic circuits, or memory circuits configured to support various operations of the electronic system 1000. The plurality of devices 1210 to 1240 may be provided with power from the power management integrated circuit 1100 and may operate based on the provided power. For example, the first device 1210 may receive a first output voltage VOUT1 from the power management integrated circuit 1100 and may operate based on the first output voltage VOUT1. The second device 1220 may receive a second output voltage VOUT2 from the power management integrated circuit 1100 and may operate based on the second output voltage VOUT2. Each of the third device 1230 and the fourth device 1240 may receive a third output voltage VOUT3 from the power management integrated circuit 1100 and may operate based on the third output voltage VOUT3.

[0121] In an embodiment, the first output voltage VOUT1 to the third output voltage VOUT3 may have different values ​​or may have the same value. For example, the first output voltage VOUT1 may be the same as the second output voltage VOUT2, and the first output voltage VOUT1 may be different from the third output voltage VOUT3. In this case, the regulators 1110 to 1130 may generate the first output voltage to the third output voltage VOUT1, VOUT2 and VOUT3 respectively based on the size (e.g., W / L) of the transmission transistor unit 160 or 260 or the structure (e.g., CS structure or a combination of CS and SF structures) of the transmission transistor unit 160 or 260.

[0122] Fig.16 is a block diagram illustrating an electronic system to which a voltage regulator according to an embodiment of the present disclosure is applied.

[0123] Reference Fig.16, the electronic system 2000 may include a power management integrated circuit (PMIC) 2100 and a plurality of devices 2210 , 2220 , 2230 , and 2240 .

[0124] The power management integrated circuit 2100 may generate a plurality of reference voltages VREF1 to VREF3 by using an external power PWR. For example, the power management integrated circuit 2100 may generate a plurality of reference voltages VREF1 to VREF3 by using a reference voltage generator.

[0125] The plurality of devices 2210 to 2240 may receive the plurality of reference voltages VREF1 to VREF3 from the power management integrated circuit 2100, and may generate an operating voltage by using the reference voltages VREF1 to VREF3. For example, each of the plurality of devices 2210 to 2240 may include a voltage regulator. The voltage regulator of the first device 2210 may generate a first operating voltage to be used in the first device 2210 based on the first reference voltage VREF1. The voltage regulator of the second device 2220 may generate a second operating voltage to be used in the second device 2220 based on the second reference voltage VREF2. The voltage regulator of the third device 2230 may generate a third operating voltage to be used in the third device 2230 based on the second reference voltage VREF2. The voltage regulator of the fourth device 2240 may generate a fourth operating voltage to be used in the fourth device 2240 based on the third reference voltage VREF3.

[0126] In an embodiment, the voltage regulator included in each of the plurality of devices 2210 to 2240 may be a reference Figures 3 to 14 One of the regulators described, or a combination thereof.

[0127] In an embodiment, the operating voltages generated by using the same reference voltage may be identical to each other. For example, the second operating voltage and the third operating voltage generated by the voltage regulators of the second device 2220 and the third device 2230 using the second reference voltage VREF2 may be identical to each other. In addition, the operating voltages generated by using the same reference voltage may have different levels. For example, the second operating voltage and the third operating voltage generated by the voltage regulators of the second device 2220 and the third device 2230 using the second reference voltage VREF2 may be different from each other. This may be variously changed or modified according to the manner in which the voltage regulator is implemented and the level of the operating voltage used by each device.

[0128] Fig.17 is a diagram of a system 3000 according to an embodiment of the present disclosure.

[0129] Fig.17The system 3000 may be a mobile system, such as, for example, a portable communication terminal (eg, a mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. However, Fig.17 The system 3000 is not necessarily limited to a mobile system, and may be, for example, a PC, a laptop computer, a server, a media player, or an automotive device (eg, a navigation device).

[0130] Reference Fig.17 , the system 3000 may include a main processor 3100, a memory (e.g., 3200a and 3200b), and a storage device (e.g., 3300a and 3300b). In addition, the system 3000 may include at least one of an image capture device 3410, a user input device 3420, a sensor 3430, a communication device 3440, a connection interface 3450, a speaker 3460, a display 3470, and a power supply device 3480.

[0131] The main processor 3100 may control all operations of the system 3000, for example, operations of other components included in the system 3000. The main processor 3100 may be implemented as, for example, a general-purpose processor, a dedicated processor, or an application processor.

[0132] The main processor 3100 may include at least one CPU core 3110, and also include a controller 3120 configured to control memories 3200a and 3200b and / or storage devices 3300a and 3300b. In some embodiments, the main processor 3100 may also include an accelerator 3130, which is a dedicated circuit for high-speed data operations (such as artificial intelligence (AI) data operations). The accelerator 3130 may include a graphics processing unit (GPU), a neural processing unit (NPU) and / or a data processing unit (DPU), and may be implemented as a chip physically separated from other components of the main processor 3100.

[0133] Memories 3200a and 3200b may be used as main memory devices of system 3000. Although each of memories 3200a and 3200b may include volatile memory, such as, for example, static random access memory (SRAM) and / or dynamic RAM (DRAM), each of memories 3200a and 3200b may also include non-volatile memory, such as, for example, flash memory, phase change RAM (PRAM) and / or resistive RAM (RRAM). Memories 3200a and 3200b may be implemented in the same package as main processor 3100.

[0134] The storage devices 3300a and 3300b may be used as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have a larger storage capacity than the memories 3200a and 3200b. The storage devices 3300a and 3300b may include storage controllers (STRG CTRL) 3310a and 3310b, respectively, and non-volatile memories (NVMs) 3320a and 3320b configured to store data via the control of the storage controllers 3310a and 3310b. Although the NVMs 3320a and 3320b may include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs 3320a and 3320b may include other types of NVMs, such as, for example, PRAM and / or RRAM.

[0135] The storage devices 3300a and 3300b may be physically separated from the main processor 3100 and included in the system 3000 or implemented in the same package as the main processor 3100. In addition, the storage devices 3300a and 3300b may be, for example, solid-state devices (SSDs) or memory cards, and may be detachably combined with other components of the system 3000 through interfaces (such as the connection interface 3450 to be described below). The storage devices 3300a and 3300b may be devices to which a standard protocol (such as, for example, Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or Non-Volatile Memory Express (NVMe)) is applied, but are not limited thereto.

[0136] The image capture device 3410 can capture still images or moving images. The image capture device 3410 may include, for example, a camera, a camcorder, and / or a webcam.

[0137] The user input device 3420 may receive various types of data input by a user of the system 3000 and include, for example, a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0138] The sensor 3430 may detect various types of physical quantities that may be obtained from the outside of the system 3000 and convert the detected physical quantities into electrical signals. The sensor 3430 may include, for example, a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0139] The communication device 3440 can send and receive signals between other devices outside the system 3000 according to various communication protocols. The communication device 3440 may include, for example, an antenna, a transceiver and / or a modem. The connection interface 3450 may provide a connection between the system 3000 and an external device, which is connected to the system 3000 and can send and receive data to and from the system 3000.

[0140] The connection interface 3450 can be implemented by using various interface schemes, such as, for example, Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, MultiMediaCard (MMC) interface, eMMC interface, UFS interface, embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0141] Speaker 3460 and display 3470 may be used as output devices configured to output visual information and auditory information, respectively, to a user of system 3000 .

[0142] The power supply device 3480 may appropriately convert power from the embedded battery of the system 3000 and / or an external power source so as to supply power to each component of the system 3000. In an embodiment, the power supply device 3480 may include a reference Figures 3 to 16 A voltage regulator is described and can be configured to generate various operating voltages by using the voltage regulator.

[0143] As is conventional in the field of the present disclosure, embodiments are described and shown in the accompanying drawings in terms of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where these blocks, units and / or modules are implemented by microprocessors, etc., they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and they can be selectively driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions.

[0144] According to an embodiment of the present disclosure, a voltage regulator having a simple structure and improved PSRR characteristics, an electronic system including the voltage regulator, and an operating method of the voltage regulator are provided.

[0145] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A voltage regulator configured to generate an output voltage, comprising: a comparison unit configured to generate a second voltage based on a reference voltage and a first voltage generated by feedback of the output voltage; a power supply noise replica buffer unit configured to generate a third voltage, the third voltage including power supply noise replicated based on the second voltage; as well as a pass transistor configured to generate the output voltage in response to the third voltage, Wherein, the power supply noise replica buffer unit comprises: a zeroth transistor connected between a ground node and a zeroth node and configured to operate in response to the second voltage; a first transistor connected between the zeroth node and a power supply node and including a gate node connected to a second node; a high pass filter connected between the second node and the third node; a second transistor connected between the power supply node and a first node connected to the third node and including a gate node connected to the third node; and a current source connected between the first node and the ground node, The power supply noise replica buffer unit provides the third voltage through the zeroth node.

2. The voltage regulator according to claim 1, further comprising: A feedback unit is configured to generate the first voltage based on the output voltage.

3. The voltage regulator according to claim 1, wherein: Each of the zeroth transistor, the first transistor, and the second transistor includes a p-type metal oxide semiconductor field effect transistor.

4. The voltage regulator according to claim 1, wherein: The current source is configured to replicate a bias current generated by an external bias current generator that generates the bias current for operation of the regulator.

5. The voltage regulator according to claim 1, wherein: The high pass filter comprises: a resistor connected between the second node and the third node; and A capacitor is connected between the second node and the ground node.

6. The voltage regulator according to claim 1, further comprising: a bias current generating unit configured to generate a bias current for operation of the regulator, Wherein, the bias current generating unit comprises: a current generator configured to generate an initial current; and A low pass filter is configured to extract a low frequency component of the initial current.

7. The voltage regulator according to claim 2, wherein: The pass transistor is connected between the power supply node and the output node, and Wherein, the feedback unit is connected between the output node and the comparison unit.

8. The voltage regulator according to claim 6, wherein: The current source is configured to replicate the current generated by the bias current generating unit.

9. A voltage regulator configured to generate an output voltage, comprising: a comparison unit configured to generate a second voltage based on a reference voltage and a first voltage generated by feedback of the output voltage; a power supply noise replica buffer unit configured to generate a bias signal including noise of a power supply voltage; a first buffer configured to generate a third voltage based on the bias signal and the second voltage; a second buffer configured to buffer a fourth voltage based on the third voltage; as well as A pass transistor is configured to generate the output voltage in response to the fourth voltage.

10. The voltage regulator according to claim 9, further comprising: A feedback unit is configured to generate the first voltage based on the output voltage.

11. The voltage regulator according to claim 9, wherein: The power supply noise replica buffer unit comprises: a high pass filter configured to filter high frequency components of the power supply voltage; and An amplifier is configured to amplify the high frequency component to generate the bias signal.

12. The voltage regulator according to claim 9, further comprising: a bias current generating unit configured to generate a bias current for operation of the regulator, Wherein, the bias current generating unit comprises: a current generator configured to generate a reference current by using the power supply voltage; and A low pass filter is configured to extract a low frequency component of the reference current based on the reference current and generate the bias current.

13. The voltage regulator according to claim 9, wherein: The power supply noise replica buffer unit comprises: a bias current source configured to filter a high frequency component of the power supply voltage and generate a bias signal by amplifying the high frequency component, Wherein, the first buffer comprises: A zeroth transistor is connected between the bias current source and a ground node and is configured to operate in response to the second voltage.

14. The voltage regulator according to claim 13, wherein: The bias current source comprises: a current source connected between the ground node and the first node; a first transistor connected between the first node and a power supply node and including a gate node connected to a second node, wherein the first node and the second node are connected; a high pass filter connected between the second node and the third node; and a second transistor connected between the power supply node and the zeroth node and including a gate node connected to the third node, Wherein, the first terminal of the zeroth transistor is connected to the zeroth node.

15. The voltage regulator according to claim 14, wherein: The high pass filter comprises: a resistor connected between the second node and the third node; and A capacitor is connected between the third node and the ground node.

16. The voltage regulator according to claim 14, wherein: The current source is configured to replicate a current generated from an external bias current generator.

17. A method for operating a voltage stabilizer, the method comprising: generating a first voltage by comparing a reference voltage and a feedback voltage of the output voltage; generating a second voltage based on the first voltage and a bias signal including a high frequency component of a power supply voltage of the regulator; as well as The output voltage is generated based on the second voltage.

18. The method according to claim 17, wherein: The first voltage is generated by amplifying a difference between the output voltage and the feedback voltage.

19. The method according to claim 17, wherein: The bias signal is generated by a power supply noise replica buffer unit, Wherein, the power supply noise replica buffer unit comprises: a high pass filter configured to extract a high frequency component of a power supply voltage of the regulator; and An amplifier is configured to generate the bias signal by amplifying the high frequency component.

20. The method according to claim 17, wherein: The output voltage is generated by a transistor including a first terminal connected to a power supply node and configured to operate in response to the second voltage.

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