A self-modulating high-voltage linear regulator

Abstract

This application discloses a self-modulated high-voltage linear regulator. By electrically connecting the voltage terminal of an error amplifier to the voltage output port using this regulator, the error amplifier can operate under a self-modulated output voltage. This not only avoids the need for an additional pre-regulator module but also reduces the number of high-voltage transistors required in the circuit. The self-modulated LDO structure provided in this application reduces the number of high-voltage MOSFETs required without employing any pre-regulator circuit module and improves the output voltage's ability to suppress power supply variations, thereby improving the stability and accuracy of the output voltage.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a self-modulated high-voltage linear regulator. Background Technology

[0002] High-voltage linear regulators (LDOs) play a crucial role in power management systems, providing relatively low supply voltages to the internal modules of the chip. Typically, high-voltage LDOs not only need to adapt to a wide input voltage range but also possess excellent power supply rejection capabilities to minimize output voltage variations caused by input voltage fluctuations, ensuring the stability and reliability of the system's power supply.

[0003] Existing high-voltage linear regulator topologies such as Figure 1 As shown, VIN is a high-voltage power rail with a wide range above 5V, and VOUT is the output voltage of the LDO. VBG is a temperature-independent bandgap reference voltage, typically 1.2V. The bias circuit operates between VIN and GND, providing bias voltage or current to the error amplifier. The advantage of this topology is the simplicity of the LDO structure; it only requires replacing some of the low-voltage MOSFETs in the low-voltage LDO with high-voltage MOSFETs, reducing design complexity. However, the disadvantage is that because the error amplifier also operates between the high voltage VIN and GND, many high-voltage MOSFETs are needed to implement the error amplifier. The area occupied by a single high-voltage MOSFET is typically tens or even hundreds of times larger than that of a low-voltage MOSFET with the same width-to-length ratio, significantly increasing the area overhead of the high-voltage LDO. Another topology is shown below. Figure 2 As shown, this structure's error amplifier no longer operates directly between VIN and GND. Instead, a pre-regulator module, operating directly at VIN, generates a pre-regulated voltage of approximately 5V or lower, and the error amplifier then operates at this pre-regulated voltage. In this case, the error amplifier can be implemented using a low-voltage MOSFET, reducing circuit area overhead. However, this approach has the disadvantage of requiring an additional pre-regulator circuit, increasing circuit complexity. Furthermore, implementing the pre-regulator module typically requires a Zener diode, increasing the demands on the manufacturing process. Summary of the Invention

[0004] This application provides a self-modulated high-voltage linear regulator to solve the technical problems of large area and high circuit complexity of existing high-voltage linear regulators.

[0005] To address the aforementioned technical problems, the first aspect of this application provides a self-modulated high-voltage linear regulator, comprising: a high-voltage input voltage, a bias circuit, an error amplifier, a power load transistor, a feedback resistor network, and a voltage output port, including:

[0006] The voltage terminal of the error amplifier is electrically connected to the voltage output port.

[0007] Preferably, the feedback resistor network specifically includes a first resistor and a second resistor connected in series.

[0008] Preferably, the bias circuit specifically includes: 3 high-voltage PMOS transistors, 3 low-voltage PMOS transistors, a high-voltage NMOS transistor (MN10), a low-voltage NMOS transistor (MN9), and 3 resistive elements, wherein the 3 low-voltage PMOS transistors include: low-voltage PMOS transistor (MP9), low-voltage PMOS transistor (MP10), and low-voltage PMOS transistor (MP11); the 3 high-voltage PMOS transistors include: high-voltage PMOS transistor (MP12), high-voltage PMOS transistor (MP13), and high-voltage PMOS transistor (MP14); and the 3 resistive elements include: a third resistor, a fourth resistor, and a fifth resistor.

[0009] The source of each low-voltage PMOS transistor is connected to the high-voltage input voltage, and the drain of each low-voltage PMOS transistor is connected to the source of a high-voltage PMOS transistor. The drain of the high-voltage PMOS transistor (MP12) is connected to the drain of the high-voltage NMOS transistor (MN10) through the fifth resistor. The drains of the other two high-voltage PMOS transistors are led out as bias current output ports. The two ends of the fifth resistor are respectively led out and connected to the gates of the low-voltage PMOS transistor and the high-voltage PMOS transistor.

[0010] The source of the high-voltage NMOS transistor (MN10) is grounded through the third resistor, and the gate of the high-voltage NMOS transistor (MN10) is connected to the high-voltage input voltage through the fourth resistor.

[0011] The drain of the low-voltage NMOS transistor (MN9) is connected to the high-voltage input voltage through the fourth resistor, the gate of the low-voltage NMOS transistor (MN9) is connected to the source of the high-voltage NMOS transistor, and the source of the low-voltage NMOS transistor (MN9) is grounded.

[0012] Preferably, the error amplifier specifically includes: 7 low-voltage NMOS transistors (MN1~MN6, MN8), 7 high-voltage NMOS transistors (MN7), 6 low-voltage PMOS transistors (MP1~MP5, MP8) and a compensation capacitor (Cc).

[0013] The gate of the low-voltage PMOS transistor (MP1) is connected to the feedback resistor network. The source of the low-voltage PMOS transistor (MP1) is connected to the source of the low-voltage PMOS transistor (MP2) and the drain of the low-voltage PMOS transistor (MP8). The drain of the low-voltage PMOS transistor (MP1) is connected to the drain of the low-voltage NMOS transistor (MN2). The source of the low-voltage NMOS transistor (MN2) is grounded.

[0014] The gate of the low-voltage PMOS transistor (MP2) is used to connect to the input reference voltage. The drain of the low-voltage PMOS transistor (MP2) is connected to the drain and gate of the low-voltage NMOS transistor (MN3) and the gate of the low-voltage NMOS transistor (MN4). The source of the low-voltage NMOS transistor (MN3) is grounded.

[0015] The source of the low-voltage NMOS transistor (MN2) is grounded. The gates of both the low-voltage NMOS transistor (MN2) and the low-voltage NMOS transistor (MN1) are connected to the drain of the low-voltage PMOS transistor (MP1). The drain of the low-voltage NMOS transistor (MN1) is connected to the gate and drain of the low-voltage PMOS transistor (MP3) and the gate of the low-voltage PMOS transistor (MP4), respectively.

[0016] The sources of the low-voltage PMOS transistors (MP3) and (MP4) are connected to the first bias current output port;

[0017] The drain of the low-voltage PMOS transistor (MP4) is connected to the drain of the low-voltage NMOS transistor (MN4), and the source of the low-voltage NMOS transistor (MN4) is grounded.

[0018] The gate of the low-voltage PMOS transistor (MP5) is connected to the drain of the low-voltage PMOS transistor (MP4), the source of the low-voltage PMOS transistor (MP5) is connected to the first bias current output port, and the drain of the low-voltage PMOS transistor (MP5) is connected to the drain of the low-voltage NMOS transistor (MN5).

[0019] The source of the low-voltage PMOS transistor (MP8) is connected to the first bias current output port, and the gate of the low-voltage PMOS transistor (MP8) is connected to the drain of the low-voltage PMOS transistor (MP8).

[0020] One end of the compensation capacitor (Cc) is connected between the drain of the low-voltage PMOS transistor (MP4) and the drain of the low-voltage NMOS transistor (MN4), and the other end is connected between the drain of the low-voltage PMOS transistor (MP5) and the drain of the low-voltage NMOS transistor (MN5).

[0021] The gate of the low-voltage NMOS transistor (MN8) is connected between the drain of the low-voltage PMOS transistor (MP5) and the drain of the low-voltage NMOS transistor (MN5). The drain of the low-voltage NMOS transistor (MN8) is connected to the voltage output port, and the source of the low-voltage NMOS transistor (MN8) is grounded.

[0022] The high-voltage NMOS transistor (MN7) and the low-voltage NMOS transistor (MN6) are common-source and common-gate transistors. The drain of the high-voltage NMOS transistor (MN7) is connected to the second bias current output port, the source of the high-voltage NMOS transistor (MN7) is connected to the drain of the low-voltage NMOS transistor (MN6), and the source of the low-voltage NMOS transistor (MN6) is connected to the gate of the low-voltage NMOS transistor (MN8).

[0023] Preferably, the power load transistor is a high-voltage PMOS transistor.

[0024] Preferably, the compensation capacitor is a Miller compensation capacitor.

[0025] As can be seen from the above technical solutions, this application has the following advantages:

[0026] The high-voltage linear regulator provided in this application electrically connects the voltage terminal of the error amplifier to the voltage output port, enabling the error amplifier to operate with a self-modulated output voltage. This not only avoids the need for an additional pre-regulator module but also reduces the number of high-voltage transistors required in the circuit. The self-modulated LDO structure provided in this application reduces the number of high-voltage MOSFETs required without employing any pre-regulator circuit module and improves the output voltage's ability to suppress power supply variations, thereby improving the stability and accuracy of the output voltage. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of an existing high-voltage linear regulator.

[0029] Figure 2 This is a schematic diagram of another existing high-voltage linear regulator.

[0030] Figure 3 This is a schematic diagram of a self-modulated high-voltage linear regulator provided in this application.

[0031] Figure 4 The present application provides a specific circuit diagram of the error amplifier for a self-modulated high-voltage linear regulator.

[0032] Figure 5 The present application provides a specific circuit diagram of the bias circuit for a self-modulated high-voltage linear regulator.

[0033] Figure 6 The figure shows the simulation results of power suppression obtained based on a self-modulated high-voltage linear regulator provided in this application.

[0034] Figure 7 The simulation results show the linear regulation rate obtained based on a self-modulated high-voltage linear regulator provided in this application. Detailed Implementation

[0035] Existing high-voltage linear regulator topologies such as Figure 1 As shown, VIN is a high-voltage power rail with a wide range and a voltage level higher than 5V. OUT This is the output voltage of the LDO. V BG This is a temperature-independent bandgap reference voltage, typically 1.2V. The bias circuit operates at V... IN Between GND and the voltage source (VIN), a bias voltage or current is provided for the error amplifier. The advantage of this topology is the simplicity of the LDO structure; it only requires replacing some of the low-voltage MOSFETs in the low-voltage LDO with high-voltage MOSFETs, reducing design complexity. However, the disadvantage is that because the error amplifier also operates between the high voltage VIN and GND, many high-voltage MOSFETs are needed to implement the error amplifier. The area occupied by a single high-voltage MOSFET is typically tens or even hundreds of times larger than that of a low-voltage MOSFET with the same width-to-length ratio, significantly increasing the area overhead of the high-voltage LDO. A representative solution is a high-voltage linear regulator proposed in patent CN103955251A. The high-voltage LDO structure proposed in this patent belongs to... Figure 1 The structure shown is such that, because the amplifier operates under a high-voltage power supply, numerous high-voltage transistors are required to implement the circuit, increasing the area overhead.

[0036] Another topology, such as Figure 2 As shown, in this structure, the error amplifier no longer operates directly between VIN and GND. Instead, a pre-regulator module, which operates directly under VIN, generates a pre-regulated voltage of approximately 5V or lower, and the error amplifier then operates under this pre-regulated voltage. In this case, the error amplifier can be implemented using a low-voltage MOSFET, reducing circuit area overhead. However, the disadvantage of this scheme is the need for an additional pre-regulator circuit, increasing circuit complexity. Furthermore, implementing the pre-regulator module typically requires a Zener diode, increasing the demands on the manufacturing process. A representative solution is a high-voltage LDO circuit with clamping and current limiting function proposed in patent CN113434002A. This solution belongs to... Figure 2 The mentioned topology uses three Zener diodes connected in series at the input to reduce the high input voltage to a low voltage range. This design employs lower voltage-rated components, achieving circuit simplicity and cost reduction. Although compared to... Figure 1The structure effectively reduces the number of high-voltage tubes and the problem of excessive circuit area, but it cannot achieve further reduction in area.

[0037] This application provides a self-modulated high-voltage linear regulator to solve the technical problems of large area and high circuit complexity of existing high-voltage linear regulators.

[0038] To make the inventive objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0040] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0041] First, a detailed description of an embodiment of a self-modulated high-voltage linear regulator provided in this application is as follows:

[0042] like Figure 3 As shown in the illustration, an embodiment of this application provides a self-modulated high-voltage linear regulator, comprising: a high-voltage input voltage, a bias circuit, an error amplifier, a power load transistor, a feedback resistor network, and a voltage output port, including:

[0043] The voltage terminal of the error amplifier is electrically connected to the voltage output port.

[0044] Preferably, the bias circuit specifically includes: 3 high-voltage PMOS transistors, 3 low-voltage PMOS transistors, a high-voltage NMOS transistor MN10, a low-voltage NMOS transistor MN9, and 3 resistive elements, wherein the 3 low-voltage PMOS transistors include: low-voltage PMOS transistor MP9, low-voltage PMOS transistor MP10, and low-voltage PMOS transistor MP11; the 3 high-voltage PMOS transistors include: high-voltage PMOS transistor MP12, high-voltage PMOS transistor MP13, and high-voltage PMOS transistor MP14; and the 3 resistive elements include: a third resistor R3, a fourth resistor R4, and a fifth resistor R5.

[0045] The source of each low-voltage PMOS transistor is connected to the high-voltage input voltage, and the drain of each low-voltage PMOS transistor is connected to the source of a high-voltage PMOS transistor. The drain of the high-voltage PMOS transistor MP12 is connected to the drain of the high-voltage NMOS transistor MN10 through the fifth resistor R5. The drains of the other two high-voltage PMOS transistors are led out as bias current output ports. The two ends of the fifth resistor R5 are led out and connected to the gates of the low-voltage PMOS transistor and the high-voltage PMOS transistor, respectively.

[0046] The source of the high-voltage NMOS transistor MN10 is grounded through the third resistor R3, and the gate of the high-voltage NMOS transistor MN10 is connected to the high-voltage input voltage through the fourth resistor R4.

[0047] The drain of the low-voltage NMOS transistor MN9 is connected to the high-voltage input voltage through the fourth resistor R4. The gate of the low-voltage NMOS transistor MN9 is connected to the source of the high-voltage NMOS transistor, and the source of the low-voltage NMOS transistor MN9 is grounded.

[0048] Preferably, the error amplifier specifically includes: 7 low-voltage NMOS transistors MN1~MN6, MN8, 7 high-voltage NMOS transistor MN7, 6 low-voltage PMOS transistors MP1~MP5, MP8, and a compensation capacitor Cc;

[0049] The gate of the low-voltage PMOS transistor MP1 is connected to the feedback resistor network. The source of the low-voltage PMOS transistor MP1 is connected to the source of the low-voltage PMOS transistor MP2 and the drain of the low-voltage PMOS transistor MP8. The drain of the low-voltage PMOS transistor MP1 is connected to the drain of the low-voltage NMOS transistor MN2. The source of the low-voltage NMOS transistor MN2 is grounded.

[0050] The gate of the low-voltage PMOS transistor MP2 is used to connect to the input reference voltage. The drain of the low-voltage PMOS transistor MP2 is connected to the drain and gate of the low-voltage NMOS transistor MN3 and the gate of the low-voltage NMOS transistor MN4, respectively. The source of the low-voltage NMOS transistor MN3 is grounded.

[0051] The source of low-voltage NMOS transistor MN2 is grounded. The gates of both low-voltage NMOS transistors MN2 and MN1 are connected to the drain of low-voltage PMOS transistor MP1. The drain of low-voltage NMOS transistor MN1 is connected to the gate and drain of low-voltage PMOS transistor MP3 and the gate of low-voltage PMOS transistor MP4, respectively.

[0052] The sources of low-voltage PMOS transistors MP3 and MP4 are connected to the first bias current output port.

[0053] The drain of the low-voltage PMOS transistor MP4 is connected to the drain of the low-voltage NMOS transistor MN4, and the source of the low-voltage NMOS transistor MN4 is grounded.

[0054] The gate of the low-voltage PMOS transistor MP5 is connected to the drain of the low-voltage PMOS transistor MP4, the source of the low-voltage PMOS transistor MP5 is connected to the first bias current output port, and the drain of the low-voltage PMOS transistor MP5 is connected to the drain of the low-voltage NMOS transistor MN5.

[0055] The source of the low-voltage PMOS transistor MP8 is connected to the first bias current output port, and the gate of the low-voltage PMOS transistor MP8 is connected to the drain of the low-voltage PMOS transistor MP8.

[0056] One end of the compensation capacitor Cc is connected between the drain of the low-voltage PMOS transistor MP4 and the drain of the low-voltage NMOS transistor MN4, and the other end is connected between the drain of the low-voltage PMOS transistor MP5 and the drain of the low-voltage NMOS transistor MN5.

[0057] The gate of the low-voltage NMOS transistor MN8 is connected between the drain of the low-voltage PMOS transistor MP5 and the drain of the low-voltage NMOS transistor MN5. The drain of the low-voltage NMOS transistor MN8 is connected to the voltage output port, and the source of the low-voltage NMOS transistor MN8 is grounded.

[0058] The high-voltage NMOS transistor MN7 and the low-voltage NMOS transistor MN6 are common-source and common-gate transistors. The drain of the high-voltage NMOS transistor MN7 is connected to the second bias current output port, the source of the high-voltage NMOS transistor MN7 is connected to the drain of the low-voltage NMOS transistor MN6, and the source of the low-voltage NMOS transistor MN6 is connected to the gate of the low-voltage NMOS transistor MN8.

[0059] More specifically, the feedback resistor network includes a first resistor R1 and a second resistor R2 connected in series.

[0060] More specifically, the power load is a high-voltage PMOS transistor MP6.

[0061] More specifically, the compensation capacitor Cc is a Miller compensation capacitor.

[0062] It should be noted that the high-voltage LDO topology used in this invention is as follows: Figure 3 As shown in the figure, the circuit includes a bias circuit, an error amplifier, and a power load transistor M. POW And the feedback resistor network R2, R1. V IN It is a wide-range high-voltage input voltage, V OUT This is the output voltage of the LDO, and its specific value is determined by the ratio of R2 to R1. In the application scenario of this embodiment, V IN The input voltage range is 7-20V. OUT The output voltage is 5V. In the diagram, the error amplifier operates at the self-modulated 5V output, not at V. IN Under input voltage.

[0063] Figure 4 This is a schematic diagram of the main circuit structure of the self-modulated high-voltage linear regulator provided in this application. Figure 4 The structure mainly shows the connection relationship between the error amplifier and other components, such as the bias circuit, power load transistor, and feedback resistor network, as shown in the figure. REF The input reference voltage of the LDO is typically the bandgap reference voltage V. BG The error amplifier, composed of NMOS transistors MN1-MN8, PMOS transistors MP1-MP5 and MP8, and compensation capacitor Cc, operates at a self-modulated output voltage V. OUT Below. MN7 and MN6 are common-source cascode transistors. MN7 is a high-voltage cascode transistor, its purpose being to isolate MN6 from the high-voltage power supply and prevent the low-voltage MN6 from breaking down and failing. MN6 is a low-voltage cascode transistor, its purpose being to clamp and fold the small-signal current output by MP5 transistor to the current bias current I. bias MP6 is a high-voltage PMOS transistor; this component corresponds to... Figure 3 The power load transistor M in POW This is used to provide a strong output current capability. R1 and R2 form a voltage divider resistor network that determines V. OUT The output voltage of C. C It is a Miller compensation capacitor, used for frequency compensation. It keeps the dominant pole of the LDO in the low-frequency range, improving the loop stability of the LDO.

[0064] in, Figure 4 The bias current I shown bias Specifically generated by a bias circuit, the circuit structure of which in this embodiment is as follows: Figure 5 As shown in the figure, the bias circuit includes two NMOS transistors MN9 and MN10, six PMOS transistors MP9~MP14, and three resistor elements R3~R5. Among them, MP12, MP13, MP14, and MN10 are high-voltage transistors LDMOS.

[0065] pass Figure 4 and Figure 5 As can be seen from the circuit structure shown, the LDO structure used in this embodiment only requires 6 high-voltage transistors and does not require Zener transistors or other pre-regulatory circuits, which can effectively reduce the circuit area overhead and cost.

[0066] like Figure 6 and Figure 7 As shown, where, Figure 6 The figure shows the simulation results of power supply rejection for the self-modulated high-voltage linear regulator (LDO) structure based on this application. As can be seen from the figure, the self-modulation structure of the high-voltage LDO effectively improves the power supply rejection performance. At low frequencies, the power supply rejection of the LDO is -92dB. Figure 7 The figure shows the simulation results of the linear regulation of the self-modulated high-voltage linear regulator structure based on this application. As can be seen from the figure, when the high-voltage input power supply changes from 7-20V, the LDO output only changes by 330uV. Figure 6 and Figure 7 As can be seen, the self-modulated high-voltage linear regulator structure provided in this application not only has a simple circuit structure and does not require many high-voltage LDMOS transistors to implement the circuit, but also ensures the ability to suppress power supply changes, thereby improving the stability and accuracy of the output voltage.

[0067] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A self-modulated high-voltage linear regulator, comprising: The high-voltage input voltage, bias circuit, error amplifier, power load transistor, feedback resistor network, and voltage output port are characterized by comprising: The voltage terminal of the error amplifier is electrically connected to the voltage output port; The error amplifier specifically includes: 7 low-voltage NMOS transistors MN1~MN6, MN8, 7 high-voltage NMOS transistor MN7, 6 low-voltage PMOS transistors MP1~MP5, MP8, and a compensation capacitor Cc; The gate of the low-voltage PMOS transistor MP1 is connected to the feedback resistor network. The source of the low-voltage PMOS transistor MP1 is connected to the source of the low-voltage PMOS transistor MP2 and the drain of the low-voltage PMOS transistor MP8. The drain of the low-voltage PMOS transistor MP1 is connected to the drain of the low-voltage NMOS transistor MN2. The source of the low-voltage NMOS transistor MN2 is grounded. The gate of the low-voltage PMOS transistor MP2 is used to connect to the input reference voltage. The drain of the low-voltage PMOS transistor MP2 is connected to the drain and gate of the low-voltage NMOS transistor MN3 and the gate of the low-voltage NMOS transistor MN4, respectively. The source of the low-voltage NMOS transistor MN3 is grounded. The source of low-voltage NMOS transistor MN2 is grounded. The gates of both low-voltage NMOS transistors MN2 and MN1 are connected to the drain of low-voltage PMOS transistor MP1. The drain of low-voltage NMOS transistor MN1 is connected to the gate and drain of low-voltage PMOS transistor MP3 and the gate of low-voltage PMOS transistor MP4, respectively. The sources of low-voltage PMOS transistors MP3 and MP4 are connected to the first bias current output port. The drain of the low-voltage PMOS transistor MP4 is connected to the drain of the low-voltage NMOS transistor MN4, and the source of the low-voltage NMOS transistor MN4 is grounded. The gate of the low-voltage PMOS transistor MP5 is connected to the drain of the low-voltage PMOS transistor MP4, the source of the low-voltage PMOS transistor MP5 is connected to the first bias current output port, and the drain of the low-voltage PMOS transistor MP5 is connected to the drain of the low-voltage NMOS transistor MN5. The source of the low-voltage PMOS transistor MP8 is connected to the first bias current output port, and the gate of the low-voltage PMOS transistor MP8 is connected to the drain of the low-voltage PMOS transistor MP8. One end of the compensation capacitor Cc is connected between the drain of the low-voltage PMOS transistor MP4 and the drain of the low-voltage NMOS transistor MN4, and the other end is connected between the drain of the low-voltage PMOS transistor MP5 and the drain of the low-voltage NMOS transistor MN5. The gate of the low-voltage NMOS transistor MN8 is connected between the drain of the low-voltage PMOS transistor MP5 and the drain of the low-voltage NMOS transistor MN5. The drain of the low-voltage NMOS transistor MN8 is connected to the voltage output port, and the source of the low-voltage NMOS transistor MN8 is grounded. The high-voltage NMOS transistor MN7 and the low-voltage NMOS transistor MN6 are common-source and common-gate transistors. The drain of the high-voltage NMOS transistor MN7 is connected to the second bias current output port. The source of the high-voltage NMOS transistor MN7 is connected to the drain of the low-voltage NMOS transistor MN6. The source of the low-voltage NMOS transistor MN6 is connected to the gate of the low-voltage NMOS transistor MN8. The gate of the low-voltage NMOS transistor MN6 is connected to the drain of the low-voltage PMOS transistor MP8.

2. The self-modulated high-voltage linear regulator according to claim 1, characterized in that, The feedback resistor network specifically includes a first resistor and a second resistor connected in series.

3. The self-modulated high-voltage linear regulator according to claim 1, characterized in that, The bias circuit specifically includes: 3 high-voltage PMOS transistors, 3 low-voltage PMOS transistors, a high-voltage NMOS transistor MN10, a low-voltage NMOS transistor MN9, and 3 resistors. The 3 low-voltage PMOS transistors are: MP9, MP10, and MP11; the 3 high-voltage PMOS transistors are: MP12, MP13, and MP14; and the 3 resistors are: a third resistor, a fourth resistor, and a fifth resistor. The source of each low-voltage PMOS transistor is connected to the high-voltage input voltage, and the drain of each low-voltage PMOS transistor is connected to the source of a high-voltage PMOS transistor. The drain of the high-voltage PMOS transistor MP12 is connected to the drain of the high-voltage NMOS transistor MN10 through the fifth resistor. The drains of the other two high-voltage PMOS transistors are led out as bias current output ports. The two ends of the fifth resistor are respectively led out and connected to the gates of the low-voltage PMOS transistor and the high-voltage PMOS transistor. The source of the high-voltage NMOS transistor MN10 is grounded through the third resistor, and the gate of the high-voltage NMOS transistor MN10 is connected to the high-voltage input voltage through the fourth resistor. The drain of the low-voltage NMOS transistor MN9 is connected to the high-voltage input voltage through the fourth resistor, the gate of the low-voltage NMOS transistor MN9 is connected to the source of the high-voltage NMOS transistor, and the source of the low-voltage NMOS transistor MN9 is grounded.

4. A self-modulated high-voltage linear regulator according to claim 1, characterized in that, The power load transistor is specifically a high-voltage PMOS transistor.

5. A self-modulated high-voltage linear regulator according to claim 3, characterized in that, The compensation capacitor is specifically a Miller compensation capacitor.

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