A constant-voltage-drop large-current active inductor circuit

Abstract

The present invention discloses a constant voltage drop large current active inductor circuit, which includes a bias circuit, a first-stage gain stage, a compensation stage, and a second-stage gain stage. The bias circuit generates a fixed voltage difference through a bias resistor, which is used to keep a constant voltage drop of the active inductor when the loop is locked; the first-stage gain stage is used to provide gain so that there is a certain accuracy when the loop is locked; while compensating for the loop stability, the compensation stage cooperates with the high output impedance of the first-stage gain stage, so that its output terminal exhibits inductive characteristics in a wide frequency band range; the second-stage gain stage is both an output stage and an active inductor device, which makes the current of the active inductor flow from the positive terminal to the negative terminal, thereby ensuring the normal operating point of the active device. The present invention realizes the simplification of the application. Especially in the application scenario of large current, only a small voltage drop is required to achieve the inductance effect.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a constant voltage drop large current active inductor circuit. Background Art

[0002] As Figure 1a The inductor shown is widely used in circuits, mainly for functions including current blocking, frequency selection, providing impedance that increases with frequency, etc. Taking the current blocking function as an example, it is required to maintain a high impedance for AC signals of a certain frequency to block the passage of high-frequency signal energy; at the same time, it can pass a certain DC current and contribute as little voltage drop as possible, that is, it has a low impedance for low-frequency signals. Discrete passive inductor components often have relatively large sizes, especially large current passive inductors, which bring great integration difficulties in the application end. The on-chip integrated passive inductor is also difficult to achieve a large inductance value economically. Active inductors can solve the two problems of large inductance value and large current at the same time, with low cost and very high integration, and have great advantages.

[0003] Traditional solutions for active inductors only require diodes and large resistors to achieve, as Figure 1b shown. The simple active inductor itself has various disadvantages. For example, the high impedance brought by the resistor often limits the maximum value that the impedance of the simple active inductor can reach, thus limiting its application; for example, it limits the blocking effect on high-frequency signals in the current blocking application. In addition, different from passive inductors, because there is an active circuit in the active inductor, its positive and negative terminals (Ind_P, Ind_N) are strictly distinguished, and there must be a certain voltage drop to ensure the normal operation of the active circuit. Let's call the end with a higher potential of the active inductor Ind_P and the end with a lower potential Ind_N. For example Figure 1b in the simple active inductor in, the Ind_P terminal is higher than the Ind_N terminal by the gate-source voltage of an NMOS when it is operating normally. Since the gate-source voltage of the active device will change with the current flowing during operation, the DC voltage drop of the simple active inductor will change significantly with the current flowing, which limits the application conditions again. Especially in the application scenario of large current, the large voltage drop will consume too much voltage, making it difficult to be used under the condition of a lower power supply voltage. Summary of the Invention

[0004] The purpose of the present invention is to provide a constant voltage drop large current active inductor circuit to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides a constant voltage drop large current active inductor circuit, including:

[0006] A bias circuit that generates a fixed voltage difference through a bias resistor and is used to keep the active inductor at a constant voltage drop when the loop is locked;

[0007] A first - stage gain stage, which is used to provide gain so that there is a certain accuracy when the loop is locked;

[0008] A compensation stage, while compensating for the loop stability, cooperates with the high output impedance of the first - stage gain stage, so that its output terminal exhibits inductive characteristics in a wide frequency band range;

[0009] A second - stage gain stage, which is both an output stage and an active inductor device, makes the current of the active inductor flow from the positive terminal to the negative terminal, thereby ensuring the normal operating point of the active device.

[0010] In one embodiment, the bias circuit includes: a bias resistor Rref for fixing the voltage drop of the active inductor, voltage regulator devices MPB1 and MPB2 for adapting the static operating point of the input stage of the operational amplifier, and bias current elements Ib1, Ib2, Ib3;

[0011] The first end of the bias resistor Rref is connected to the positive terminal Ind_P of the active circuit, the second end is connected to the source of the voltage regulator device MPB1, and the gate and drain of the voltage regulator device MPB1 are both grounded through the bias current element Ib1; the input end of the bias current element Ib2 is connected to the first - stage gain stage, and the output end is grounded; the input end of the bias current element Ib3 is connected to the gate and drain of the voltage regulator device MPB2, and the output end is grounded; the source of the voltage regulator device MPB2 is connected to the negative terminal Ind_N of the active circuit.

[0012] In one embodiment, the first - stage gain stage includes: PMOS transistors MPM1 and MPM2, PMOS transistors MPC1 and MPC2, NMOS transistors MNC1 and MNC2, and NMOS transistors MIN1 and MIN2;

[0013] The sources of PMOS transistors MPM1 and MPM2 are both connected to the positive terminal Ind_P of the active circuit, the drain of PMOS transistor MPM1 is connected to the source of PMOS transistor MPC1, and the gate is simultaneously connected to the gate of PMOS transistor MPM2 and the drain of PMOS transistor MPC2; the drain of PMOS transistor MPM2 is connected to the source of NMOS transistor MPC2, and the gates of PMOS transistors MPC1 and MPC2 are interconnected;

[0014] The drain of NMOS transistor MNC1 is connected to the drain of PMOS transistor MPC1, and the source is connected to the drain of NMOS transistor MIN1; the drain of NMOS transistor MNC2 is connected to the drain of PMOS transistor MPC2, and the source is connected to the drain of NMOS transistor MIN2; the gates of NMOS transistors MNC1 and MNC2 are interconnected; the gate of NMOS transistor MIN1 is connected to the gate of the voltage regulator device MPB1, and the gate of NMOS transistor MIN2 is connected to the second - stage gain stage; the sources of NMOS transistors MIN1 and MIN2 are both connected to the input end of the bias current element Ib2.

[0015] In one embodiment, the compensation stage consists of a capacitor C C and the first terminal of the capacitor C C is connected to the positive terminal Ind_P of the active circuit, and the second terminal is connected to the drains of both the PMOS transistor MPC1 and the NMOS transistor MNC1 simultaneously.

[0016] In one embodiment, the second-stage gain stage includes: a PMOS transistor MP2;

[0017] The source of the PMOS transistor MP2 is connected to the positive terminal Ind_P of the active circuit, the gate is connected to the second terminal of the capacitor C C and the drain is connected to the source of the voltage regulator device MPB2; the gate and the drain of the voltage regulator device MPB2 are connected to the gate of the NMOS transistor MIN2 simultaneously.

[0018] A constant-voltage-drop large-current active inductor circuit provided by the present invention simplifies the application. Especially in the application scenario of large current, only a small voltage drop needs to be consumed to achieve the inductor effect. Using active devices to replace passive large resistors realizes a higher impedance effect. Compared with the relatively large current-carrying capacity of the active inductor, the bias current of the active circuit is smaller, resulting in lower overall static power consumption. The lower DC impedance brought by the loop and the higher AC impedance brought by the active devices make the active inductor of this architecture obtain a larger equivalent inductance value than a simple active inductor, and this inductance value can be adjusted according to the compensation capacitor, making it more flexible to use than a passive inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1a is a schematic diagram of the inductor structure.

[0020] Figure 1b is a schematic diagram of a simple active inductor structure.

[0021] Figure 2 is a schematic diagram of a constant-voltage-drop large-current active inductor circuit structure provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] The following further describes in detail a constant-voltage-drop large-current active inductor circuit proposed by the present invention with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0023] The present invention provides a constant-voltage-drop large-current active inductor circuit, the structure of which is as Figure 2 shown, using a closed-loop feedback to lock the voltage drop of the active inductor; using a closed-loop circuit to realize the active inductor function in a wide frequency range. Figure 2The circuit also realizes the equivalent inductance between the positive terminal Ind_P and the negative terminal Ind_N. However, the voltage drop between the positive terminal Ind_P and the negative terminal Ind_N is controlled at a fixed value VREF. Even when a large current flows between the positive terminal Ind_P and the negative terminal Ind_N, theoretically this voltage drop can basically remain unchanged.

[0024] The active inductor circuit includes a bias circuit, a first-stage gain stage, a compensation stage, and a second-stage gain stage; among them,

[0025] The bias circuit includes: a bias resistor Rref for fixing the voltage drop of the active inductor, voltage regulator devices MPB1 and MPB2 for adapting the static operating point of the input stage of the operational amplifier, and bias current elements Ib1, Ib2, and Ib3. Among them, the bias resistor Rref generates a reference voltage VREF, which is used to ensure that when the loop is locked, the active inductor maintains a constant voltage drop.

[0026] The first-stage gain stage includes: PMOS transistors MPM1 and MPM2, PMOS transistors MPC1 and MPC2, NMOS transistors MNC1 and MNC2, and NMOS transistors MIN1 and MIN2. The first-stage gain stage is used to provide gain, so that there is a certain accuracy when the loop is locked. The first-stage gain stage cooperates with the voltage regulator devices MPB1 and MPB2 to ensure a reasonable static operating point.

[0027] The compensation stage consists of a capacitor C C to ensure loop stability.

[0028] The second-stage output stage includes: PMOS transistor MP2. Similar to a common two-stage operational amplifier, the PMOS transistor MP2 is used to transmit current, and the bias current element Ib3 is only used to provide static bias. When a large current needs to flow through the active inductor, the current will flow in from the positive terminal Ind_P and out from the negative terminal Ind_N. The large current only flows through the PMOS transistor MP2 and will not flow into other devices except this.

[0029] The present invention uses a fixed reference voltage to lock the voltage drop of the active inductor and uses the loop locking method to realize an active inductor with a wide frequency range.

[0030] The bias circuit uses the bias resistor Rref to generate a voltage with a fixed voltage difference VREF relative to the positive terminal Ind_P. This reference voltage is used for loop locking. After the loop is locked, a constant voltage drop is maintained between the positive terminal Ind_P and the negative terminal Ind_N. The active inductor only consumes almost a constant voltage during operation, especially when operating at a large current. Therefore, the equivalent parasitic DC resistance is smaller and the transmission efficiency is higher when operating at a large current.

[0031] The first-stage gain stage uses a cascode structure to provide sufficient gain for the loop. A compensation capacitor is placed at the output of the first-stage gain stage. While compensating for the loop stability, in combination with the high output impedance of the first-stage gain stage, it makes the output exhibit inductive characteristics within a wide frequency band. The size of the output compensation capacitor of the first-stage gain stage determines the value of the equivalent active inductor. The larger the capacitance value of the compensation capacitor, the larger the value of the active inductor. A relatively large value of the active inductor often requires an off-chip capacitor in the nF or uF range. A relatively small value can often be achieved with on-chip capacitors, and the value of the equivalent active inductor can be adjusted by controlling the size of the compensation capacitor to achieve more flexible applications.

[0032] The second-stage gain stage is both the output stage and the active inductor device. The two ports Ind_P and Ind_N of the active inductor appear at the source and drain of the output-stage device of the second-stage gain stage respectively, and the current of the active inductor also appears between these two ports. However, since the active inductor uses active devices, the current flow direction of the active inductor must be from the positive terminal Ind_P to the negative terminal Ind_N to ensure the normal operating point of the active devices.

[0033] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A constant voltage drop high current active inductor circuit, characterized in that: include: A bias circuit generates a fixed voltage difference through a bias resistor, which is used to keep a constant voltage drop across the active inductor when the loop is locked; The first gain stage is used to provide gain so that the loop can be locked with a certain accuracy; The compensation stage compensates for loop stability and, in conjunction with the high output impedance of the first gain stage, makes its output exhibit inductive characteristics over a wide frequency band; The second gain stage is both an output stage and an active device, which makes the current of the active inductor flow from the positive end to the negative end, thereby ensuring the normal working point of the active device; The bias circuit includes: a bias resistor Rref for fixing the active inductor voltage drop, voltage regulators MPB1 and MPB2 for adapting the static operating point of the first gain stage, and bias current elements Ib1, Ib2, and Ib3; The first end of the bias resistor Rref is connected to the positive end Ind_P of the active circuit, and the second end is connected to the source of the voltage regulator MPB1. The gate and drain of the voltage regulator MPB1 are both grounded through the bias current element Ib1; the input end of the bias current element Ib2 is connected to the first-stage gain stage, and the output end is grounded; the input end of the bias current element Ib3 is connected to the gate and drain of the voltage regulator MPB2, and the output end is grounded; the source of the voltage regulator MPB2 is connected to the negative end Ind_N of the active circuit; The first gain stage includes: PMOS tubes MPM1 and MPM2, PMOS tubes MPC1 and MPC2, NMOS tubes MNC1 and MNC2, and NMOS tubes MIN1 and MIN2; The source of the PMOS tube MPM1 and the source of MPM2 are both connected to the positive terminal Ind_P of the active circuit, the drain of the PMOS tube MPM1 is connected to the source of the PMOS tube MPC1, and the gate is connected to the gate of the PMOS tube MPM2 and the drain of the PMOS tube MPC2 at the same time; the drain of the PMOS tube MPM2 is connected to the source of the NMOS tube MPC2, and the gate of the PMOS tube MPC1 and the gate of the PMOS tube MPC2 are interconnected; The drain of NMOS tube MNC1 is connected to the drain of PMOS tube MPC1, and the source is connected to the drain of NMOS tube MIN1; the drain of NMOS tube MNC2 is connected to the drain of PMOS tube MPC2, and the source is connected to the drain of NMOS tube MIN2; the gate of NMOS tube MNC1 and the gate of NMOS tube MNC2 are interconnected; the gate of NMOS tube MIN1 is connected to the gate of voltage regulating device MPB1, and the gate of NMOS tube MIN2 is connected to the gate and drain of voltage regulating device MPB2; the source of NMOS tube MIN1 and the source of NMOS tube MIN2 are both connected to the input end of bias current element Ib2.

2. The constant voltage drop high current active inductor circuit as claimed in claim 1, characterized in that: The compensation stage consists of a capacitor C C Composition, capacitor C C The first end is connected to the positive end Ind_P of the active circuit, and the second end is connected to the drain of the PMOS tube MPC1 and the drain of the NMOS tube MNC1 at the same time.

3. The constant voltage drop high current active inductor circuit as claimed in claim 2, characterized in that: The second gain stage includes: a PMOS tube MP2; The source of the PMOS tube MP2 is connected to the positive terminal Ind_P of the active circuit, and the gate is connected to the capacitor C C The second end of the power supply circuit has a drain connected to the source of the voltage regulating device MPB2.

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