Data reading method and memory controller

Abstract

The invention discloses a data reading method and a memory controller. The method comprises the following steps: respectively storing a plurality of reading commands into cache pools corresponding to different chip enabling pins; when a preset condition is met, pre-sequencing operation is executed on the read commands in the cache pool, the read commands are grouped into a plurality of read command groups, the read commands in each group correspond to different planes, and the storage units belong to the same storage unit type; generating an execution command sequence according to the read command group; and completing a parallel read operation based on the execution command sequence. According to the method, the reading commands are optimally sorted and grouped, so that the reading speed and the data channel utilization rate of the SSD are improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to an AIPR (Asynchronous Independent Plane Read)-based data reading method and a memory controller suitable for a storage device equipped with a rewritable non-volatile memory module. Background Art

[0002] Non-volatile memory refers to computer memory in which the stored data does not disappear when the current is cut off. It has the advantages of non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory is a memory configured with NAND Flash (such as a solid-state drive), which has the characteristics of high read and write speed and does not require a mechanical structure to access data.

[0004] The storage organization of flash memory chips usually includes Die (chip) / LUN (Logical Unit Number), Plane (plane), Block (block) and Page (page). Among them, LUN is the smallest unit that independently executes commands in flash memory. A Die / LUN can contain multiple planes, and each plane is composed of hundreds or even thousands of blocks.

[0005] At present, SSD mainly uses command + address to read, write, erase and other operations on flash memory. For read operations, the mainstream methods include Single-plane read (SP), Multi-plane read (MP) and Asynchronous Independent Plane Read (AIPR).

[0006] SP read operations only perform read operations on one plane in a chip at a time. Although MP can perform operations on multiple planes in a chip, the same page address needs to be set. AIPR is a more advanced MP read operation that can perform independent read operations on different pages of multiple planes of the same chip. Compared with MP read operations, it significantly improves the read rate of SSDs. However, how to maximize the use of AIPR is still a problem that the industry needs to solve urgently. Summary of the invention

[0007] The purpose of the present invention is to provide a data reading method and a memory controller, aiming to solve the problem of low efficiency of AIPR command execution in the prior art, give full play to the multi-plane concurrent reading capability of the flash memory chip, and improve the command execution rate and data channel utilization of the storage device.

[0008] One or more embodiments of the present invention provide a data reading method based on asynchronous independent plane read (AIPR), which is applicable to a storage device equipped with a rewritable non-volatile memory module. The method includes: storing the plurality of read commands from the host system into one or more buffer pools, respectively, wherein the one or more buffer pools correspond to different chip enable pins; when a preset condition is met, performing a pre-sorting operation on the plurality of first read commands in the first buffer pool of the one or more buffer pools to group the plurality of first read commands into a plurality of read command groups, wherein one or more second read commands belonging to the same read command group correspond to different planes of the same chip in the storage device, and the storage units corresponding to the one or more second read commands belong to the same storage unit type; generating an execution command sequence corresponding to the first buffer pool according to the plurality of read command groups of the first buffer pool, and executing the plurality of commands according to the execution command sequence to complete the parallel reading operation corresponding to the plurality of first read commands.

[0009] In one or more embodiments of the present invention, the preset condition includes at least one of the following: the number of the multiple first read commands stored in the first cache pool reaches a predetermined threshold; or the waiting time of the earliest first read command stored in the first cache pool reaches a predetermined time threshold.

[0010] In one or more embodiments of the present invention, the method further includes: obtaining the physical address of each read command based on the recorded mapping information; and obtaining the physical characteristics of the physical address of the read command based on the physical address of the read command, wherein the physical characteristics include the chip enable pin, the plane, the chip and the storage unit type.

[0011] In one or more embodiments of the present invention, the step of performing the pre-sorting operation includes: grouping the multiple first read commands according to the storage cell types corresponding to each of the multiple first read commands to obtain one or more storage cell type command groups, wherein one or more first read commands belonging to the same storage cell type command group correspond to the same storage cell type; grouping the one or more first read commands in the same storage cell type command group according to the chips corresponding to each of the one or more first read commands in the same storage cell type command group to obtain one or more chip command groups, wherein one or more first read commands belonging to the same chip command group correspond to the same chip; and compiling one or more second read commands in each chip command group that each point to a different plane into the same read command group to obtain the multiple read command groups, wherein the processing order of the one or more second read commands in each read command group is set based on the order of the corresponding planes.

[0012] In one or more embodiments of the present invention, the multiple commands within the execution command sequence include the following types: read trigger commands, polling commands, and data access commands, wherein the step of generating the execution command sequence includes: performing a command sequence generation operation on each read command group in turn according to the compilation order of the multiple read command groups, wherein when the command sequence generation operation is performed on a current read command group among the multiple read command groups, the read trigger command, the polling command, and the data access command corresponding to each current second read command are generated according to the processing order of one or more current second read commands of the current read command group to obtain a first command sequence corresponding to the current read command group; and storing the generated first command sequence into the execution command sequence.

[0013] In one or more embodiments of the present invention, the method further includes: when executing the command sequence generation operation on the current read command group among the multiple read command groups, checking the next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group and the working status of the plane, wherein the working status includes an idle state and a busy state; and adjusting the processing order of the one or more next second read commands according to the working status of the plane pointed to by the one or more next second read commands.

[0014] In one or more embodiments of the present invention, the step of obtaining the plane pointed to by the one or more next second read commands in the next read command group and the working status of the plane includes: if the first plane pointed to by one of the one or more next second read commands is not pointed to by the one or more current second read commands in the current read command group, determining that the working status of the first plane is the idle state; and if the second plane pointed to by one of the one or more next second read commands is already pointed to by the one or more current second read commands in the current read command group, determining that the working status of the second plane is the busy state.

[0015] In one or more embodiments of the present invention, the step of adjusting the processing order of the one or more next second read commands includes: giving priority to processing the target next second read command of the second plane corresponding to the idle state among the one or more next second read commands.

[0016] In one or more embodiments of the present invention, the method further includes: when executing the command sequence generation operation on the current read command group among the multiple read command groups, checking the next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group and the working status of the plane, wherein the working status includes an idle state and a busy state; obtaining the target next second read command of the target plane corresponding to the idle state in the one or more next second read commands; generating a target read trigger command, a target polling command and a target data access command corresponding to the target next second read command; inserting the target read trigger command into the first command sequence; and inserting the target polling command and the target data access command after the first command sequence.

[0017] In one or more embodiments of the present invention, the method further includes: when executing the command sequence generation operation on the current read command group among the multiple read command groups, checking the next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group; and when the target plane pointed to by the target next second read command in the one or more next second read commands is different from the plane corresponding to all the current second read commands, generating a target read trigger command, a target polling command and a target data access command corresponding to the target next second read command; inserting the target read trigger command into the first command sequence; and inserting the target polling command and the target data access command after the first command sequence.

[0018] In one or more embodiments of the present invention, the step of generating the read trigger command, the polling command and the data access command corresponding to each current second read command according to the processing order of the one or more current second read commands of the current read command group includes: generating the first read trigger command corresponding to each current second read command one by one according to the processing order of the one or more current second read commands; generating a pair of first polling commands and first data access commands corresponding to each current second read command one by one according to the processing order of the one or more current second read commands; and storing the one or more first read trigger commands, one or more pairs of the first polling commands and the first data access commands of the one or more current second read commands as the first command sequence into the execution command sequence.

[0019] In one or more embodiments of the present invention, the step of storing the generated first command sequence into the execution command sequence includes: checking whether there is a previous read command group that is sorted before the current read command group. If the previous read command group exists, perform the following steps: obtain a second command sequence of the previous read command group, wherein the second command sequence includes one or more second read trigger commands, one or more pairs of second polling commands and second data access commands corresponding to one or more previous second read commands of the previous read command group; according to the processing order of the one or more current second read commands, sequentially insert the one or more first read trigger commands after the second data access commands corresponding to the same plane; and according to the processing order of the one or more current second read commands, sequentially store the one or more pairs of the first polling commands and the first data access commands.

[0020] In one or more embodiments of the present invention, executing the command sequence generation operation on the multiple read command groups includes: performing command conversion on each second read command of each read command group according to the compilation order of the multiple read command groups, wherein the command conversion includes generating a read trigger command, a polling command and a data access command according to the corresponding second read command. Among them, for the current read command group that is undergoing the command conversion: for each current second read instruction of the current read command group that has not yet undergone the command conversion, a read trigger command corresponding to the current second read command is generated; a corresponding polling command and a data access command are generated for each read trigger command; for each read trigger command, the plane corresponding to the read trigger command is obtained, and it is checked whether there is a target read command pointing to the same plane in the next read command group; if there is a target read command pointing to the same plane, a corresponding target read trigger command is generated based on the target read command of the next read command group, the target read trigger command is inserted after the data access command corresponding to the read trigger command, and a target polling command and a target data access command corresponding to the target read trigger command are generated; and if there is no target read command pointing to the same plane, the command conversion of all current second read commands of the current read command group is completed, and the next read command group is used as the new current read command group to perform the corresponding command conversion, wherein if it is checked that there is no next read command group, the generation of the execution command sequence is completed.

[0021] In one or more embodiments of the present invention, performing the command sequence generation operation on the multiple read command groups includes: performing command conversion on each second read command of each read command group according to the compilation order of the multiple read command groups, wherein the command conversion includes generating a read trigger command, a polling command and a data access command according to the corresponding second read command. Wherein, for the current read command group that is undergoing the command conversion: performing the command conversion on each current second read instruction of the current read command group that has not yet undergone the command conversion, including: if the read trigger command of the current second read instruction that is undergoing the command conversion has not yet been generated, generating a read trigger command corresponding to the current second read command, and generating a corresponding polling command and data access command for the read trigger command; if the read trigger command of the current second read instruction that is undergoing the command conversion has been generated, generating a corresponding polling command and data access command for the read trigger command; after generating the corresponding polling command and data access command, obtaining the plane corresponding to the read trigger command, and Check whether there is a target read command pointing to the same plane in the next read command group; if there is a target read command pointing to the same plane, generate a corresponding target read trigger command based on the target read command of the next read command group, insert the target read trigger command after the data access command corresponding to the read trigger command, and complete the command conversion of the current second read instruction; and if there is no target read command pointing to the same plane, complete the command conversion of the current second read command, set the next read command group as the new current read command group, and repeat the above steps to perform the command conversion on the new current read command.

[0022] One or more embodiments of the present invention provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module; a data management circuit for electrically connecting to a connection interface circuit of the storage device for receiving data and commands from a host system via the connection interface circuit; a buffer memory for caching data; and a processor for electrically connecting to the memory interface control circuit, the data management circuit, and the buffer memory. The processor is configured to: store the multiple read commands from the host system in one or more buffer pools of the buffer memory respectively, wherein the one or more buffer pools correspond to different chip enable pins respectively, and multiple read commands in the same buffer pool all point to the chip enable pins corresponding to the buffer pool to which they belong; when a preset condition is met, perform a pre-sorting operation on multiple first read commands in a first buffer pool of the one or more buffer pools to group the multiple first read commands into multiple read command groups, wherein one or more second read commands belonging to the same read command group correspond to different planes of the storage device of the rewritable non-volatile memory module respectively and the storage units corresponding to the one or more second read commands belong to the same storage unit type; generate an execution command sequence corresponding to the first buffer pool according to the multiple read command groups of the first buffer pool; and execute the multiple commands according to the generated execution command sequence to complete the parallel read operation corresponding to the multiple first read commands.

[0023] Based on the above, the data reading method and memory controller provided by the embodiments of the present invention can achieve the following beneficial effects: by pre-sorting and grouping the read commands, the parallel reading capability of the AIPR technology is fully utilized, thereby improving the reading speed of the SSD; by generating an optimized execution command sequence, the utilization rate of the data channel is improved; by considering the storage unit type of the storage unit, the performance loss caused by the difference in reading time of different types of storage units is avoided; by dynamically adjusting the command execution order, the utilization rate of the idle plane is improved, and the overall reading performance is further optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0025] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0026] Figure 2is a flow chart of a data reading method according to an embodiment of the present invention;

[0027] Figure 3 A schematic diagram of caching multiple read commands into multiple cache pools according to an embodiment of the present invention;

[0028] Figure 4 is a schematic diagram of a pre-sorting operation according to an embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of command conversion according to an embodiment of the present invention;

[0030] Figure 6 A schematic diagram of performing command conversion on a read command group to generate a first command sequence according to an embodiment of the present invention;

[0031] Figure 7 A schematic diagram of a command sequence of inserting an AIPR command of a read command group into a previous read command group according to an embodiment of the present invention;

[0032] Figure 8 A schematic diagram of a sequence of polling commands and data access commands stored in a read command group to an execution command according to an embodiment of the present invention;

[0033] Fig. 9 A command execution timing diagram of an execution command sequence according to an embodiment of the present invention;

[0034] Fig.10 A schematic diagram of generating corresponding execution command sequences according to a plurality of read command groups according to an embodiment of the present invention;

[0035] Fig.11 A schematic diagram of generating corresponding execution command sequences according to a plurality of read command groups according to another embodiment of the present invention;

[0036] Fig.12 A command execution timing diagram showing an execution command sequence according to another embodiment of the present invention.

[0037] Description of Figure Numbers

[0038] 10: Host system

[0039] 20: Storage device

[0040] 211: First processor

[0041] 110: Second processor

[0042] 120: Host memory

[0043] 130: Data transmission interface circuit

[0044] 210: Memory controller

[0045] 212: Data management circuit

[0046] 213: Memory interface control circuit

[0047] 214: Buffer memory

[0048] 220: Rewritable non-volatile memory module

[0049] 230: Connecting interface circuit

[0050] S210~S240: Process steps of data reading method

[0051] 214(1), 214(2) to 214(N): Cache pool

[0052] RC, RC1(1)~RC1(P), RC2(1)~RC2(Q), RCN(1)~RC(R): Read command

[0053] A41: Arrow (first step grouping)

[0054] A42: Arrow (second step grouping)

[0055] A43: Arrow (third step grouping)

[0056] 411: SLC command group

[0057] 412: TLC command group

[0058] 421: SLC_D0 command group

[0059] 422: SLC_D1 command group

[0060] 423: TLC_D0 command group

[0061] 424: TLC_D1 command group

[0062] RP1, RP2: Result Pool

[0063] A51: Arrow (pre-sort operation)

[0064] A52: Arrow (the first read command group command sequence generation operation)

[0065] A53: Arrow (second read command group command sequence generation operation)

[0066] A54, A55: Arrow (command sequence is stored in the execution command sequence)

[0067] CQ1~CQ5: Execute command sequence

[0068] A611~A614: Arrow (generated by AIPR command)

[0069] A61: Arrow (polling command and data access command pair generation)

[0070] A621~A624: Arrows (corresponding to the polling command and data access command generation of AIPR commands for each plane)

[0071] A62: Arrow (command sequence generation and storage)

[0072] A71: Arrow (AIPR command insertion)

[0073] A721~A724: Arrows (corresponding to AIPR command insertion of each plane)

[0074] A72: Arrow (get execution command sequence CQ2)

[0075] A81: Arrow (generates polling commands and data access commands corresponding to AIPR commands)

[0076] A821~A824: Arrows (each read command generates a corresponding polling command and data access command pair)

[0077] A83: Arrow (poll command and data access command storage)

[0078] P1: Block (indicates the storage location of polling commands and data access commands)

[0079] A84: Arrow (get the final execution command sequence CQ3)

[0080] A91: Arrow (execute command sequence CQ3)

[0081] A111~A114: Arrow (first read command group AIPR command generation)

[0082] A115~A118: Arrow (first read command group polling command and data access command generation)

[0083] A121~A124: Arrow (the second read command group AIPR command is inserted)

[0084] A125~A128: Arrow (second read command group polling command and data access command generation)

[0085] A1210: Arrow (Execute command sequence CQ5)

[0086] A1220: Arrow (read command "7" related commands are executed in advance)

[0087] tR1~tR8: Data preparation time DETAILED DESCRIPTION

[0088] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0089] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention. Figure 1 , the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In the present embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0090] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0091] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0092] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0093] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0094] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0095] In this embodiment, the host memory 120 is used to temporarily store commands or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0096] The memory controller 210 is used to execute a plurality of logic gates or control commands implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to commands of the host system 10 .

[0097] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control commands / program codes, and when the storage device 20 operates, these control commands / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control commands / program codes can be further executed to implement the data reading method provided by the present invention. The control commands / program codes corresponding to the data reading method can be further implemented as a circuit unit in the form of hardware to implement the data reading method provided by the present invention.

[0098] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present invention is not limited thereto.

[0099] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0100] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., the write operation is performed according to the write command from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more storage units in the one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., the read operation is performed according to the read command from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0101] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation on the rewritable non-volatile memory module 220 .

[0102] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these command sequences may include a write command sequence indicating writing data, a read command sequence indicating reading data, an erase command sequence indicating erasing data, and corresponding command sequences for indicating various memory operations. These command sequences may include one or more signals, or data on the bus. These signals or data may include command codes or program codes. For example, in a read command sequence, information such as a read identification code, a memory address, and a physical address may be included.

[0103] In the present invention, the execution command sequence (also known as the AIPR command sequence) is a specially optimized read command sequence generated by the processor and transmitted to the memory interface control circuit. This command sequence makes full use of the characteristics of the asynchronous independent plane read (AIPR) technology and can perform read operations on different pages of multiple planes at the same time. Specifically, the execution command sequence includes multiple AIPR commands (also known as read trigger commands), polling commands, and direct memory access (DMA) commands. Each AIPR command contains a specific command code, a target plane identifier, a physical page address, and other information. The polling command is used to check the completion status of the read operation, while the DMA command (also known as the data access command) is used to transfer the read data to the specified memory location. These commands are carefully sorted and organized to maximize the parallel read efficiency. For example, the AIPR command sequence may first send multiple AIPR commands for different planes, and then send polling commands and DMA commands alternately to achieve overlapping execution of read operations and data transfers. After receiving the optimized AIPR command sequence, the memory interface control circuit converts it into a specific signal and timing acceptable to the rewritable non-volatile memory module, thereby achieving efficient parallel reading operations. The following will illustrate the generation method of the AIPR command sequence provided by the data reading method of the present invention through multiple embodiments and corresponding drawings.

[0104] In the present invention, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page or logical column) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page, physical column). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called the logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called the physical to logical mapping table).

[0105] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and commands from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, address lists, multiple buffer pools for caching multiple read commands, result pools for storing pre-sorted results, one or more AIPR command sequences, and other information associated with the present method), so that the processor 211 can quickly access the data, commands, or system data from the buffer memory 214.

[0106] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store data written by the host system 10 .

[0107] In the present embodiment, the rewritable non-volatile memory module 220 has a plurality of word lines, wherein each of the plurality of word lines is electrically connected to a plurality of storage cells, also known as columns (also known as physical columns). A plurality of columns on the same word line constitute a physical programming unit (also known as a physical page). Each physical page corresponds to a physical address for recording the location of the data stored in the physical page. In addition, a plurality of physical pages may constitute a physical block (also known as a physical erase unit). Each memory grain (chip) of the plurality of memory grains of the rewritable non-volatile memory module has a plurality of planes, and each plane has a plurality of physical blocks. It should be noted that the present invention is not limited to the size of each physical page and logical page.

[0108] Channel (CH) pins (also called physical channels) are a group of physical pins in the rewritable non-volatile memory module 220, which are responsible for receiving and transmitting data and commands.

[0109] The chip enable (CE) pin is used to select or deselect the memory chip. Each CE pin corresponds to a physical chip (memory chip). If a chip enable pin is in a valid state, the corresponding physical chip is selected.

[0110] In the architecture of flash memory, Die (chip) is the most basic physical unit, usually corresponding to an independent storage area on a chip. Each chip can contain one or more LUNs (Logical Unit Numbers), which are the smallest units that can execute commands independently. Each LUN is divided into multiple planes, which are the basic units of parallel operations and can perform read and write operations simultaneously to improve performance.

[0111] The storage cell type can be used to indicate the number of bits that can be stored in each storage cell. Common types include SLC (single-level cell, each cell stores 1 bit), MLC (multi-level cell, each cell stores 2 bits), TLC (triple-level cell, each cell stores 3 bits), etc. Different storage cell types vary in storage density, read / write speed, and durability, which affects the overall performance and characteristics of flash memory.

[0112] In the hierarchical structure of flash memory, the chip enable pin (CE) is used to select and activate a specific memory chip. Each CE can control one or more Dies (chips). Each chip is an independent physical storage unit and can contain one or more LUNs (logical unit numbers). LUN is the smallest unit that can execute commands independently, and each LUN is divided into multiple planes (Plane) for parallel operation. The plane is composed of multiple blocks (Block), and each block contains multiple pages (Page). The page is the basic unit of read and write operations and consists of multiple memory cells (Memory Cell). The type of memory cell (such as SLC, MLC, TLC) determines the number of bits that can be stored in each cell. This hierarchical structure allows flash memory to implement parallel operations at different levels, thereby improving overall performance. For example, AIPR technology allows independent read operations to be performed simultaneously on different planes of the same LUN, making full use of this structural feature.

[0113] Figure 2 FIG. 4 is a flow chart of a data reading method according to an embodiment of the present invention.

[0114] Please refer to Figure 2 The present invention provides a data reading method based on asynchronous independent plane reading (AIPR), the method comprising the following main steps:

[0115] Step S210: storing the multiple read commands from the host system into one or more buffer pools respectively, wherein the one or more buffer pools correspond to different chip enable pins respectively, and all read commands of each buffer pool point to the chip enable pin corresponding to the buffer pool.

[0116] In this embodiment, the memory controller 210 receives multiple read commands from the host system 10, and distributes these commands to different buffer pools according to the chip enable pin corresponding to each read command. These buffer pools can be part of the buffer memory 214. When the number of commands in a buffer pool reaches a predetermined threshold or the waiting time of the earliest stored command reaches a predetermined time threshold, the processor 211 of the memory controller 210 performs a pre-sorting operation on the commands in the buffer pool.

[0117] Figure 3 FIG. 1 is a schematic diagram of caching multiple read commands into multiple buffer pools according to an embodiment of the present invention. In one embodiment, the present invention provides a method for caching multiple read commands into multiple buffer pools. Figure 3 As shown, the method involves interaction between the host system 10 and the buffer memory 214 of the memory controller 210 of the storage device 20 .

[0118] The host system 10 sends a plurality of read commands (RC) to the storage device 20. The buffer memory 214 includes a plurality of buffer pools, each of which corresponds to a specific chip enable pin (CE). Specifically, the buffer pool 214 (1) corresponds to the chip enable pin CE1, the buffer pool 214 (2) corresponds to the chip enable pin CE2, and so on, until the buffer pool 214 (N) corresponds to the chip enable pin CEN. This one-to-one mapping relationship ensures that the read commands stored in each buffer pool point to the same chip enable pin.

[0119] When the memory controller 210 receives read commands, it stores the commands in the corresponding buffer pools according to the chip enable pins corresponding to each read command. For example, the read commands RC1(1), RC1(2), ..., RC1(P) associated with CE1 are stored in the buffer pool 214(1). Similarly, the read commands RC2(1), RC2(2), ..., RC2(Q) associated with CE2 are stored in the buffer pool 214(2), and so on.

[0120] This storage method has several important advantages:

[0121] (1) Command isolation: Commands for different chip enable pins are stored separately to avoid confusion and conflict.

[0122] (2) Parallel processing preparation: This lays the foundation for subsequent AIPR operations, as commands in each cache pool can be pre-sorted and optimized independently.

[0123] (3) Resource allocation: Allows the memory controller 210 to manage and allocate resources more efficiently because it can process the command queue for each chip enable pin individually.

[0124] (4) Flexibility: This structure supports the dynamic addition or removal of chip enable pins by simply increasing or decreasing the cache pool accordingly.

[0125] In one embodiment, the data reading method of the present invention further includes the step of processing and analyzing the read command in detail to prepare for the subsequent pre-sorting operation and generation of the AIPR command sequence. Specifically, the method includes the following steps:

[0126] First, when storing multiple read commands in one or more buffer pools, the memory controller 210 sets a unique sequence number for each read command in each buffer pool. For example, for the read commands in the buffer pool 214 (1), the sequence numbers (e.g., "1", "2", ..., "P") may be assigned in the order of RC1 (1), RC1 (2), ..., RC1 (P). This sequence number assignment mechanism helps to track the order in which the commands are received and maintain the timing relationship of the commands in subsequent processing.

[0127] Secondly, the processor 211 obtains the physical address of each read command according to the recorded mapping information (e.g., logical to physical mapping table). This step involves the process of converting the logical address to the physical address, which is usually completed by the flash translation layer (FTL). The mapping information is usually stored in the buffer memory 214 or in the dedicated cache of the processor 211.

[0128] Finally, based on the acquired physical address, the processor 211 further acquires the physical characteristics of the physical address. These physical characteristics include:

[0129] Chip enable pin (CE): indicates the CE corresponding to this physical address.

[0130] Plane: Identifies the specific plane location of this physical address within the chip.

[0131] Die: Indicates the chip where this physical address is located.

[0132] Storage unit type: indicates the type of storage unit corresponding to this physical address, such as SLC, MLC or TLC.

[0133] The chip enable pin and chip information help determine which specific physical device the command should be sent to. Plane information is extremely important for parallel execution of AIPR operations because it allows the system (memory controller 210) to access different planes on the same chip simultaneously. Memory cell type information helps optimize read timing because different types of memory cells require different read times.

[0134] The above preprocessing steps provide an information basis for subsequent pre-sorting operations. For example, when performing pre-sorting, commands pointing to different planes can be grouped according to plane information, while considering the storage unit type to ensure that the read time of commands in the same group is similar. This not only improves the parallelism of AIPR operations, but also optimizes the overall reading efficiency.

[0135] In addition, this information also provides the necessary parameters for the generation of AIPR command sequences. When generating AIPR commands, the system can accurately specify the read command, target chip, plane, and read timing.

[0136] Please go back Figure 2 In step S220, when a preset condition is met, the processor 211 performs a pre-sorting operation on a plurality of first read commands in a first cache pool in the one or more cache pools to group the plurality of first read commands into a plurality of read command groups, wherein one or more second read commands belonging to the same read command group correspond to different planes of the same chip in the storage device respectively and the storage units corresponding to the one or more second read commands respectively belong to the same storage unit type.

[0137] The purpose of the pre-sort operation is to group the read commands so that the commands in the same group correspond to different planes, and the storage cells corresponding to these commands belong to the same storage cell type (such as SLC, MLC or TLC). This grouping strategy can fully utilize the parallel reading capability of AIPR technology while taking into account the reading characteristics of different storage cell types.

[0138] In one embodiment, the step of performing the pre-sorting operation includes: grouping the multiple first read commands according to the storage cell types to which the multiple first read commands correspond respectively to obtain one or more storage cell type command groups, wherein one or more first read commands belonging to the same storage cell type command group correspond to the same storage cell type; grouping the one or more first read commands in the same storage cell type command group according to the chips to which the one or more first read commands in the same storage cell type command group correspond respectively to obtain one or more chip command groups, wherein one or more first read commands belonging to the same chip command group correspond to the same chip; and compiling one or more second read commands pointing to different planes in each chip command group into the same read command group to obtain the multiple read command groups, wherein the processing order of the one or more second read commands in each read command group is set based on the order of the corresponding planes. This multi-level grouping strategy ensures that commands in the same group have similar execution characteristics, which is beneficial to subsequent AIPR operations.

[0139] The following use Figure 4 The pre-sort operation shown is taken as an example to explain this process in detail. Figure 4 It is a schematic diagram of a pre-sorting operation according to an embodiment of the present invention.

[0140] exist Figure 4In the example, assuming that the preset condition is met, the cache pool 214 (1) includes 8 read commands RC1 (1) to RC1 (8), each of which has a serial number and a corresponding physical characteristic. The physical characteristic includes the chip number (D0 or D1), the plane number (P0 or P1), and the storage unit type (SLC or TLC). For example, the physical characteristic "D0_P1_SLC" of the read command RC1 (1) indicates that the physical address corresponding to the read command RC1 (1) points to the chip D0 and the plane P1 in the chip D0, and the type of the storage unit of the physical address is SLC.

[0141] The first step of the pre-sort operation (indicated by arrow A41) is to group the memory cells according to their type. In one embodiment, the present invention further optimizes the pre-sort operation, taking into account the different times (tR) required to perform read operations for different flash memory types. This maximizes the utilization of each plane and avoids affecting the overall command execution efficiency due to a long read time for a certain plane. The specific implementation is as follows:

[0142] (1) Flash memory type identification:

[0143] When grouping and sorting the read commands, the system first determines which flash memory type (eg, SLC, MLC, TLC, etc.) the physical address pointed to by each read command belongs to.

[0144] (2) Grouping of the same type:

[0145] Only read commands belonging to the same flash type are organized into the same command group. For example,

[0146] The SLC command group 411 includes read commands RC1(1), RC1(2), RC1(3), RC1(7) and RC1(8), and the physical addresses of these read commands all correspond to the SLC storage unit types.

[0147] The TLC command group 412 includes read commands RC1(4), RC1(5) and RC1(6), and the physical addresses of these read commands all correspond to the SLC storage cell type.

[0148] The second step (indicated by arrow A42) is to group the chips within each memory cell type group:

[0149] The SLC command group 411 may be grouped into a SLC_D0 command group 421 and a SLC_D1 command group 422. For example:

[0150] The SLC_D0 command group 421 includes read commands RC1(1) and RC1(8). The physical addresses of these read commands all correspond to chip D0.

[0151] The SLC_D1 command group 422 includes read commands RC1(2), RC1(3) and RC1(7). The physical addresses of these read commands all correspond to the chip D1.

[0152] The TLC command group 412 may be grouped into a TLC_D0 command group 423 and a TLC_D1 command group 424. For example:

[0153] The TLC_D0 command group 423 includes read commands RC1(4) and RC1(5). The physical addresses of these read commands all correspond to chip D0.

[0154] The TLC_D1 command group 424 includes a read command RC1 (6). The physical addresses of the read commands all correspond to the chip D1.

[0155] The third step (indicated by arrow A43) is to compile the commands directed to different planes into the same read command group within each chip command group:

[0156] In the SLC_D0 command group 421, the read commands RC1(1) and RC1(8) point to planes P1 and P0 respectively, so they can be compiled into one read command group. It is worth mentioning that, according to the order of planes P0 and P1, the processing order of the read command RC1(8) (used to process the generation of the corresponding AIPR sequence) can be set to take precedence over the read command RC1(1).

[0157] In the SLC_D1 command group 422, the read commands RC1(2) and RC1(3) point to planes P0 and P1 respectively and can be compiled into one read command group; the remaining read commands RC1(7) are grouped separately.

[0158] In the TLC_D0 command group 423, the read commands RC1(4) and RC1(5) are directed to planes P1 and P0 respectively, and can be compiled into one read command group. It is worth mentioning that, according to the order of planes P0 and P1, the processing order of the read command RC1(5) can be set to take precedence over the read command RC1(4).

[0159] In the TLC_D1 command group 424, the remaining read commands RC1 (6) are grouped separately.

[0160] Finally, these read command groups form a result pool RP1 (for example, a cache area of ​​the cache memory 214 can be allocated as the result pool RP1), which includes command groups that are optimized and sorted according to the storage unit type, chip, and plane. For example, {"8", "1"} represents a read command group, including two read commands with serial numbers 8 and 1, which correspond to different planes but belong to the same chip and storage unit type.

[0161] It should be noted that {"8", "1"} also indicates that the processing order of the read command "8" may take precedence over the read command "1".

[0162] Furthermore, in another embodiment, the first step grouping and the second step grouping may be swapped.

[0163] Please go back Figure 2 In step S230, the processor 211 generates an AIPR command sequence corresponding to the first cache pool according to the multiple read command groups of the first cache pool.

[0164] Specifically, in one embodiment, the step of generating the AIPR command sequence includes: performing a command sequence generation operation on each read command group in turn according to the compilation order of the multiple read command groups, wherein when performing the command sequence generation operation on the current read command group in the multiple read command groups, generating the AIPR command, the polling command and the DMA command corresponding to each current second read command according to the processing order of one or more current second read commands of the current read command group to obtain a first command sequence corresponding to the current read command group; and storing the generated first command sequence in the AIPR command sequence. The generation of the command sequence of each read command group can also be referred to as the command conversion of the read command group.

[0165] Figure 5 FIG. 1 is a schematic diagram of command conversion according to an embodiment of the present invention. Figure 5 To explain the command conversion process in detail, please refer to Figure 5 , the cache pool 214(1) includes 8 read commands RC1(1) to RC1(8), each command having a serial number and corresponding physical characteristics. The physical characteristics include the chip number (for the sake of convenience, all are D0 in this example), the plane number (P0, P1, P2 or P3) and the storage unit type (for the sake of convenience, all are SLC in this example).

[0166] As shown by arrow A51, after the pre-sorting operation, these 8 read commands will be divided into two read command groups to form a result pool RP2: the first group: {"1", "2", "3", "4"}, including read commands (these grouped read commands are also called second read commands) "1" to "4"; the second group: {"5", "6", "7", "8"}, including read commands "5" to "8".

[0167] Next, the processor 211 performs command sequence generation operations on the two read command groups respectively.

[0168] As shown by arrow A52, a command sequence is generated for the first read command group (also referred to as the current read command group), including:

[0169] An AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command are generated for the read command (also referred to as the current second read command) RC1 (1), corresponding to plane P0.

[0170] An AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command are generated for the read command RC1 (2), corresponding to plane P1.

[0171] An AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command are generated for the read command RC1 (3), corresponding to plane P2.

[0172] An AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command are generated for the read command RC1 (4), corresponding to plane P3.

[0173] As shown by arrow A53, a command sequence is generated for the second read command group (i.e., the next current read command group), including:

[0174] An AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command are generated for the read command RC1 (5), corresponding to plane P0.

[0175] An AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command are generated for the read command RC1 (6), corresponding to plane P1.

[0176] An AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command are generated for the read command RC1 (7), corresponding to plane P2.

[0177] An AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command are generated for the read command RC1 (8), corresponding to plane P3.

[0178] Next, as indicated by arrows A54 and A55 , the generated command sequence (the AIPR command, the polling command and the DMA command corresponding to each read command group) is stored in the AIPR command sequence CQ1 .

[0179] In one embodiment, the steps of generating an AIPR command sequence are as follows:

[0180] First, according to the processing order of the current second read command (ie, the read command of the current read command group), corresponding first AIPR commands are generated one by one. These AIPR commands are used to start the read operation of a specific plane.

[0181] Then, according to the processing order of the current second read command, a corresponding pair of first polling command and first DMA command is generated for each AIPR command. The polling command is used to check the completion status of the read operation, while the DMA command is used to transfer the read data to the specified memory location.

[0182] Finally, all generated first AIPR commands, first polling commands and first DMA commands are combined in a specific order to form a first command sequence, and the first command sequence is stored in the AIPR command sequence.

[0183] The following is more Figure 6 Taking the command conversion process shown in the figure as an example, the process of converting the read command group to generate and store the first command sequence is described in detail.

[0184] Figure 6 For a schematic diagram of converting a read command group to generate a first command sequence according to an embodiment of the present invention, please refer to Figure 6 , Figure 6 A read command group containing 4 read commands ("1", "2", "3", "4") is shown. These commands correspond to 4 different planes (P0, P1, P2, P3), where the processing order from first to last is "1", "2", "3", "4". The command conversion process is as follows:

[0185] (1) AIPR command generation (as shown by arrows A611-A614): Generate an AIPR command corresponding to plane P0 for read command "1"; generate an AIPR command corresponding to plane P1 for read command "2"; generate an AIPR command corresponding to plane P2 for read command "3"; and generate an AIPR command corresponding to plane P3 for read command "4".

[0186] (2) Generate polling command and DMA command pair: After obtaining the AIPR command corresponding to each read command of this read command group, you can start generating the polling command and DMA command pair corresponding to each AIPR command (as shown by arrow A61).

[0187] For example, as shown by arrow A621: based on the read command "1", a polling command and a DMA command of the AIPR command corresponding to plane P0 are generated; as shown by arrow A622: based on the read command "2", a polling command and a DMA command of the AIPR command of plane P1 are generated; as shown by arrow A623: based on the read command "3", a polling command and a DMA command of the AIPR command of plane P2 are generated; as shown by arrow A624: based on the read command "4", a polling command and a DMA command of the AIPR command of plane P3 are generated.

[0188] (3) Command sequence generation and storage (as shown by arrow A62):

[0189] All previously generated commands are combined in an optimized order (in this example, a plane order) to form a first command sequence, and stored in the AIPR command sequence CQ1.

[0190] The processor 211 may execute the commands in sequence based on the order of the commands in the AIPR command sequence CQ1:

[0191] First, all AIPR commands are issued in sequence (corresponding to read commands "1", "2", "3", and "4", respectively) to start parallel read operations on the four planes.

[0192] Then, the polling commands and DMA commands of each plane are executed alternately, for example, the polling commands and DMA commands of plane P0; the polling commands and DMA commands of plane P1; the polling commands and DMA commands of plane P2; and the polling commands and DMA commands of plane P3.

[0193] In one embodiment, the present invention provides an optimization method for storing a newly generated first command sequence into an AIPR command sequence. This method takes into account the relationship between the current read command group and the previously possible read command group to achieve more efficient command execution. The specific steps are as follows:

[0194] First, the processor 211 checks whether there is a previous read command group that is sequenced before the current read command group. This step ensures the continuity and correctness of the command sequence.

[0195] If there is a previous read command group, the processor 211 performs the following operations:

[0196] (1) Obtain the second command sequence of the last read command group, which includes the second AIPR command, the second polling command and the second DMA command corresponding to the last read command group.

[0197] (2) According to the processing order of each current second read command of the current read command group, the processor 211 inserts the newly generated first AIPR command into the previous command sequence. Specifically, each first AIPR command will be inserted after the second DMA command corresponding to the same plane. This insertion method ensures that a new AIPR read operation (also known as a parallel read operation) of the same plane can be started immediately after the previous AIPR read operation completes data transmission.

[0198] (3) Finally, the processor 211 will sequentially store the newly generated first polling command and first DMA command pair into the AIPR command sequence according to the processing order of the current second read command.

[0199] This method not only ensures the continuity of command execution, but also maximizes the parallel operation capability of the flash memory chip by optimizing the command insertion position.

[0200] The following use Figure 7 Let’s explain this process in detail. Figure 7 FIG. 1 is a schematic diagram of a command sequence of inserting an AIPR command of a read command group into a previous read command group according to an embodiment of the present invention. Figure 7 , Figure 7 It shows how to insert a newly generated command sequence when a command sequence (CQ1) of the previous read command group already exists in the AIPR command sequence.

[0201] (1) Initial state:

[0202] The AIPR command sequence CQ1 already includes the command sequence of the previous read command group, including AIPR commands corresponding to read commands "1", "2", "3", and "4" (also called the second AIPR commands) and corresponding 4 pairs of polling commands (also called the second polling commands) and DMA commands (also called the second DMA commands).

[0203] (2) Generate AIPR command for new command sequence:

[0204] As shown by arrows A711 to A714, new AIPR commands (also called first AIPR commands) corresponding to read commands "5", "6", "7", and "8" respectively are generated for the current read command group {"5", "6", "7", and "8"}.

[0205] (3) AIPR command insertion (as shown by arrow A71):

[0206] As shown by arrow A721: the AIPR command corresponding to the read command "5" is inserted after the DMA command corresponding to the read command "1" of the same plane (P0).

[0207] As shown by arrow A72: the AIPR command corresponding to the read command "6" is inserted after the DMA command corresponding to the read command "2" of the same plane (P1).

[0208] As shown by arrow A73: the AIPR command corresponding to the read command "7" is inserted after the DMA command corresponding to the read command "3" of the same plane (P2).

[0209] As shown by arrow A74: the AIPR command corresponding to the read command "8" is inserted after the DMA command corresponding to the read command "4" of the same plane (P3).

[0210] Next, as shown by arrow A72, as in the above steps, after determining whether the planes are the same, and inserting the AIPR commands of the read commands "5", "6", "7", and "8" of the current read command group {"5", "6", "7", and "8"} into the AIPR command sequence CQ1, the AIPR command sequence CQ2 is obtained.

[0211] After inserting the AIPR commands of the read commands "5", "6", "7", and "8" of the current read command group {"5", "6", "7", and "8"} into the AIPR command sequence CQ1, it is also necessary to generate and store a pair of polling commands (also called the first polling command) and DMA commands (also called the first DMA command) corresponding to the AIPR commands of the read commands "5", "6", "7", and "8" respectively, so as to complete the operation of generating and storing the command sequence corresponding to the current read command group {"5", "6", "7", and "8"}.

[0212] Next, continue Figure 7 Example, combined with Figure 8 Let’s explain this process in detail. Figure 8 Schematic diagram of the polling command stored in the read command group and the DMA command to AIPR command sequence according to an embodiment of the present invention. Figure 8 , Figure 8 It shows how to generate and store the corresponding polling command and DMA command after inserting the AIPR command of the current read command group {"5", "6", "7", "8"} into the AIPR command sequence CQ1.

[0213] Assume that the AIPR commands corresponding to the read commands "5", "6", "7", and "8" respectively have been inserted after the DMA commands of the corresponding planes, forming an intermediate AIPR command sequence CQ2.

[0214] (1) Generate a polling command and a DMA command corresponding to the AIPR command (as shown by arrow A81):

[0215] As shown by arrow A821: a corresponding polling command and DMA command pair are generated for the read command "5"; as shown by arrow A822: a corresponding polling command and DMA command pair are generated for the read command "6"; as shown by arrow A823: a corresponding polling command and DMA command pair are generated for the read command "7"; as shown by arrow A824: a corresponding polling command and DMA command pair are generated for the read command "8".

[0216] (2) Polling command and DMA command storage (as shown by arrow A83):

[0217] The polling command and DMA command pairs generated in steps A821-A824 are stored in sequence at the end of the AIPR command sequence CQ2 (as shown in block P1) in the processing order of "5", "6", "7", and "8".

[0218] (3) The final AIPR command sequence is formed (as shown by arrow step A84):

[0219] After storing these pairs of polling commands and DMA commands, the final AIPR command sequence CQ3 is obtained.

[0220] The above embodiment has explained that, in the case where the AIPR command sequence has the command sequence of the previous read command group, the command sequence corresponding to the current read command group is generated and stored in the AIPR command sequence. In the AIPR command sequence CQ3: AIPR commands "5", "6", "7", and "8" are inserted after the previous DMA command of the corresponding plane, and the newly generated polling command and DMA command pair are arranged in order at the end of the sequence (P1).

[0221] Please go back Figure 2 In step S240, the processor 211 executes the multiple commands according to the generated AIPR command sequence to complete the AIPR read operations corresponding to the multiple first read commands.

[0222] Based on the pre-ordered command group, the processor 211 generates an AIPR command sequence, which includes AIPR commands, polling commands, and direct memory access (DMA) commands, which are generated and stored in the AIPR command sequence according to the present method to achieve optimal parallel read performance.

[0223] Finally, the memory interface control circuit 213 executes the corresponding command according to the generated AIPR command sequence to complete the AIPR read operation on the rewritable non-volatile memory module 220. This method significantly improves the efficiency of data reading, especially in the scenario of a large number of random read requests.

[0224] Fig. 9 FIG. 1 is a command execution timing diagram of an AIPR command sequence according to an embodiment of the present invention. Fig. 9 In one embodiment, the AIPR command sequence CQ3 is actually executed as follows:

[0225] (1) AIPR command execution:

[0226] First, the system (processor 211) simultaneously sends AIPR commands corresponding to read commands "1", "2", "3", and "4" to the four planes (P0, P1, P2, and P3) to start a parallel read operation.

[0227] (2) Data preparation time:

[0228] Each AIPR command is followed by a corresponding data preparation time (tR1, tR2, tR3, tR4), during which each plane performs data read operations independently.

[0229] (3) Interleaving polling and DMA commands:

[0230] When the data preparation time tR1 of the read command "1" corresponding to plane P0 ends, the system executes the polling command and DMA command of the read command "1".

[0231] After plane P0 executes the DMA command, the system sends an AIPR command of a read command "5" to plane P0, and starts the next round of reading of plane P0 (entering the data preparation time tR6 of the AIPR command of the read command "5").

[0232] During the data preparation time tR5 of the AIPR command of the read command "5", the operation of the next plane P1 can be executed. More specifically, because the data preparation time tR2 of the read command "2" of the next plane P1 has ended, the polling command and DMA command of the read command "2" can be executed.

[0233] After plane P1 executes the DMA command, the system sends an AIPR command of the read command "6" to plane P1, and starts the next round of reading of plane P1 (entering the data preparation time tR6 of the AIPR command of the read command "6").

[0234] During the data preparation time tR6 of the AIPR command of the read command "6", the system continues to execute the operation of the next plane P2. More specifically, because the data preparation time tR3 of the read command "3" of the plane P2 has ended, the system executes the polling command and DMA command of the read command "3".

[0235] After plane P2 executes the DMA command, the system sends an AIPR command of the read command "7" to plane P2, and starts the next round of reading of plane P2 (entering the data preparation time tR7 of the AIPR command of the read command "7").

[0236] During the data preparation time tR7 of the AIPR command of the read command "7", the system turns to the operation of processing the last plane P3. Since the data preparation time tR4 of the read command "4" of the plane P3 has ended, the system executes the polling command and DMA command of the read command "4".

[0237] After plane P3 executes the DMA command, the system sends an AIPR command of the read command "8" to plane P3, and starts the next round of reading of plane P3 (entering the data preparation time tR8 of the AIPR command of the read command "8").

[0238] At this point, the system has completed the first round of read operations on all four planes and has started the second round of read operations. Next, the system will return to plane P0 to check whether the data of read command "5" is ready. If the data preparation time tR5 has ended, the polling command and DMA command of read command "5" will be executed. Similarly, after the corresponding data preparation time tR6-tR8 has ended, the polling command and DMA command of the corresponding read commands "6" to "8" will be executed.

[0239] This cyclic process continues until all read commands are executed. Through this highly optimized interleaved execution method, the maximum read operation utilization of each plane of the flash memory is achieved, significantly improving the parallelism and efficiency of data reading.

[0240] In one embodiment, the present invention provides another method for generating an AIPR command sequence. This method performs command conversion on each second read command in each group according to the compilation order of the read command groups. The command conversion process not only considers the current read command group, but also considers the next read command group. The specific steps are as follows:

[0241] (1) Generate an AIPR command for each second read command in the current read command group that has not yet been converted (also referred to as the current second read command).

[0242] (2) Generate corresponding polling commands and DMA commands for each AIPR command.

[0243] (3) For each AIPR command, check its corresponding plane and see if there is a target read command pointing to the same plane in the next read command group.

[0244] (4) If there is a target read command pointing to the same plane, a corresponding target AIPR command is generated and inserted after the DMA command corresponding to the current AIPR command (AIPR command of the same plane), and a target polling command and a target DMA command are generated.

[0245] (5) If there is no target read command pointing to the same plane, all command conversions of the current read command group are completed, and the next read command group is set as the new current read command group.

[0246] It should be noted that if there is no next read command group, the generation of the entire AIPR command sequence corresponding to this buffer pool is completed.

[0247] The following use Fig.10 Let’s explain this process in detail. Fig.10 It is a schematic diagram of generating corresponding AIPR command sequences according to multiple read command groups according to an embodiment of the present invention.

[0248] Please refer to Fig.10 , Fig.10 It shows how two read command groups ({"1", "2", "3", "4"} and {"5", "6", "7", "8"}) generate corresponding AIPR command sequences CQ4.

[0249] (1) Process the first read command group:

[0250] As shown by arrows A111 to A114, AIPR commands are generated for read commands "1", "2", "3", and "4" and stored in the AIPR command sequence. Since there is no command sequence of any read command group in the AIPR command sequence, the generated AIPR commands can be directly stored (without considering the previous read command group).

[0251] As shown by arrows A115 to A118, corresponding polling commands and DMA commands are generated for these AIPR commands.

[0252] (2) Process the second read command group and interleave it with the first read command group:

[0253] As shown by arrow A121, it is checked that the read command "5" corresponds to plane P0, which is the same as the read command "1", so an AIPR command corresponding to the read command "5" is generated and inserted after the DMA command of the read command "1".

[0254] Similarly, as shown by arrows A122 to A124, the AIPR commands of the read commands "6", "7", and "8" are respectively inserted after the DMA commands of the read commands "2", "3", and "4" corresponding to the same plane.

[0255] The polling commands and DMA commands corresponding to the read commands "1", "2", "3", and "4" and the AIPR commands corresponding to the read commands "5", "6", "7", and "8" generated above are all stored in the AIPR command sequence CQ4.

[0256] As shown by arrows A125 to A128, corresponding polling commands and DMA commands are finally generated for the read commands "5", "6", "7", and "8", and are inserted into the end of the sequence in sequence.

[0257] In another embodiment, executing the command sequence generation operation on the multiple read command groups includes: performing command conversion on each second read command of each read command group according to the compilation order of the multiple read command groups, wherein the command conversion includes generating an AIPR command, a polling command and a DMA command according to the corresponding second read command.

[0258] Wherein, for the current read command group for performing the command conversion:

[0259] Performing the command conversion on each current second read instruction of the current read command group that has not yet undergone the command conversion comprises the following steps:

[0260] If the AIPR command of the current second read instruction for the command conversion has not been generated, generate an AIPR command corresponding to the current second read command, and generate a corresponding polling command and a DMA command for the AIPR command;

[0261] If the AIPR command of the current second read instruction for the command conversion has been generated, generating a corresponding polling command and a DMA command for the AIPR command;

[0262] After generating the corresponding polling command and DMA command, obtain the plane corresponding to the AIPR command, and check whether there is a target read command pointing to the same plane in the next read command group;

[0263] Wherein, if the target read command pointing to the same plane exists, a corresponding target AIPR command is generated based on the target read command of the next read command group, the target AIPR command is inserted after the DMA command corresponding to the AIPR command, and the command conversion of the current second read instruction is completed; and

[0264] If the target read command pointing to the same plane does not exist, the command conversion of the current second read command is completed, and the above steps are repeated to perform the command conversion on the next current read command.

[0265] The following use Fig.10 To illustrate this concept. Fig.10 As shown in the arrows A111 to A128, we can describe the order in which each command is generated and stored as follows:

[0266] As shown by arrow A111, an AIPR command corresponding to the read command "1" is generated and stored in the AIPR command sequence CQ4;

[0267] As shown by arrow A112, an AIPR command corresponding to the read command "2" is generated and stored in the AIPR command sequence CQ4;

[0268] As shown by arrow A113, an AIPR command corresponding to the read command "3" is generated and stored in the AIPR command sequence CQ4;

[0269] As shown by arrow A114, an AIPR command corresponding to the read command "4" is generated and stored in the AIPR command sequence CQ4;

[0270] As shown by arrow A115, a polling command and a DMA command corresponding to the read command "1" are generated and stored in the AIPR command sequence CQ4, completing the command conversion of the read command "1";

[0271] As shown by arrow A121, after completing the command conversion of the read command "1", it is detected that the read command "5" of the next read command group points to the same plane P0, and an AIPR command corresponding to the read command "5" is generated and inserted after the DMA command corresponding to the read command "1";

[0272] As shown by arrow A116, a polling command and a DMA command corresponding to the read command "2" are generated and stored in the AIPR command sequence CQ4, completing the command conversion of the read command "2";

[0273] As shown by arrow A122, after completing the command conversion of the read command "2", it is detected that the read command "6" of the next read command group points to the same plane P1, and an AIPR command corresponding to the read command "6" is generated and inserted after the DMA command corresponding to the read command "2";

[0274] As shown by arrow A117, a polling command and a DMA command corresponding to the read command "3" are generated and stored in the AIPR command sequence CQ4, completing the command conversion of the read command "3";

[0275] As shown by arrow A123, after completing the command conversion of the read command "3", it is detected that the read command "7" of the next read command group points to the same plane P2, and an AIPR command corresponding to the read command "7" is generated and inserted after the DMA command corresponding to the read command "3";

[0276] As shown by arrow A118, a polling command and a DMA command corresponding to the read command "4" are generated and stored in the AIPR command sequence CQ4, completing the command conversion of the read command "4";

[0277] As shown by arrow A124, after completing the command conversion of the read command "4", it is detected that the read command "8" of the next read command group points to the same plane P3, and an AIPR command corresponding to the read command "8" is generated and inserted after the DMA command corresponding to the read command "4";

[0278] As shown by arrow A125, a polling command and a DMA command corresponding to the read command "5" are generated and stored at the end of the AIPR command sequence CQ4, and the command conversion of the read command "5" is completed. After the command conversion of the read command "5" is completed, it is checked that there is no read command of the next read command group pointing to the same plane P0, and it is determined that the next read command "6" can be processed;

[0279] As shown by arrow A126, a polling command and a DMA command corresponding to the read command "6" are generated and stored at the end of the AIPR command sequence CQ4, and the command conversion of the read command "6" is completed. After the command conversion of the read command "6" is completed, it is checked that there is no read command of the next read command group pointing to the same plane P1, and it is determined that the next read command "7" can be processed;

[0280] As shown by arrow A127, a polling command and a DMA command corresponding to the read command "7" are generated and stored at the end of the AIPR command sequence CQ4, and the command conversion of the read command "7" is completed. After the command conversion of the read command "7" is completed, it is checked that there is no read command of the next read command group pointing to the same plane P2, and it is determined that the next read command "7" can be processed;

[0281] As shown by arrow A128, a polling command and a DMA command corresponding to the read command "8" are generated and stored at the end of the AIPR command sequence CQ4, completing the command conversion of the read command "8". After completing the command conversion of the read command "8", it is checked that there is no read command of the next read command group pointing to the same plane P3, and it is determined that the next read command "8" can be processed.

[0282] The command generation and storage order in this alternative embodiment ensures efficient execution of AIPR commands while maximizing the potential for parallel read operations. By inserting the AIPR commands of the second set of read commands after the DMA commands of the first set of commands, the system is able to start the next read operation immediately after completing the data transfer of the previous read operation, thereby significantly improving the read efficiency of the flash memory.

[0283] Based on the above-mentioned embodiments, the generation method of the AIPR command sequence of the present invention has multiple advantages:

[0284] (1) Maximizing parallel execution: By inserting the next set of AIPR commands in advance, the system can start a new read operation immediately after the previous read operation completes data transfer.

[0285] (2) Reduced latency: This approach minimizes the idle time between planes, ensuring that each plane can continue to work.

[0286] (3) Dynamic adjustment: This method can dynamically adjust the command sequence according to actual conditions to adapt to different reading modes and workloads.

[0287] (4) Forward-looking optimization: By considering the situation of the next read command group, a longer-term optimization strategy is achieved.

[0288] In another embodiment, the present invention also provides a method for dynamically optimizing the generation of AIPR command sequences, which proactively considers the next read command group when processing the current read command group, and adjusts the processing order of multiple commands of the next read command group according to the working state of the plane. The specific steps are as follows:

[0289] (1) Check the next read command group:

[0290] When executing the command sequence generation operation for the current read command group, the system will check the next read command group that is sequenced after it. The purpose of this step is to obtain the plane pointed to by each second read command in the next group and its working status.

[0291] (2) Determine the plane working status:

[0292] The system determines the working status of the plane through the following rules:

[0293] (a) If a plane pointed to by a second read command in the next read command group (referred to as the first plane) is not pointed to by any command in the current read command group, it is determined that the first plane is in an idle state.

[0294] (b) If a plane pointed to by a second read command in the next read command group (referred to as a second plane) has been pointed to by a command in the current read command group, it is determined that the second plane is in a busy state.

[0295] (3) Adjust the command processing order:

[0296] Based on the above judgment results, the system will adjust the processing order of the commands in the next read command group. Specifically, the system will give priority to processing the read commands corresponding to the idle state planes.

[0297] For example, assume that the current read command group includes commands directed to planes P0 and P1, and the next read command group includes commands directed to planes P0, P1, P2, and P3.

[0298] (1) The system first processes the commands of the current read command group.

[0299] (2) When generating the AIPR command sequence for the current read command group, the system checks the command for the next read command group:

[0300] Planes P0 and P1 are considered busy (because the current read command group is already in use)

[0301] Planes P2 and P3 are considered idle.

[0302] (3) The system adjusts the processing order of the next read command group:

[0303] Original order: P0, P1, P2, P3

[0304] After adjustment: P2, P3, P0, P1

[0305] In this way, commands directed to free planes P2 and P3 are processed in advance.

[0306] (4) When generating the AIPR command sequence, the system will:

[0307] After the AIPR commands for the corresponding planes P0 and P1 of the current read command group are generated and stored, the AIPR commands for the corresponding planes P2 and P3 of the next read command group are generated and stored.

[0308] After the polling command and DMA command of the read command corresponding to plane P0 in the current read command group are stored, the AIPR command corresponding to plane P0 in the next read command group is immediately inserted.

[0309] After the polling command and DMA command corresponding to plane P1 in the current read command group are stored, the AIPR command corresponding to plane P1 in the next read command group is immediately inserted.

[0310] Since all read commands of the current read command group have completed command conversion, the generation and storage of the next polling command and DMA command will be processed. It should be noted that the polling command and DMA command corresponding to the read commands of planes P2 and P3 will be generated and stored first.

[0311] The following use Fig.11 To explain. Fig.11 It is a schematic diagram showing generation of corresponding AIPR command sequences according to multiple read command groups according to another embodiment of the present invention.

[0312] Please refer to Fig.11 , taking two read command groups as an example for explanation.

[0313] The first set of read command groups contains three SLC type commands {"1", "2", "3"}, corresponding to planes P0, P1 and P2 respectively. The second set of read command groups contains four TLC type commands {"4", "5", "6", "7"}, corresponding to planes P0, P1, P2 and P3 respectively. The processing process is as follows:

[0314] (1) Process the first read command group:

[0315] As indicated by arrows A111, A112, and A113, the system first generates and stores AIPR commands for reading commands "1", "2", and "3".

[0316] (2) Check the second read command group:

[0317] When processing the first read command group, the system checks the planes pointed to by the second read command group and their working status:

[0318] Planes P0, P1, and P2 pointed to by read commands "4", "5", and "6" are determined to be busy because they are already used by read commands "1", "2", and "3" of the first read command group.

[0319] Plane P3 pointed to by the read command "7" is determined to be in an idle state because the first read command group does not use plane P3.

[0320] (3) Adjust the processing order of the second group of commands:

[0321] Based on the above judgment, the system adjusts the processing order of the second read command group from the original {"4", "5", "6", "7"} to {"7", "4", "5", "6"}, giving priority to the read command "7" pointing to the idle plane P3.

[0322] (4) Generate optimized AIPR command sequence:

[0323] As indicated by arrow A121, processor 211 first generates and inserts an AIPR command of a read command "7" immediately after the AIPR command of the first read command group.

[0324] Next, as shown by arrows A115, A116 and A117, the processor 211 generates and stores corresponding polling commands and DMA commands for read commands "1", "2" and "3". At this point, the command conversion of the first read command group and the storage of the command sequence have been completed.

[0325] At the same time, as indicated by arrows A122, A123 and A124, the processor 211 subsequently generates and inserts AIPR commands for read commands "4", "5" and "6" after the DMA commands corresponding to read commands "1", "2" and "3".

[0326] As shown by arrows A125, A126, A127 and A128, the processor 211 finally generates and stores the polling commands and DMA commands of the read commands "7", "4", "5" and "6". At this point, the command conversion of the second read command group and the storage of the command sequence have been completed.

[0327] Finally, obtain the AIPR command sequence CQ5.

[0328] This approach brings the following advantages:

[0329] (1) Improve parallelism: By giving priority to processing commands on idle planes, the parallel operation capability of the flash memory is maximized.

[0330] (2) Reduce waiting time: The idle plane can start a new read operation immediately without waiting for all commands in the current group to complete.

[0331] (3) Dynamic optimization: Adjust the command sequence according to the real-time plane status to achieve greater adaptability.

[0332] (4) Improve overall efficiency: Through intelligent scheduling, the idle time of the plane is reduced and the overall throughput of the storage system is improved.

[0333] Fig.12 FIG. 1 is a command execution timing diagram of an AIPR command sequence according to another embodiment of the present invention. Fig.12 , continued Fig.11 For example, as shown by arrow A1210, the execution status of AIPR command sequence CQ5 may be:

[0334] (1) AIPR command execution:

[0335] First, the system sends AIPR commands corresponding to SLC type read commands "1", "2", and "3" to three planes (P0, P1, and P2) at the same time to start a parallel read operation.

[0336] (2) Data preparation time:

[0337] Each AIPR command is followed by a corresponding data preparation time (tR1, tR2, tR3), during which each plane independently performs SLC-type data read operations.

[0338] (3) Check the next read command group: The processor 211 determines the read command "7" in the next read command group with the corresponding idle plane P3. The processor 211 generates and inserts the AIPR command of the read command "7" (the processing order of the read command "7" has been advanced because the processing order of the second read command group before the adjustment is "4", "5", "6", "7").

[0339] (4) Interleave the polling and DMA commands of the current read command group:

[0340] When the data preparation time tR1 of the read command "1" corresponding to plane P0 is over, the system executes the polling command and DMA command of the read command "1". It should be noted that this step will be executed after inserting the AIPR command of the read command "7".

[0341] After plane P0 executes the DMA command of the read command "1", processor 211 checks that the next read command group has the read command "4" of the same plane P0, and sends the AIPR command of the read command "4" of the next read command group to plane P0, starting the next round of reading of plane P0 (entering the data preparation time tR4 of the AIPR command of the read command "4").

[0342] During the data preparation time tR4 of the AIPR command of the read command "4", the system performs the operation of plane P1. Since the data preparation time tR2 of the read command "2" of plane P1 has ended, the system executes the polling command and DMA command of the read command "2".

[0343] After plane P1 executes the DMA command of read command "2", the system sends an AIPR command of read command "5" to plane P1 to start the next round of reading of plane P1 (entering the data preparation time tR5 of the AIPR command of read command "5").

[0344] During the data preparation time tR5 of the AIPR command of the read command "5", the system continues to execute the operation of plane P2. Since the data preparation time tR3 of the read command "3" of plane P2 has ended, the system executes the polling command and DMA command of the read command "3".

[0345] After plane P2 executes the DMA command of read command "3", the system sends the AIPR command of read command "6" to plane P2, and starts the next round of reading of plane P2 (entering the data preparation time tR6 of the AIPR command of read command "6").

[0346] During the data preparation time tR6 of the AIPR command of the read command "6", the system continues to execute the operation of plane P3. Since the data preparation time tR7 of the read command "7" of plane P3 has ended, the system executes the polling command and DMA command of the read command "7".

[0347] Next, as the data preparation time tR4-tR6 corresponding to the read commands "4"-"6" ends, the system executes the polling command and DMA command corresponding to the read commands "4"-"6" to complete the execution of the entire AIPR command sequence CQ5.

[0348] It is worth noting that, as shown by arrow A1220, the AIPR command, polling command and DMA command corresponding to the read command "7" are executed in advance as a whole. This is because the system detects that plane P3 is in an idle state, so the read command "7" directed to P3 is processed first.

[0349] Through this highly optimized AIPR command sequence execution method, the present invention significantly improves the read efficiency of flash memory, especially in complex scenarios dealing with mixed storage types and different plane states. This approach not only maximizes the advantages of parallel reading, but also ensures the best utilization of system resources through intelligent scheduling.

[0350] It should be noted that in this embodiment, the read command group of the SLC is processed first because its overall processing time is faster.

[0351] In one embodiment, the present invention provides a method for further optimizing the generation of AIPR command sequences, which reduces command transmission overhead and improves overall reading efficiency by identifying continuous read operations and merging multiple AIPR commands. The specific steps are as follows:

[0352] (1) Identify continuous read operations:

[0353] When generating the target command sequence, the system analyzes the physical addresses of the read commands. If multiple read commands are found to point to consecutive pages of the same plane, these commands are identified as consecutive read operations.

[0354] (2) Merge AIPR commands:

[0355] For identified continuous read operations, the system no longer generates a separate AIPR command for each read command, but merges them into one multi-page AIPR command.

[0356] (3) Generate multi-page AIPR command:

[0357] The multi-page AIPR command contains the starting address and number of consecutive pages, allowing the flash controller to initiate read operations on multiple pages at one time.

[0358] (4) Adjust polling and DMA commands:

[0359] Accordingly, the system adjusts subsequent polling commands and DMA commands to accommodate multi-page read operations.

[0360] This approach brings the following advantages:

[0361] (1) Reduce command transmission overhead:

[0362] By combining multiple AIPR commands into one, the number of command transmissions is significantly reduced, reducing bus occupancy and processor burden.

[0363] (2) Improve reading efficiency:

[0364] The flash controller can initiate reads of multiple pages at once, reducing the latency between each individual page read.

[0365] (3) Simplify the command sequence:

[0366] The combined command sequence is more concise and easier to manage and execute.

[0367] Finally, this embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code, when the computer readable code runs in the processor of the host system, the processor executes the steps of the above-mentioned memory simulator and storage device testing method. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0368] Based on the above, the data reading method and memory controller provided by the embodiments of the present invention can achieve the following effects:

[0369] (1) Improved parallel reading efficiency:

[0370] The present invention optimizes the generation and execution of AIPR command sequences and fully utilizes the multi-plane structure of flash memory to significantly improve the parallel reading efficiency. By sending AIPR commands to multiple planes at the same time, the system can start multiple read operations at the same time, greatly improving the data access speed.

[0371] (2) Dynamic scheduling optimization:

[0372] The present invention introduces a dynamic scheduling mechanism that can adjust the processing order of read commands according to the real-time working status of the plane. By giving priority to processing commands directed to idle planes, the system reduces the idle time of the plane, improves resource utilization, and further improves the overall reading performance.

[0373] (3) Hybrid storage type support:

[0374] The present invention can simultaneously process read commands of different types of storage units (such as SLC and TLC). By considering the characteristics of different storage types, the system can optimize the command execution sequence in a targeted manner and perform well when processing complex hybrid storage structures.

[0375] (4) Minimize delay:

[0376] By staggered execution of AIPR commands, polling commands and DMA commands, the present invention minimizes the waiting time between various operations. For example, when one plane is performing data transmission, the system can simultaneously start the reading operation of other planes, effectively reducing the overall reading delay.

[0377] (5) Maximizing resource utilization:

[0378] The method of the present invention ensures efficient utilization of each plane in the flash memory. Through intelligent scheduling and dynamic adjustment, the system can maximize the number of active planes at any given time point, thereby improving the overall throughput.

[0379] (6) Adaptability and flexibility:

[0380] The method of the present invention can adapt to various reading modes and workloads. Whether it is continuous reading or random reading, the system can dynamically adjust the strategy to obtain the best performance. This flexibility enables the present invention to maintain high efficiency in various application scenarios.

[0381] (7) Command queue optimization:

[0382] By pre-sorting and dynamic adjustment, the present invention optimizes the structure of the AIPR command sequence, which not only improves the efficiency of command execution, but also reduces the overhead of command transmission and processing.

[0383] (8) Improved data transmission efficiency:

[0384] By optimizing the execution timing of DMA commands, the present invention ensures the continuity and efficiency of the data transmission process, thereby reducing the interruption and waiting time in data transmission and improving the overall data throughput.

[0385] It should be noted that in the above embodiments, the target AIPR command is also called a target read trigger command; the target DMA command is also called a target data access command; the first AIPR command and the second AIPR command are also respectively called the first read trigger command and the second read trigger command; the first DMA command and the second DMA command are also respectively called the first data access command and the second data access command.

[0386] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data reading method, applicable to a storage device equipped with a rewritable non-volatile memory module, wherein the storage device supports asynchronous independent plane reading, characterized in that: The method comprises: storing a plurality of read commands from the host system into one or more buffer pools respectively, wherein the one or more buffer pools correspond to different chip enable pins respectively, and all read commands of each buffer pool point to the chip enable pin corresponding to the buffer pool to which it belongs; When a preset condition is met, a pre-sorting operation is performed on a plurality of first read commands in a first buffer pool of the one or more buffer pools to group the plurality of first read commands into a plurality of read command groups, wherein one or more second read commands belonging to the same read command group correspond to different planes of the same chip in the storage device, respectively, and the storage cells corresponding to the one or more second read commands respectively belong to the same storage cell type; generating an execution command sequence corresponding to the first buffer pool according to the plurality of read command groups of the first buffer pool; and According to the execution command sequence, the plurality of commands are executed to complete the parallel read operations corresponding to the plurality of first read commands.

2. The data reading method according to claim 1, characterized in that: The preset condition includes at least one of the following: The number of the plurality of first read commands stored in the first cache pool reaches a predetermined threshold; or The waiting time of the first read command stored earliest in the first buffer pool reaches a predetermined time threshold.

3. The data reading method according to claim 1, characterized in that: The method further comprises: According to the recorded mapping information, obtaining the physical address of each read command; and According to the physical address of the read command, physical characteristics of the physical address of the read command are obtained, wherein the physical characteristics include the chip enable pin, the plane, the chip, and the storage unit type.

4. The data reading method according to claim 3, characterized in that: The steps of performing the pre-sorting operation include: According to the storage unit types corresponding to the plurality of first read commands, the plurality of first read commands are grouped to obtain one or more storage unit type command groups, wherein one or more first read commands belonging to the same storage unit type command group correspond to the same storage unit type; According to the chips to which the one or more first read commands in the same storage unit type command group respectively correspond, grouping the one or more first read commands in the same storage unit type command group to obtain one or more chip command groups, wherein the one or more first read commands belonging to the same chip command group correspond to the same chip; as well as One or more second read commands pointing to different planes in each chip command group are compiled into the same read command group to obtain the multiple read command groups, wherein the processing order of the one or more second read commands in each read command group is set based on the order of the corresponding planes.

5. The data reading method according to claim 3, characterized in that: The plurality of commands in the execution command sequence include the following types: read trigger command, polling command and data access command, and the step of generating the execution command sequence includes: According to the compilation order of the plurality of read command groups, a command sequence generation operation is performed on each read command group in turn, wherein when the command sequence generation operation is performed on a current read command group among the multiple read command groups, the read trigger command, the polling command and the data access command corresponding to each current second read command are generated according to the processing order of one or more current second read commands of the current read command group to obtain a first command sequence corresponding to the current read command group; as well as The generated first command sequence is stored in the execution command sequence.

6. The data reading method according to claim 5, characterized in that: The method further comprises: When performing the command sequence generation operation on a current read command group among the multiple read command groups, checking a next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group and the working status of the plane, wherein the working status includes an idle state and a busy state; and The processing order of the one or more next second read commands is adjusted according to the working status of the plane to which the one or more next second read commands are respectively pointed.

7. The data reading method according to claim 6, characterized in that: The step of obtaining the plane pointed to by each of the one or more next second read commands in the next read command group and the working status of the plane comprises: If the first plane pointed to by one of the one or more next second read commands is not pointed to by the one or more current second read commands in the current read command group, determine that the working state of the first plane is the idle state; and If the second plane pointed to by one of the one or more next second read commands has been pointed to by the one or more current second read commands in the current read command group, the working state of the second plane is determined to be the busy state.

8. The data reading method according to claim 7, characterized in that: The step of adjusting the processing order of the one or more next second read commands comprises: A target next second read command corresponding to the second plane in an idle state among the one or more next second read commands is preferentially processed.

9. The data reading method according to claim 5, characterized in that: The method further comprises: When performing the command sequence generation operation on a current read command group among the multiple read command groups, checking a next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group and the working state of the plane, wherein the working state includes an idle state and a busy state; Obtain a target next second read command corresponding to the target plane in the idle state among the one or more next second read commands; Generate a target read trigger command, a target polling command and a target data access command corresponding to a next second read command of the target; inserting the target read trigger command into the first command sequence; as well as The target polling command and the target data access command are inserted after the first command sequence.

10. The data reading method according to claim 5, characterized in that: The method further comprises: When performing the command sequence generation operation on a current read command group among the plurality of read command groups, checking a next read command group sorted after the current read command group to obtain the planes pointed to by one or more next second read commands in the next read command group; as well as When the target plane pointed to by the target next second read command in the one or more next second read commands is different from the planes corresponding to all the current second read commands, Generate a target read trigger command, a target polling command and a target data access command corresponding to a next second read command of the target; inserting the target read trigger command into the first command sequence; as well as The target polling command and the target data access command are inserted after the first command sequence.

11. The data reading method according to claim 5, characterized in that: The step of generating the read trigger command, the polling command and the data access command corresponding to each current second read command according to the processing order of the one or more current second read commands of the current read command group comprises: Generate a first read trigger command corresponding to each current second read command one by one according to the processing order of the one or more current second read commands; According to the processing order of the one or more current second read commands, one by one generates a pair of first polling command and first data access command corresponding to each current second read command; and One or more of the first read trigger commands, one or more pairs of the first polling commands, and the first data access command of the one or more current second read commands are stored in the execution command sequence as the first command sequence.

12. The data reading method according to claim 11, characterized in that: The step of storing the generated first command sequence into the execution command sequence comprises: Check whether there is a previous read command group that is sorted before the current read command group; If the previous read command group exists, execute the following steps: Acquire a second command sequence of the last read command group, wherein the second command sequence includes one or more second read trigger commands corresponding to one or more last second read commands of the last read command group, one or more pairs of second polling commands and second data access commands; According to the processing order of the one or more current second read commands, sequentially inserting the one or more first read trigger commands after the second data access commands corresponding to the same plane; and The one or more pairs of the first polling command and the first data access command are stored in sequence according to the processing order of the one or more current second read commands.

13. The data reading method according to claim 5, characterized in that: Executing the command sequence generation operation on the plurality of read command groups includes: According to the compilation order of the plurality of read command groups, each second read command of each read command group is converted into a command, wherein the command conversion includes generating a read trigger command, a polling command and a data access command according to the corresponding second read command, Wherein, for the current read command group for performing the command conversion: For each current second read instruction of the current read command group that has not yet undergone the command conversion, generating a read trigger command corresponding to the current second read command; Generate a corresponding polling command and data access command for each read trigger command; For each read trigger command, obtain the plane corresponding to the read trigger command, and check whether there is a target read command pointing to the same plane in the next read command group; If the target read command pointing to the same plane exists, generating a corresponding target read trigger command based on the target read command of the next read command group, inserting the target read trigger command after the data access command corresponding to the read trigger command, and generating a target polling command and a target data access command corresponding to the target read trigger command; and If there is no target read command pointing to the same plane, the command conversion of all current second read commands of the current read command group is completed, and the next read command group is used as a new current read command group to perform the corresponding command conversion, If it is detected that there is no next read command group, the generation of the execution command sequence is completed.

14. The data reading method according to claim 5, characterized in that: Executing the command sequence generation operation on the plurality of read command groups includes: According to the compilation order of the plurality of read command groups, each second read command of each read command group is converted into a command, wherein the command conversion includes generating a read trigger command, a polling command and a data access command according to the corresponding second read command, Wherein, for the current read command group for performing the command conversion: Performing the command conversion on each current second read instruction of the current read command group that has not yet undergone the command conversion comprises: If the read trigger command of the current second read instruction for the command conversion has not been generated, generate a read trigger command corresponding to the current second read command, and generate a corresponding polling command and a data access command for the read trigger command; If a read trigger command of the current second read instruction for performing the command conversion has been generated, generating a corresponding polling command and a data access command for the read trigger command; After generating the corresponding polling command and data access command, obtaining the plane corresponding to the read trigger command, and checking whether there is a target read command pointing to the same plane in the next read command group; Wherein, if the target read command pointing to the same plane exists, a corresponding target read trigger command is generated based on the target read command of the next read command group, the target read trigger command is inserted after the data access command corresponding to the read trigger command, and the command conversion of the current second read instruction is completed; and If the target read command pointing to the same plane does not exist, the command conversion of the current second read command is completed, the next read command group is set as the new current read command group and the above steps are repeated to perform the command conversion on the new current read command.

15. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: A memory interface control circuit, used for electrically connecting to the rewritable non-volatile memory module; A data management circuit electrically connected to the connection interface circuit of the storage device, for receiving data and commands from a host system via the connection interface circuit; A buffer memory for caching data; and a processor electrically connected to the memory interface control circuit, the data management circuit and the buffer memory, wherein the processor is configured to: storing a plurality of read commands from the host system in one or more buffer pools of the buffer memory, respectively, wherein the one or more buffer pools correspond to different chip enable pins, respectively, and all read commands of each buffer pool point to the chip enable pin corresponding to the buffer pool to which it belongs; When a preset condition is met, a pre-sorting operation is performed on a plurality of first read commands in a first buffer pool of the one or more buffer pools to group the plurality of first read commands into a plurality of read command groups, wherein one or more second read commands belonging to the same read command group correspond to different planes of the storage device of the rewritable non-volatile memory module respectively and the storage units corresponding to the one or more second read commands respectively belong to the same storage unit type; generating an execution command sequence corresponding to the first buffer pool according to the plurality of read command groups of the first buffer pool; and According to the generated execution command sequence, the plurality of commands are executed to complete the parallel read operation corresponding to the plurality of first read commands.

16. The memory controller according to claim 15, characterized in that: The preset condition includes at least one of the following: The number of the plurality of first read commands stored in the first cache pool reaches a predetermined threshold; or The waiting time of the first read command stored earliest in the first buffer pool reaches a predetermined time threshold.

17. The memory controller according to claim 15, wherein: The processor is also configured to: According to the recorded mapping information, obtaining the physical address of each read command; and According to the physical address of the read command, physical characteristics of the physical address of the read command are obtained, wherein the physical characteristics include the chip enable pin, the plane, the chip, and the storage unit type.

18. The memory controller according to claim 17, wherein: The steps of performing the pre-sorting operation include: According to the storage unit types corresponding to the plurality of first read commands, the plurality of first read commands are grouped to obtain one or more storage unit type command groups, wherein one or more first read commands belonging to the same storage unit type command group correspond to the same storage unit type; According to the chips to which the one or more first read commands in the same storage unit type command group respectively correspond, grouping the one or more first read commands in the same storage unit type command group to obtain one or more chip command groups, wherein the one or more first read commands belonging to the same chip command group correspond to the same chip; as well as One or more second read commands pointing to different planes in each chip command group are compiled into the same read command group to obtain the multiple read command groups, wherein the processing order of the one or more second read commands in each read command group is set based on the order of the corresponding planes.

19. The memory controller according to claim 18, wherein: The plurality of commands in the execution command sequence include the following types: read trigger command, polling command and data access command, and the step of generating the execution command sequence includes: According to the compilation order of the plurality of read command groups, a command sequence generation operation is performed on each read command group in turn, wherein when the command sequence generation operation is performed on a current read command group among the multiple read command groups, the read trigger command, the polling command and the data access command corresponding to each current second read command are generated according to the processing order of one or more current second read commands of the current read command group to obtain a first command sequence corresponding to the current read command group; as well as The generated first command sequence is stored in the execution command sequence.

20. The memory controller according to claim 19, wherein: The processor is also configured to: When performing the command sequence generation operation on a current read command group among the multiple read command groups, checking a next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group and the working state of the plane, wherein the working state includes an idle state and a busy state; as well as The processing order of the one or more next second read commands is adjusted according to the working status of the plane to which the one or more next second read commands are respectively pointed.

21. The memory controller according to claim 20, wherein: The step of obtaining the plane pointed to by each of the one or more next second read commands in the next read command group and the working status of the plane comprises: If the first plane pointed to by one of the one or more next second read commands is not pointed to by the one or more current second read commands in the current read command group, determine that the working state of the first plane is the idle state; and If the second plane pointed to by one of the one or more next second read commands has been pointed to by the one or more current second read commands in the current read command group, the working state of the second plane is determined to be the busy state.

22. The memory controller according to claim 21, wherein: The step of adjusting the processing order of the one or more next second read commands comprises: A target next second read command corresponding to the second plane in an idle state among the one or more next second read commands is preferentially processed.

23. The memory controller according to claim 19, wherein: The processor is also configured to: When performing the command sequence generation operation on a current read command group among the multiple read command groups, checking a next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group and the working state of the plane, wherein the working state includes an idle state and a busy state; Obtain a target next second read command corresponding to the target plane in the idle state among the one or more next second read commands; Generate a target read trigger command, a target polling command and a target data access command corresponding to a next second read command of the target; inserting the target read trigger command into the first command sequence; as well as The target polling command and the target data access command are inserted after the first command sequence.

24. The memory controller according to claim 19, wherein: The processor is also configured to: When performing the command sequence generation operation on a current read command group among the plurality of read command groups, checking a next read command group sorted after the current read command group to obtain the planes pointed to by one or more next second read commands in the next read command group; as well as When the target plane pointed to by the target next second read command in the one or more next second read commands is different from the planes corresponding to all the current second read commands, Generate a target read trigger command, a target polling command and a target data access command corresponding to a next second read command of the target; inserting the target read trigger command into the first command sequence; as well as The target polling command and the target data access command are inserted after the first command sequence.

25. The memory controller according to claim 19, wherein: The step of generating the read trigger command, the polling command and the data access command corresponding to each current second read command according to the processing order of the one or more current second read commands of the current read command group comprises: Generate a first read trigger command corresponding to each current second read command one by one according to the processing order of the one or more current second read commands; According to the processing order of the one or more current second read commands, one by one generates a pair of first polling command and first data access command corresponding to each current second read command; and One or more of the first read trigger commands, one or more pairs of the first polling commands, and the first data access command of the one or more current second read commands are stored in the execution command sequence as the first command sequence.

26. The memory controller according to claim 25, characterized in that The step of storing the generated first command sequence into the execution command sequence comprises: Check whether there is a previous read command group that is sorted before the current read command group; If the previous read command group exists, execute the following steps: Acquire a second command sequence of the last read command group, wherein the second command sequence includes one or more second read trigger commands corresponding to one or more last second read commands of the last read command group, one or more pairs of second polling commands and second data access commands; According to the processing order of the one or more current second read commands, sequentially inserting the one or more first read trigger commands after the second data access commands corresponding to the same plane; and The one or more pairs of the first polling command and the first data access command are stored in sequence according to the processing order of the one or more current second read commands.

27. The memory controller according to claim 19, wherein: Executing the command sequence generation operation on the plurality of read command groups includes: According to the compilation order of the plurality of read command groups, each second read command of each read command group is converted into a command, wherein the command conversion includes generating a read trigger command, a polling command and a data access command according to the corresponding second read command, Wherein, for the current read command group for performing the command conversion: For each current second read instruction of the current read command group that has not yet undergone the command conversion, generating a read trigger command corresponding to the current second read command; Generate a corresponding polling command and data access command for each read trigger command; For each read trigger command, obtain the plane corresponding to the read trigger command, and check whether there is a target read command pointing to the same plane in the next read command group; If the target read command pointing to the same plane exists, generating a corresponding target read trigger command based on the target read command of the next read command group, inserting the target read trigger command after the data access command corresponding to the read trigger command, and generating a target polling command and a target data access command corresponding to the target read trigger command; and If there is no target read command pointing to the same plane, the command conversion of all current second read commands of the current read command group is completed, and the next read command group is used as a new current read command group to perform the corresponding command conversion, If it is detected that there is no next read command group, the generation of the execution command sequence is completed.

28. The memory controller according to claim 19, wherein: Executing the command sequence generation operation on the plurality of read command groups includes: According to the compilation order of the plurality of read command groups, each second read command of each read command group is converted into a command, wherein the command conversion includes generating a read trigger command, a polling command and a data access command according to the corresponding second read command, Wherein, for the current read command group for performing the command conversion: Performing the command conversion on each current second read instruction of the current read command group that has not yet undergone the command conversion comprises: If the read trigger command of the current second read instruction for the command conversion has not been generated, generate a read trigger command corresponding to the current second read command, and generate a corresponding polling command and a data access command for the read trigger command; If a read trigger command of the current second read instruction for performing the command conversion has been generated, generating a corresponding polling command and a data access command for the read trigger command; After generating the corresponding polling command and data access command, obtaining the plane corresponding to the read trigger command, and checking whether there is a target read command pointing to the same plane in the next read command group; Wherein, if the target read command pointing to the same plane exists, a corresponding target read trigger command is generated based on the target read command of the next read command group, the target read trigger command is inserted after the data access command corresponding to the read trigger command, and the command conversion of the current second read instruction is completed; and If the target read command pointing to the same plane does not exist, the command conversion of the current second read command is completed, the next read command group is set as the new current read command group and the above steps are repeated to perform the command conversion on the new current read command.

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