Butterfly computing unit, butterfly computing unit array, reconfigurable array and chip

Abstract

An embodiment of the present application provides a butterfly computing unit, a butterfly computing unit array, a reconfigurable array, and a chip. The butterfly computing unit includes a first-in first-out (FIFO) buffer unit, a butterfly computing module, a multiplier module, a rotation factor storage module, and first and second external interfaces. The first external interface inputs radix-2 or radix-3 FFT data. The FIFO buffer unit caches the input data, the data output by the butterfly computing module, or the data output by the multiplier module. The butterfly computing module receives the data output by the FIFO buffer unit and performs butterfly computation to obtain butterfly computation result data. The multiplier module obtains a rotation factor from the rotation factor storage module and performs multiplication computation on the data output by the FIFO buffer unit or the data output by the butterfly computing module according to the rotation factor to obtain multiplication computation result data. The second external interface sends out the multiplication computation result data. The present application simplifies the structure of the butterfly computing unit and reduces the consumption of hardware resources.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular, to a butterfly computing unit, a butterfly computing unit array, a reconfigurable array, and a chip. Background Art

[0002] In modern computing, the butterfly computing unit is widely used in signal processing tasks such as the Fast Fourier Transform (FFT). The efficient computing ability of the butterfly structure enables it to quickly process complex mathematical operations.

[0003] In the related art, a butterfly arithmetic unit is provided. However, the structure of the butterfly arithmetic unit is complex, and the hardware resources consumed by the butterfly arithmetic unit for performing one butterfly operation are large. Summary of the Invention

[0004] Embodiments of this application provide a butterfly computing unit, a butterfly computing unit array, a reconfigurable array, and a chip, so as to achieve the technical effects of reducing the structural complexity of the butterfly arithmetic unit and reducing the hardware resources consumed by the butterfly arithmetic unit for performing one butterfly operation.

[0005] In a first aspect, an embodiment of this application provides a butterfly computing unit, including: a first-in first-out buffer unit, a butterfly computing module, a multiplier module, a rotation factor storage module, a first external interface, and a second external interface;

[0006] The first-in first-out buffer unit is respectively connected to the butterfly computing module, the multiplier module, the first external interface, and the second external interface. The butterfly computing module is connected to the multiplier module. The multiplier module is connected to the rotation factor storage module and the second external interface;

[0007] The first external interface is used to input data in the radix-2 or radix-3 frequency-domain decimation Fast Fourier Transform mode. The data in the radix-2 and radix-3 frequency-domain decimation Fast Fourier Transform modes both include multiple groups of data;

[0008] The first-in first-out buffer unit is used to cache at least one group of data, or the butterfly computing result data output by the butterfly computing module, or the multiplication computing result data output by the multiplier module;

[0009] The butterfly computing module is used to receive the data output by the first-in first-out buffer unit and perform a butterfly calculation on the data output by the first-in first-out buffer unit to obtain butterfly computing result data;

[0010] The multiplier module is used to obtain rotation factors from the rotation factor storage module, and perform multiplication calculations on the butterfly calculation result data output by the first-in-first-out cache unit or the butterfly calculation result data output by the butterfly calculation module according to the rotation factors, so as to obtain multiplication calculation result data;

[0011] The second external interface is used to send out the multiplication calculation result data.

[0012] In a possible implementation manner, the first-in-first-out cache unit includes: a first first-in-first-out cache module, a second first-in-first-out cache module, and a third first-in-first-out cache module;

[0013] The input end of the first first-in-first-out cache module is respectively connected to the output end of the butterfly calculation module and the input end of the first external interface, and the output end of the first first-in-first-out cache module is connected to the input end of the butterfly calculation module;

[0014] The input end of the second first-in-first-out cache module is respectively connected to the output end of the butterfly calculation module and the input end of the first external interface, and the output end of the second first-in-first-out cache module is respectively connected to the input end of the butterfly calculation module and the input end of the multiplier module;

[0015] The input end of the third first-in-first-out cache module is connected to the output end of the multiplier module, and the output end of the third first-in-first-out cache module is respectively connected to the input end of the butterfly calculation module and the input end of the second external interface.

[0016] In a possible implementation manner, the butterfly calculation module includes: a first input interface, a first output interface, a second input interface, and a second output interface;

[0017] The first input interface is respectively connected to the output end of the first first-in-first-out cache module, the output end of the second first-in-first-out cache module, and the input end of the first external interface, and the first output interface is respectively connected to the input end of the first first-in-first-out cache module and the input end of the second external interface;

[0018] The second input interface is respectively connected to the output end of the first first-in-first-out cache module, the output end of the second first-in-first-out cache module, and the input end of the first external interface, and the second output interface is connected to the input end of the second first-in-first-out cache module.

[0019] In a possible implementation manner, the data output from the input end of the first external interface includes at least a first group of data and a second group of data, and the first group of data and the second group of data are data in the radix-2 frequency-domain decimation fast Fourier transform mode;

[0020] The first external interface is specifically configured to: send the first set of data to the first first-in-first-out buffer module, and send the second set of data to the second input interface of the butterfly calculation module;

[0021] The butterfly calculation module is specifically configured to: receive the first set of data sent by the first first-in-first-out buffer module, perform a first butterfly calculation based on the first set of data and the second set of data to obtain a first butterfly calculation result data and a second butterfly calculation result data, and send the first butterfly calculation result data to the second external interface through the first output interface, and send the second butterfly calculation result data to the second first-in-first-out buffer module through the second output interface;

[0022] The multiplier module is specifically configured to: receive the second butterfly calculation result data sent by the second first-in-first-out buffer module, read the first rotation factor stored in the rotation factor storage module, perform a complex multiplication calculation on the second butterfly calculation result data according to the first rotation factor to obtain a first multiplication calculation result data, and send the first multiplication calculation result data to the third first-in-first-out buffer module, so that the first multiplication calculation result data is sent to the second external interface through the third first-in-first-out buffer module.

[0023] In a possible implementation manner, at least the third set of data, the fourth set of data, and the fifth set of data are included in the data output at the input end of the first external interface, and the third set of data, the fourth set of data, and the fifth set of data are data in the base-three frequency-domain decimation fast Fourier transform mode;

[0024] The first external interface is specifically configured to: send the third set of data to the second first-in-first-out buffer module, send the fourth set of data to the first first-in-first-out buffer module, and send the fifth set of data to the second input interface of the butterfly calculation module;

[0025] The butterfly calculation module is specifically configured to: receive the fourth set of data sent by the first first-in-first-out buffer module, perform a second butterfly calculation based on the fourth set of data and the fifth set of data to obtain a third butterfly calculation result data and a fourth butterfly calculation result data, and send the third butterfly calculation result data to the first first-in-first-out buffer module through the first output interface, and send the fourth butterfly calculation result data to the second first-in-first-out buffer module through the second output interface;

[0026] The multiplier module is specifically configured to: receive the fourth butterfly calculation result data sent by the second first-in-first-out buffer module, read the second rotation factor stored in the rotation factor storage module, perform a constant multiplication calculation on the fourth butterfly calculation result data and the second rotation factor to obtain second multiplication calculation result data, and send the second multiplication calculation result data to the third first-in-first-out buffer module.

[0027] In a possible implementation manner, the butterfly calculation module is specifically further configured to:

[0028] receive the third butterfly calculation result data sent by the first first-in-first-out buffer module, and receive the third group of data sent by the second first-in-first-out buffer module;

[0029] perform a third butterfly calculation based on the third butterfly calculation result data and the third group of data to obtain fifth butterfly calculation result data and sixth butterfly calculation result data;

[0030] send the fifth butterfly calculation result data to the second external interface through the first output interface, and send the sixth butterfly calculation result data to the second first-in-first-out buffer module through the second output interface.

[0031] In a possible implementation manner, the butterfly calculation module is specifically further configured to:

[0032] receive the sixth butterfly calculation result data sent by the second first-in-first-out buffer module, and receive the second multiplication calculation result data sent by the third first-in-first-out buffer module;

[0033] perform a fourth butterfly calculation based on the sixth butterfly calculation result data and the second multiplication calculation result data to obtain seventh butterfly calculation result data and eighth butterfly calculation result data;

[0034] send the seventh butterfly calculation result data to the multiplier module through the first output interface, and send the eighth butterfly calculation result data to the second first-in-first-out buffer module through the second output interface.

[0035] In a possible implementation manner, the multiplier module is specifically further configured to:

[0036] receive the seventh butterfly calculation result data sent by the butterfly calculation module;

[0037] Read the third rotation factor stored in the rotation factor storage module, perform complex multiplication calculation on the seventh butterfly calculation result data according to the third rotation factor to obtain the third multiplication calculation result data, and send the third multiplication calculation result data to the third first-in-first-out cache module, so that the third multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

[0038] In a possible implementation manner, the multiplier module is further specifically configured to:

[0039] Receive the eighth butterfly calculation result data sent by the second first-in-first-out cache module;

[0040] Read the fourth rotation factor stored in the rotation factor storage module, perform complex multiplication calculation on the eighth butterfly calculation result data according to the fourth rotation factor to obtain the fourth multiplication calculation result data, and send the fourth multiplication calculation result data to the third first-in-first-out cache module, so that the fourth multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

[0041] In a second aspect, an embodiment of the present application provides a butterfly calculation unit array, including a plurality of butterfly calculation units as described in the first aspect and / or various possible implementation manners of the first aspect, and the plurality of butterfly calculation units are serially connected.

[0042] In a third aspect, an embodiment of the present application provides a mixed-radix reconfigurable array, including the butterfly calculation unit array as described in the second aspect.

[0043] In a possible implementation manner, it further includes: a memory, an input controller, an output controller, and a timing controller;

[0044] The memory is respectively connected to the input end of the input controller, the input end of the output controller, and the input end of the timing controller, and the output end of the input controller, the input end of the output controller, and the output end of the timing controller are respectively connected to the butterfly calculation unit array;

[0045] The memory is used to store configuration information, and the configuration information includes data to be calculated and the operation mode of the data to be calculated, and the operation mode includes a radix-two frequency-domain decimation fast Fourier transform mode or a radix-three frequency-domain decimation fast Fourier transform mode;

[0046] The timing controller is used to determine the timing logic of each butterfly calculation unit in the butterfly calculation unit array according to the configuration information;

[0047] The input controller is configured to group the data to be computed according to the operation mode, obtaining multiple groups of data;

[0048] The output controller is configured to receive the output result data of the data to be computed from the butterfly computing unit array.

[0049] In a possible implementation manner, the output end of the input controller, the input end of the output controller, and the output end of the timing controller are respectively connected to a plurality of the butterfly computing units in the butterfly computing unit array.

[0050] Fourthly, an embodiment of the present application provides a chip, including the hybrid base reconfigurable array as described in the third aspect and / or various possible implementation manners of the third aspect.

[0051] An embodiment of the present application provides a butterfly computing unit, a butterfly computing unit array, a reconfigurable array, and a chip. Among them, the butterfly computing unit includes: a first-in first-out buffer unit, a butterfly computing module, a multiplier module, a rotation factor storage module, a first external interface, and a second external interface. The connection relationships of the above components are as follows: the first-in first-out buffer unit is respectively connected to the butterfly computing module, the multiplier module, the first external interface, and the second external interface; the butterfly computing module is connected to the multiplier module; the multiplier module is connected to the rotation factor storage module and the second external interface. Among them, the first external interface is used to input data in the radix-2 or radix-3 frequency-domain decimation fast Fourier transform mode, and the data in the radix-2 and radix-3 frequency-domain decimation fast Fourier transform modes both include multiple groups of data. The first-in first-out buffer unit is configured to buffer at least one group of data, or the butterfly computing result data output by the butterfly computing module, or the multiplication calculation result data output by the multiplier module. The butterfly computing module is configured to receive the data output by the first-in first-out buffer unit and perform butterfly computing on the data output by the first-in first-out buffer unit to obtain butterfly computing result data. The multiplier module is configured to obtain a rotation factor from the rotation factor storage module and perform multiplication calculation on the butterfly computing result data output by the first-in first-out buffer unit or the butterfly computing result data output by the butterfly computing module according to the rotation factor to obtain multiplication calculation result data. The second external interface is used to send out the multiplication calculation result data. Description of the Drawings

[0052] The drawings here are incorporated into the description and form a part of this description, showing embodiments consistent with the present application, and are used together with the description to explain the principles of the present application.

[0053] Figure 1 It is a schematic structural diagram of a butterfly arithmetic unit in a related art provided by the present application;

[0054] Figure 2Schematic diagram of a butterfly computing unit provided by an embodiment of the present application;

[0055] Figure 3 Schematic diagram of another butterfly computing unit provided by an embodiment of the present application;

[0056] Figure 4 Schematic diagram of a butterfly computing unit structure for performing radix-2 butterfly operations on data in a radix-2 frequency-domain decimation fast Fourier transform mode provided by an embodiment of the present application;

[0057] Figure 5A Schematic diagram of a butterfly computing unit structure for performing the first group of butterfly operations on data in a radix-3 frequency-domain decimation fast Fourier transform mode provided by an embodiment of the present application;

[0058] Figure 5B Schematic diagram of a butterfly computing unit structure for performing the second group of butterfly operations on data in a radix-3 frequency-domain decimation fast Fourier transform mode provided by an embodiment of the present application;

[0059] Figure 5C Schematic diagram of a butterfly computing unit structure for performing the third group of butterfly operations on data in a radix-3 frequency-domain decimation fast Fourier transform mode provided by an embodiment of the present application;

[0060] Figure 6A Schematic diagram of a radix-3 butterfly operation structure in the related art provided by the present application;

[0061] Figure 6B Schematic diagram of a radix-3 butterfly operation structure provided by an embodiment of the present application;

[0062] Figure 7 Schematic diagram of a structure of a butterfly computing unit array provided by an embodiment of the present application;

[0063] Figure 8 Schematic diagram of a structure of a mixed-radix FFT processor in another related art provided by the present application;

[0064] Figure 9 Schematic diagram of a structure of a mixed-radix reconfigurable array provided by an embodiment of the present application;

[0065] Figure 10 Schematic diagram of a calculation result provided by an embodiment of the present application;

[0066] Figure 11 Schematic diagram of another calculation result provided by an embodiment of the present application.

[0067] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and will be described in more detail hereinafter. These drawings and the written description are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed Description of the Embodiments

[0068] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0069] In the description of the embodiments of the present application, terms such as "inner" and "outer" indicating the direction or positional relationship are based on the direction or positional relationship shown in the drawings. This is only for the convenience of description and does not indicate or imply that the device or component must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application.

[0070] In the description of the embodiments of the present application, herein, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0071] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, the terms "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific situations.

[0072] In the related art, there is a multi-path hybrid base FFT reconfigurable butterfly arithmetic unit, as Figure 1 shown, Figure 1A structural schematic diagram of a butterfly arithmetic unit in a related art provided for this application. The butterfly arithmetic unit includes a control unit 11, a first selection switch unit 12, and an arithmetic unit 13. The control unit 11 is respectively connected to the first selection switch unit 12 and the arithmetic unit 13, and the first selection switch unit 12 is connected to the arithmetic unit 13.

[0073] Among them, the arithmetic unit 13 includes two radix-2 butterfly arithmetic units 131, a first complex adder 132, and a second complex adder 133. Each radix-2 butterfly arithmetic unit 131 includes a first complex multiplier 1311, a third complex adder 1312, and a complex subtractor 1313.

[0074] The control unit 11 is used to generate arithmetic instructions according to the received data to be operated. Among them, the data to be operated includes digital signals to be processed, rotation factors, and preset rotation factor coefficients.

[0075] The first selection switch unit 12 is used to select a corresponding conduction mode according to the arithmetic instructions.

[0076] The arithmetic unit 13 is used to perform butterfly operations on the data to be operated according to the conduction mode. Specifically, the radix-2 butterfly arithmetic unit 131 is used to perform radix-2 butterfly operations according to the data to be operated and the corresponding conduction mode of the first selection switch unit 12. The two radix-2 butterfly arithmetic units 131 are also used to form a radix-3 butterfly arithmetic unit 14 with the first complex adder 132 and the second complex adder 133 according to the corresponding conduction mode of the first selection switch unit 12, and are used to perform radix-3 butterfly operations on the data to be operated.

[0077] Optionally, the radix-3 butterfly arithmetic unit 14 includes a second complex multiplier, a third complex multiplier, a complex adder group, a first complex adder, and a second complex adder. Among them, the second complex multiplier is the first complex multiplier 1311 in a radix-2 butterfly arithmetic unit, the third complex multiplier is the first complex multiplier 1311 in another radix-2 butterfly arithmetic unit, and the complex adder group includes the third complex adder 1312 and the complex subtractor 1313 of the two radix-2 butterfly arithmetic units.

[0078] However, in the structure of the above-mentioned reconfigurable butterfly arithmetic unit, in addition to the first complex adder 132 and the second complex adder 133 required by the structure of the radix-3 butterfly arithmetic unit itself, it is also necessary to use the first complex multiplier 1311, the third complex adder 1312, and the complex subtractor 1313 in the two radix-2 butterfly arithmetic units 131, resulting in a complex overall structure of the reconfigurable butterfly arithmetic unit and a large consumption of hardware resources for the reconfigurable butterfly arithmetic unit to perform one radix-2 butterfly operation or radix-3 butterfly operation.

[0079] Therefore, in view of the above technical problems in the prior art, the inventors found in the research process that the reason why the reconfigurable butterfly arithmetic unit in the above related art is complex is that the radix-2 butterfly arithmetic unit and the radix-3 butterfly arithmetic unit have their respective corresponding structures. Therefore, the inventors found that if the same structure can be used as a radix-2 butterfly arithmetic unit for radix-2 butterfly arithmetic and also as a radix-3 butterfly arithmetic unit for radix-3 butterfly arithmetic, the complexity of the overall structure of the reconfigurable butterfly arithmetic unit can be greatly simplified, thereby reducing the hardware resource consumption for performing one butterfly arithmetic. Based on this, the inventors improved the reconfigurable butterfly arithmetic unit, that is, the butterfly calculation unit in this application. Specifically, the butterfly calculation unit includes: a first-in first-out (FIFO) buffer unit, a butterfly calculation module, a multiplier module, a rotation factor storage module, a first external interface, and a second external interface. The connection relationships of the above components are as follows: the FIFO buffer unit is respectively connected to the butterfly calculation module, the multiplier module, the first external interface, and the second external interface; the butterfly calculation module is connected to the multiplier module; the multiplier module is connected to the rotation factor storage module and the second external interface. Among them, the first external interface is used to input data in the radix-2 or radix-3 frequency-domain decimation fast Fourier transform (FFT) mode, and the data in the radix-2 and radix-3 frequency-domain decimation FFT modes both include multiple groups of data. The FIFO buffer unit is used to cache at least one group of data, or the butterfly calculation result data output by the butterfly calculation module, or the multiplication calculation result data output by the multiplier module. The butterfly calculation module is used to receive the data output by the FIFO buffer unit and perform butterfly calculation on the data output by the FIFO buffer unit to obtain butterfly calculation result data. The multiplier module is used to obtain a rotation factor from the rotation factor storage module and perform multiplication calculation on the butterfly calculation result data output by the FIFO buffer unit or the butterfly calculation result data output by the butterfly calculation module according to the rotation factor to obtain multiplication calculation result data. The second external interface is used to send out the multiplication calculation result data. Therefore, this application proposes a butterfly calculation unit, a butterfly calculation unit array, a reconfigurable array, and a chip.

[0080] The following uses specific embodiments to elaborate in detail on the technical solution of this application and how the technical solution of this application solves the above technical problems. The following several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0081] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of a butterfly calculation unit provided by an embodiment of this application. The butterfly calculation unit (PE) includes: a first-in first-out (FIFO) buffer unit 21, a butterfly calculation module 22, a multiplier module 23, a rotation factor storage module 24, a first external interface 25, and a second external interface 26.

[0082] The connection relationship can be as follows:

[0083] The first-in first-out buffer unit 21 is respectively connected to the butterfly calculation module 22, the multiplier module 23, the first external interface 25, and the second external interface 26. The butterfly calculation module 22 is connected to the multiplier module 23, and the multiplier module 23 is connected to the rotation factor storage module 24 and the second external interface 26.

[0084] The functions of each structure can be as follows:

[0085] The first external interface 25 is used to input data in the radix-2 or radix-3 frequency-domain decimation fast Fourier transform mode. The data in the radix-2 and radix-3 frequency-domain decimation fast Fourier transform modes both include multiple groups of data.

[0086] Optionally, in this embodiment, the first external interface 25 can be the data output port of the previous butterfly calculation unit. The data output by the previous butterfly calculation unit is input to the current butterfly calculation unit participating in the calculation through the first external interface 25.

[0087] Optionally, the data output by the previous butterfly calculation unit can be data in the radix-2 frequency-domain decimation fast Fourier transform mode, i.e., radix-2 DIF-FFT, or data in the radix-3 frequency-domain decimation fast Fourier transform mode, i.e., radix-3 DIF-FFT. The data in the radix-2 or radix-3 frequency-domain decimation fast Fourier transform mode can both include multiple groups of data.

[0088] The first-in first-out buffer unit 21 is used to cache at least one group of data, or the butterfly calculation result data output by the butterfly calculation module 22, or the multiplication calculation result data output by the multiplier module 23.

[0089] Optionally, in this embodiment, the first-in first-out buffer unit 21 can include three first-in first-out buffer modules. Since the data sources received by each first-in first-out buffer module can be at least one group of data input through the first external interface 25, or the butterfly calculation result data output by the butterfly calculation module 22, or the multiplication calculation result data output by the multiplier module 23. Therefore, the first-in first-out buffer unit 21 can cache the above different data.

[0090] The butterfly calculation module 22 is used to receive the data output by the first-in first-out buffer unit 21 and perform butterfly calculation on the data output by the first-in first-out buffer unit 21 to obtain butterfly calculation result data.

[0091] In the FFT algorithm, the butterfly calculation module 22 is an important component, which can decompose the calculation process of the Fourier transform, thereby reducing the calculation amount.

[0092] Optionally, the butterfly calculation module 22 may include two adders and two subtractors. Among them, the adder is used to perform complex addition calculations on the data output by the first-in first-out buffer unit 21, and the subtractor is used to perform complex subtraction calculations on the data output by the first-in first-out buffer unit 21. By performing addition and subtraction calculations, the butterfly calculation of the data input to the butterfly calculation module 22 is completed, thereby obtaining the butterfly calculation result data after the butterfly calculation.

[0093] Optionally, the butterfly calculation module 22 may also be connected to the first external interface 25.

[0094] Optionally, the butterfly calculation module 22 may also be used to receive a set of data sent by the first external interface 25 and perform a butterfly calculation on the set of data.

[0095] The multiplier module 23 is used to obtain a rotation factor from the rotation factor storage module 24 and perform a multiplication calculation on the butterfly calculation result data output by the first-in first-out buffer unit 21 or the butterfly calculation result data output by the butterfly calculation module 22 according to the rotation factor, so as to obtain the multiplication calculation result data.

[0096] Optionally, the multiplier module 23 may include four multipliers, an adder, and a subtractor. The four multipliers obtain the rotation factor from the rotation factor storage module 24, perform multiplication calculations on the data input to the multiplier module 23 according to the rotation factor, and then perform addition or subtraction calculations respectively, and finally obtain the multiplication calculation result data.

[0097] In this embodiment, the rotation factor storage module 24 stores a plurality of rotation factors, and the number of stored rotation factors is not limited in this embodiment.

[0098] The second external interface 26 is used to send out the multiplication calculation result data.

[0099] Optionally, the multiplication calculation result data is sent to the next butterfly calculation unit through the second external interface 26.

[0100] In the above embodiments of the present application, the butterfly calculation unit includes: a first-in first-out (FIFO) buffer unit 21, a butterfly calculation module 22, a multiplier module 23, a rotation factor storage module 24, a first external interface 25, and a second external interface 26. The connection relationships of the above components are as follows: the FIFO buffer unit 21 is respectively connected to the butterfly calculation module 22, the multiplier module 23, the first external interface 25, and the second external interface 26; the butterfly calculation module 22 is connected to the multiplier module 23; the multiplier module 23 is connected to the rotation factor storage module 24 and the second external interface 26. Among them, the first external interface 25 is used to input data in the radix-2 or radix-3 frequency-domain decimation fast Fourier transform (FFT) mode, and the data in the radix-2 and radix-3 frequency-domain decimation FFT modes both include multiple groups of data. The FIFO buffer unit 21 is used to cache at least one group of data, or the butterfly calculation result data output by the butterfly calculation module 22, or the multiplication calculation result data output by the multiplier module 23. The butterfly calculation module 22 is used to receive the data output by the FIFO buffer unit 21 and perform butterfly calculation on the data output by the FIFO buffer unit 21 to obtain butterfly calculation result data. The multiplier module 23 is used to obtain a rotation factor from the rotation factor storage module 24 and perform multiplication calculation on the butterfly calculation result data output by the FIFO buffer unit 21 or the butterfly calculation result data output by the butterfly calculation module 22 according to the rotation factor to obtain multiplication calculation result data. The second external interface 26 is used to send out the multiplication calculation result data. In the butterfly calculation unit of this embodiment, through the same structure (the FIFO buffer unit 21, the butterfly calculation module 22, the multiplier module 23, the rotation factor storage module 24, the first external interface 25, and the second external interface 26), both radix-2 butterfly operations and radix-3 butterfly operations can be performed, which improves the reuse rate of each component, simplifies the structure of the butterfly calculation unit, and thus reduces the consumption of hardware resources for performing one radix-2 or radix-3 butterfly operation.

[0101] Further, on the basis of the above embodiments, the structural composition of the butterfly calculation unit in the present application is described in detail through the following embodiments. Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of another butterfly calculation unit provided by an embodiment of the present application.

[0102] Optionally, in this embodiment, the FIFO buffer unit 21 may include a first FIFO buffer module (FIFO_A) 211, a second FIFO buffer module (FIFO_B) 212, and a third FIFO buffer module (FIFO_C) 213.

[0103] The connection relationships of the first first-in-first-out (FIFO) cache module 211, the second FIFO cache module 212, and the third FIFO cache module 213 with the butterfly calculation module 22, the multiplier module 23, the first external interface 25, and the second external interface 26 in the butterfly calculation unit are as follows Figure 3 shown as

[0104] The input end of the first FIFO cache module 211 is respectively connected to the output end of the butterfly calculation module 22 and the input end of the first external interface 25, and the output end of the first FIFO cache module 211 is connected to the input end of the butterfly calculation module 22.

[0105] Optionally, the first FIFO cache module 211 can receive and cache the input data of the first external interface 25, and can also receive and cache the butterfly calculation result data output by the butterfly calculation module 22.

[0106] The input end of the second FIFO cache module 212 is respectively connected to the output end of the butterfly calculation module 22 and the input end of the first external interface 25, and the output end of the second FIFO cache module 212 is respectively connected to the input end of the butterfly calculation module 22 and the input end of the multiplier module 23.

[0107] Optionally, the second FIFO cache module 212 can receive and cache the input data of the first external interface 25, and can also receive and cache the butterfly calculation result data output by the butterfly calculation module 22.

[0108] The input end of the third FIFO cache module 213 is connected to the output end of the multiplier module 23, and the output end of the third FIFO cache module 213 is respectively connected to the input end of the butterfly calculation module 22 and the input end of the second external interface 26.

[0109] Optionally, the third FIFO cache module 213 can receive and cache the multiplication calculation result data output by the multiplier module 23.

[0110] Optionally, in this embodiment, the butterfly calculation module 22 includes: a first input interface (In0) 221, a first output interface (Out0) 222, a second input interface (In1) 223, and a second output interface (Out1) 224. The connection relationships of each interface with the first FIFO cache module 211, the second FIFO cache module 212, the third FIFO cache module 213, the multiplier module 23, the first external interface 25, and the second external interface 26 in the butterfly calculation unit are as follows Figure 3 shown as

[0111] The first input interface 221 is respectively connected to the output end of the first first-in-first-out buffer module 211, the output end of the second first-in-first-out buffer module 212, and the input end of the first external interface 25. The first output interface 222 is respectively connected to the input end of the first first-in-first-out buffer module 211 and the input end of the second external interface 26.

[0112] Optionally, in this embodiment, the data received or sent is generally complex. The first input interface 221 will simultaneously receive the real part (re) of the complex data and the imaginary part (im) of the complex data, and send the real part and the imaginary part to the adder or subtractor connected to the butterfly calculation module 22.

[0113] Correspondingly, the first output interface 222 will simultaneously output the real part (re) of the complex data and the imaginary part (im) of the complex data according to the connected adder.

[0114] The second input interface 223 is respectively connected to the output end of the first first-in-first-out buffer module 211, the output end of the second first-in-first-out buffer module 212, and the input end of the first external interface 25. The second output interface 224 is connected to the input end of the second first-in-first-out buffer module 212.

[0115] Optionally, the second input interface 223 will simultaneously receive the real part (re) of the complex data and the imaginary part (im) of the complex data, and send the real part and the imaginary part to the subtractor or adder connected to the butterfly calculation module 22.

[0116] Correspondingly, the second output interface 224 will simultaneously output the real part (re) of the complex data and the imaginary part (im) of the complex data according to the connected subtractor.

[0117] In the above embodiments of the present application, the first-in-first-out buffer unit includes a first first-in-first-out buffer module 211, a second first-in-first-out buffer module 212, and a third first-in-first-out buffer module 213. The butterfly calculation module 22 includes a first input interface 221, a first output interface 222, a second input interface 223, and a second output interface 224. Through the connection relationship in this embodiment, the data of the radix-two frequency-domain decimation fast Fourier transform mode and / or the data of the radix-three frequency-domain decimation fast Fourier transform mode all perform butterfly operations through the respective first-in-first-out buffer modules in the first-in-first-out buffer unit, the respective interfaces in the butterfly calculation module 22, and the multiplier module 23, further improving the reuse rate of each component, simplifying the structure of the butterfly calculation unit, and thus reducing the consumption of hardware resources for performing a single butterfly operation.

[0118] Next, on the basis of the above embodiments, the butterfly calculation unit will illustrate the specific functions of each component through the data flow flowing through each component.

[0119] Suppose there are N data points to be processed. Here, N represents the number of data, and N is an integer power of 2. The data to be processed is in the form of a radix-2 frequency-domain decimation fast Fourier transform (FFT) pattern. Suppose the current calculation stage of the butterfly calculation unit is m, where m is 1, 2, …, log 2 (N), and the specific value of m has been determined by the current butterfly calculation unit according to the pre-set configuration information. Only one set of butterfly operations and one set of multiplication operations need to be performed in one calculation stage. The N data points to be processed are divided into a total of 2 m groups with N / 2 m data points in each group, and are alternately input into FIFO_A and the second input interface 223 (In1) of the butterfly calculation module 22 in groups.

[0120] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a butterfly calculation unit for performing radix-2 butterfly operations on data in the form of a radix-2 frequency-domain decimation fast Fourier transform pattern provided by an embodiment of the present application. Optionally, the data output at the input end of the first external interface 25 includes at least a first group of data and a second group of data.

[0121] Among them, the first external interface 25 sends the first group of data to the first first-in-first-out (FIFO) buffer module 211, and sends the second group of data to the second input interface 223 of the butterfly calculation module 22.

[0122] After the first external interface 25 finishes sending the group data, the butterfly calculation module 22 receives the first group of data sent by the first FIFO buffer module 211, and performs a first butterfly calculation based on the first group of data and the second group of data to obtain a first butterfly calculation result data and a second butterfly calculation result data, and sends the first butterfly calculation result data to the second external interface 26 through the first output interface 222, and sends the second butterfly calculation result data to the second FIFO buffer module 212 through the second output interface 224.

[0123] When the butterfly calculation module 22 finishes the first butterfly calculation, the multiplier module 23 starts to work. The multiplier receives the second butterfly calculation result data sent by the second FIFO buffer module 212, reads the first rotation factor stored in the rotation factor storage module 24, and performs a complex multiplication calculation on the second butterfly calculation result data according to the first rotation factor to obtain a first multiplication calculation result data, and sends the first multiplication calculation result data to the third FIFO buffer module 213, so that the first multiplication calculation result data is sent to the second external interface 26 through the third FIFO buffer module 213, so that the first multiplication calculation result data enters the next butterfly calculation unit through the second external interface 26 for the next stage of calculation until all groups of data are calculated.

[0124] In the above embodiments of the present application, for the data in the radix-2 frequency-domain decimation fast Fourier transform mode, the radix-2 butterfly operation is completed through the structure of the butterfly calculation unit in the present application. The radix-2 butterfly operation is performed by a simpler butterfly calculation unit, reducing the time for performing the radix-2 butterfly operation and improving the operation efficiency.

[0125] Further, when the data to be processed is in the radix-3 frequency-domain decimation fast Fourier transform mode, the specific functions of the components in the butterfly calculation unit are described.

[0126] Suppose there are N points of data to be processed, where N represents the number of data, and N is an integer power of 2. The data to be processed is in the radix-3 frequency-domain decimation fast Fourier transform mode. Suppose the current calculation stage of the butterfly calculation unit is m, where m is 1, 2, …, log 2 (N), and the specific value of m has been determined by the current butterfly calculation unit according to the pre-set configuration information. One calculation stage needs to perform three groups of butterfly operations and three groups of multiplication operations. One of the three groups of multiplication operations includes a constant multiplication calculation. The N points of data to be processed are divided into a total of 3 m groups with N / 3 m data in each group. Taking the input of 3 groups of data as an input cycle, the 3 groups of data are respectively input to the second input interface 223 (In1) of the FIFO_B, FIFO_A, and the butterfly calculation module 22 within one input cycle.

[0127] Please refer to Figure 5A , Figure 5A which is a schematic diagram of the structure of the butterfly calculation unit for performing the first group of butterfly operations on the data in the radix-3 frequency-domain decimation fast Fourier transform mode provided by the embodiment of the present application. Optionally, the data output from the input end of the first external interface 25 includes at least the third group of data, the fourth group of data, and the fifth group of data.

[0128] Among them, the first external interface 25 sends the third group of data to the second first-in-first-out cache module 212, sends the fourth group of data to the first first-in-first-out cache module 211, and sends the fifth group of data to the second input interface 223 of the butterfly calculation module 22.

[0129] The butterfly calculation module 22 receives the fourth group of data sent by the first first-in-first-out cache module 211, and performs the second butterfly calculation according to the fourth group of data and the fifth group of data to obtain the third butterfly calculation result data and the fourth butterfly calculation result data. The third butterfly calculation result data is sent to the first first-in-first-out cache module 211 through the first output interface 222, and the fourth butterfly calculation result data is sent to the second first-in-first-out cache module 212 through the second output interface 224.

[0130] The multiplier module 23 receives the fourth butterfly calculation result data sent by the second first-in-first-out buffer module 212, reads the second rotation factor stored in the rotation factor storage module 24, performs a constant multiplication calculation on the fourth butterfly calculation result data and the second rotation factor to obtain the second multiplication calculation result data, and sends the second multiplication calculation result data to the third first-in-first-out buffer module 213. The second rotation factor is a constant, and the constant can be 。

[0131] Please refer to Figure 5B , Figure 5B which is a schematic structural diagram of a butterfly calculation unit for performing a second group of butterfly operations on the data in the base-three frequency-domain decimation fast Fourier transform mode provided by an embodiment of the present application.

[0132] Among them, the butterfly calculation module 22 receives the third butterfly calculation result data sent by the first first-in-first-out buffer module 211 and the third group of data sent by the second first-in-first-out buffer module 212.

[0133] Performs a third butterfly calculation based on the third butterfly calculation result data and the third group of data to obtain a fifth butterfly calculation result data and a sixth butterfly calculation result data.

[0134] Sends the fifth butterfly calculation result data to the second external interface 26 through the first output interface 222, and sends the sixth butterfly calculation result data to the second first-in-first-out buffer module 212 through the second output interface 224.

[0135] Please refer to Figure 5C , Figure 5C which is a schematic structural diagram of a butterfly calculation unit for performing a third group of butterfly operations on the data in the base-three frequency-domain decimation fast Fourier transform mode provided by an embodiment of the present application. When the second group of butterfly operations is completed, the butterfly calculation module 22 starts to perform the third group of butterfly operations. The butterfly calculation module 22 receives the sixth butterfly calculation result data sent by the second first-in-first-out buffer module 212 and the second multiplication calculation result data sent by the third first-in-first-out buffer module 213.

[0136] Performs a fourth butterfly calculation based on the sixth butterfly calculation result data and the second multiplication calculation result data to obtain a seventh butterfly calculation result data and an eighth butterfly calculation result data.

[0137] Sends the seventh butterfly calculation result data to the multiplier module 23 through the first output interface 222, and sends the eighth butterfly calculation result data to the second first-in-first-out buffer module 212 through the second output interface 224.

[0138] The multiplier module 23 receives the seventh butterfly calculation result data sent by the butterfly calculation module 22, reads the third rotation factor stored in the rotation factor storage module 24, performs a complex multiplication calculation on the seventh butterfly calculation result data according to the third rotation factor to obtain the third multiplication calculation result data, and sends the third multiplication calculation result data to the third first-in-first-out buffer module 213, so that the third multiplication calculation result data is sent to the second external interface 26 through the third first-in-first-out buffer module 213.

[0139] Specifically, the multiplier module 23 is further configured to: receive the eighth butterfly calculation result data sent by the second first-in-first-out buffer module 212, read the fourth rotation factor stored in the rotation factor storage module 24, perform a complex multiplication calculation on the eighth butterfly calculation result data according to the fourth rotation factor to obtain the fourth multiplication calculation result data, and send the fourth multiplication calculation result data to the third first-in-first-out buffer module 213, so that the fourth multiplication calculation result data is sent to the second external interface 26 through the third first-in-first-out buffer module 213.

[0140] In summary, the calculation of three groups of data in one input cycle is completed, and the calculation of three groups of data in the next cycle is entered until all data is completed.

[0141] In this embodiment, the structure for performing the radix-3 butterfly operation in the related art is as Figure 6A shown. Figure 6A FIG. is a schematic diagram of a radix-3 butterfly operation structure in the related art provided by the present application. The radix-3 butterfly operation structure in the related art is complex. For three groups of data ( , , ), a complex radix-3 butterfly operation needs to be performed. In this embodiment, as Figure 6B shown, Figure 6B FIG. is a schematic diagram of a radix-3 butterfly operation structure provided by an embodiment of the present application. For three groups of data ( or or ), by dividing it into 3 structures similar to the radix-2 butterfly operation and performing three radix-2 mode butterfly calculations, the calculation result can be obtained.

[0142] In the above embodiment of the present application, the data in the radix-3 frequency domain decimation fast Fourier transform mode is subjected to three butterfly operations through the structure of the butterfly calculation unit in the present application. Among them, each butterfly operation is similar to the butterfly operation of the data in the radix-2 frequency domain decimation fast Fourier transform mode. Thus, the radix-3 butterfly operation can be performed through the same structure, improving the reuse rate of each component, simplifying the structure of the butterfly calculation unit, and thus reducing the consumption of hardware resources for performing the radix-3 butterfly operation.

[0143] The present application also provides a butterfly computing unit array, as Figure 7 shown, Figure 7 which is a schematic structural diagram of a butterfly computing unit array provided by an embodiment of the present application. The butterfly computing unit array includes a plurality of butterfly computing units, and the plurality of butterfly computing units are serially connected. Serial connection can also be referred to as pipeline structure connection in the present application.

[0144] It can be understood that the number of butterfly computing units is not limited in this embodiment.

[0145] In the above embodiment of the present application, by performing radix-2 or radix-3 butterfly operations through a plurality of serially connected butterfly computing units in the butterfly computing unit array, the efficiency of radix-2 or radix-3 butterfly operations can be effectively improved, thereby reducing the calculation period.

[0146] The present application also provides a mixed-radix reconfigurable array, which can also be referred to as a coarse-grained reconfigurable array of mixed-radix FFT, and includes the butterfly computing unit array in the above embodiment.

[0147] To facilitate the understanding of the mixed-radix reconfigurable array in the present application, the mixed-radix reconfigurable array in the related art will be described below. The mixed-radix reconfigurable array in the related art is called a mixed-radix FFT processor.

[0148] As Figure 8 shown, Figure 8 which is a schematic structural diagram of another mixed-radix FFT processor in the related art provided by the present application. The mixed-radix FFT processor includes a storage unit 81, a control unit 82, a block floating-point unit 83, and an arithmetic unit 84.

[0149] Among them, the arithmetic unit 84 is equivalent to the butterfly computing unit in the present application. The arithmetic unit 84 includes a multiplication unit 841 and a butterfly unit 842. The data parallelism of the arithmetic unit 84 is 16, and it can perform at most one radix-16 butterfly operation, or two radix-8 butterfly operations, or two radix-5 butterfly operations, or four radix-4 butterfly operations, or four radix-3 butterfly operations, or eight radix-2 butterfly operations simultaneously.

[0150] The connection relationship is as follows: The storage unit 81 is respectively connected to the arithmetic unit 84 and the control unit 82. The control unit 82 is also connected to the arithmetic unit 84. The block floating-point unit 83 is connected to the arithmetic unit 84. The multiplication unit 841 is connected to the butterfly unit 842.

[0151] The multiplication unit 841 includes fifteen rotation factor multipliers. The butterfly unit 842 includes six interleaving modules and a five-stage operation unit. Among them, the six interleaving modules are the first interleaving module, the second interleaving module, the third interleaving module, the fourth interleaving module, the fifth interleaving module, and the sixth interleaving module. The five-stage operation unit is the first-stage operation unit, the second-stage operation unit, the third-stage operation unit, the fourth-stage operation unit, and the fifth-stage operation unit. The first-stage operation unit consists of 8 parallel radix-2 butterfly units. The second-stage operation unit consists of 4 parallel radix-2 butterfly units, 4 variable butterfly units, and 4 simple multipliers. The third-stage operation unit includes parallel simple multipliers, multiple complex multipliers, and 2 complex adders. The fourth-stage operation unit consists of 8 parallel radix-2 butterfly units. The fifth-stage operation unit consists of 8 parallel radix-2 butterfly units and 4 simple multipliers.

[0152] It can be seen that for the operation units in the above-mentioned mixed-radix FFT processor, although the parallelism of data processing can be improved by increasing the interleaving modules included in the butterfly units in the operation units and the operation units at all levels, it will lead to an increase in the complexity of the overall structure of the mixed-radix FFT processor, a relatively low reuse rate of each component, and still a large consumption of hardware resources.

[0153] Therefore, for the complex structure of the above-mentioned mixed-radix FFT processor, the mixed-radix reconfigurable array provided in this application has a simpler structure.

[0154] For details, please refer to Figure 9 , Figure 9 which is a schematic structural diagram of a mixed-radix reconfigurable array provided in an embodiment of this application. In addition to including a butterfly calculation unit array, it further includes a memory 91, an input controller 92, an output controller 93, and a timing controller 94.

[0155] The connection relationship can be:

[0156] The memory 91 is respectively connected to the input end of the input controller 92, the input end of the output controller 93, and the input end of the timing controller 94. The output end of the input controller 92, the input end of the output controller 93, and the output end of the timing controller 94 are respectively connected to the butterfly calculation unit array.

[0157] Optionally, the output end of the input controller 92, the input end of the output controller 93, and the output end of the timing controller 94 are specifically respectively connected to multiple butterfly calculation units in the butterfly calculation unit array. Figure 9 In order to make the attached drawings clearly visible and not show the connection situation of all butterfly calculation units with the input controller 92, the output controller 93, and the timing controller 94, Figure 9 the connections shown in do not limit this application.

[0158] The functions of each component are as follows:

[0159] Optionally, the memory 91 is used to store configuration information. The configuration information may include the data to be computed and the computation mode of the data to be computed. The computation mode includes the radix-2 frequency-domain decimation fast Fourier transform mode or the radix-3 frequency-domain decimation fast Fourier transform mode.

[0160] Optionally, after the configuration information is loaded into the timing controller 94, the timing controller 94 can determine the timing logic of each butterfly computing unit in the butterfly computing unit array according to the configuration information.

[0161] Exemplarily, the timing controller 94 can determine the butterfly computing units required for performing butterfly operations in the butterfly computing unit array, and the timing relationship between each butterfly computing unit.

[0162] Optionally, after the configuration information is loaded into the input controller 92, the input controller 92 can group the data to be computed according to the computation mode to obtain multiple groups of data.

[0163] Exemplarily, if the computation mode is the radix-2 frequency-domain decimation fast Fourier transform mode, the data to be computed is decomposed into a power of 2 in length to obtain multiple groups of grouped data.

[0164] Exemplarily, if the computation mode is the radix-3 frequency-domain decimation fast Fourier transform mode, the data to be computed is decomposed into a power of 3 in length to obtain multiple groups of grouped data.

[0165] Optionally, after the configuration information is loaded into the output controller 93, the output controller 93 can determine the butterfly computing unit at the end point of the final output result data and receive the output result data of the butterfly computing unit for the data to be computed.

[0166] The mixed-radix reconfigurable array in this embodiment can compute -point fast Fourier transform, where the number of points needs to satisfy the following formula:

[0167]

[0168] where and can take values of 0, 1,..., q, less than or equal to , , and are exponents and their values are integers.

[0169] Taking 256 data points to be processed as an example, the configuration information is first imported into the timing controller 94, the input controller 92, the butterfly calculation unit array, and the output controller 93. Figure 9 The first two rows of butterfly calculation units in the butterfly calculation unit array in Figure 9 are configured as circuits for performing 256-point radix-2 DIF-FFT. These eight butterfly calculation units successively complete eight calculation stages, and the last row of butterfly calculation units is idle. The input controller 92 first serially inputs the data to be processed into the butterfly calculation unit in the first row and first column. The timing controller 94 generates timing signals to control the calculation process of the butterfly calculation units. Finally, the output controller 93 receives the output result data obtained from the butterfly calculation unit in the second row and fourth column.

[0170] In the above embodiments of the present application, the mixed-radix reconfigurable array includes a butterfly calculation unit array, a memory 91, an input controller 92, an output controller 93, and a timing controller 94. Compared with the mixed-radix FFT processor in the related art, the mixed-radix reconfigurable array in the present application has a simpler structure, improves the reuse rate of each component, and thus reduces the hardware resource consumption.

[0171] In the present application, a chip is also provided. The chip includes the mixed-radix reconfigurable array in the above embodiments to perform FFT calculations on data. The technical effects achieved are similar to those in the above embodiments, and for the sake of avoiding redundancy, no further description will be repeated.

[0172] In the present application, the data calculated by the butterfly calculation unit in the chip of the present application is also verified by simulation.

[0173] In the present application, the butterfly calculation unit is described in Verilog language. One butterfly calculation unit serves as one stage (calculation stage) in the FFT calculation. By verifying on a preset platform, the resource usage situation as shown in Table 1 is obtained.

[0174] Table 1

[0175]

[0176] Exemplarily, taking 288 data points as an example for the data to be processed, when performing the FFT calculation task of 288 data points, a total of 7 levels of calculation are required. Decompose 288 into , that is, the first two levels are implemented through radix-3 butterfly operations, and the last 5 levels are implemented through radix-2 butterfly operations.

[0177] By simulating the 288-point fast Fourier transform in a preset circuit drawing software, the calculation result is obtained as shown in Figure 10 shown, Figure 10A schematic diagram of calculation results provided by an embodiment of the present application. Here, the abscissa X represents frequency, and the ordinate Y represents amplitude. When X is 7, Y is 130.061; when X is 283, Y is 130.086.

[0178] By performing simulation calculations for 288-point fast Fourier transform in a preset data analysis software, the calculation results are as Figure 11 shown. Figure 11 Another schematic diagram of calculation results provided by an embodiment of the present application. Here, the abscissa X represents frequency, and the ordinate Y represents amplitude. When X is 7, Y is 130.598; when X is 283, Y is 130.598.

[0179] Comparing Figure 10 and Figure 11 it can be seen that the difference between the peak values of the results obtained by simulation calculations in the preset circuit drawing software and the results calculated by the preset data analysis software is within the preset error threshold range, meeting the index requirements of FFT calculations.

[0180] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps including the above method embodiments; and the foregoing storage medium includes: various media such as ROM, RAM, magnetic disks, or optical disks that can store program codes.

[0181] Finally, it should be noted that: After considering the specification and practicing the invention disclosed herein, those skilled in the art will easily think of other implementation schemes of the present invention. The present invention aims to cover any variations, uses, or adaptive changes of the present invention. These variations, uses, or adaptive changes follow the general principles of the present invention and include common general knowledge or conventional technical means in the technical field not disclosed in the present invention. It is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A butterfly computing unit, characterized in that: include: A first-in-first-out cache unit, a butterfly calculation module, a multiplier module, a rotation factor storage module, a first external interface and a second external interface; wherein the first-in-first-out cache unit includes a first first-in-first-out cache module, a second first-in-first-out cache module and a third first-in-first-out cache module, and the butterfly calculation module includes a first input interface, a first output interface, a second input interface and a second output interface; The first-in-first-out cache unit is connected to the butterfly calculation module, the multiplier module, the first external interface and the second external interface respectively, the butterfly calculation module is connected to the multiplier module, and the multiplier module is connected to the rotation factor storage module and the second external interface; A first external interface is used to input data in a radix-2 or radix-3 frequency domain extraction fast Fourier transform mode, wherein the data in the radix-2 and radix-3 frequency domain extraction fast Fourier transform mode both include multiple groups of data; The first-in-first-out cache unit is used to cache at least one set of data or the butterfly calculation result data output by the butterfly calculation module or the multiplication calculation result data output by the multiplier module; The butterfly calculation module is used to receive the data output by the first-in first-out cache unit, and perform butterfly calculation on the data output by the first-in first-out cache unit to obtain butterfly calculation result data; The multiplier module is used to obtain the rotation factor from the rotation factor storage module, and perform multiplication calculation on the butterfly calculation result data output by the first-in first-out cache unit or the butterfly calculation result data output by the butterfly calculation module according to the rotation factor to obtain the multiplication calculation result data; The second external interface is used to send out the multiplication result data.

2. The butterfly computing unit according to claim 1, characterized in that: The first FIFO cache module input end is respectively connected to the butterfly computing module output end and the first external interface input end, and the first FIFO cache module output end is connected to the butterfly computing module input end; The second FIFO buffer module input end is respectively connected to the butterfly calculation module output end and the first external interface input end, and the second FIFO buffer module output end is respectively connected to the butterfly calculation module input end and the multiplier module input end; The input end of the third FIFO buffer module is connected to the output end of the multiplier module, and the output end of the third FIFO buffer module is respectively connected to the input end of the butterfly calculation module and the input end of the second external interface.

3. The butterfly computing unit according to claim 2, characterized in that: The first input interface is respectively connected to the first FIFO buffer module output end, the second FIFO buffer module output end and the first external interface input end, and the first output interface is respectively connected to the first FIFO buffer module input end and the second external interface input end; The second input interface is connected to the output end of the first FIFO buffer module, the output end of the second FIFO buffer module and the input end of the first external interface respectively, and the second output interface is connected to the input end of the second FIFO buffer module.

4. The butterfly computing unit according to claim 3, characterized in that: The output data of the first external interface input terminal at least includes a first group of data and a second group of data, wherein the first group of data and the second group of data are data in a base-2 frequency domain decimation fast Fourier transform mode; The first external interface is specifically used to: send the first set of data to the first first-in first-out cache module, and send the second set of data to the second input interface of the butterfly calculation module; The butterfly calculation module is specifically used to: receive the first group of data sent by the first first-in-first-out cache module, and perform a first butterfly calculation according to the first group of data and the second group of data to obtain first butterfly calculation result data and second butterfly calculation result data, and send the first butterfly calculation result data to the second external interface through the first output interface, and send the second butterfly calculation result data to the second first-in-first-out cache module through the second output interface; The multiplier module is specifically used to: receive the second butterfly calculation result data sent by the second first-in-first-out cache module, read the first rotation factor stored in the rotation factor storage module, and perform complex multiplication calculation on the second butterfly calculation result data according to the first rotation factor to obtain first multiplication calculation result data, and send the first multiplication calculation result data to the third first-in-first-out cache module, so that the first multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

5. The butterfly computing unit according to claim 3, characterized in that: The output data of the first external interface input terminal at least includes a third group of data, a fourth group of data and a fifth group of data, wherein the third group of data, the fourth group of data and the fifth group of data are data in a base-three frequency domain decimation fast Fourier transform mode; The first external interface is specifically used to: send the third group of data to the second first-in first-out cache module, send the fourth group of data to the first first-in first-out cache module, and send the fifth group of data to the second input interface of the butterfly calculation module; The butterfly calculation module is specifically used to: receive the fourth group of data sent by the first first-in-first-out cache module, and perform a second butterfly calculation according to the fourth group of data and the fifth group of data to obtain third butterfly calculation result data and fourth butterfly calculation result data, and send the third butterfly calculation result data to the first first-in-first-out cache module through the first output interface, and send the fourth butterfly calculation result data to the second first-in-first-out cache module through the second output interface; The multiplier module is specifically used to: receive the fourth butterfly calculation result data sent by the second first-in-first-out cache module, read the second rotation factor stored in the rotation factor storage module, perform constant multiplication calculation on the fourth butterfly calculation result data and the second rotation factor to obtain second multiplication calculation result data, and send the second multiplication calculation result data to the third first-in-first-out cache module.

6. The butterfly computing unit according to claim 5, characterized in that: The butterfly computing module is also specifically used for: receiving the third butterfly calculation result data sent by the first first-in-first-out buffer module, and receiving the third set of data sent by the second first-in-first-out buffer module; Perform a third butterfly calculation according to the third butterfly calculation result data and the third group of data to obtain fifth butterfly calculation result data and sixth butterfly calculation result data; The fifth butterfly calculation result data is sent to the second external interface through the first output interface, and the sixth butterfly calculation result data is sent to the second first-in-first-out cache module through the second output interface.

7. The butterfly computing unit according to claim 6, characterized in that: The butterfly computing module is also specifically used for: receiving the sixth butterfly calculation result data sent by the second FIFO buffer module, and receiving the second multiplication calculation result data sent by the third FIFO buffer module; Performing a fourth butterfly calculation according to the sixth butterfly calculation result data and the second multiplication calculation result data to obtain seventh butterfly calculation result data and eighth butterfly calculation result data; The seventh butterfly calculation result data is sent to the multiplier module through the first output interface, and the eighth butterfly calculation result data is sent to the second first-in-first-out cache module through the second output interface.

8. The butterfly computing unit according to claim 7, characterized in that: The multiplier module is further specifically used for: Receiving the seventh butterfly calculation result data sent by the butterfly calculation module; Read the third rotation factor stored in the rotation factor storage module, perform complex multiplication calculation on the seventh butterfly calculation result data according to the third rotation factor to obtain third multiplication calculation result data, and send the third multiplication calculation result data to the third first-in-first-out cache module, so that the third multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

9. The butterfly computing unit according to claim 8, characterized in that: The multiplier module is further specifically used for: receiving the eighth butterfly calculation result data sent by the second first-in-first-out cache module; Read the fourth rotation factor stored in the rotation factor storage module, perform complex multiplication calculation on the eighth butterfly calculation result data according to the fourth rotation factor to obtain fourth multiplication calculation result data, and send the fourth multiplication calculation result data to the third first-in-first-out cache module, so that the fourth multiplication calculation result data is sent to the second external interface through the third first-in-first-out cache module.

10. A butterfly computing unit array, characterized in that: It comprises a plurality of butterfly computing units as described in any one of claims 1 to 9, wherein the plurality of butterfly computing units are connected in series.

11. A hybrid-based reconfigurable array, characterized in that: Comprising the butterfly computing unit array as claimed in claim 10.

12. The hybrid-based reconfigurable array according to claim 11, characterized in that: Also includes: Memory, input controller, output controller and timing controller; The memory is connected to the input controller input terminal, the output controller input terminal and the timing controller input terminal respectively, and the input controller output terminal, the output controller input terminal and the timing controller output terminal are connected to the butterfly computing unit array respectively; The memory is used to store configuration information, the configuration information includes data to be operated and an operation mode of the data to be operated, the operation mode includes a base-2 frequency domain extraction fast Fourier transform mode or a base-3 frequency domain extraction fast Fourier transform mode; The timing controller is used to determine the timing logic of each butterfly computing unit in the butterfly computing unit array according to the configuration information; The input controller is used to group the data to be operated according to the operation mode to obtain multiple groups of data; The output controller is used to receive output result data of the butterfly computing unit array on the data to be calculated.

13. The hybrid-based reconfigurable array according to claim 12, characterized in that: The input controller output terminal, the output controller input terminal and the timing controller output terminal are respectively connected to a plurality of the butterfly computing units in the butterfly computing unit array.

14. A chip, characterized in that: Comprising a hybrid-based reconfigurable array as described in any one of claims 11-13.

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