A logic online upgrading method and system based on UART-to-JTAG logic core

Abstract

The application provides a logic online upgrading method and system based on a UATR to JTAG logic core, relates to the technical field of embedded computer application, and the method comprises the following steps: a processor acquires data needing to be upgraded through an external network; the acquired data needing to be upgraded is transmitted to a UART to JTAG core through a serial port; the UART to JTAG core realizes protocol conversion from UART data to JTAG, and realizes online upgrading of logic by simulating a JTAG protocol. The method optimizes the upgrading mode of an FPGA in a product, and reduces the labor cost and time cost of product maintenance.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded computer applications, and in particular provides a logic online upgrade method and system based on a UART-to-JTAG logic core. Background Art

[0002] UART (Universal Asynchronous Receiver / Transmitter) is a serial communication protocol used to transfer data between external or internal computer resources. UART uses two signals for communication: one for transmitting data (TX) and the other for receiving data (RX).

[0003] JTAG (Joint Test Action Group) is an international standard test protocol primarily used for internal chip testing and system simulation and debugging. The JTAG interface typically includes several key signal lines: test clock input (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO).

[0004] Programmable logic is essential software for embedded computer products, providing specific logic functions. For computer circuit design, it can reduce development cycles, provide high flexibility and reusability, high performance, and cost-effectiveness, offering powerful support and solutions for a variety of application scenarios.

[0005] However, the solidification of programmable logic relies on a complex development environment and expensive debugging equipment. Taking the JYXSIP25-256 programmable logic chip as an example, it supports standard debugging interfaces (such as Figure 3 ). The debugging environment is attached. Figure 2 The debugger includes an industrial computer with the Xilinx software environment and a Xilinx emulator. During JYXSIP25-256 debugging, users connect the debug host to the product's programmable logic chip through the emulator. Only after the programmable logic chip is connected can the programmable logic program be solidified.

[0006] This process faces two main problems. First, it relies on Xilinx simulators and proprietary debugging environments. Second, if the programmable logic of delivered batch products needs to be updated and maintained, a large amount of human resources will be required. Summary of the Invention

[0007] The purpose of this application is to address the problems existing in the prior art and provide a logic online upgrade method based on UART to JTAG logic core.

[0008] To achieve the above object, the present invention adopts the following technical solution: a logic online upgrade method based on UART to JTAG logic core, the method comprising:

[0009] The processor obtains the data that needs to be updated through the external network;

[0010] Transfer the acquired data that needs to be upgraded to the UART-to-JTAG core via the serial port;

[0011] The UART to JTAG core converts UART data to JTAG protocol and simulates the JTAG protocol to implement online upgrade of logic.

[0012] The logic online upgrade method based on the UART-to-JTAG logic core provided by the present invention also has the following technical features: the UART-to-JTAG core implements the protocol conversion from UART data to JTAG, including:

[0013] Step 1: The core UART receives the communication serial port handshake request and forwards the information to the core ACK;

[0014] Step 2: The core ACK compares the handshake information. If they are consistent, it sends a confirmation reply to the core UART and enables the core FIFO. If they are inconsistent, it is ignored.

[0015] Step 3: The core UART sends the confirmation reply information to the communication serial port;

[0016] Step 4: The communication serial port receives the confirmation reply information and starts sending the upgrade information to the core UART;

[0017] Step 5: The core UART receives the upgrade information and sends it to the core FIFO for buffering;

[0018] Step 6: Perform a cache update every 32 bytes of data, and send the update information from the core FIFO to the core JTAG for update;

[0019] Step 7: The upgrade information is sent from the core FIFO to the core JTAG, the buffer area is cleared, and steps 5 to 7 are repeated until the data transfer is completed.

[0020] Another object of the present invention is to provide a logic online upgrade system based on a UART-to-JTAG logic core, the system being used to implement the method described in any one of claims 1-2, comprising: a processor communicating with an external network, an FPGA configured with a UART-to-JTAG logic core, and a communication module for implementing communication between the processor and the FPGA.

[0021] The logic online upgrade system provided by the present invention also has the following technical features: the UART to JTAG logic core includes a serial communication function sub-core UART, a serial handshake protocol sub-core ACK, a cache function sub-core FIFO and an interface protocol sub-core JTAG.

[0022] The logic online upgrade system provided by the present invention also has the following technical features: the interface protocol sub-core JTAG is used to implement switching of multiple states, thereby simulating JTAG protocol data including:

[0023] The platform sends the logic target code binary file that needs to be updated to the processor through the external network;

[0024] After the processor receives the logic target code file, it sends it to the FPGA chip through the serial port that communicates with the logic;

[0025] The UART-to-JTAG logic core running in the FPGA chip receives the target code and transmits the target code to its own JTAG interface in a manner that simulates the communication mode of the JTAG interface to complete the update of the logical target code.

[0026] The logic online upgrade system provided by the present invention also has the following technical features: the processor provides an external communication network and a communication serial port for the FPGA chip. During communication, the serial port driver baud rate is set to 115200, 1KB of data is sent, and a response is waited for by the logic U2J core. If there is no response within 60ms, it is judged as a timeout.

[0027] The logic online upgrade system provided by the present invention also has the following technical features: the FPGA connects its own JTAG interface to its own 3.3V IO BANK, and when not in the online upgrade state, the JTAG pin is set to a high-impedance state.

[0028] Beneficial effects

[0029] The logic online upgrade method based on UART to JTAG logic core provided by the present invention optimizes the upgrade mode of FPGA in the product and reduces the labor cost and time cost of product maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0031] Figure 1 A schematic diagram of a topology architecture provided by an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram for burning the logic target code during initial debugging;

[0033] Figure 3 This is a schematic diagram of the U2J logic core topology. DETAILED DESCRIPTION

[0034] The present application is further described in detail below with reference to the accompanying drawings and examples. However, it should be noted that these embodiments are not limitations of the present application, and any equivalent transformations or substitutions in functions, methods, or structures made by ordinary technicians in this field based on these embodiments are within the scope of protection of the present application.

[0035] In the description of the embodiments of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the creation of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the creation of the present application.

[0036] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of the features. In the description of the inventions of this application, unless otherwise specified, "plurality" means two or more.

[0037] The terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. A person of ordinary skill in the art will understand the specific meanings of these terms in the context of this application based on specific circumstances.

[0038] like Figure 1-3 As shown, an embodiment of the present application provides a logic online upgrade method based on a UART to JTAG logic core, the method comprising:

[0039] The processor obtains the data that needs to be updated through the external network;

[0040] Transfer the acquired data that needs to be upgraded to the UART-to-JTAG core via the serial port;

[0041] The UART to JTAG core converts UART data to JTAG protocol and simulates the JTAG protocol to implement online upgrade of logic.

[0042] In some embodiments, the UART to JTAG core implements the protocol conversion of UART data to JTAG, including:

[0043] Step 1: The core UART receives the communication serial port handshake request and forwards the information to the core ACK;

[0044] Step 2: The core ACK compares the handshake information. If they are consistent, it sends a confirmation reply to the core UART and enables the core FIFO. If they are inconsistent, it is ignored.

[0045] Step 3: The core UART sends the confirmation reply information to the communication serial port;

[0046] Step 4: The communication serial port receives the confirmation reply information and starts sending the upgrade information to the core UART;

[0047] Step 5: The core UART receives the upgrade information and sends it to the core FIFO for buffering;

[0048] Step 6: Perform a cache update every 32 bytes of data, and send the update information from the core FIFO to the core JTAG for update;

[0049] Step 7: The upgrade information is sent from the core FIFO to the core JTAG, the buffer area is cleared, and steps 5 to 7 are repeated until the data transfer is completed.

[0050] In some embodiments, a logic online upgrade system based on a UART-to-JTAG logic core is provided. The system is used to implement the method described in any one of claims 1-2, comprising: a processor that communicates with an external network, an FPGA configured with a UART-to-JTAG logic core, and a communication module for implementing communication between the processor and the FPGA.

[0051] In some embodiments, the UART-to-JTAG logic core includes a serial port communication function sub-core UART, a serial port handshake protocol sub-core ACK, a cache function sub-core FIFO, and an interface protocol sub-core JTAG.

[0052] In some embodiments, the interface protocol sub-core JTAG is used to implement switching of multiple states, thereby simulating JTAG protocol data including:

[0053] The platform sends the logic target code binary file that needs to be updated to the processor through the external network;

[0054] After the processor receives the logic target code file, it sends it to the FPGA chip through the serial port that communicates with the logic;

[0055] The UART-to-JTAG logic core running in the FPGA chip receives the target code and transmits the target code to its own JTAG interface in a manner that simulates the communication mode of the JTAG interface to complete the update of the logical target code.

[0056] In some embodiments, the processor provides an external communication network and a communication serial port for the FPGA chip. During communication, the serial port driver baud rate is set to 115200, 1KB of data is sent, and the logic U2J core waits for a response. If there is no response within 60ms, it is judged as a timeout.

[0057] In some embodiments, the FPGA connects its own JTAG interface to its own 3.3V IO BANK. When not in the online upgrade state, the JTAG pin is set to a high-impedance state.

[0058] In some embodiments, one FT-2000 / 4 processor, one JYXSIP25-256 programmable control logic chip, and Ethernet are used as the hardware design architecture of the external network.

[0059] During the initial debugging, the debugger needs to use the programmable logic debugging environment on the PC to connect to the emulator, and establish a communication link between the debugging environment and the FPGA chip through the emulator to realize the burning of the control logic target code.

[0060] After the product is delivered, the logical object code can be updated either through initial debugging or through online upgrade. The method provided in the above embodiment can provide a fast and stable online upgrade mechanism. The specific steps are as follows:

[0061] Step 1: The external platform sends the logic target code that needs to be updated to the FT2000 / 4 processor via Ethernet;

[0062] Step 2: After receiving the data, the FT2000 / 4 processor sends the data to JYXSIP25-256 through the communication serial port with JYXSIP25-256.

[0063] Step 3: After receiving the target code, the UART-to-JTAG logic core running in the JYXSIP25-256 chip transmits the target code to its own JTAG interface in a manner that simulates the communication mode of the JTAG interface, thus completing the update of the logic target code.

[0064] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application. The above description is merely a preferred embodiment of the present application. It should be noted that those skilled in the art can make various improvements and variations without departing from the technical principles of the present application, and such improvements and variations shall also be considered within the scope of protection of the present application.

Claims

1. A logic online upgrade method based on UART to JTAG logic core, characterized in that: The method comprises: The processor obtains the data that needs to be updated through the external network; Transfer the acquired data that needs to be upgraded to the UART-to-JTAG core via the serial port; The UART to JTAG core converts UART data to JTAG protocol and simulates the JTAG protocol to implement online upgrade of logic. The UART to JTAG core implements the protocol conversion from UART data to JTAG, including: Step 1: The core UART receives the communication serial port handshake request and forwards the information to the core ACK; Step 2: The core ACK compares the handshake information. If they are consistent, it sends a confirmation reply to the core UART and enables the core FIFO. If they are inconsistent, it is ignored. Step 3: The core UART sends the confirmation reply information to the communication serial port; Step 4: The communication serial port receives the confirmation reply information and starts sending the upgrade information to the core UART; Step 5: The core UART receives the upgrade information and sends it to the core FIFO for buffering; Step 6: Perform a cache update every 32 bytes of data, and send the update information from the core FIFO to the core JTAG for update; Step 7: The upgrade information is sent from the core FIFO to the core JTAG, the buffer area is cleared, and steps 5 to 7 are repeated until the data transfer is completed.

2. A logic online upgrade system based on UART to JTAG logic core, characterized in that: The system is used to implement the method according to claim 1, comprising: a processor communicating with an external network, an FPGA configured with a UART to JTAG logic core, and a communication module for implementing communication between the processor and the FPGA.

3. The logic online upgrade system according to claim 2, characterized in that: The UART to JTAG logic core comprises a serial port communication function sub-core UART, a serial port handshake protocol sub-core ACK, a cache function sub-core FIFO and an interface protocol sub-core JTAG.

4. The logic online upgrade system according to claim 3, characterized in that: The interface protocol sub-core JTAG is used to implement switching of multiple states, thereby simulating JTAG protocol data including: The platform sends the logic target code binary file that needs to be updated to the processor through the external network; After the processor receives the logic target code file, it sends it to the FPGA chip through the serial port that communicates with the logic; The UART-to-JTAG logic core running in the FPGA chip receives the target code and transmits the target code to its own JTAG interface in a manner that simulates the communication mode of the JTAG interface to complete the update of the logical target code.

5. The logic online upgrade system according to claim 2, characterized in that: The processor provides an external communication network and a communication serial port for the FPGA chip. During communication, the serial port driver baud rate is set to 115200, 1KB of data is sent, and the logic U2J core waits for a response. If there is no response within 60ms, it is judged as a timeout.

6. The logic online upgrade system according to claim 2, characterized in that: The FPGA connects its JTAG interface to its own 3.3V IO BANK. When not in online upgrade mode, the JTAG pin is set to high impedance.

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