Memory controller, memory system, and operating method

Abstract

An operating method of a memory controller that controls a memory device includes: passing a first read command corresponding to a first cell region of the memory device through a first channel; receiving first data read from the first cell region from the memory device through a second channel physically separated from the first channel; passing a state information request command through the first channel, the state information request command requesting to pass state information on a second cell region of the storage device; receiving state information on the second cell region from the storage device through the first channel; and transmitting a second read command corresponding to a second cell region of the storage device through the first channel, in which at least a part of a period in which the state information is received through the first channel overlaps a period in which the first data is received through the second channel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0137042 filed on October 13, 2023, and Korean Patent Application No. 10-2023-0180103 filed on December 12, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a memory controller, and more particularly, to a memory controller for transmitting memory state information, a memory system including the memory controller, and an operating method of the memory controller. Background Art

[0004] Flash memory, i.e., nonvolatile memory, can retain data stored therein even when power is cut off. Storage systems (or storage devices) such as solid-state drives (SSDs) and memory cards are widely used as storage systems including flash memory and can be used to store or move large amounts of data.

[0005] In a memory cell of a flash memory, a degradation phenomenon in which data reliability is reduced may occur due to various reasons, and for example, various factors such as voltage level shift, process characteristics, and interference with adjacent cells may cause degradation. A memory system may perform error detection / correction operations and recovery operations in order to ensure data reliability, but has a problem that a complicated process of recovery operation, which frequently enters a recovery operation mode or takes a long time, may reduce the performance of the memory system. Summary of the invention

[0006] The inventive concept provides a memory controller, a memory system including the memory controller, and an operating method of the memory controller, which can transfer status information between the memory controller and a memory device and thus can use the status information in an efficient memory operation.

[0007] According to some example embodiments, an operating method of a memory controller controlling a storage device includes: transmitting a first read command corresponding to a first unit area of ​​a storage device through a first channel; receiving first data read from the first unit area from the storage device through a second channel physically separated from the first channel; transmitting a status information request command through the first channel, the status information request command requesting status information about a second unit area of ​​the storage device to be transmitted through the first channel; receiving status information about the second unit area from the storage device through the first channel; and transmitting a second read command corresponding to the second unit area of ​​the storage device through the first channel, wherein at least a portion of a period of receiving the status information through the first channel overlaps with a period of receiving the first data through the second channel.

[0008] According to some example embodiments, a memory controller that communicates with a storage device includes: a processor configured to control a storage operation on the storage device; a memory interface connected to the storage device through a first channel for transmitting commands / addresses and a second channel for transmitting data, and the second channel is physically separated from the first channel; an error correction code (ECC) circuit configured to perform an ECC decoding process on data read from the storage device to correct errors in the read data; and a status information processor configured to receive and process status information transmitted from the storage device through the first channel, the status information indicating a degradation state of a storage cell of the storage device, the memory controller being configured to receive status information about a first cell region of a storage cell array of the storage device through the first channel before performing a read operation on the first cell region, and the processor being configured to differently control a read level in a read operation on the first cell region according to the degradation state of the storage cell of the first cell region, or to differently perform an error correction or recovery operation on the data read from the first cell region based on the status information.

[0009] According to some example embodiments, a storage system includes a storage device, the storage device including: a storage cell array, the storage cell array including a plurality of pages, each page including a plurality of storage cells; a control logic configured to control a storage operation on the storage cell array and generate status information indicating a degradation state of the plurality of storage cells; and an interface circuit configured to transmit a command / address through a first channel and to transmit data through a second channel physically separated from the first channel, the interface circuit being configured to sequentially receive a first read command corresponding to a first page and a second read command corresponding to a second page from an external device, receive a status information request command that issues a request to transmit status information about the second page through the first channel before receiving the second read command, output status information about the second page through the first channel, and output data of the first page read in response to the first read command in parallel with outputting the status information about the second page through the second channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a storage system according to some example embodiments;

[0012] Figure 2 is a diagram illustrating the concepts of channel interleaving and way interleaving in a memory system including a plurality of memory chips;

[0013] Figure 3 is a block diagram illustrating an implementation example of a memory controller according to some example embodiments;

[0014] Figure 4 and Figure 5 is a flowchart illustrating a method of operating a storage system according to some example embodiments;

[0015] Figure 5 An example is shown in which a memory controller controls memory operations based on status information;

[0016] Figure 6 is a schematic diagram showing a method according to some example embodiments Figure 1 A diagram of the structure of a storage device;

[0017] Figure 7 It is shown Figure 1 A diagram of a memory cell array;

[0018] Figure 8 It is shown that the Figure 7 A perspective view of an example of a structure of a block in a memory cell array;

[0019] Fig. 9 is a block diagram illustrating an example of storing state information in a memory cell array according to some example embodiments;

[0020] Fig.10 is a diagram illustrating an example of transmission timing of status information according to some example embodiments;

[0021] Fig.11A and Fig. 11B is a diagram showing an example of generating and managing a history read level;

[0022] Fig.12 is a diagram illustrating an example of controlling an operation of reading data based on state information according to some example embodiments;

[0023] Fig.13A and FIG. 13B to FIG. 15 is a block diagram illustrating an implementation example of a storage system according to some example embodiments;

[0024] Fig.16 is a flowchart illustrating a method of operating a storage system according to some example embodiments; and

[0025] Fig.17 is a block diagram illustrating an example in which a memory system according to some example embodiments is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0026] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, regions, layers and / or parts, these elements, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, region, layer or part from another region, layer or part. Therefore, without departing from the teachings of the exemplary embodiments, the first element, component, region, layer or part discussed below may be referred to as a second element, region, layer or part.

[0027] Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating a storage system 10 according to some example embodiments.

[0029] refer to Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200, and the memory device 200 may include a memory cell array 210, a page buffer 220, a control logic 230, and an interface circuit 240. In addition, the control logic 230 may include a state information generator 231. Figure 1 In the example embodiment of FIG. 2 , the state information generator 231 is illustrated as being included in the control logic 230 , but the state information generator 231 according to some example embodiments may be a separate element outside the control logic 230 .

[0030] For example, the storage system 10 may communicate with the host through various interfaces, and for example, the storage system 10 may communicate with the host through various interfaces, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Peripheral Component Interconnect (PCI), PCI express (PIC-E), Advanced Technology Attachment (ATA), Serial-ATA (SATA), Parallel-ATA (PATA), Small Computer System Interface (SCSI), External SATA (e-SATA), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), and Non-Volatile Memory Express (NVMe).

[0031] According to some example embodiments, the storage device 200 may include a non-volatile storage device. In some example embodiments, the storage system 10 may be implemented as a memory embedded in an electronic device or detachably attached to an electronic device. For example, the storage system 10 may be implemented as various types, such as an embedded UFS storage device, an eMMC, a solid-state drive (SSD), a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme speed (xD) card, and a memory stick. In addition, the storage system 10 may be referred to as a storage device that stores data in a non-volatile manner.

[0032] In response to a write / read request from the host HOST, the memory controller 100 may read data stored in the storage device 200, or may control the storage device 200 to write data into the storage device 200. For example, the memory controller 100 may include a processor 110, and the processor 110 may control the overall operation of the memory controller 100 and may control storage operations on the storage device 200. In detail, the memory controller 100 may provide commands / addresses CMD / ADD and control signals CTRL to the storage device 200 based on the control of the processor 110, and thus may control write operations, read operations, and erase operations on the storage device 200. In addition, data DATA to be stored in the storage device 200 and data DATA to be read from the storage device 200 may be transmitted and received between the memory controller 100 and the storage device 200.

[0033] In some exemplary embodiments, the memory cell array 210 may include a three-dimensional (3D) memory cell array, the 3D memory cell array may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines stacked vertically on a substrate. However, the inventive concept is not limited thereto, and in some example embodiments, the memory cell array 210 may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged in row and column directions. Hereinafter, an exemplary embodiment will be described, and for example, a case where the memory cell is a NAND flash memory cell will be described. However, the inventive concept is not limited thereto, and the memory cell may include various non-volatile memory cells, such as resistive random access memory (RAM) (ReRAM), phase change RAM (PRAM), and magnetic RAM (MRAM).

[0034] The page buffer 220 may temporarily store data to be written into the memory cell array 210 or data to be read from the memory cell array 210. The control logic 230 may control the overall operation of the memory device 200, the command / address CMD / ADD, and the control signal CTRL, and may output various internal control signals for programming data in the memory cell array 210 or reading data from the memory cell array 210, for example.

[0035] According to some example embodiments, the memory controller 100 may further include an error correction code (ECC) circuit 120, a status information processor 130, and a memory interface 140. Figure 1 Although not shown in the figure, the memory controller 100 may further include a host interface (not shown) that performs an interface with a host.

[0036] The ECC circuit 120 may perform an error detection / correction operation on data read from the memory device 200. Various ECC decoding algorithms based on various error correction capabilities may be applied to the ECC circuit 120, and for example, in the case where the ECC circuit 120 performs error correction based on a low-density parity check (LDPC), the memory controller 100 may receive hard decision (HD) data determined with respect to a normal read level and soft decision (SD) data determined with respect to at least one offset read level, and may perform an error correction operation based on the HD data and the SD data.

[0037] According to some example embodiments, the state information generator 231 of the memory device 200 may generate the state information Info_S including various pieces of information associated with the state of the memory cell. In some example embodiments, the state information Info_S may be generated by the memory device 200 and may be stored in the memory cell array 210. Alternatively, the state information Info_S may be generated by the memory controller 100 and may be stored in the memory cell array 210. Alternatively, based on a request of the memory controller 100, the state information Info_S may be generated by the memory device 200 and may be provided to the memory controller 100 without being stored separately. Alternatively, the state information Info_S may include various information, some of which may be generated by the memory controller 100, and some of which may be generated by the memory device 200.

[0038] The memory cell array 210 may include a plurality of blocks, each of which may include a plurality of pages, and each of which may correspond to a write / read unit. Moreover, the status information Info_S may be generated and managed by units of certain memory cells, and may be generated, for example, by page units or by various units such as block units.

[0039] The state information Info_S may include information associated with the degradation state of each memory cell, and in some example embodiments, may be referred to as degradation information or health information. Alternatively, the state information Info_S may contain information representing characteristics of the memory cell (e.g., threshold voltage distribution characteristics). In the description of the example embodiments, in addition to information representing the degree of degradation of the memory cell, the state information Info_S may be defined as including various types of information that can be used in association with storage operations such as data writing / reading and error correction.

[0040] In some example embodiments, the state information Info_S may include a cell count value (e.g., an on-chip valley search (OVS) count value), a historical read level, a write / erase count value, and a previous error value. For example, the memory device 200 may count each of the turn-on cells (or turn-off cells) relative to at least two read levels near the valley between the threshold voltage distributions, and may provide a difference between the count results as an OVS count value. The memory controller 100 may refer to the OVS count value, and thus may determine the degree of degradation of the memory cell or may determine an optimal valley value or an expected valley value between the threshold voltage distributions.

[0041] In addition, in the case where no error occurs or only a correctable error occurs in the read operation, the read level used in the read operation can be managed as historical read level information. For example, the historical read level information can be managed by a page unit or a block unit included in the memory cell array 210. Alternatively, the historical read level information can be managed by a super block unit configured with a plurality of blocks included in each of a plurality of memory chips. The storage device 200 can store the historical read level information and can provide the historical read level information as the status information Info_S to the memory controller 100.

[0042] In addition, the write / erase count value may be managed by a block unit or a page unit included in the memory cell array 210, and may be referred to when determining the life of each block or page. For example, the write count value may be managed by a page unit and the erase count value may be managed by a block unit. Whenever a write / erase operation is performed on the memory cell array 210, the memory controller 100 may perform a counting operation, and may store the write / erase count value in the memory device 200. The memory device 200 may provide the write / erase count value as the status information Info_S to the memory controller 100 based on a request from the memory controller 100.

[0043] In addition, the previous error value may include information associated with an error that occurred in a previously performed read operation, and may include, for example, information about the number of errors (or a bit error rate) of data that occurred by an error detection / correction unit or a page unit. The status information Info_S associated with the previous error value may be managed by a certain unit, and, for example, the memory controller 100 may store information about the error value detected by the page unit in the memory device 200. The memory device 200 may provide the previous error value as the status information Info_S to the memory controller 100.

[0044] The memory controller 100 may receive the state information Info_S from the memory device 200, and may control the next memory operation based on the state information Info_S. For example, the memory controller 100 may control the read level in the read operation based on the state information Info_S, or may perform a control operation of selecting the type of data to be read. In addition, the memory controller 100 may correct an error of the data based on various algorithms or may perform a recovery operation, and further, the memory controller 100 may refer to the state information Info_S to perform an optimal or desired error correction operation or an optimal or desired recovery operation.

[0045] In some example embodiments, the memory controller 100 may transmit commands / addresses CMD / ADD and data DATA through a channel separate from the memory device 200. For example, a first channel for transmitting commands / addresses CMD / ADD may be physically separated from a second channel for transmitting data DATA, and the memory interface 140 may communicate with the interface circuit 240 through the first channel and the second channel. The first channel may be referred to as a command / address channel or a command / address bus, and the second channel may be referred to as a data channel or a data bus.

[0046] In some example embodiments, the state information Info_S may be transferred from the memory device 200 to the memory controller 100 through the first channel. Therefore, the state information Info_S may be provided to the memory controller 100 in parallel with a period in which data is transferred between the memory controller 100 and the memory device 200. Alternatively, at least a portion of a period in which the state information Info_S is provided to the memory controller 100 may overlap with a period in which data is transferred.

[0047] In some example embodiments, a separate command (hereinafter, referred to as a status information request command CMD_Q) for transferring status information Info_S between the memory controller 100 and the storage device 200 may be defined. The memory controller 100 may output the status information request command CMD_Q, which issues a request for transferring status information Info_S about a specific unit (e.g., a page unit, a block unit, or a chip unit) including data of the specific unit area, before outputting a read command that issues a request to read data of the specific unit area. For example, as described above, because the first channel is physically separated from the second channel, the memory controller 100 may output the status information request command CMD_Q to the storage device 200 and receive the status information Info_S from the storage device 200 in the middle of transmitting data DATA with the storage device 200.

[0048] The state information processor 130 may perform a processing operation on the state information Info_S, may generate control information Ctrl_I so that a write / read operation, an error detection / correction operation, or a recovery operation is performed based on the state information Info_S, and may provide the control information Ctrl_I to the elements of the memory controller 100. For example, the memory controller 100 may use one or more recovery modules to recover the error, and when the error of the read data is not corrected, the memory controller 100 may perform a recovery operation for recovering the error of the data based on the control of the processor 110. In some example embodiments, based on the consumed resources and time, the plurality of recovery modules may have different recovery capabilities, and when a recovery module optimized or desired for the degree of degradation of the memory cell is selected based on the control information Ctrl_I, the possibility of performing an unexpected recovery operation may be prevented or reduced. The state information processor 130 or each recovery module may be configured as hardware, software, or a combination thereof, and a control operation using the control information Ctrl_I may be performed by hardware processing or software processing.

[0049] According to some example embodiments, without reducing data transfer efficiency, the memory controller 100 may receive status information Info_S from the storage device 200 by using a command / address channel capable of performing bidirectional communication, and may use the received status information Info_S in a storage operation for enhancing data reliability.

[0050] In addition, according to some example embodiments, the state information Info_S may be stored in the memory device 200, read from the memory device 200 in response to a command of the memory controller 100, and provided to the memory controller 100, and therefore, the memory controller 100 may not need to include an expensive high-speed random access memory (RAM) for storing the state information, thereby reducing the manufacturing cost of the memory system. In addition, because the state information Info_S may be stored in the memory cell array 210 having a large capacity, the state information Info_S may be generated and managed by a page unit having a relatively small size, and therefore, the degree of degradation of the memory cell may be accurately determined and a storage operation optimized or desired for the degree of degradation may be controlled.

[0051] In some of the above-mentioned example embodiments, the case where the status information Info_S is transmitted through the command / address channel has been described, but the example embodiments are not limited thereto. For example, each of the memory controller 100 and the storage device 200 may further include at least one other channel for transmitting various pieces of information, and by using a channel that does not reduce the transmission efficiency of data, the communication of the status information request command CMD_Q and the status information Info_S may be performed.

[0052] Figure 1 The elements of the memory device 200 shown in the figure may be elements included in one memory chip or die. In some example embodiments, the memory system 10 may include a plurality of memory chips, and the memory controller 100 may communicate with the plurality of memory chips through different channels. For example, the memory device 200 may include a plurality of memory chips, and each of the memory chips may include Figure 1 Elements of the storage device 200 are shown in FIG.

[0053] Figure 2 is a diagram illustrating the concepts of channel interleaving and way interleaving in a memory system including a plurality of memory chips.

[0054] refer to Figure 2, the storage system may include a memory controller, and the memory controller may be connected to a plurality of storage devices (e.g., non-volatile storage devices NVM) through one or more channels. In addition, according to the above example embodiments, each storage device NVM may store status information Info_S. For example, the memory controller may be connected to one or more storage devices NVM through the Ath channel CH_A and may be connected to one or more storage devices NVM through the Bth channel CH_B. In addition, according to the example embodiments described above, the command / address channel may be physically separated from the data channel, and the Ath channel CH_A may include a first channel CH_1 corresponding to the command / address channel and a second channel CH_2 corresponding to the data channel. The Ath channel CH_A and the Bth channel CH_B may transmit data in parallel, and parallel data communication may be referred to as channel interleaving.

[0055] Each of the channels may correspond to a plurality of ways representing a logical path. For example, the Ath channel CH_A may correspond to a first way WAY 1 and a second way WAY 2, and each way may include one or more storage devices NVM. Figure 2 In the example embodiment of , a case where each way includes two storage devices NVM is shown. In implementations of some example embodiments, the storage device NVM of each way may correspond to a memory chip included in the same package, or may correspond to a memory die, but the storage system according to the example embodiment is not limited thereto and may be implemented in various types.

[0056] The storage operation on each of the A-th channel CH_A and the B-th channel CH_B may be performed independently and in parallel. On the other hand, the first way WAY 1 and the second way WAY 2 may share the A-th channel CH_A, and therefore, the data input / output (I / O) on the storage device NVM of the first way WAY 1 and the second way WAY 2 may be performed by an interleaving scheme.

[0057] In the manner of the above-mentioned interleaved structure, the data channel can be shared by at least two storage device NVMs, and therefore, the channel efficiency and performance can be enhanced. However, considering the time consumed by inputting / outputting data and the time consumed by correcting / recovering data errors, limitations may occur in increasing the number of storage device NVMs that share the channel. On the other hand, according to some example embodiments, the status information request command CMD_Q and the status information Info_S can be transmitted by using a command / address channel that is physically separated from the data channel, and therefore the possibility of a reduction in data transfer bandwidth can be prevented or reduced. In addition, by using the status information Info_S, the data channel can be effectively used in association with data write / read operations and correction / recovery of data errors, and in addition, the time and resources consumed by correcting / recovering data errors can be reduced, thereby improving the overall efficiency and performance of the storage system.

[0058] Figure 3 is a block diagram illustrating an implementation example of a memory controller 300 according to some example embodiments.

[0059] refer to Figure 3 , the memory controller 300 may include a host interface 310, a processor 320, a random access memory (RAM) 330, an error correction code (ECC) circuit 340, a state information processing module 350, a recovery module 360, and a memory interface 370. In addition, the RAM 330 may be used as a working memory, and the processor 320 may execute firmware loaded into the RAM 330 to control the overall operation of the memory controller 300. The RAM 330 may be implemented as various memories, and, for example, may be implemented as at least one of resistive memory devices such as a cache memory, a dynamic RAM (DRAM), a static RAM (SRAM), and a PRAM.

[0060] As an example of firmware, a flash translation layer (FTL) may be loaded into the RAM 330, and various functions associated with flash memory operations may be performed by driving the FTL. In addition, according to the above-described exemplary embodiments, the recovery module 360 ​​may perform one or more recovery operations, and in the case where the recovery operation is performed by software, the recovery module 360 ​​may include software corresponding to the recovery algorithm loaded into the RAM 330 based on the control of the processor 320.

[0061] In some example embodiments, the state information processing module 350 may be implemented by hardware, software, or a combination thereof. For example, when the state information processing module 350 is firmware and implemented by software, the state information processing module 350 may be loaded into the RAM 330 and may be executed by the processor 320. Alternatively, when the state information processing module 350 is implemented by hardware, the state information processing module 350 may include a circuit that performs logic processing on the state information provided from the storage device NVM.

[0062] The host interface 310 may communicate with the host through various interfaces according to the above-described example embodiments. In addition, the memory interface 370 may provide a physical connection between the memory controller 300 and the storage device NVM. For example, commands / addresses and data may be transmitted and received between the memory controller 300 and the storage device NVM through the memory interface 370, and according to the above-described example embodiments, the command / address channel and the data channel between the memory controller 300 and the storage device NVM may be physically separated from each other. In addition, in the above-described example embodiments, the status information request command CMD_Q and the status information Info_S may be transmitted between the memory controller 300 and the storage device NVM through the command / address channel.

[0063] The ECC circuit 340 may perform error detection and error correction operations on data read from the storage device NVM, and when an error occurs or is not corrected, a determination of data failure may be performed. In some example embodiments, the ECC circuit 340 may perform ECC decoding processes with different correction capabilities, and according to the example embodiments described above, an optimal or expected ECC decoding process corresponding to the degree of degradation of the storage unit may be performed based on the state information Info_S. For example, when an ECC decoding process using HD data is defined as an error correction operation and an SD ECC decoding process using HD data and SD data is defined as a recovery operation applied to a storage system, a storage operation may be controlled based on the state information Info_S so that a recovery operation using HD data and SD data is performed without performing an ECC decoding process using HD data.

[0064] The state information processing module 350 can generate control information Ctrl_I corresponding to the information available to the memory controller 300 by processing the state information Info_S received from the storage device NVM. The memory controller 300 can control the storage operation of the storage device NVM based on the control information Ctrl_I, and for example, the memory controller 300 can control the read level in the read operation, or can control the type of data (e.g., HD data and SD data) read from the storage device NVM. In addition, the memory controller 300 can control the error detection / correction operation of the data based on the control information Ctrl_I, and can control the recovery operation for recovering the error of the data. For example, the control information Ctrl_I can be provided to the processor 320, and the processor 320 can perform a control operation so that the degradation state optimization or desired recovery operation for the storage unit is performed. In addition, the control information Ctrl_I can be provided to the ECC circuit 340, and the ECC circuit 340 can perform a control operation based on the control information Ctrl_I so that the degradation state optimization or desired ECC decoding process for each storage unit is performed. Furthermore, control information Ctrl_I may be provided to the memory interface 370 , and for example, the memory interface 370 may add information associated with a read level to be used in a read operation (eg, level shift information) to a read command based on the control information Ctrl_I, or may output as separate information.

[0065] The recovery module 360 ​​may include an element for recovering an error of data read from the storage device NVM. The recovery module 360 ​​may support a plurality of recovery operations with different recovery capabilities based on the consumed resources and time. For example, in a method of recovering a data error, a read retry operation of changing a read level to read data may be performed, or an ECC decoding process using SD data read based on the above-mentioned at least two offset read levels may be performed, or an algorithm for detecting an optimal or expected valley value between threshold voltage distributions of a storage cell may be performed, or a recovery operation (e.g., a redundant array of independent disks (RAID)) further using data other than the read request data may be performed.

[0066] exist Figure 3 In the illustrated example embodiment, it has been described that the state information processing module 350 generates separate control information Ctrl_I, but the example embodiment is not limited thereto. For example, the control information Ctrl_I may correspond to the same information as the state information Info_S, or the processor 320 may directly process the state information Info_S to control various operations of the memory controller 300.

[0067] Figure 4 and Figure 5is a flowchart illustrating an operating method of a storage system according to some example embodiments. Figure 4 and Figure 5 Each operation shown in may be an operation performed by a memory controller or an operation performed by a memory device.

[0068] refer to Figure 4 The storage device may include one or more memory chips, each of the memory chips may include a plurality of blocks, and each of the blocks may include a plurality of memory cells. In a cell region including memory cells having a specific size, for example, the memory controller may output a first read command of a first cell region of the storage device through a first channel for command / address in operation S11.

[0069] Subsequently, in operation S12, the memory controller may output a status information request command through the first channel, the status information request command issuing a request to provide status information of a storage cell of a second cell region of the storage device. In some example embodiments, a storage cell array of the storage device may store multiple pieces of status information about a plurality of cell regions, and the memory controller may add an address representing a second cell region of the plurality of cell regions to the status information request command. The storage device may generate status information about the second cell region, or may read status information about the second cell region indicated by the address from the storage cell array, and may output status information about the second cell region through the first channel. In operation S13, the memory controller may receive status information from the storage device through the first channel.

[0070] In operation S14, the memory controller may receive the read first data through the second channel for data in response to the previously output first read command. The first channel for command / address may be physically separated from the second channel for data, and therefore, the period of receiving the first data may overlap with at least a portion of the period of outputting the status information request command and the period of receiving the status information. In addition, in operation S15, the memory controller may output a second read command for the second unit area through the first channel based on the received status information. In some example embodiments, the second read command may be output to the storage device through the first channel before the memory controller completes the reception of the first data, and therefore, at least a portion of the period of outputting the second read command may overlap with the period of receiving the first data.

[0071] In some example embodiments, each of the first and second cell regions may be an element included in any block. For example, the first cell region and the second cell region may be included in the same memory chip, or may be included in different memory chips. In addition, the first cell region and the second cell region may be included in the same block, or may be included in different blocks.

[0072] Figure 5 Some example embodiments are shown in which a memory controller controls memory operations based on status information.

[0073] refer to Figure 5 In operation S21, the memory controller may receive state information about the memory cells of the first cell region, and for example, the state information may indicate a degradation state of the memory cells of the first cell region to be subsequently subjected to a read operation. In operation S22, the memory controller may control various storage operations on the memory device based on the state information, and for example, may control a read operation on the first cell region.

[0074] In some example embodiments, the memory controller may control the read level when performing a read operation on the first cell region based on the state information. For example, when the state information includes information referenced when determining an optimal or desired read level (such as an OVS count value or a historical read level), the memory controller may provide the memory device with offset information (difference information relative to a reference level) or a read level value in the process of controlling the read operation, and thus may control the read level.

[0075] The memory controller may receive data of the first unit area read from the storage device, and may perform an error correction operation based on the ECC decoding process in operation S23, and when the error does not occur or is corrected, the memory controller may determine that the data read is passed in operation S24. On the other hand, when the error is not corrected by the ECC decoding process, a recovery algorithm corresponding to the state information may be selected from various recovery algorithms applied to the memory controller in operation S25. For example, the first to Nth recovery algorithms may be applied and sequentially executed based on the error recovery capability of the data, and some of the first to Nth recovery algorithms may be selectively executed based on the degree of degradation of the memory cell of the first unit area determined based on the state information.

[0076] As described above, the reading of data may be performed by page units, and in the exemplary embodiments described above, the cell area may correspond to a page. In addition, the state information may be managed by various units such as a page, a plurality of pages, a block, or a chip unit, and a plurality of pieces of state information may be stored in a memory cell array of a memory device. For example, in the case where the state information is managed by page units, the state information corresponding to the page to be subsequently read may be selected based on a request of the memory controller and provided to the memory controller.

[0077] Alternatively, in various example embodiments, the status information may be generated and managed in a relatively large size such as a plurality of pages or blocks, and the status information corresponding to a cell including a page to be subsequently read may be selected based on a request of the memory controller and provided to the memory controller. According to the above example embodiments, when outputting a status information request command, the memory controller may add an address for selecting one piece of status information from a plurality of pieces of status information to the status information request command.

[0078] In the following exemplary embodiments, it may be described that the state information is generated and managed by page units, and the memory controller issues a request to transfer the state information by page units, but as described above, the exemplary embodiments are not limited thereto.

[0079] Figure 6 is a schematic diagram showing a method according to some example embodiments Figure 1 A diagram of the structure of a storage device, Figure 7 It is shown Figure 1 A diagram of a memory cell array 210, and Figure 8 It is shown that it is included in Figure 7 2 is a perspective view of an example of a structure of a block in the memory cell array 210. Figure 8 , a cell on periphery (COP) structure is illustrated as an implementation example of a memory device, but example embodiments are not limited thereto and the memory device may be implemented to have various structures.

[0080] Reference Figure 6 , the memory device 200 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 in a vertical direction VD. In detail, the second semiconductor layer L2 may be arranged below the first semiconductor layer L1 in the vertical direction VD, and thus, the second semiconductor layer L2 may be arranged close to the substrate.

[0081] In some exemplary embodiments, Figure 1 The memory cell array 210 may be formed in the first semiconductor layer L1, and Figure 1Other peripheral circuits may be formed in the second semiconductor layer L2. Therefore, the memory device 200 may have a structure (e.g., a COP structure) in which the memory cell array 210 is arranged on the peripheral circuits. The COP structure may effectively reduce the horizontal area and may enhance the integration of the memory device 200.

[0082] In some exemplary embodiments, the second semiconductor layer L2 may include a substrate, and a peripheral circuit may be formed in the second semiconductor layer L2 by forming a transistor and a metal pattern for wiring the transistor on the substrate. After the peripheral circuit is formed in the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 210 may be formed, and a metal pattern for electrically connecting the word lines WL and the bit lines BL of the memory cell array 210 to the peripheral circuit formed in the second semiconductor layer L2 may be formed. For example, the bit lines BL may extend in the first horizontal direction HD1, and the word lines WL may extend in the second horizontal direction HD2.

[0083] refer to Figure 7 , the memory cell array 210 may include a plurality of blocks BLK0 to BLKi, where i may be a positive integer. Each of the plurality of blocks BLK0 to BLKi may have a 3D structure (or a vertical structure). In detail, each of the plurality of blocks BLK0 to BLKi may include a plurality of NAND strings extending in a vertical direction VD. In this case, the plurality of NAND strings may be arranged at a certain distance apart from each other in a first horizontal direction HD1 and a second horizontal direction HD2. The plurality of blocks BLK0 to BLKi may be selected by a row decoder (not shown) of the memory device 200. For example, the row decoder may select a block corresponding to a block address from the plurality of blocks BLK0 to BLKi.

[0084] refer to Figure 8 , the block BLK0 may be formed in a vertical direction relative to the substrate SUB. The substrate SUB may have a first conductivity type (e.g., p-type), and a common source line CSL extending in the second horizontal direction HD2 and doped with impurities of a second conductivity type (e.g., n-type) may be provided on the substrate SUB. A plurality of insulating layers IL extending in the second horizontal direction HD may be sequentially provided in the vertical direction VD in a region of the substrate SUB between two adjacent common source lines CSL, and the plurality of insulating layers IL may be separated from each other by a certain distance in the vertical direction VD. For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

[0085] A plurality of pillars P sequentially arranged in the first horizontal direction HD1 and respectively passing through the plurality of insulating layers IL in the vertical direction VD may be provided in a region between two adjacent common source lines CSL of the substrate SUB. For example, the plurality of pillars P may pass through the plurality of insulating layers IL and may contact the substrate SUB. In detail, the surface layer S of each pillar P may include a first type of silicon material and may be used as a channel region. The inner layer I of each pixel P may include an air gap or an insulating material such as silicon oxide.

[0086] In the region between two adjacent common source lines CSL, a charge storage layer CS may be provided along the exposed surfaces of the insulating layer IL, the pillar P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (or referred to as a tunneling insulating layer), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, a gate electrode GE (such as word lines WL0 to WL7 and selection lines GSL and SSL) may be provided on the exposed surface of the charge storage layer CS in the region between two adjacent common source lines CSL.

[0087] Drains or drain contacts DR may be provided on the plurality of pillars P, respectively. For example, the drain or drain contacts DR may include a silicon material doped with impurities of the second conductivity type. Bit lines BL1 to BL3 extending in the first horizontal direction HD1 and spaced apart from each other by a certain distance in the second horizontal direction HD2 may be provided on the drain / drain contacts DR.

[0088] Fig. 9 is a block diagram illustrating an example in which state information is stored in a memory cell array according to some example embodiments.

[0089] refer to Fig. 9 , the memory system 400 may include a memory controller 410 and a memory device 420, and the memory controller 410 and the memory device 420 may communicate with each other through a command / address channel CA CH and a data channel Data CH that are physically separated from each other. In addition, the memory controller 410 may include a command / address controller 411 and an ECC decoder 412, the command / address controller 411 includes an element associated with processing of information transmitted and received through the command / address channel CA_CH, and the ECC decoder 412 performs an ECC decoding process on the data. In addition, the memory device 420 may include a memory cell array 421, a data latch 422, and a counter 423, and the data latch 422 may include a circuit that temporarily stores data read from the memory cell array 421. For example, according to some example embodiments, the data latch 422 may be an element included in the page buffer PB, or may be an element that receives data from the page buffer PB and temporarily stores the received data.

[0090] The memory cell array 421 may include a storage space for storing information other than user data, and the state information according to the above-described example embodiment may be stored in the memory cell array 421. For example, the state information according to the example embodiment may be generated by the memory controller 410 and may be stored in the memory cell array 421, or may be generated by the memory device 420 and may be stored in the memory cell array 421. Alternatively, some state information may be generated by the memory device 420 and may be provided to the memory controller 410 in response to a state information request command CMD_Q from the memory controller 410, without being stored in the memory cell array 421. In addition, according to the above-described example embodiment, the address ADD_Q may be provided to the memory device 420 through the command / address channel CA_CH in association with selection of a plurality of pieces of state information stored in the memory cell array 421.

[0091] In addition, when the status information generated and provided by the memory controller 410 is defined as the write status information Info_ws, the storage device 420 may receive the write status information Info_ws and may store the write status information Info_ws as status information in the memory cell array 421. The write status information Info_ws may be provided to the storage device 420 according to various schemes, and for example, similar to a normal write operation, the write status information Info_ws may be provided to the storage device 420 through the data channel DATA_CH.

[0092] At least some of the various status information may be read from the memory cell array 421 and output to the memory controller 410, and the status information stored in the memory cell array 421 may include information such as a historical read level, a previous error value, and a write / erase count value. Alternatively, some status information may be generated by the memory device 420 and may be provided to the memory controller 410 through the command / address channel CA_CH without being stored in the memory cell array 421, and for example, the counter 423 may calculate an OVS count value based on a cell count (e.g., an on cell count or an off cell count) operation, and the memory device 420 may output the OVS count value to the memory controller 410 as status information.

[0093] The command / address controller 411 may include a status information processor (not shown) according to the example embodiment described above, and may provide control information Ctrl_I to the ECC decoder 412 based on a result obtained by processing the status information. The ECC decoder 412 may receive data through a data channel and may control an ECC decoding process of the data based on the control information Ctrl_I from the command / address controller 411. As an example of operation, the memory controller 410 may control a read operation of HD data and a read operation of SD data on the storage device 420 based on the status information, and the ECC decoder 412 may perform an HD ECC decoding process using the HD data or may perform an SD ECC decoding process using the HD data and the SD data based on the control information Ctrl_I.

[0094] In some example embodiments, the state information provided to the memory controller 410 may include only one kind of information, or may include at least two kinds of information. The memory controller 410 may determine the degree of degradation of the memory cell or the optimal read level or the expected read level by using each piece of information. Alternatively, the memory controller 410 may receive at least two pieces of information as the state information and may determine the degree of degradation of the memory cell based on a combination of the at least two pieces of information.

[0095] Fig.10 is a diagram showing an example of the timing of transmission of status information according to some example embodiments. Fig.10 , a case is shown where the memory controller sequentially reads data of an nth page and data of an n+1th page, and each of the nth page and the n+1th page may be a page included in any block of any memory chip.

[0096] refer to Fig.10 , the memory controller may output a status information request command CMD_Q(N) requesting status information about the Nth page through the command / address CA channel. For example, the memory controller may determine a page of the storage device on which a read will be subsequently performed, and based on this, the memory controller may output the status information request command CMD_Q(N). The memory controller may receive status information Info_S(N) indicating the degradation status of the memory cells of the Nth page from the storage device.

[0097] Subsequently, the memory controller may output a first read command RD(N) corresponding to the Nth page, and may receive first data data(N) in response to the first read command RD(N) through the data DATA channel. Subsequently, the memory controller may output a status information request command CMD_Q(N+1) requesting status information about the N+1th page, and may also receive status information Info_S(N+1) indicating a degradation state of a memory cell of the N+1th page. According to the above-described example embodiment, at least a portion of a period of outputting the status information request command CMD_Q(N+1) and a period of receiving the status information Info_S(N+1) may overlap with a period of receiving the first data data(N).

[0098] Similar to the operation, the memory controller may output a second read command RD(N+1) corresponding to the N+1th page, and may receive the second data DATA(N+1) through the data DATA channel. In addition, in parallel with receiving the second data data(N+1), the memory controller may output a status information request command CMD_Q(N+2) requesting status information about the N+2th page to be read subsequently, and may receive status information Info_S(N+2) indicating the degradation status of the memory cell of the N+2th page. In addition, the memory controller may output a third read command RD(N+2) corresponding to the N+2th page after receiving the status information Info_S(N+2).

[0099] like Fig.10 As shown in , although a relatively long time is consumed when inputting / outputting data, the status information can be transmitted through the command / address channel physically separated from the data channel, and therefore, the degradation state of the storage unit in which the reading is actually performed can be predetermined without reducing the data bandwidth, and the storage operation can be controlled based on this. Therefore, the execution of the recovery operation or the undesired ECC decoding process can be skipped based on the degradation state, and therefore, the flow of the data recovery process can be reduced, and the resources consumed in the ECC decoding process or the recovery operation can be reduced, thereby reducing the reduction in the performance of the storage system.

[0100] In the example embodiment, the case where the memory controller receives the status information about the nth page immediately before outputting the read command corresponding to a page (e.g., the nth page), has been described, but the example embodiment is not limited thereto. For example, the memory controller may schedule multiple read operations and then may predetermine the location of the page to be read subsequently. Therefore, the memory controller may also output a status information request command requesting status information about the nth page at an earlier time than the case described in the example embodiment.

[0101] In addition, according to the above exemplary embodiments, the status information may be generated by a block unit and may be output by a block unit, or the status information may be generated by a page unit, and the unit of the status information provided to the memory controller may be set to a block unit (including a unit of status information about a plurality of pages). In this case, in the case where the memory controller sequentially reads several pages of the same block, the memory controller may receive the status information about the block unit in advance, and may control the read operation of at least two subsequent pages with reference to the received status information, without receiving the status information each time the read operation is performed.

[0102] In the following description, examples of state information and control examples of storage operations using the state information in some example embodiments are described.

[0103] Fig.11A and Fig. 11B is a diagram showing an example of generating and managing a history read level.

[0104] Reference Fig.11A , the memory device may include one or more memory chips, and the memory cell array of each memory chip may include a plurality of blocks (eg, first to Nth blocks) BLK1 to BLKN. In addition, each block may include a first to Mth page.

[0105] The data read from each page may be provided to the memory controller, and the memory controller may perform an error detection / correction operation on the data. When no error occurs in the read operation or only a correctable error occurs, the read level used in the read operation may be managed as historical read level information. For example, the historical read level may be managed by block units, or may be managed by page units. In the case where the historical read level is managed by page units, such as Fig.11A As shown, the first to M-th historical read level information (historical RL Info_P1 to Info_PM) may be managed on the N-th block (eg, the first to M-th pages included in the N-th block).

[0106] refer to Fig. 11B , the memory controller may provide the storage device with write status information Info_ws including historical read level information about the page of each block, and may store the write status information Info_ws in the storage device. Subsequently, when a read operation is performed on the storage device, the memory controller may output a status information request command CMD_Q to the storage device, and may output addresses ADD_B / P of pages and blocks to the storage device, each address ADD_B / P indicating the location of a storage cell on which a read is to be performed. The memory controller may receive status information Info_S indicating the degradation state of the page on which a read is to be performed from the storage device.

[0107] The memory controller may determine an optimal or desired read level of a page to be read based on the state information Info_S received from the memory device, and may provide a level control signal Ctrl_RL for controlling the read level in the read operation on the page to the memory device. In some example embodiments, a reference read level may be pre-set in the memory device, and the memory controller may provide offset information indicating a level difference between the optimal or desired read level and the reference read level as the level control signal Ctrl_RL to the memory device. Moreover, in some example embodiments, since each of the memory cells stores data having two or more bits, the memory cells may include three or more threshold voltage distributions, and the level control signal Ctrl_RL may include information associated with an optimal or desired read level for determining the three or more threshold voltage distributions.

[0108] Fig.12 is a diagram illustrating an example of controlling an operation of reading data based on state information according to some example embodiments. Fig.12 In the figure, for the convenience of explanation, the status information request command is omitted.

[0109] refer to Fig.12 In response to a first read command (not shown), first data read from the Nth page may be output to the memory controller. For example, the first data may correspond to HD data HD data (N) determined based on a normal read level. Fig.12 As depicted in , the command / address CA channel and the data / data channel can be physically separate channels.

[0110] The memory controller may receive status information Info_S(N+1) about the N+1th page in parallel with receiving the first data, and may control a read operation on the N+1th page based on the status information Info_S(N+1). For example, when it is determined that the degree of degradation of the memory cell of the N+1th page is greater than a specific threshold, the memory controller may output a second read command RD_H / S that issues a request to read HD data and SD data from the N+1th page, and may receive second data read from the N+1th page in response to the second read command RD_H / S. The second data may include HD data HDData(N+1) determined based on a normal read level and SD data SD Data(N+1) determined based on at least one offset read level.

[0111] In addition, the memory controller may receive status information Info_S(N+2) about the N+2th page in parallel with receiving the second data, and may control a read operation on the N+2th page based on the status information Info_S(N+2). For example, when it is determined that the degree of degradation of the memory cell of the N+2th page is less than a specific threshold, the memory controller may output a third read command RD_H that issues a request to read HD data from the N+2th page, and may receive the third data read from the N+2th page in response to the third read command RD_H, and the third data may include HD data HDData(N+2). In addition, the memory controller may receive status information Info_S(N+3) about the N+3th page in parallel with receiving the third data, and when it is determined that the degree of degradation of the memory cell of the N+3th page is greater than a specific threshold, the memory controller may output a fourth read command RD_H / S that issues a request to read HD data and SD data.

[0112] According to example embodiments, a normal ECC decoding process using only HD data can be skipped for data read from a page with a high degree of degradation, and an SD ECC decoding process using SD data can be performed, thereby selectively performing a recovery algorithm with a higher error correction probability. Therefore, time and resources consumed when performing an unexpected error correction operation and a recovery algorithm can be reduced.

[0113] Fig.13A and FIG. 13B to FIG. 15 is a block diagram illustrating an example of an embodiment of a storage system according to an example implementation. Fig.13A , Fig. 13B and Fig.14 shows a case where information generated based on a count value corresponds to state information according to some example embodiments, and Fig.15 A case where an error value in a previous read operation corresponds to state information according to example embodiments is illustrated.

[0114] exist Fig.13A and 13B In the example, the OVS count value is shown as status information. Fig.13A , the OVS counting function may be implemented as an on-chip function in the storage device NVM. The storage device NVM may perform a cell counting operation based on data read relative to at least two predetermined read levels or alternatively desired read levels among a plurality of read levels shown by dashed lines, and, for example, may count turn-on cells (memory cells having a threshold voltage level less than the read level). For example, a cell counting operation may be performed based on read level A and read level B.

[0115] For example, when the number of errors in the memory cell is relatively small and the read level A and the read level B are arranged close to the valley between the threshold voltage distributions, the difference between the cell count values ​​calculated based on the read level A and the read level B can be relatively small. On the other hand, when the threshold voltage distribution is shifted based on the reduction of the data retention characteristic and the number of errors in the memory cell is relatively large, the difference between the cell count values ​​can be calculated as a large value. That is, when the difference between the cell count values ​​is large, it can be determined that the degree of degradation of the memory cell of the corresponding cell area is high.

[0116] In association with calculating the OVS count value, the number "a" of turn-on cells (or turn-off cells) determined based on the read level A and the number "b" of turn-on cells (or turn-off cells) determined based on the read level B may be calculated. In some example embodiments, the number "a" of turn-on cells determined based on the read level A and the number "b" of turn-on cells determined based on the read level B may each be provided to the memory controller as the OVS count value, or a difference "ba" between the number "a" of turn-on cells determined based on the read level A and the number "b" of turn-on cells determined based on the read level B may be provided to the memory controller as the OVS count value.

[0117] refer to Fig. 13B , the storage device may include elements associated with calculation of the OVS count value and a memory cell array, and for example, at least some of the elements associated with calculation of the OVS count value may be elements included in the control logic according to the above exemplary embodiments.

[0118] The OVS read controller may control a read operation based on a plurality of read levels associated with the calculation of the OVS count value according to the above-described example embodiments, and for example, data read based on the read level A may be stored in the first readout buffer, and data read based on the read level B may be stored in the second readout buffer. In addition, the OVS counter may perform a counting operation based on the data stored in the first readout buffer and the data stored in the second readout buffer, and for example, the number of turn-on cells of the data stored in the first readout buffer may be counted, and the number of turn-on cells of the data stored in the second readout buffer may be counted. In addition, in some example embodiments, the OVS counter may provide the memory controller with a difference between the count value of the turn-on cells based on the read level A and the count value of the turn-on cells based on the read level B as the OVS count value.

[0119] Fig.14 Some example embodiments of storing and using write / erase count values ​​are shown.

[0120] The memory system 500 may include a memory controller 510 and a memory device 520, the memory controller 510 may include a processor 511 and a write / erase counter 512, and the memory device 520 may include a memory cell array 521 and a control logic 522. The memory cell array 521 may include a first block BLK 1 to an N-th block BLK N, and further, state information according to some example embodiments may be stored in the memory cell array 521. Fig.14 , it is shown that the area storing the state information is distinguished from the first to Nth blocks BLK1 to BLKN, but the state information may also be stored in the first to Nth blocks BLK1 to BLKN.

[0121] According to the exemplary embodiment described above, the status information can be managed by page units, and for example, a write count value can be managed on each page and an erase count value can be managed on each page. For example, an erase operation can be performed by a block unit in a flash memory, and therefore, the same erase count value can be managed on pages included in the same block. The write / erase count operation can be performed by the memory controller 510, and the memory controller 510 can provide the write / erase count value of each page as the write status information Info_ws to the storage device 520.

[0122] In some example embodiments, a case where a write count value is managed may be described, for example.

[0123] When it is assumed that one block includes M number of pages, M number of write count values ​​may be stored in the memory cell array 521 for each of the first to Nth blocks BLK 1 to BLK N. For example, the first to Mth write count values ​​CNT_w1 to wM(BLK 1) may be stored in the memory cell array 521 in association with the first block BLK 1, and the first to Mth write count values ​​CNT_w1 to wM(BLK N) may be stored in the memory cell array 521 in association with the Nth block BLK N. The memory controller 510 may output a status information request command CMD_Q for issuing a request for transferring status information Info_S, and may output an address ADD_Q(B / P) indicating the location of a page for which status information Info_S is required together. In the case where the status information is managed by page units, the address ADD_Q(B / P) may include a block address and a page address indicating the locations of a block and a page, respectively. Alternatively, in the case where the status information is managed by block units, the address ADD_Q(B / P) may include a block address indicating the location of a block including a page.

[0124] The memory controller 510 may receive the state information Info_S, and based thereon, the memory controller 510 may determine the degradation state of the memory cells of the page. In some example embodiments, the memory controller 510 may control various storage operations by using the state information Info_S, and may output, for example, a control signal Ctrl_RA to allow execution of a recovery algorithm optimized or desired for the degradation state. The control signal Ctrl_RA may be output through various channels, and may be output through a command / address channel when a read command corresponding to a page is transmitted, for example, or the control signal Ctrl_RA may be output through a control channel additionally included in the memory system 500.

[0125] Fig.15 An example of storing and using error information in a previous read operation is shown.

[0126] The memory system 600 may include a memory controller 610 and a memory device 620 . The memory controller 610 may include a processor 611 , an ECC circuit 612 , and an error information generator 613 . The memory device 620 may include a memory cell array 621 and a control logic 622 .

[0127] According to the exemplary embodiment described above, the state information can be managed by page units, and for example, information associated with errors that occurred in a read operation previously performed on each page can be managed. The information associated with the error may include a bit error rate or the number of errors that occurred in each page. Alternatively, the information associated with the error may include information indicating whether the number of errors is greater than a criterion, and, for example, the information associated with the error may be processed in various forms.

[0128] Based on various schemes, the ECC circuit 612 may generate an error detection result of the data, and the error information generator 613 may generate write status information Info_ws including information associated with a previous error value. The write status information Info_ws may be provided to the storage device 620. The storage device 620 may store the status information Info_S, and the status information Info_S may include information about a previous error value of each page of each block. For example, Fig.15 As shown, the first to Mth previous error values ​​Err_Val_P1 to PM(BLK 1) can be stored in the memory cell array 621 in association with the M pages of the first block BLK 1, and the first to Mth previous error values ​​Err_Val_P1 to PM(BLK N) can be stored in the memory cell array 621 in association with the M pages of the Nth block BLK N.

[0129] The memory controller 610 may output a status information request command CMD_Q issuing a request to transfer the status information Info_S, and may output an address ADD_Q indicating the location of the page for which the status information Info_S is required. The memory controller 610 may receive the status information Info_S, and based thereon, the memory controller 510 may determine the degradation state of the memory cells of the page. In some example embodiments, the memory controller 610 may output a control signal Ctrl_RA based on the status information Info_S to allow execution of a recovery algorithm optimized or desired for the degradation state.

[0130] Fig.16 is a flowchart illustrating a method of operating a storage system according to some example embodiments.

[0131] Before performing a read operation on the Nth page, the memory controller may output a status information request command corresponding to the Nth page to the storage device, and may receive status information about the Nth page from the storage device in operation S31. In addition, in operation S32, the memory controller may determine the degree of degradation of the memory cells of the Nth page based on the status information, and may determine whether the degree of degradation is less than a reference value. For example, when the degree of degradation is less than the reference value, because the degree of degradation of the memory cells of the Nth page is not large, an ECC decoding process using normal data (e.g., HD data according to the above-described example embodiment) may be performed together with performing a normal read operation in operation S33.

[0132] It may be determined in operation S34 whether there is an uncorrectable erroneous UECC in the data of the Nth page, and when there is no uncorrectable erroneous UECC, the read operation may be completed in operation S37. On the other hand, when there is an uncorrectable erroneous UECC, recovery algorithms that consume different resources and time and have various error recovery capabilities may be sequentially executed. For example, a first recovery algorithm may be executed on the data of the Nth page in operation S35, and when the error is recovered, the read operation may be completed in operation S37. On the other hand, when the error is not recovered by the first recovery algorithm, the next recovery algorithm may be executed, and the Nth recovery algorithm may be finally executed in operation S36. When the error is not recovered by the Nth recovery algorithm, it may be finally determined that the reading of the data has failed, and when the error is recovered by the Nth recovery algorithm, the read operation may be completed in operation S37.

[0133] In addition, when it is determined based on the state information that the degree of degradation is greater than the reference value, the execution of at least one recovery algorithm may be skipped based on the degree of degradation. For example, when the degree of degradation is greater than the reference value and is relatively low, a recovery algorithm may be executed to perform an ECC decoding process using two pieces of SD data using two offset read levels. On the other hand, when the degree of degradation is greater than the reference value and is relatively high, a recovery algorithm for detecting an optimal or expected valley value between threshold voltage distributions may be executed, or a recovery algorithm may be executed to perform an ECC decoding process using three or more pieces of SD data, or a recovery algorithm for recovering errors may be executed by using read request data such as RAID and other data together.

[0134] Fig.17 is a block diagram illustrating an example in which a memory system according to some example embodiments is applied to an SSD system 700 .

[0135] refer to Fig.17 , the SSD system 700 may include a host 710 and an SSD 720. The SSD 720 may send or receive a signal SIG to or from the host 710 through a signal connector, and may be powered PWR through a power connector. The SSD 720 may include an SSD controller 721, an auxiliary power supply 722, and non-volatile memory devices 723_1 to 723_n. The non-volatile memory devices 723_1 to 723_n may include NAND flash memories. In this case, the SSD 720 may be powered PWR by using the above reference. Figures 1 to 16 The described example embodiment implements SSD 720 .

[0136] For example, the SSD controller 721 included in the SSD 720 may include a memory interface 721_1 and a status information processor 721_2 according to the above-described example embodiment, and each of the non-volatile storage devices 723_1 to 723_n may store status information (not shown). In addition, the SSD controller 721 and the non-volatile storage devices 723_1 to 723_n may communicate with each other through a plurality of channels, and the command / address channel may be physically separated from the data channel. In addition, the SSD controller 721 and the non-volatile storage devices 723_1 to 723_n may transmit the status information request command and the status information according to the above-described example embodiment through the command / address channel. In addition, the SSD controller 721 may control the storage operation of each of the non-volatile storage devices 723_1 to 723_n with reference to the status information, and may, for example, adjust the read level, adjust the type of read data, and control the ECC decoding process and the recovery operation.

[0137] Any of the elements and / or functional blocks disclosed above may include or be implemented in a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include an electrical component such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include an electronic component such as a logic gate, and the logic gate includes at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0138] In the above, example embodiments have been described in the drawings and the specification. Example embodiments have been described by using the terms described herein, but this is only used to describe the inventive concept and is not used to limit the meaning of the inventive concept defined in the appended claims or to limit its scope. Therefore, it can be understood by those of ordinary skill in the art that various modifications and other example embodiments can be implemented according to the inventive concept. Therefore, the spirit and scope of the inventive concept can be defined based on the spirit and scope of the appended claims.

[0139] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An operating method for controlling a memory controller of a storage device, the operating method comprising: transmitting a first read command corresponding to a first unit region of a storage device through a first channel; receiving first data read from the first cell region from a storage device through a second channel physically separated from the first channel; transmitting a status information request command through the first channel, the status information request command requesting transmission of status information about a second unit area of ​​the storage device; receiving status information about the second unit region from the storage device via the first channel; as well as transmitting a second read command corresponding to a second unit area of ​​the storage device through the first channel, At least a portion of a time period for receiving the state information through the first channel overlaps with a time period for receiving the first data through the second channel.

2. The operating method according to claim 1, wherein The second unit region corresponds to a page included in one block included in the memory device, and The status information request command includes address information indicating a location of the second unit area.

3. The operating method according to claim 1, wherein: Status information is Generated by the memory controller, is stored in the memory cell array of the storage device, is read from the memory cell array in response to a status information request command, and is received via the first channel.

4. The operating method according to claim 1, wherein: At least a portion of a period during which the status information request command is transmitted through the first channel overlaps with a period during which the first data is received through the second channel.

5. The operating method according to claim 1, further comprising: A read level in a read operation on the second cell region is controlled based on a degradation state of each memory cell of the second cell region, the degradation state being determined based on the state information.

6. The operating method according to claim 1, wherein The state information includes information associated with a read level in a read operation previously performed on a second cell region of the memory device, and The operating method further includes controlling a read level in a read operation on the second cell region to correspond to a read level included in the state information.

7. The operating method according to claim 1, wherein the second read command includes a first type of command issuing a request to output hard decision (HD) data based on a normal read level, or the second read command includes a second type of command issuing a request to output soft decision (SD) data based on at least one offset read level together with the HD data, and Based on the status information, when the degradation degree of the memory cells of the second cell region is greater than a specific threshold, the second read command includes the second type of command.

8. The operating method according to claim 7, further comprising: receiving second data from the storage device through a second channel, the second data including HD data and SD data each read from the second unit area; as well as An SD error correction code (ECC) decoding process using the HD data and the SD data is performed on the second data, while an HD ECC decoding process using the HD data is not performed.

9. The operating method according to claim 1, further comprising: receiving second data from the storage device via a second channel, the second data being read from the second cell region; as well as When an uncorrectable error occurs in the second data, a recovery operation for recovering the error is performed, wherein a plurality of recovery modules associated with error recovery are applied to the memory controller, and A recovery module executed for recovering an error of the second data is selected differently based on the state information.

10. The operating method according to claim 1, further comprising: receiving second data from the storage device via a second channel, the second data being read from the second cell region; transmitting a status information request command through the first channel, the status information request command requesting transmission of status information about a third unit area of ​​the storage device; as well as receiving status information about the third unit area from the storage device via the first channel, At least a portion of a period during which the state information about the third unit region is received through the first channel overlaps with a period during which the second data is received through the second channel.

11. A memory controller for communicating with a storage device, the memory controller comprising: a processor configured to control storage operations on the storage device; A memory interface connected to a storage device via a first channel for transmitting commands / addresses and a second channel for transmitting data, the second channel being physically separated from the first channel; an error correction code (ECC) circuit configured to perform an ECC decoding process on data read from the storage device to correct errors in the read data; as well as a state information processor configured to receive and process state information transmitted from the storage device through the first channel, the state information indicating a degradation state of a storage unit of the storage device, The memory controller is configured to receive status information about the first cell region through a first channel before performing a read operation on the first cell region of the memory cell array of the memory device, and The processor is configured to differently control a read level in a read operation on the first cell region or differently perform an error correction or recovery operation on data read from the first cell region according to a degradation state of a memory cell of the first cell region based on the state information.

12. The memory controller of claim 11, wherein The memory interface is configured to output status information request commands, and The status information request command issues a request for transferring status information on the first unit area through the first channel.

13. The memory controller of claim 12, wherein The memory interface is configured to output a read command corresponding to the second cell area of ​​the memory cell array through the first channel before outputting a status information request command corresponding to the first cell area, and At least a portion of a period during which state information on the first cell region is received through the first channel overlaps with a period during which data read from the second cell region is received through the second channel.

14. The memory controller according to claim 11, wherein: The memory cell array includes a plurality of blocks, and each of the plurality of blocks includes a plurality of pages, The first unit region corresponds to one of the plurality of pages, and status information is received in units of one or more pages each including the first unit region.

15. The memory controller according to claim 11, wherein: The status information includes at least one selected from the following: an on-chip valley search (OVS) count value corresponding to a difference between the number of on cells and the number of off cells determined based on at least two read levels, a read level applied to at least one read operation previously performed on the memory device, Write or erase count values, corresponding to the memory cell array, or An error value occurred in at least one previously performed read operation.

16. The memory controller according to claim 15, wherein: At least one piece of status information is stored in a memory cell array, and the status information is read from the memory cell array and received through the first channel.

17. The memory controller according to claim 11, wherein: The memory interface is configured to output a read command for issuing a request to output hard decision (HD) data based on a normal read level on a first cell region based on the status information, or to output a read command for issuing a request to output soft decision (SD) data based on at least one offset read level as well as the HD data on the first cell region.

18. A storage system comprising: Storage devices, including, A memory cell array, comprising a plurality of pages, each page comprising a plurality of memory cells; control logic configured to control storage operations on the memory cell array and generate status information representing a degradation state of the plurality of memory cells; as well as The interface circuit is configured to transmit commands / addresses through a first channel and transmit data through a second channel physically separated from the first channel, The interface circuit is configured as: sequentially receiving a first read command corresponding to the first page and a second read command corresponding to the second page from outside the memory device, receiving a status information request command that issues a request for transferring status information about the second page through the first channel before receiving the second read command, outputting status information about the second page via the first channel, and In parallel with outputting status information about the second page, data of the first page read in response to the first read command is output through the second channel.

19. The storage system according to claim 18, further comprising: a memory controller configured to communicate with the memory device through a first channel and a second channel and output a first read command and a second read command and a status information request command, The memory controller is configured to control a read level in a read operation on the second page differently or to perform error correction or recovery operations on data read from the second page differently according to a degradation state of each memory cell in the second page based on status information about the second page.

20. The storage system of claim 18, wherein The state information is stored in the memory cell array and includes information associated with a read level in a read operation previously performed on a plurality of pages, and The memory device is configured to output status information to the memory controller in response to a status information request command from the memory controller, the status information being associated with a read level in a read operation performed on the second page.

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