Verification method and device of memory ECC function, electronic equipment and storage medium

Abstract

The invention relates to the technical field of integrated circuits, and provides a memory ECC function verification method and device, electronic equipment and a storage medium. The method comprises the steps that when a first read command is executed, first error data stored at an address is read from a memory according to the address included in the first read command, and the first error data comprises errors actively inserted by a verification platform; correcting the first error data according to a first variable corresponding to the address to obtain first corrected data, and recording whether each data bit of the first error data has an error or not by the first variable; acquiring second correction data obtained by correcting the first error data by the memory by using the ECC function; and comparing the first correction data with the second correction data, determining that the ECC function of the memory is normal when the comparison succeeds, and determining that the ECC function of the memory is abnormal when the comparison fails. According to the method, the complexity of an ECC function verification process can be reduced, and the verification efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a method, device, electronic device and storage medium for verifying an ECC function of a memory. Background Art

[0002] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), also known as memory, is one of the most commonly used data storage devices. In daily use, the internal data of the memory may be erroneous due to various factors. Therefore, the memory usually also has an error checking and correcting (ECC) function.

[0003] When an error occurs in the internal data of the memory, whether the ECC function correctly checks and corrects the error will greatly affect the memory performance, so the ECC function of the memory needs to be verified. However, the ECC function verification process of the prior art is very complicated, resulting in low verification efficiency. Summary of the invention

[0004] In view of this, the present disclosure proposes a memory ECC function verification method, device, electronic device and storage medium. The memory ECC function verification method of the present disclosure embodiment can reduce the complexity of the ECC function verification process and improve the verification efficiency.

[0005] According to one aspect of the present disclosure, a method for verifying an ECC function of a memory is provided, the method being applied to a verification platform, the method comprising: when a first read command is executed, according to an address included in the first read command, reading first error data stored at the address from a memory, the first error data comprising an error actively inserted by the verification platform; correcting the first error data according to a first variable corresponding to the address to obtain first corrected data, the first variable recording whether there is an error in each data bit of the first error data; obtaining second corrected data obtained by correcting the first error data using the ECC function of the memory; comparing the first corrected data with the second corrected data, determining that the ECC function of the memory is normal when the comparison is successful, and determining that the ECC function of the memory is abnormal when the comparison fails.

[0006] In one possible implementation, before executing the first read command, the method also includes: monitoring read-type commands, and when the first read command is detected, using the backdoor access function of the memory to read the first original data stored at the address; inserting an error into the first original data to obtain the first error data, and writing the first error data back to the address.

[0007] In a possible implementation, the first original data includes content data and a check code, and the data bit width of the first variable is equal to the sum of the bit width of the content data and the bit width of the check code.

[0008] In one possible implementation, inserting an error into the first original data includes: selecting at least one data bit from the first original data, inserting an error into each selected data bit, and inserting an error into each data bit at least once; wherein, a method of inserting an error once into any selected data bit is to invert the value of the data bit.

[0009] In a possible implementation, before correcting the first erroneous data according to the first variable corresponding to the address, the method further includes: generating the first variable according to a method of inserting an error into the first original data, wherein an initial value of each data bit of the first variable is 0, and each time an error is inserted into the i-th data bit in the first original data, the i-th data bit of the first variable is inverted once, and i is a positive integer.

[0010] In a possible implementation, the first error data is corrected according to the first variable corresponding to the address to obtain first corrected data, including: determining the number of erroneous data bits in the first error data according to the first variable; when the number of data bits meets a preset condition, performing an XOR operation on the first error data and the first variable to obtain first corrected data.

[0011] In a possible implementation manner, the preset condition is that the number of data bits is less than or equal to a first threshold.

[0012] In a possible implementation, after executing the first read command, the method further includes: when a first write command is executed and the first write command also includes the address, clearing the first variable.

[0013] In one possible implementation, the device is applied to a verification platform, and the device includes: a first reading module, which is used to read first error data stored at the address from a memory according to the address included in the first read command when executing a first read command, and the first error data includes an error actively inserted by the verification platform; a first correction module, which is used to correct the first error data according to a first variable corresponding to the address to obtain first corrected data, and the first variable records whether there is an error in each data bit of the first error data; a first acquisition module, which is used to obtain second corrected data obtained by correcting the first error data using an ECC function of the memory; and a comparison module, which is used to compare the first corrected data with the second corrected data, and determine that the ECC function of the memory is normal when the comparison is successful, and determine that the ECC function of the memory is abnormal when the comparison fails.

[0014] In one possible implementation, the device also includes: a monitoring module, used to monitor read-type commands before the device executes the first read command, and when the first read command is detected, use the backdoor access function of the memory to read the first original data stored at the address; an error insertion module, used to insert an error into the first original data, obtain the first error data, and write the first error data back to the address.

[0015] In a possible implementation, the first original data includes content data and a check code, and the data bit width of the first variable is equal to the sum of the bit width of the content data and the bit width of the check code.

[0016] In one possible implementation, inserting an error into the first original data includes: selecting at least one data bit from the first original data, inserting an error into each selected data bit, and inserting an error into each data bit at least once; wherein, a method of inserting an error once into any selected data bit is to invert the value of the data bit.

[0017] In a possible implementation, the device also includes: a first generating module, used to generate the first variable according to a method of inserting an error into the first original data before the device corrects the first erroneous data according to the first variable corresponding to the address, wherein the initial value of each data bit of the first variable is 0, and each time an error is inserted into the i-th data bit in the first original data, the i-th data bit of the first variable is inverted once, and i is a positive integer.

[0018] In a possible implementation, the first error data is corrected according to the first variable corresponding to the address to obtain first corrected data, including: determining the number of erroneous data bits in the first error data according to the first variable; when the number of data bits meets a preset condition, performing an XOR operation on the first error data and the first variable to obtain first corrected data.

[0019] In a possible implementation manner, the preset condition is that the number of data bits is less than or equal to a first threshold.

[0020] In a possible implementation, the device further includes: a clearing module, configured to clear the first variable after the device executes the first read command and when a first write command is executed and the first write command also includes the address.

[0021] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0022] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0023] According to another aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0024] According to the verification method of the memory ECC function of the embodiment of the present disclosure, when the first read command is executed, according to the address included in the first read command, the first error data stored at the address is read from the memory, and the first error data includes the error actively inserted by the verification platform; according to the first variable corresponding to the address, the first error data is corrected to obtain the first correction data, and the first variable records whether each data bit of the first error data has an error; the memory uses the ECC function to correct the first error data to obtain the second correction data; the first correction data and the second correction data are compared, and when the comparison is successful, it is determined that the ECC function of the memory is normal, and when the comparison fails, it is determined that the ECC function of the memory is abnormal. Since only one variable is needed to indicate the error insertion mode of the data stored at a certain address, the number of variables that the verification platform needs to maintain is reduced, and the verification complexity of the platform is reduced; when verifying whether the ECC function correctly corrects the error data stored at a certain address, the verification platform only needs to compare once, further reducing the verification complexity of the verification platform. Thereby improving the verification efficiency.

[0025] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0027] Figure 1 An exemplary application scenario of the method for verifying the ECC function of a memory according to an embodiment of the present disclosure is shown.

[0028] Figure 2 A schematic diagram showing the process of a method for verifying the ECC function of a memory according to an embodiment of the present disclosure.

[0029] Figure 3 A schematic diagram showing the process of a method for verifying the ECC function of a memory according to an embodiment of the present disclosure.

[0030] Figure 4 A schematic diagram showing the structure of a verification device for an ECC function according to an embodiment of the present disclosure.

[0031] Figure 5 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0033] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0034] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0035] The principle of ECC function verification and the ECC function verification process of the prior art are introduced below.

[0036] DDR includes a memory controller (DDR Controller, DDRC), a physical layer interface (Physical, PHY), and a data memory (Memory). DDRC is responsible for controlling the data storage / reading process. PHY is a key component connecting DDRC and data memory, and is mainly responsible for data transmission and data processing at the physical layer. The data memory is used to store data.

[0037] In actual applications, the read / write commands from the upstream processor are transmitted to the data memory through DDRC and PHY in sequence, and data is read from / written to the data memory. The role of the ECC function is to generate a corresponding check code based on the characteristics of the data stored in the data memory, and store the check code together with the data in the data memory. When reading data from DDR, the corresponding check code is also read to check whether the characteristics of the read data are consistent with the characteristics indicated by the read check code. If they are consistent, the read data is determined to be correct. If they are inconsistent, the read data is determined to be wrong and corrected.

[0038] The ECC function usually supports 1-bit correction and 2-bit error detection, that is, if only 1-bit of the read data is erroneous, the ECC function can determine the location of the error and correct the error. If 2-bit of the read data is erroneous, the ECC function can only determine that the data is erroneous but cannot determine the specific location of the error or correct the error. If more than 2 bits of the read data are erroneous, there is no guarantee that the data error can be determined, nor can the specific location of the error be determined or the error corrected.

[0039] Verification of ECC includes two main steps, one is inserting errors, and the other is checking. For the insertion error part, in the prior art, errors are usually inserted when the read data passes through the interface between DDRC and PHY, or when the read data passes through the interface between PHY and data storage. This method of inserting errors requires the maintenance of additional signals, which increases the verification complexity of the verification platform. Second, the timing of the error is different from the actual application scenario. In some scenarios, the verification platform may misidentify the error. Third, it is difficult to accurately control the position of the inserted error. For the inspection part, the prior art records the insertion method of the error by defining multiple variables (such as: error_addr, 1bit_error, err_position, 2bit_error, etc.). During the inspection, the correct data is predicted based on multiple variables, and the correct data is compared with the data corrected by the ECC function to confirm whether the ECC function is normal. This inspection method requires the maintenance of multiple variables and multiple comparisons, which further increases the verification complexity of the verification platform.

[0040] In summary, the ECC function verification process in the prior art is very complex, resulting in low verification efficiency.

[0041] In view of this, the present disclosure proposes a memory ECC function verification method, device, electronic device and storage medium. The memory ECC function verification method of the present disclosure embodiment can reduce the complexity of the ECC function verification process and improve the verification efficiency.

[0042] Figure 1 An exemplary application scenario of the method for verifying the ECC function of a memory according to an embodiment of the present disclosure is shown.

[0043] like Figure 1 As shown, in an exemplary application scenario, a memory to be verified for ECC function and a verification platform may be included. The verification platform is responsible for inserting errors into the data stored in the memory and executing the verification method for the memory ECC function of the embodiment of the present disclosure to verify whether the ECC function of the memory is normal.

[0044] The memory may be a physical memory or a code form that has not yet been put into production. The verification platform may be a hardware platform or a software platform. The embodiments of the present disclosure do not limit the specific form of the memory or the specific form of the verification platform.

[0045] Figure 2 A schematic diagram showing the process of a method for verifying the ECC function of a memory according to an embodiment of the present disclosure.

[0046] like Figure 2As shown, in a possible implementation, the method is applied to a verification platform, and the method includes:

[0047] Step S21, when a first read command is executed, first error data stored at the address included in the first read command is read from the memory, wherein the first error data includes an error actively inserted by the verification platform;

[0048] Step S22, correcting the first error data according to the first variable corresponding to the address to obtain first corrected data, the first variable recording whether each data bit of the first error data has an error;

[0049] Step S23, obtaining second corrected data obtained by correcting the first erroneous data using an ECC function of the memory;

[0050] Step S24, comparing the first corrected data and the second corrected data, and determining that the ECC function of the memory is normal when the comparison is successful, and determining that the ECC function of the memory is abnormal when the comparison fails.

[0051] For example, the verification platform can execute test cases, and the test cases are used to simulate the scenario of reading / writing data in the memory, so the test cases may include multiple read type commands and multiple write type commands. Each command includes an address, wherein the address included in the read command is the address where the data is stored to be read, and the address included in the write command is the address where the data is to be written.

[0052] Assume that the multiple read-type commands include a first read command, which is a command for reading data and includes the storage address of the first error data. When the verification platform executes the first read command, step S21 can be executed to read the first error data stored at the address included in the first read command from the memory. At this time, the first error data already includes the error actively inserted by the verification platform. An example of the verification platform actively inserting an error is given later.

[0053] Since the error is actively inserted by the verification platform, when inserting an error into the data stored at the address included in the first read command, the verification platform can generate a first variable corresponding to the address, so that the first variable can record whether there is an error in each data bit of the first error data. An example of generating the first variable is given later. After reading the first error data, step S22 can be executed to correct the first error data according to the first variable corresponding to the address included in the first read command to obtain the first corrected data, and the first corrected data is correct data. An example of correcting the first error data is given later.

[0054] Since the first error data read in step S21 includes an error, when the error included in the first error data is an error that can be corrected by the ECC function, the memory will use the ECC function to correct the first error data to obtain the second corrected data. If the ECC function of the memory is normal, the second corrected data should also be correct data and consistent with the first corrected data. If the ECC function of the memory is abnormal, the second corrected data will be inconsistent with the first corrected data.

[0055] Therefore, after executing step S21 to read the first error data, step S23 may be executed to obtain second corrected data obtained by correcting the first error data using the ECC function of the memory.

[0056] If the second correction data is successfully obtained and the first correction data has also been obtained, step S24 can be executed to compare the first correction data with the second correction data, and a verification result can be obtained according to the comparison result. Among them, when the first correction data and the second correction data are consistent, the comparison between the first correction data and the second correction data is successful, and the verification result can be determined to be that the ECC function of the memory is normal. When the first correction data and the second correction data are inconsistent, the comparison between the first correction data and the second correction data fails, and the verification result can be determined to be that the ECC function of the memory is abnormal.

[0057] The embodiment of the present disclosure does not limit the execution order of step S22 and step S23, as long as step S22 and step S23 are both executed after step S21 and before step S24.

[0058] According to the verification method of the memory ECC function of the embodiment of the present disclosure, when the first read command is executed, according to the address included in the first read command, the first error data stored at the address is read from the memory, and the first error data includes the error actively inserted by the verification platform; according to the first variable corresponding to the address, the first error data is corrected to obtain the first correction data, and the first variable records whether each data bit of the first error data has an error; the memory uses the ECC function to correct the first error data to obtain the second correction data; the first correction data and the second correction data are compared, and when the comparison is successful, it is determined that the ECC function of the memory is normal, and when the comparison fails, it is determined that the ECC function of the memory is abnormal. Since only one variable is needed to indicate the error insertion mode of the data stored at a certain address, the number of variables that the verification platform needs to maintain is reduced, and the verification complexity of the platform is reduced; when verifying whether the ECC function correctly corrects the error data stored at a certain address, the verification platform only needs to compare once, further reducing the verification complexity of the verification platform. Thereby improving the verification efficiency.

[0059] The following is an example of a verification platform actively inserting errors. Figure 3A schematic diagram showing the process of a method for verifying the ECC function of a memory according to an embodiment of the present disclosure.

[0060] like Figure 3 As shown, in a possible implementation, before executing the first read command, the method further includes:

[0061] Step S31, monitoring the read type commands, and when a first read command is detected, using the backdoor access function of the memory to read the first original data stored at the address included in the first read command;

[0062] Step S32, inserting an error into the first original data to obtain first error data, and writing the first error data back to the address included in the first read command.

[0063] For example, after the verification platform starts to execute the verification method of the memory ECC function of the embodiment of the present disclosure, it can first use the verification IP (VIP) or the monitor (monitor) of the verification platform to monitor the read type command. The embodiment of the present disclosure does not limit the specific method for the verification platform to monitor the read type command. When the first read command is detected, step S31 can be executed to use the backdoor access function of the memory to read the first original data stored at the address included in the first read command. The first original data can be correct data.

[0064] The backdoor access function of the memory is a function already existing in the prior art, and the backdoor access function of the memory is not described here. Those skilled in the art should understand that it is also possible to use direct memory access (Direct Programming Interface, DPI) and other technologies to directly read or modify the data stored in the data memory without going through the interface between DDRC, PHY, and data memory. The present disclosure does not limit the specific method of reading the first original data stored at the address included in the first read command.

[0065] After reading the first original data, step S32 may be executed to insert an error into the first original data to obtain first error data, and the first error data may be written back to the address included in the first read command. The backdoor access function of the memory may still be used when writing the first error data back.

[0066] In this way, the error is not inserted during the data reading process, but has already appeared in the data storage before the data is read, which is more consistent with the error appearance in real scenarios and improves the error recognition accuracy of the verification platform. And when inserting errors, there is no need to maintain additional signals, which can reduce the verification complexity of the verification platform.

[0067] In a possible implementation, the first original data includes content data and a check code, and the data bit width of the first variable is equal to the sum of the bit width of the content data and the bit width of the check code.

[0068] For example, since the memory has an ECC function, the check code is also stored in the data storage device, so the first original data may include content data and a check code corresponding to the content data. The check code may indicate a feature of the content data, for example, it may indicate the number of "0"s in the content data. The embodiments of the present disclosure do not limit the specific setting method of the check code.

[0069] For example, when the content data is 1111 1111, the number of "0" in the content data is 0, and the check code may be 000. When the content data is 1010 1010, the number of "0" in the content data is 4, and the check code may be 100.

[0070] The data bit width of the first variable can be made equal to the sum of the bit width of the content data and the bit width of the check code. In this case, the data bits of the first variable can correspond one-to-one with the data bits of the first original data, and also correspond one-to-one with the data bits of the first error data, so that the value of each data bit of the first variable can indicate whether there is an error in the corresponding data bit in the first error data, so that the first variable can completely represent the number and position of error data bits in the first error data, and can support the representation of errors with any number of error data bits and any position.

[0071] Furthermore, when the data bit width of the first variable is equal to the sum of the bit width of the content data and the bit width of the check code, the verification platform is supported to insert errors into both the content data and the check code of the first original data, thereby improving the flexibility of the error insertion method.

[0072] An exemplary method of inserting errors into the first original data and an exemplary method of generating the first variable are introduced below.

[0073] In a possible implementation manner, inserting an error into the first original data includes:

[0074] Select at least one data bit from the first original data, insert an error into each of the selected data bits, and insert an error into each data bit at least once;

[0075] The method of inserting an error into any selected data bit is to invert the value of the data bit.

[0076] For example, when inserting an error into the first original data, at least one data bit may be selected from the first original data, and an error may be inserted into each of the selected data bits, with each data bit having at least one error inserted therein. The at least one data bit may be selected randomly or in other ways, and the present disclosure does not limit this. The method of inserting an error into any selected data bit may be to invert the value of the data bit.

[0077] In this case, when an odd number of errors are inserted into any selected data bit, the value of the data bit is different from the value before the errors are inserted; when an even number of errors are inserted into any selected data bit, the value of the data bit is the same as the value before the errors are inserted. Therefore, the verification platform can be further configured to insert an odd number of errors into each selected data bit to improve the confidence level of the verification result obtained by the verification method of the memory ECC function.

[0078] When there is an upper limit on the number of erroneous data bits that the ECC function can support correcting (assuming it is equal to the first threshold), the number of selected data bits can also be made less than or equal to the first threshold so that a verification result can be obtained after each error insertion.

[0079] In one example, assuming that the first original data is 1111 1111, when the first threshold is equal to 1, one data bit may be selected from the first original data, for example, the first data bit is selected to insert an error. Assuming that one error is inserted, the first data bit of the first original data is inverted to obtain 0111 1111 as the first error data.

[0080] Since the verification method of the ECC function of the memory disclosed in the present invention is to directly insert the error into the data storage, and the storage address of the data in the data storage is more stable, the position to insert the error can be found quickly and accurately, thereby improving the error insertion accuracy and insertion efficiency.

[0081] Those skilled in the art should understand that the verification platform of the embodiment of the present disclosure may also adopt other existing technologies to insert errors to obtain first error data, and the present disclosure does not limit the method for obtaining the first error data.

[0082] An exemplary method of generating the first variable is described below.

[0083] In a possible implementation, before correcting the first erroneous data according to the first variable corresponding to the address included in the first read command, the method further includes:

[0084] A first variable is generated according to a method of inserting an error into the first original data, wherein,

[0085] The initial value of each data bit of the first variable is 0. Each time an error is inserted into the i-th data bit in the first original data, the i-th data bit of the first variable is inverted once, where i is a positive integer.

[0086] For example, the initial value of each data bit of the first variable may be set to 0. For example, assuming that the first original data is 1111 1111, the initial value of the first variable may be 0000 0000.

[0087] Each time an error is inserted into the ith data bit in the first original data, the ith data bit of the first variable may be inverted once. For example, when i=1, after inserting an error into the first data bit once, the first variable may be 1000 0000.

[0088] In this way, each data bit of the first variable can indicate whether an error occurs in the first error data. The first variable can be generated while inserting an error, so that the first variable can accurately indicate the real-time error state of the first error data, avoiding errors in the first corrected data obtained according to the first variable.

[0089] In the prior art, in the case of multiple insertion errors, the error state after each insertion error needs to be analyzed respectively, and finally the data to be compared with the correction data generated by the ECC function is obtained. Therefore, the ECC verification process is very complicated in the case of multiple insertion errors. In the embodiment of the present disclosure, even if the same data bit is inserted with errors multiple times, the final error state of the first error data can be quickly determined according to the first variable, and the first correction data can be obtained quickly and accurately.

[0090] For example, the initial value of the first variable can be set to 0000 0000, and the first original data is 111111111. Assuming that two errors are inserted into the first data bit of the first original data, after the first error insertion, the first original data can be changed to 0111 1111, and the first variable can be 1000 0000; after the second error insertion, the first original data can be changed to 11111111 (that is, the first error data), and the first variable can be 0000 0000.

[0091] In this case, the actual value of the first variable is the same as the initial value of the first variable, so it can be determined based on the first variable that the first error data is actually the same as the first original data, and the first error data is not wrong. The XOR result of the first error data and the first variable is 1111 1111, which is the first corrected data. The first corrected data is correct data, so the correct data can be obtained by a single XOR.

[0092] Those skilled in the art should understand that the first variable may also be in other forms, such as recording the serial number of the data bit in which an error occurs in the first error data, etc. As long as the first variable can indicate whether an error occurs in each data bit in the first error data, the embodiments of the present disclosure do not limit the specific content of the first variable.

[0093] The following describes an example in which the verification platform corrects the first erroneous data.

[0094] In a possible implementation, correcting the first erroneous data according to the first variable corresponding to the address included in the first read command to obtain the first corrected data includes:

[0095] Determine the number of erroneous data bits in the first erroneous data according to the first variable;

[0096] When the number of data bits meets a preset condition, an XOR is performed on the first error data and the first variable to obtain first corrected data.

[0097] For example, the number of erroneous data bits in the first error data can be determined based on the first variable. If the number of data bits meets the preset condition, it can be considered that the first error data is correctable by the ECC function of the memory. Therefore, when the number of data bits meets the preset condition, the first error data and the first variable can be XORed to obtain the first corrected data.

[0098] For example, the first error data is 0111 1111, and the first variable is 1000 0000, then the first corrected data 1111 1111 can be obtained after XORing the two, which is consistent with the first original data.

[0099] In this way, the verification platform can correctly correct the first erroneous data only according to the first variable.

[0100] Those skilled in the art should understand that there are more ways to correct the error in the first error data according to the first variable. For example, when the initial value of the first variable is 1, the first error data and the first variable may be XORed. The embodiments of the present disclosure do not limit the specific implementation of correcting the error in the first error data according to the first variable.

[0101] In a possible implementation manner, the preset condition is that the number of data bits is less than or equal to a first threshold.

[0102] It is understandable that if the error inserted in the first error data is an uncorrectable error, the second corrected data may not be successfully obtained, and even if the first corrected data is obtained, it cannot be compared. Therefore, when the error inserted in the first error data is an uncorrectable error, steps S22-S24 are not necessary.

[0103] The maximum value of the error data bits that can be corrected by the ECC function of the memory can be a first threshold value, and the embodiment of the present disclosure does not limit the specific value of the first threshold value. In this case, the preset condition can be that the number of data bits is less than or equal to the first threshold value, so that the number of data bits that meet the preset condition belongs to the number of error data bits that can be corrected by the ECC function.

[0104] It can be understood that the setting method of the preset conditions is related to the number of erroneous data bits that can be corrected by the ECC function. As long as the number of data bits that meet the preset conditions is within the number of erroneous data bits that can be corrected by the ECC function, the embodiments of the present disclosure do not limit the specific setting method of the preset conditions.

[0105] In a possible implementation, after executing the first read command, the method further includes:

[0106] When the first write command is executed and the first write command also includes the address (the address included in the first read command), the first variable is cleared.

[0107] For example, as described above, the test case includes multiple write commands. Assuming that the multiple write commands include a first write command, and the first read command and the first write command include the same address, the first write command can be a command to write data to the address. If the verification platform executes the first read command and then executes the first write command, it means that new data will be written to the address included in the first read command, and the data originally stored at the address is invalid. In this case, the first variable corresponding to the address is also invalid, and the first variable can be cleared. In this way, the total number of variables that need to be maintained by the verification platform can be reduced.

[0108] In one example, the first variable may be a variable of an associative array type defined in the SystemVerilong language (SV for short) of the prior art, and its index may be an address in a data storage device corresponding to the first variable. The disclosed embodiment does not limit the specific type of the first variable. Accordingly, the $countones() function defined in SV may be used to count the number of erroneous data bits in the first error data. The disclosed embodiment does not limit which function is used to determine the number of erroneous data bits in the first error data.

[0109] SV language is a commonly used hardware description language, which facilitates the wide application of the verification method of the ECC function of the memory. Those skilled in the art should understand that other hardware description languages ​​can also be used to define the first variable and use functions of other hardware description languages ​​to count the number of erroneous data bits in the first erroneous data, and the embodiments of the present disclosure are not limited to this.

[0110] The present disclosure also provides a verification device for the ECC function of a memory, Figure 4 A schematic diagram showing the structure of a verification device for an ECC function according to an embodiment of the present disclosure.

[0111] like Figure 4 As shown, in a possible implementation, the device is applied to a verification platform, and the device includes:

[0112] A first reading module 41 is used for reading first error data stored at an address included in the first reading command from a memory when executing a first reading command, wherein the first error data includes an error actively inserted by the verification platform;

[0113] A first correction module 42, configured to correct the first error data according to a first variable corresponding to the address to obtain first corrected data, wherein the first variable records whether each data bit of the first error data has an error;

[0114] A first acquisition module 43 is used to acquire second corrected data obtained by the memory using an ECC function to correct the first erroneous data;

[0115] The comparison module 44 is used to compare the first corrected data with the second corrected data, and determine that the ECC function of the memory is normal when the comparison is successful, and determine that the ECC function of the memory is abnormal when the comparison fails.

[0116] In one possible implementation, the device also includes: a monitoring module, used to monitor read-type commands before the device executes the first read command, and when the first read command is detected, use the backdoor access function of the memory to read the first original data stored at the address; an error insertion module, used to insert an error into the first original data, obtain the first error data, and write the first error data back to the address.

[0117] In a possible implementation, the first original data includes content data and a check code, and the data bit width of the first variable is equal to the sum of the bit width of the content data and the bit width of the check code.

[0118] In one possible implementation, inserting an error into the first original data includes: selecting at least one data bit from the first original data, inserting an error into each selected data bit, and inserting an error into each data bit at least once; wherein, a method of inserting an error once into any selected data bit is to invert the value of the data bit.

[0119] In a possible implementation, the device also includes: a first generating module, used to generate the first variable according to a method of inserting an error into the first original data before the device corrects the first erroneous data according to the first variable corresponding to the address, wherein the initial value of each data bit of the first variable is 0, and each time an error is inserted into the i-th data bit in the first original data, the i-th data bit of the first variable is inverted once, and i is a positive integer.

[0120] In a possible implementation, the first error data is corrected according to the first variable corresponding to the address to obtain first corrected data, including: determining the number of erroneous data bits in the first error data according to the first variable; when the number of data bits meets a preset condition, performing an XOR operation on the first error data and the first variable to obtain first corrected data.

[0121] In a possible implementation manner, the preset condition is that the number of data bits is less than or equal to a first threshold.

[0122] In a possible implementation, the device further includes: a clearing module, configured to clear the first variable after the device executes the first read command and when a first write command is executed and the first write command also includes the address.

[0123] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0124] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0125] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0126] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0127] Figure 51 is a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Figure 5 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0128] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2003. TM , Mac OS X TM , Unix TM ,Linux TM , FreeBSD TM or similar.

[0129] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0130] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0131] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0132] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0133] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0134] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0135] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0136] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0137] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0138] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for verifying the ECC function of a memory, characterized in that: The method is applied to a verification platform, and the method comprises: When a first read command is executed, first error data stored at the address included in the first read command is read from a memory, wherein the first error data includes an error actively inserted by the verification platform; Correcting the first error data according to a first variable corresponding to the address to obtain first corrected data, wherein the first variable records whether each data bit of the first error data has an error; Acquire second corrected data obtained by correcting the first erroneous data using an ECC function of the memory; The first corrected data and the second corrected data are compared, and when the comparison is successful, it is determined that the ECC function of the memory is normal, and when the comparison fails, it is determined that the ECC function of the memory is abnormal.

2. The method according to claim 1, characterized in that: Before executing the first read command, the method further includes: Monitoring a read-type command, and when the first read command is detected, using the backdoor access function of the memory to read the first original data stored at the address; Insert an error into the first original data to obtain the first error data, and write the first error data back to the address.

3. The method according to claim 2, characterized in that The first original data includes content data and a check code, and the data bit width of the first variable is equal to the sum of the bit width of the content data and the bit width of the check code.

4. The method according to claim 2, characterized in that: The inserting an error into the first original data comprises: Select at least one data bit from the first original data, insert an error into each of the selected data bits, and insert an error into each data bit at least once; The method of inserting an error into any selected data bit is to invert the value of the data bit.

5. The method according to claim 2, characterized in that: The method further comprises: The first variable is generated according to a method of inserting errors into the first original data, wherein, The initial value of each data bit of the first variable is 0. Each time an error is inserted into the i-th data bit of the first original data, the i-th data bit of the first variable is inverted once, and i is a positive integer.

6. The method according to claim 5, characterized in that The step of correcting the first erroneous data according to the first variable corresponding to the address to obtain first corrected data includes: Determine the number of erroneous data bits in the first erroneous data according to the first variable; When the number of data bits meets a preset condition, an XOR operation is performed on the first error data and the first variable to obtain first corrected data.

7. The method according to claim 6, characterized in that The preset condition is that the number of data bits is less than or equal to a first threshold.

8. The method according to claim 1, characterized in that After executing the first read command, the method further includes: When a first write command is executed and the first write command also includes the address, the first variable is cleared.

9. A device for verifying the ECC function of a memory, characterized in that: The device is applied to a verification platform, and the device comprises: A first reading module is used for reading first error data stored at an address included in the first reading command from a memory when executing a first reading command, wherein the first error data includes an error actively inserted by the verification platform, and the first reading command is a command of any read type; A first correction module, used for correcting the first error data according to a first variable corresponding to the address to obtain first corrected data, wherein the first variable records whether each data bit of the first error data has an error; A first acquisition module, used for acquiring second corrected data obtained by the memory correcting the first erroneous data using an ECC function; A comparison module is used to compare the first corrected data and the second corrected data, and determine that the ECC function of the memory is normal when the comparison is successful, and determine that the ECC function of the memory is abnormal when the comparison fails.

10. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to implement the method described in any one of claims 1 to 8 when executing the instructions stored in the memory.

11. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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