FPGA-based satellite 5g downlink service configuration buffer

Abstract

The application relates to a satellite 5G industry service configuration buffer based on FPGA, which comprises an invalid information filtering module, a time reference generating module, a service rate buffering module, a DDR2 write information generating module, a DDR2 read information generating module, a DDR2 read-write control module and a DDR2 output information buffering module. The application searches the frame header and frame length of service input, analyzes the service type and service length, combines the BRAM to control the reading and writing of the DDR2, meets the large storage and flexible scheduling requirements of adaptive service types, sets the invalid information filtering and service rate buffering modules, reduces the buffering writing and reading pressure, solves the problem of too large instantaneous rate caused by time jitter of burst signals, and improves the buffering throughput.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic communication, in particular to a satellite 5G downlink service configuration buffer based on FPGA. BACKGROUND

[0002] In the fifth generation mobile communication new radio (NR) communication system, the modulated data of downlink service needs to be generated according to configuration information. The differences in user capability and demand result in the change of data rate, number of beams and service frame length of downlink configuration information. Moreover, for satellite communication system, due to large transmission jitter, the time of ground base station configuration information arriving at the payload has differences, and the traditional storage scheme is difficult to meet the requirements of time jitter and flexible service of 5G satellite communication system.

[0003] The prior art relates to a high-speed multi-channel cache and storage cooperative scheduling scheme based on SRAM (Static Random-Access Memory), but the memory needs to wait for the FIFO (First Input First Output) cache to be full of 256 words before issuing a read application to the SDRAM (Synchronous DRAM) control module. It is suitable for continuous systems and cannot be applied to 5G flexible burst communication. SUMMARY

[0004] In order to overcome at least one of the deficiencies in the prior art, the present application provides a satellite 5G downlink service configuration buffer based on FPGA.

[0005] In a first aspect, a satellite 5G downlink service configuration buffer based on FPGA is provided, comprising: an invalid information filtering module, a time reference generating module, a service rate buffer module, a DDR2 write information generating module, a DDR2 read information generating module, a DDR2 read-write control module and a DDR2 output information cache module.

[0006] The invalid information filtering module receives the configuration data sent by the ground base station, filters the invalid data in the configuration data, and outputs the valid data packet.

[0007] The time reference generating module receives 1PPS and TOD information, and outputs a read enable signal, a write request signal, a read request and a read area according to the 1PPS and TOD information.

[0008] The service rate buffering module expands the parallel number of the valid data packets output by the invalid information filtering module, and writes the data with expanded parallel number into the first BRAM; a cache reading process is started, a frame header is searched, and the data corresponding to the frame length in the frame header is taken out after the frame header is searched, and the rate control data packet is output after the condition of allowing output is met; the condition of allowing output is that the read enable signal is valid, and no write operation is performed within the protection time interval, and there is valid data in the first BRAM;

[0009] The DDR2 write information generation module receives the rate control data packet output by the service rate buffering module, and performs frame analysis on the rate control data packet; and according to the write request signal and the frame analysis result, a write request, a write area, a write length and write data are output;

[0010] The DDR2 read information generation module caches the write length into the write area of the second BRAM according to the write request output by the DDR2 write information generation module; and according to the read request and the read area output by the time reference generation module, valid read request, valid read area and valid read length are output, and the corresponding storage content in the second BRAM is cleared;

[0011] The DDR2 read-write control module realizes write control of the MIG core according to the write request, the write area, the write data and the write length output by the DDR2 write information generation module; realizes read control of the MIG core according to the valid read request, the valid read area and the valid read length output by the DDR2 read information generation module; and outputs the cache data;

[0012] The DDR2 output information cache module receives the cache data output by the DDR2 read-write control module, and outputs the corresponding cache data according to the read request and the read area output by the modulator.

[0013] In one embodiment, the invalid information filtering module calculates the frame length of each data frame in the configuration data, and filters out the data frame if the calculated frame length does not match the frame length field in the data frame; and according to the frame type of the data frame, the data frame corresponding to the frame type that does not need to be cached is filtered out.

[0014] In one embodiment, the time reference generation module calculates the system frame number and the time slot number according to the 1PPS and TOD information, and performs cache reading 10 time slots in advance;

[0015] Suppose the number of frame types of the configuration content is Nclass, and the maximum frame length of each frame type is LENmax, the maximum frame length of the configuration content of all frame types is summed after each time slot starts, and a length of Nclass*LENmax is generated as an enable as a write request signal;

[0016] When the write request signal is 0, the read enable signal is valued as 1, indicating that no write is performed on the DDR2 at this moment, and the read operation can be performed;

[0017] When the read enable signal is 1, according to the number Nclass of frame types of the configuration content, Nclass pulse signals with an interval of LENmax are generated as read requests;

[0018] The system frame number, the time slot number and the frame type are spliced as the read area.

[0019] In one embodiment, the DDR2 write information generation module performs frame analysis on the speed control data packet to obtain a data frame structure; the system frame number, the time slot number, the beam number and the frame type in the data frame structure are spliced to generate a write area;

[0020] According to the frame length in the data frame structure, a write length is generated;

[0021] When the write request signal is 0, the DDR2 write information generation module buffers the input data and stops output; when the write request signal is 1, the DDR2 write information generation module outputs the buffered data as write data; the write data side enable is used as a write request, and the write area and the write length are outputted side by side.

[0022] Compared with the prior art, the present application has the following beneficial effects:

[0023] 1. The present application searches the frame header and the frame length of the service input, analyzes the service type and the service length, and combines the BRAM (Buffer Random Access Memory) to control the read and write of the DDR2, thereby meeting the large storage and flexible scheduling requirements of adaptive service types.

[0024] 2. The present application sets the invalid information filtering and service rate buffering module, reduces the cache write and read pressure, solves the problem of too large instantaneous rate caused by time jitter of burst signals, and improves the cache throughput. BRIEF DESCRIPTION OF DRAWINGS

[0025] The present application can be better understood by referring to the description given below in conjunction with the accompanying drawings, which are included in the specification and form a part of the specification. In the drawings:

[0026] Figure 1 A structural block diagram of a satellite 5G industry service configuration buffer based on an FPGA is shown;

[0027] Figure 2 A frame length analysis schematic diagram is shown;

[0028] Figure 3 A schematic diagram of the service rate buffer module is shown;

[0029] Figure 4 A schematic diagram of the internal BRAM storage of the DDR2 read information generation module is shown. DETAILED DESCRIPTION

[0030] In the following, exemplary embodiments of the present application will be described with reference to the accompanying drawings. In the description, not all features of a practical embodiment are described in order to avoid obscuring the application with unnecessary detail. It should be appreciated that in developing any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, and these decisions will vary from one implementation to another.

[0031] It should also be noted that, in the drawings, the structures closely related to the scheme according to the present application are shown only, and other details not closely related to the present application are omitted, in order to avoid obscuring the present application with unnecessary details.

[0032] It should be understood that the present application is not limited to the described embodiments only due to the following description with reference to the drawings. In this context, the embodiments can be combined with each other, features of different embodiments can be replaced or borrowed, one or more features can be omitted in one embodiment.

[0033] The embodiment of the present application provides a satellite 5G downlink service configuration buffer based on FPGA (Field Programmable Gate Array, field programmable gate array), Figure 1 A structural block diagram of the satellite 5G downlink service configuration buffer based on FPGA is shown, referring to Figure 1 , comprising: an invalid information filtering module, a time reference generation module, a service rate buffer module, a DDR2 write information generation module, a DDR2 read information generation module, a DDR2 read-write control module and a DDR2 output information buffer module. The specific implementation functions of each module are described in detail below.

[0034] The invalid information filtering module receives configuration data sent by a ground base station, and filters invalid data in the configuration data to output valid data packets;

[0035] Specifically, Figure 2 A frame length analysis schematic diagram is shown. The invalid information filtering module calculates the frame length of each data frame in the configuration data. If the calculated frame length does not match the frame length field in the data frame, the data frame is filtered out to avoid the influence of incorrect configuration and packet loss on the buffer controller. In addition, according to the frame type of the data frame, the data frame corresponding to the frame type that does not need to be buffered is filtered out to reduce the data buffer amount.

[0036] The time reference generating module receives the 1PPS and TOD information, and outputs a read enable signal, a write request signal, a read request and a read area according to the 1PPS and TOD information.

[0037] Here, the 1PPS and TOD information are time scale information, 1PPS (Pulse Per Second) is a second pulse, and the number of pulses per second is an abbreviation of the number of pulses per second. TOD (Time of Day) is a time synchronization technology based on a computer system clock, which is used to synchronize the computer system clock to the global standard time.

[0038] Specifically, the time reference generating module calculates the system frame number and the time slot number according to the 1PPS and TOD information, and performs a cache read 10 time slots in advance; and according to the time, the write request signal, the read enable signal, the read request and the read area of each configuration content are distributed in each time slot, so as to ensure the time interval requirement between each read and write of the DDR2 memory.

[0039] Supposing that the number of frame types of the configuration content is Nclass, and the maximum frame length of each frame type is LENmax, the maximum frame length of the configuration content of all frame types is summed after each time slot starts, and an enable with a length of Nclass*LENmax is generated as the write request signal;

[0040] When the write request signal is 0, the read enable signal is assigned as 1, which indicates that the DDR2 is not written at this moment, and the read operation can be performed;

[0041] When the read enable signal is 1, Nclass pulse signals with an interval of LENmax are generated as the read request according to the number Nclass of frame types of the configuration content;

[0042] The system frame number, the time slot number and the frame type are spliced as the read area.

[0043] The service rate buffering module expands the parallel path number of the valid data packet output by the invalid information filtering module, and writes the data after the parallel path number is expanded into the first BRAM; a cache read process is started, a frame header is searched, and the data corresponding to the frame length in the frame header is taken out after the frame header is searched, and the speed control data packet is output after the condition of allowing output is met. The condition of allowing output is that the read enable signal is valid, and no write operation is performed within the protection time interval, and there is valid data in the first BRAM.

[0044] Figure 3 A schematic diagram of the service rate buffering module is shown, which is described with reference to FIG. 2. Figure 3The service rate buffering module is used to reduce the rate of burst service data. The module performs 8 times parallel processing on the input data, and adds time guard interval to the output data frame, thus allowing the input data to be input at the maximum line rate, and ensuring the read-write switching interval requirement of DDR2.

[0045] The DDR2 write information generating module receives the rate-controlled data packet output by the service rate buffering module, and performs frame analysis on the rate-controlled data packet; and according to the write request signal and the frame analysis result, outputs the write request, the write region, the write length and the write data.

[0046] Specifically, the DDR2 write information generating module performs frame analysis on the rate-controlled data packet to obtain a data frame structure; splices the system frame number, the time slot number, the beam number and the frame type in the data frame structure to generate the write region;

[0047] According to the frame length in the data frame structure, the write length is generated;

[0048] When the write request signal is 0, the DDR2 write information generating module buffers the input data and stops output; when the write request signal is 1, the DDR2 write information generating module outputs the buffered data as the write data; the side enable of the write data is used as the write request, and the write region and the write length are output side by side.

[0049] The DDR2 read information generating module buffers the write length into the write region of the second BRAM according to the write request output by the DDR2 write information generating module; and outputs the valid read request, the valid read region and the valid read length according to the read request and the read region output by the time reference generating module, and clears the corresponding storage content in the second BRAM.

[0050] Figure 4 The internal BRAM storage diagram of the DDR2 read information generating module is shown. Here, the time reference generating module periodically issues the read request and the read region, and judges whether the content at the read region address of the second BRAM is 0. If not, it means that the read content in the region is valid, and the content stored by the second BRAM at this place is the read length.

[0051] The DDR2 read-write control module realizes write control of the MIG core (Memory Interface Generator) according to the write request, the write region, the write data and the write length output by the DDR2 write information generating module; realizes read control of the MIG core according to the valid read request, the valid read region and the valid read length output by the DDR2 read information generating module; and outputs the buffered data;

[0052] The DDR2 output information cache module receives the cache data output by the DDR2 read-write control module, and outputs corresponding cache data according to the read request and read area output by the modulator. Here, if the corresponding cache data does not exist, an empty packet is output, and if there is no valid data frame in the continuous 5 time slots, an idle reset signal is output to the modulator to enhance the program robustness and reduce the dynamic power consumption of the FPGA.

[0053] In summary, the present application has the following technical effects:

[0054] 1. The present application searches the frame header and frame length of the service input, analyzes the service type and service length, and combines the BRAM (Buffer Random Access Memory) to control the read-write of the DDR2, thereby meeting the large storage and flexible scheduling requirements of adaptive service types.

[0055] 2. The present application sets the invalid information filtering and service rate buffering module, reduces the cache write and read pressure, solves the problem of excessive instantaneous rate caused by time jitter of burst signals, and improves the cache throughput.

[0056] The above is only various embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A satellite 5G downlink service configuration buffer based on FPGA, characterized in that, include: Invalid information filtering module, time base generation module, service rate buffer module, DDR2 write information generation module, DDR2 read information generation module, DDR2 read / write control module, and DDR2 output information buffer module; The invalid information filtering module receives configuration data sent by the ground base station, filters invalid data in the configuration data, and outputs valid data packets. The time base generation module receives 1PPS and TOD information, and outputs a read enable signal, a write request signal, a read request, and a read area based on the 1PPS and TOD information. The service rate buffer module increases the number of parallel paths for the valid data packets output by the invalid information filtering module, and writes the data with increased parallel paths into the first BRAM; The cache read process is started, a frame header search is performed, and after the frame header is found, the data of the corresponding frame length in the frame header is retrieved. After the conditions for allowing output are met, the rate control data packet is output. The conditions for allowing output are that the read enable signal is valid, no write operation is performed within the protection time interval, and there is valid data in the first BRAM. The DDR2 write information generation module receives the speed control data packet output by the service rate buffer module, performs frame parsing on the speed control data packet, and outputs the write request, write area, write length, and write data according to the write request signal and the result of frame parsing. The DDR2 read information generation module caches the write length in the write area of ​​the second BRAM according to the write request output by the DDR2 write information generation module; Based on the read request and read area output by the time base generation module, the system outputs a valid read request, a valid read area, and a valid read length, and clears the corresponding storage content in the second BRAM to zero. The DDR2 read / write control module controls the write operation of the MIG core based on the write request, write area, write data, and write length output by the DDR2 write information generation module; and controls the read operation of the MIG core based on the valid read request, valid read area, and valid read length output by the DDR2 read information generation module. And output the cached data; The DDR2 output information cache module receives the cached data output by the DDR2 read / write control module, and outputs the corresponding cached data according to the read request and read area output by the modulator.

2. The FPGA-based satellite 5G downlink service configuration buffer as described in claim 1, characterized in that, The invalid information filtering module calculates the frame length of each data frame in the configuration data. If the calculated frame length does not match the frame length field in the data frame, the data frame is filtered out. Based on the frame type of the data frame, data frames corresponding to frame types that do not need to be cached are filtered out.

3. The FPGA-based satellite 5G downlink service configuration buffer as described in claim 1, characterized in that, The time base generation module calculates the system frame number and time slot number based on the 1PPS and TOD information, and performs buffer reading 10 time slots in advance; Let the number of frame types in the configuration content be Nclass, and the maximum frame length of each frame type be LENmax. After the start of each time slot, the maximum frame length of the configuration content of all frame types is summed to generate an enable signal of length Nclass*LENmax as a write request signal. When the write request signal is 0, the read enable signal is set to 1, indicating that no write is being performed on DDR2 at this time, and a read operation can be performed. When the read enable signal is 1, Nclass pulse signals with an interval of LENmax are generated according to the number of frame types Nclass in the configuration content as read requests; The system frame number, the time slot number, and the frame type are concatenated to form the reading area.

4. The FPGA-based satellite 5G downlink service configuration buffer as described in claim 1, characterized in that, The DDR2 write information generation module performs frame parsing on the speed control data packet to obtain a data frame structure; the system frame number, time slot number, beam number and frame type in the data frame structure are concatenated to generate a write area; The write length is generated based on the frame length in the data frame structure; When the write request signal is 0, the DDR2 write information generation module buffers the input data and stops outputting; when the write request signal is 1, the DDR2 write information generation module outputs the buffered data as write data; the write data's accompanying enable is used as a write request, and the write area and write length are output along with the data.

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