Data caching method of on-chip logic analyzer and related device

Abstract

The invention relates to the field of data processing, in particular to a data caching method of an on-chip logic analyzer and a related device. The method comprises the following steps: acquiring to-be-processed input data through a trigger unit; marking corresponding to-be-analyzed data bits in the input data by adopting a significant bit mask; comparing whether the to-be-analyzed data bit is matched with the mode mask to obtain a matching result of the to-be-analyzed data bit; and according to the matching result and / or the data caching mode of the trigger unit, controlling the data storage process of the custom storage array and the ping-pong buffer area, so that target input data meeting the caching requirement in the input data is stored in the ping-pong buffer area. According to the method, the trigger conditions can be flexibly set according to specific analysis requirements, different debugging and analysis scenes are met, data related to the target event are more accurately captured, the adaptability and debugging efficiency of the logic analyzer and the utilization rate of storage resources are improved, and powerful support is provided for deep data analysis.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a triggering method of a logic analyzer and a related device. Background Art

[0002] On-Chip Logic Analyzer (OCLA) is a special tool integrated into an integrated circuit (IC) and is designed specifically for digital system debugging and fault diagnosis. It helps engineers understand the logical and timing relationships of various signals in the system by capturing and displaying the logic level status of the digital system in real time. Compared with traditional external logic analyzers, on-chip logic analyzers have unique advantages and application areas.

[0003] In the related art, the on-chip logic analyzer includes a trigger unit. The trigger unit is usually used to set capture conditions, such as a specific signal combination or an edge trigger condition. At present, the trigger unit usually only supports fixed trigger conditions, such as level trigger, edge trigger, etc. However, in complex integrated circuits, signal changes are often more complex and diverse, and a single trigger condition may not meet the needs of accurately capturing specific signal changes. This may cause engineers to miss key signals during the debugging process, thereby increasing the difficulty of troubleshooting.

[0004] Therefore, it is urgent to design a technical solution to solve the technical problems existing in the trigger unit in the related technology. Summary of the invention

[0005] In view of the technical problems existing in the prior art, the present application provides a data caching method and related devices for an on-chip logic analyzer, so as to solve the technical problem that the triggering conditions of the on-chip logic analyzer in the related art are single and cannot capture changes in specific models, resulting in high difficulty in troubleshooting.

[0006] In a first aspect, an embodiment of the present application provides a data caching method for an on-chip logic analyzer, wherein the on-chip logic analyzer comprises at least the following structures: a trigger unit and a ping-pong buffer, wherein the trigger unit comprises at least a custom storage array; the method comprises: Acquiring input data to be processed through a trigger unit; Using a valid digit mask to mark the corresponding data bits to be analyzed in the input data; Comparing whether the data bit to be analyzed matches the pattern mask to obtain a matching result of the data bit to be analyzed; wherein the pattern mask is used to indicate a data flag bit corresponding to a specific trigger event; and the specific trigger event is associated with a data analysis process performed by the on-chip logic analyzer; According to the matching result and / or the data cache mode of the trigger unit, the data storage process of the custom storage array and the ping-pong buffer is controlled so that the target input data that meets the cache requirements in the input data is stored in the ping-pong buffer.

[0007] In a second aspect, an embodiment of the present application provides an on-chip logic analyzer, the on-chip logic analyzer comprising at least the following structures: a trigger unit, a ping-pong buffer, the trigger unit comprising at least a custom storage array; wherein, A trigger unit is configured to obtain input data to be processed; mark the corresponding data bits to be analyzed in the input data using a valid bit mask; compare whether the data bits to be analyzed match the pattern mask to obtain the matching result of the data bits to be analyzed; wherein the pattern mask is used to indicate the data flag bit corresponding to a specific trigger event; the specific trigger event is associated with the data analysis process performed by the on-chip logic analyzer; and control the data storage process of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching mode of the trigger unit, so that the target input data that meets the caching requirements in the input data is stored in the ping-pong buffer; A ping-pong buffer is configured to receive target input data input through a custom storage array.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: at least one processor, memory, and input-output unit; The memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the data caching method of the on-chip logic analyzer of the first aspect.

[0009] In a fourth aspect, a computer-readable storage medium is provided, which includes instructions. When the instructions are executed on a computer, the computer executes the data caching method of the on-chip logic analyzer of the first aspect.

[0010] The present application provides a data caching method and related devices for an on-chip logic analyzer. In this technical solution, first, the input data to be processed is obtained through a trigger unit. Then, a valid bit mask is used to mark the corresponding data bits to be analyzed in the input data. Next, the data bits to be analyzed are compared to see whether they match the pattern mask to obtain the matching results of the data bits to be analyzed. Among them, the pattern mask is used to indicate the data flag bit corresponding to a specific trigger event; the specific trigger event is associated with the data analysis process performed by the on-chip logic analyzer. Finally, according to the matching result and / or the data caching mode in which the trigger unit is located, the data storage process of the custom storage array and the ping-pong buffer is controlled so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer.

[0011] The technical solution of the present application, through the coordinated control of the effective bit number mask, pattern mask, custom storage array and ping-pong buffer, can flexibly set the trigger conditions according to specific analysis needs, meet different debugging and analysis scenarios, and more accurately capture data related to the target event, thereby improving the adaptability and practicality of the logic analyzer, effectively improving the debugging efficiency and the utilization of storage resources, and further providing strong support for in-depth data analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a flow chart of a data caching method of an on-chip logic analyzer according to an embodiment of the present application; Figure 2 It is a schematic diagram of the principle of a data caching method of an on-chip logic analyzer according to an embodiment of the present application; Figure 3 is a structural schematic diagram of an on-chip logic analyzer according to an embodiment of the present application; Figure 4 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application; Figure 5 It is a structural schematic diagram of a medium device according to an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0014] The on-chip logic analyzer (OCLA) is a special tool integrated into an integrated circuit and is designed specifically for digital system debugging and fault diagnosis. It helps engineers understand the logical and timing relationships of various signals in the system by capturing and displaying the logic level status of the digital system in real time. Compared with traditional external logic analyzers, on-chip logic analyzers have unique advantages and application areas.

[0015] In the related art, the on-chip logic analyzer includes a trigger unit. The trigger unit is usually used to set capture conditions, such as a specific signal combination or an edge trigger condition. At present, the trigger unit usually only supports fixed trigger conditions, such as level trigger, edge trigger, etc. However, in complex integrated circuits, signal changes are often more complex and diverse, and a single trigger condition may not meet the needs of accurately capturing specific signal changes. This may cause engineers to miss key signals during the debugging process, thereby increasing the difficulty of troubleshooting.

[0016] In addition, in the related art, the trigger bit number of traditional on-chip logic analyzers is usually limited, and it may not be possible to monitor and process a large number of signal lines at the same time. In highly integrated circuits, the number of signal lines is often very large, and the limited number of trigger bits will limit the monitoring range of the on-chip logic analyzer, making it impossible to capture and analyze some important signals. In the related art, the trigger mode of traditional on-chip logic analyzers is usually relatively fixed, and may not be able to adapt to the needs of different application scenarios. For example, in some cases, engineers may need to trigger capture based on specific signal patterns or timings, but traditional logic analyzers may not provide such flexibility.

[0017] In summary, it is urgent to design a technical solution to overcome at least one of the technical problems existing in the related art of the trigger unit, namely, a single trigger condition, a limited number of trigger bits, and a fixed trigger mode.

[0018] In order to solve at least one technical problem in the related art, an embodiment of the present application provides a data caching method and related devices for an on-chip logic analyzer.

[0019] In the technical solution provided by the present application, first, the input data to be processed is obtained through the trigger unit. Then, the corresponding data bits to be analyzed are marked in the input data using a valid bit mask. Next, the data bits to be analyzed are compared to see whether they match the pattern mask to obtain the matching result of the data bits to be analyzed. Among them, the pattern mask is used to indicate the data flag bit corresponding to a specific trigger event; the specific trigger event is associated with the data analysis process performed by the on-chip logic analyzer. Finally, according to the matching result and / or the data caching mode in which the trigger unit is located, the data storage process of the custom storage array and the ping-pong buffer is controlled so that the target input data in the input data that meets the caching requirements is stored in the ping-pong buffer.

[0020] The technical solution of the present application, through the effective bit mask, marks the data bits to be analyzed in the input data, can focus on the key data part and avoid processing a large amount of irrelevant data. At the same time, the data flag corresponding to the specific trigger event is identified by the pattern mask, so that the user can flexibly set the trigger conditions according to the specific analysis needs to meet different debugging and analysis scenarios. It is no longer limited to fixed trigger conditions, and can more accurately capture the data related to the target event, which improves the adaptability and practicality of the logic analyzer. For example, in different chip designs, different pattern masks can be set to trigger data caching according to the functions of the chip and possible problems. Finally, according to the matching results and the data caching mode where the trigger unit is located, the data storage process of the custom storage array and the ping-pong buffer is controlled. On the one hand, it can optimize the utilization of storage resources, avoid the problem of waste or insufficient storage resources that may occur in traditional methods, so that storage resources can be more reasonably allocated and used, and the overall performance and stability of the system are improved. On the other hand, through a variety of data caching methods (such as pre-trigger, mid-trigger, post-trigger, etc.), it is possible to flexibly manage the required data types based on the user's debugging needs, ensure the integrity and accuracy of the data, and adapt to the diverse data analysis needs. Whether it is verifying chip functions, evaluating performance or troubleshooting, accurate and useful data can be obtained by setting appropriate mode masks and data caching methods, providing strong support for in-depth data analysis.

[0021] The technical solution of the present application, through the coordinated control of the effective bit number mask, pattern mask, custom storage array and ping-pong buffer, can flexibly set the trigger conditions according to specific analysis needs, meet different debugging and analysis scenarios, and more accurately capture data related to the target event, thereby improving the adaptability and practicality of the logic analyzer, effectively improving the debugging efficiency and the utilization of storage resources, and further providing strong support for in-depth data analysis.

[0022] The data caching solution of the on-chip logic analyzer provided in the embodiment of the present application can also be executed by an electronic device, which can be a server, a server cluster, or a cloud server. The electronic device can also be a terminal device such as a mobile phone, a computer, a tablet computer, a wearable device, or a dedicated device (such as a dedicated terminal device with a data caching method system for an on-chip logic analyzer, etc.). These electronic devices can also be equipped with the chips introduced in the above embodiments. Alternatively, these electronic devices can also be installed with a service program for executing the data caching solution of the on-chip logic analyzer.

[0023] Figure 1 A flow chart of a data caching method for an on-chip logic analyzer provided in an embodiment of the present application is shown in FIG. Figure 1As shown, the method comprises the following steps: Step 101, obtaining input data to be processed through a trigger unit; Step 102, using a valid digit mask to mark the corresponding data bits to be analyzed in the input data; Step 103, comparing whether the data bit to be analyzed matches the pattern mask to obtain a matching result of the data bit to be analyzed; Step 104, according to the matching result and / or the data cache mode of the trigger unit, control the data storage process of the custom storage array and the ping-pong buffer, so that the target input data that meets the cache requirement in the input data is stored in the ping-pong buffer.

[0024] The embodiment of the present application is applied to an on-chip logic analyzer. The on-chip logic analyzer includes at least the following structures: a trigger unit and a ping-pong buffer. Further, the trigger unit includes at least a custom storage array. Specifically, the trigger unit filters out the valid data bits that are really concerned from the input data through the effective bit mask, filters out irrelevant data bits, reduces the amount of data to be processed subsequently, and improves the pertinence of the analysis. For example, for a wide-bit data, when only some key bits are concerned, this module can be used to implement it. The custom storage array is used to temporarily store the data processed by the effective bit mask. Further optionally, the array works according to the first-in-first-out principle, can cache data to a certain extent, wait for comparison with the pattern mask and subsequent processing, and prevent data loss or untimely processing. The trigger unit stores the data flag bit corresponding to the specific trigger event through the pattern mask, compares it with the data temporarily stored in the custom storage array, determines whether the trigger condition is met, and then generates a control signal to control the ping-pong buffer. Under the control signal generated by the pattern mask comparison result in the trigger unit, the ping-pong buffer stores the target input data that meets the cache requirements, plays the role of data caching and transfer, and ensures that the data can be transmitted to the host computer in an orderly and stable manner. The host computer receives the data from the ping-pong buffer and performs subsequent analysis, display and other operations to help users intuitively understand the data collected by the on-chip logic analyzer.

[0025] See also Figure 2 In the schematic diagram of the structure of the on-chip logic analysis shown in the figure, the input data first enters the effective bit mask module in the trigger logic unit (i.e., the trigger unit), and the processed data flows into the FIFO (i.e., the custom storage array). The input data in the FIFO will be compared with the pattern mask, and the control signal generated according to the comparison result will control the data storage in the ping-pong buffer. Furthermore, the ping-pong buffer is connected to the host computer, and the data stored in the ping-pong buffer is used as the basis for data analysis by the host computer.

[0026] Further optionally, the custom storage array and ping-pong buffer in the trigger unit are configured as a multi-level first-in-first-out storage array (FIFO). The FIFO depth and number of layers corresponding to the custom storage array and ping-pong buffer can be dynamically configured based on the trigger mode of the trigger unit.

[0027] Specifically, the custom storage array and ping-pong buffer can use the storage resources in FPGA (field programmable gate array) or ASIC (application-specific integrated circuit), such as block RAM (BRAM) or distributed RAM (DRAM) to build FIFO. In FPGA, the internal FIFO IP core can be directly called to define its depth (the number of stored data) and width (the bit width of each data) by setting parameters. For example, if 32-bit data needs to be stored and the FIFO depth is expected to be 1024, the corresponding settings can be made in the IP core configuration interface. In ASIC design, a special circuit structure needs to be designed according to the storage requirements to implement the FIFO function, including address generator, read and write control logic, etc. The working principle can be that data is written into the FIFO in the order in which it enters, and the data is read according to the first-in first-out principle. When new data arrives, it is written into the FIFO when the write enable signal is valid; when data needs to be read, it is read from the FIFO when the read enable signal is valid. At the same time, there will be full signals and empty signals to indicate whether the FIFO is full or empty to avoid data overflow or read empty errors. In an on-chip logic analyzer, the FIFO can be used to temporarily store data after the effective bit number mask is processed, waiting to be compared with the pattern mask.

[0028] In another example, a custom storage array and ping-pong buffer can be implemented based on SRAM (static random access memory). Specifically, the SRAM chip is connected to the control logic circuit of the on-chip logic analyzer, including address lines, data lines, and control lines. The address line is used to specify the address of the storage unit to be accessed, the data line is used to transmit data, and the control line includes read enable, write enable and other signals to control the read and write operations of the SRAM. In FPGA design, the interface connection with the SRAM chip can be made through the I / O pins of the FPGA, and the corresponding control logic code can be written; in ASIC design, the SRAM interface circuit needs to be integrated into the chip.

[0029] Based on the above structure, the address and read / write control signals are sent to the SRAM through the control logic circuit to realize random read / write operations on the data. When writing data, the data and the corresponding address are sent to the SRAM, and the data is stored in the specified address unit when the write enable signal is valid; when reading data, the address and read enable signal are sent to read the data from the specified address unit. This method can flexibly access any location in the storage array as needed, and is suitable for scenarios that require random storage and reading of data, such as recording specific data before and after triggering in a custom storage array.

[0030] In another example, a custom storage array and ping-pong buffer can be implemented based on a register file. Specifically, it consists of multiple registers, each of which can store data of a certain bit width. The size of the register file and the bit width of each register can be customized according to specific needs. For example, if you need to store 8 32-bit data, you can build a register file containing 8 32-bit registers. In FPGA design, HDL (hardware description language, such as Verilog or VHDL) can be used to directly describe the structure and operation logic of the register file; in ASIC design, it is implemented by designing a dedicated register circuit.

[0031] Based on the above structure, the registers in the register file are read and written through the control logic circuit. Each register usually has an independent read and write enable signal. When the write enable signal of a register is valid, data can be written to the register; when the read enable signal is valid, data can be read from the register. The register file has a fast read and write speed and is suitable for scenarios with high requirements for data storage and access speed, such as fast storage and processing of temporary data in the trigger logic unit.

[0032] Furthermore, in the application scenario of the on-chip logic analyzer, the custom storage array and ping-pong buffer in the trigger unit are set as a multi-level first-in-first-out storage array (FIFO), and the corresponding FIFO depth and number of layers can be dynamically configured based on the trigger mode of the trigger unit. The following is a detailed introduction.

[0033] The multi-level FIFO in the custom storage array is used to temporarily store data after the effective bit mask processing. Each level of FIFO can be regarded as an independent data storage queue, and the data flows in each level of FIFO in turn according to the first-in-first-out principle. This multi-level structure can increase the data cache capacity and provide more intermediate stages for data processing, which is convenient for complex pattern detection and data processing operations.

[0034] The multi-level FIFO of the ping-pong buffer is mainly used to store target input data that meets the cache requirements. It works in conjunction with the FIFO of the custom storage array. When the data in the custom storage array meets the trigger condition, the data will be transferred to the FIFO of the ping-pong buffer for storage. The multi-level structure of the ping-pong buffer can realize continuous storage and processing of data, improving the efficiency and stability of data storage.

[0035] Based on the aforementioned multi-level structure, the FIFO depth configuration in the pre-trigger mode can be that data for a period of time before the trigger event occurs needs to be stored. Therefore, the FIFO depth of the custom storage array and the ping-pong buffer needs to be configured according to the length of the historical data you want to trace back. For example, if you want to record the data of 100 clock cycles before the trigger event, the FIFO depth must be set to at least 100. This ensures that when the trigger event occurs, the previous relevant data can be fully obtained. The FIFO layer configuration in the pre-trigger mode can be configured according to the complexity of data processing and the analysis requirements of the data. If more complex pattern detection is required, it may be necessary to increase the number of FIFO layers so that different processing and analysis can be performed at different levels. For example, preliminary data screening is performed in the first-level FIFO, and more refined pattern matching is performed in the second-level FIFO.

[0036] The FIFO depth configuration in the medium trigger mode can be that the medium trigger mode needs to record the data before and after the trigger event occurs. Therefore, the configuration of the FIFO depth should take into account the amount of data that needs to be stored before and after the trigger event. For example, if you want to record the data of 50 clock cycles before the trigger event and 50 clock cycles after the trigger event, then the FIFO depth must be set to at least 100. At the same time, the FIFO depth can be further adjusted according to the configurable additional storage length. Similarly, the number of layers is configured according to the needs of data processing and analysis. In order to fully analyze the entire process of the trigger event, more layers may be required for data processing and storage at different stages. For example, key data before, during, and after the trigger are stored in different layers for subsequent detailed comparison and analysis.

[0037] The FIFO depth configuration in post-trigger mode can be to focus on data storage after the trigger event occurs. The FIFO depth can be configured based on the length of time you want to observe the post-trigger data. For example, if you want to record data 200 clock cycles after the trigger event, then the FIFO depth is set to 200. In addition, factors such as the time it takes for the ping-pong buffer to be full and the data input rate need to be considered to ensure that the critical post-trigger data can be fully stored. At the same time, the number of layers can be configured based on the processing requirements for the post-trigger data. If you need to perform multi-stage processing and analysis on the post-trigger data, such as preliminary screening of the data first, and then detailed pattern analysis, you can increase the number of FIFO layers.

[0038] Therefore, by dynamically configuring the FIFO depth and number of layers based on the trigger mode, the performance of the storage array and buffer can be flexibly adjusted according to different debugging and analysis requirements. In different application scenarios, it can quickly adapt to various trigger conditions and data processing requirements, improving the versatility and adaptability of the on-chip logic analyzer. In addition, it can avoid the problem of resource waste or shortage caused by fixed configuration. When a large amount of data storage is not required, the FIFO depth and number of layers can be reduced to save the storage resources of the chip; when complex data needs to be processed and in-depth analysis is required, the corresponding configuration can be added to ensure that the actual needs can be met. In summary, setting the custom storage array and ping-pong buffer as a multi-level FIFO and dynamically configuring its depth and number of layers based on the trigger mode can provide the on-chip logic analyzer with more flexible and efficient data storage and processing capabilities to meet diverse debugging and analysis needs.

[0039] In the embodiment of the present application, input data refers to a data stream related to the function to be monitored and analyzed from inside or outside the chip. These data can be of various types, such as binary data transmitted in a digital circuit, digital representation corresponding to an analog signal after analog-to-digital conversion, etc. For example, in a processor chip, instruction data, operation data, etc. transmitted on the processor internal bus can be used as input data for an on-chip logic analyzer. In a communication chip, data packet data transmitted in a communication link can also become input data. It covers all data information generated or received during the operation of the chip that needs to be monitored and analyzed.

[0040] In the embodiment of the present application, the effective digit mask is a binary number used to filter the key data bits in the input data. Its bit width is the same as the bit width of the input data, and the attention to the corresponding bit in the input data is indicated by setting "1" and "0" in the mask. When a certain bit in the mask is "1", it means that the corresponding bit in the input data is the effective data bit that the user really cares about; if it is "0", it means that the bit is a bit that can be ignored in the current analysis. For example, if the input data is 32 bits, and the user only cares about the data of bits 8-15, the effective digit mask can be set to 000000001111111100000000000000000. When the on-chip logic analyzer is working, the input data is logically ANDed with the effective digit mask to obtain the filtered data containing only the effective data bits, thereby reducing the amount of data to be processed later and focusing on key information for analysis.

[0041] In the embodiment of the present application, the mode mask is used to indicate the data flag bit corresponding to the specific trigger event. Here, the specific trigger event is associated with the data analysis process executed by the on-chip logic analyzer.

[0042] Specifically, the pattern mask is a binary number whose bit width is usually the same as the bit width of the input data. It is like a "data key" used to filter out data that meets specific requirements. Each bit in the mask corresponds to the corresponding bit of the input data. When a bit in the pattern mask is set to a specific value (such as "1" or "0"), it means that when judging the trigger condition, the corresponding bit of the input data must match it; if it is set to a wildcard (such as "X"), it means that the specific value of this bit does not need to be paid attention to when judging. For example, for 32-bit input data, if the pattern mask is 1010XXXX1100XXXX, it means paying attention to the 1st, 2nd, 5th, 6th, 9th, and 10th bits of the input data, and requiring the 1st, 2nd, 9th, and 10th bits to be 1, 0, 1, and 0 respectively, while other bits marked with "X" are not strictly required when triggering judgments.

[0043] Specific trigger events refer to key events that users want to focus on monitoring or analyzing during the operation of the chip. These events can be varied, for example, when a specific value or a group of specific values ​​appear on a specific data line, such as a specific memory address appears on the processor's address bus, or a key instruction code appears on the data bus. For example, when a signal changes from a low level to a high level, or from a high level to a low level, such as the rising or falling edge of a clock signal, the valid / invalid state switching of a control signal, etc. For example, when the data in multiple consecutive clock cycles meets a pre-set pattern, such as the continuous appearance of a data sequence such as "ABC". For example, for a chip containing a state machine, it is triggered when the state machine enters a specific state to analyze the operation of the chip in that state.

[0044] Thus, the occurrence of a specific trigger event is the "switch" that starts the data analysis process. Once the pattern mask matches the input data, indicating that a specific trigger event has occurred, the on-chip logic analyzer will begin to collect, store, and analyze relevant data according to the preset process. For example, after detecting a specific data pattern match, it will start recording all relevant data for a period of time before and after the trigger, so as to conduct a subsequent in-depth analysis of the background, process, and impact of the event.

[0045] Different specific trigger events correspond to different data analysis focuses. For example, if the trigger event is a change in a control signal, the data analysis process may focus on checking the values ​​of related registers before and after the signal changes, the synchronous changes of other signals, etc., to determine whether the control signal is working properly and its impact on the entire system; if the trigger event is an abnormal data value on the data bus, the data analysis process will analyze the source of the data value, the transmission path, and the impact on subsequent data processing.

[0046] In addition, users can define different specific trigger events by setting different pattern masks according to specific debugging and analysis needs, and then customize the corresponding data analysis process. At different stages of chip design or when troubleshooting different types of problems, the pattern mask and the corresponding analysis process can be flexibly adjusted, so that the on-chip logic analyzer can adapt to a variety of analysis tasks and improve the efficiency of debugging and troubleshooting.

[0047] In the embodiment of the present application, first, by marking the data bits to be analyzed in the input data through the effective digit mask, it is possible to focus on the key data part and avoid processing a large amount of irrelevant data. This can reduce the amount of data processing, improve the speed and efficiency of data processing, and significantly improve the analysis efficiency, especially when processing wide-bit data or data containing a large amount of redundant information. For example, for a 128-bit data, if you only care about 32 bits of key data, the use of the effective digit mask can directly locate these 32 bits without processing the entire 128-bit data.

[0048] Secondly, the pattern mask is used to indicate the data flag corresponding to a specific trigger event, and the specific trigger event is associated with the data analysis process. This allows users to flexibly set trigger conditions according to specific analysis needs to meet different debugging and analysis scenarios. No longer limited to fixed trigger conditions, it can more accurately capture data related to the target event, improving the adaptability and practicality of the logic analyzer. For example, in different chip designs, different pattern masks can be set to trigger data caching according to the chip's functions and possible problems.

[0049] In addition, since specific trigger events are associated with the data analysis process performed by the on-chip logic analyzer, this technical solution can adapt to diverse data analysis needs. Whether it is verification of chip functions, performance evaluation or troubleshooting, accurate and useful data can be obtained by setting appropriate mode masks and data caching methods, providing strong support for in-depth data analysis.

[0050] Furthermore, according to the matching results and the data caching mode of the trigger unit, the data storage process of the custom storage array and the ping-pong buffer is controlled. This enables the target input data that meets the caching requirements to be accurately stored in the ping-pong buffer, avoiding unnecessary data storage and saving storage resources. At the same time, different data caching modes (such as pre-trigger, mid-trigger, post-trigger, etc.) can be effectively controlled and managed to ensure the integrity and accuracy of the data. For example, in the mid-trigger mode, the relevant data before and after the trigger event can be accurately stored according to the matching results.

[0051] It is understandable that the combination of custom storage arrays and ping-pong buffers, as well as precise control of the data storage process, can optimize the use of storage resources, avoid the waste or shortage of storage resources that may occur in traditional methods, enable storage resources to be more reasonably allocated and used, and improve the overall performance and stability of the system.

[0052] It can be further understood that the embodiments of the present application do not rely on a specific chip architecture or data type, and can be applied to a variety of different on-chip logic analyzers, with strong versatility. Whether processing simple digital signals or complex mixed signals, efficient data caching and analysis can be achieved by adjusting parameters such as the effective bit mask and the mode mask, thereby expanding the application scope of the logic analyzer.

[0053] The following describes the specific implementation methods of each step with examples.

[0054] In step 101, the input data to be processed is obtained through the trigger unit. For example, the trigger unit first receives a data signal stream from inside or outside the chip, and these signal streams contain various input data to be processed. Then, the custom storage array in the trigger unit will monitor and compare the input data in real time according to the preset trigger conditions, such as the specific data pattern indicated by the pattern mask. When the input data matches the preset trigger condition, the trigger unit will be activated.

[0055] After activation, the trigger unit will store a certain amount of input data before and after the trigger point in a custom storage array for subsequent processing and analysis. At the same time, it will also send a signal to the ping-pong buffer to transfer the relevant data to the ping-pong buffer for further caching and processing, ensuring that the data will not be lost and can be processed in an orderly manner.

[0056] For example, suppose the input data is a series of 32-bit binary numbers, and the pattern mask is set to 1010XXXX1100XXXX. When the trigger unit receives data such as 1010111111000010, it matches the pattern mask and the trigger unit is activated. It will store this 32-bit data and several data before and after the trigger point into the custom storage array, such as the previous data 1111000011110000 and the next data 0011110000111100, and transfer these data to the ping-pong buffer at the same time to complete the acquisition of the input data to be processed.

[0057] In the above or below embodiments, before step 101, a target trigger mode matching the cache requirement can also be selected from a plurality of trigger modes configured by the trigger unit. The cache requirement is obtained based on a user input instruction; or the cache requirement is determined by data analysis of the on-chip logic analyzer. Then, the attribute parameters in the target trigger mode are set to configure the effective bit mask, mode mask, and data cache mode of the trigger unit that match the cache requirement.

[0058] Specifically, first, the trigger unit provides a variety of preset trigger modes, such as pre-trigger, middle trigger, and post-trigger modes. When the user inputs instructions or the data analysis of the on-chip logic analyzer determines the cache requirements, the system selects the target trigger mode that matches the cache requirements from these trigger modes. If the cache requirement is to obtain data before the trigger event occurs, the system will select the pre-trigger mode. If you need to obtain data before and after the trigger event occurs, the middle trigger mode will be selected. If you only care about the data after the trigger event occurs, the post-trigger mode will be selected. After selecting the target trigger mode, you need to set the attribute parameters in the mode. For the effective bit mask, determine the key data bits of interest according to the cache requirements, set the corresponding bits to 1, and set the remaining bits to 0. For example, if the input data is 32 bits, only the 8th to 15th bits are concerned, and the effective bit mask is set to 000000001111111100000000000000000. The mode mask is set according to a specific trigger event. For example, if the trigger event is the data pattern 10101010, the mode mask is set to 10101010. The data cache mode is also configured according to the target trigger mode and cache requirements. In the pre-trigger mode, data is continuously stored in the custom storage array and ping-pong buffer from the beginning until the trigger condition is met; in the mid-trigger mode, data is continuously stored, and a certain amount of data continues to be stored after the trigger condition is met; in the post-trigger mode, data storage begins after the trigger condition is met. For example, the user inputs an instruction to obtain data before a chip abnormal trigger, and the system selects the pre-trigger mode. Set the effective bit number mask to focus on the relevant bits of the chip's key control signals, and set the mode mask to the corresponding mode of the abnormal signal. The data cache mode is to continuously store data until an abnormal signal trigger is detected, realizing a configuration that matches the cache requirements.

[0059] Further optionally, the structure and storage depth of the custom storage array are determined by the data cache mode configured in the target trigger mode.

[0060] In pre-trigger mode, data before the trigger event needs to be recorded. The structure of the custom storage array should be designed to store data continuously until the trigger event occurs. Usually a continuous FIFO (first in, first out) structure can be used to ensure that the data is stored in chronological order. The storage depth depends on the length of time you want to record the pre-trigger data. For example, if the system clock period is T, assuming that the data is recorded N clock cycles before the trigger, and each clock cycle generates a data unit, then the storage depth should be set to N. In this way, when the trigger event occurs, the data of the N clock cycles before the trigger is saved in the storage array.

[0061] The medium trigger mode requires recording the data before and after the trigger event occurs. At this time, the custom storage array can be designed as a multi-level FIFO structure. The first-level FIFO is used to store data before the trigger, the second-level FIFO is used to store data during the trigger, and the third-level FIFO is used to store data after the trigger. Data is transferred and switched between each level of FIFO through control logic. The storage depth needs to comprehensively consider the amount of data that needs to be recorded before and after the trigger. Assuming that you want to record data for M clock cycles before the trigger, 1 clock cycle during the trigger, and K clock cycles after the trigger, the total storage depth should be M+1+K. Among them, the depth of the first-level FIFO is M, the depth of the second-level FIFO is 1, and the depth of the third-level FIFO is K.

[0062] The post-trigger mode focuses on the data after the trigger event occurs. The custom storage array can use an initially empty FIFO structure to start storing data after the trigger event occurs. The storage depth is determined by the length of time you want to record the post-trigger data. If you want to record data P clock cycles after the trigger, the storage depth is set to P.

[0063] Therefore, by accurately configuring the structure and storage depth of the custom storage array according to different trigger modes, it is possible to ensure that the required data can be fully recorded in various situations. For example, in the pre-trigger mode, the historical data before the trigger event can be accurately obtained, providing strong support for analyzing the root cause of the problem; in the mid-trigger mode, the entire process of the trigger event can be fully recorded, including the signal changes before and after; in the post-trigger mode, the system response data after the trigger event can be focused on. Reasonable configuration avoids the waste of storage resources. For different trigger modes, only the necessary storage depth is allocated, and excessive chip resources will not be occupied due to over-allocation. At the same time, it can also meet the actual cache requirements and improve resource utilization efficiency. This way of dynamically configuring the storage array according to the trigger mode enables the on-chip logic analyzer to flexibly adapt to different debugging and analysis scenarios. Whether it is necessary to analyze historical data, fully understand the event process, or pay attention to subsequent reactions, the structure and depth of the storage array can be adjusted to meet the needs, enhancing the versatility and practicality of the system.

[0064] Exemplarily, in the above steps, the attribute parameters in the target trigger mode are set to configure the valid bit number mask, mode mask, and data cache mode of the trigger unit that match the cache requirement, including: identifying the data analysis type in the cache requirement; determining the data bits that currently need to be analyzed based on the data analysis type, the data type of the input data, and the historical analysis method, and generating a corresponding valid bit number mask.

[0065] The effective bit mask is a binary number with the same bit width as the input data, which is used to mark which bits in the input data are the key data bits that the user is concerned about. "1" in the mask indicates that the bit is valid (need to be retained), and "0" indicates that the bit is invalid. Through the logical AND operation, the effective bit mask can extract the part that the user is concerned about from the input data, reducing the amount of data to be processed later.

[0066] In an on-chip logic analyzer, the effective bit mask is a binary number with the same bit width as the input data. Its function is to filter out the key data bits that the user is concerned about in the input data, which is specifically achieved through logical and operations. For example, the specific data analysis type is determined based on the cache requirements. If it is functional verification, the focus will be on specific instructions or register bits; if it is performance analysis, it is necessary to monitor data throughput or timing relationships; and for troubleshooting, it is necessary to locate abnormal signals or error codes. For example, in functional verification, specific instruction codes in the processor will become the focus; in performance analysis, the data transmission rate of the bus is the focus; in troubleshooting, abnormal values ​​​​of sensor output are the key.

[0067] When the input data is 32 bits, different types of data have different bit segment divisions. For address bus data, the upper 16 bits represent the address space and the lower 16 bits are the offset. In sensor data, the first 8 bits are the device ID and the last 24 bits are the measured value. Taking address bus data as an example, the upper 8 bits may correspond to the page number, which needs to be monitored during functional verification. Determine the bit segments that are prone to problems based on previous debugging experience. For example, in the past, bits 16 to 24 (temperature values) of sensor data often failed, and this part of the bit segment needs to be focused on in subsequent analysis. Generate corresponding masks according to different scenarios. In the functional verification scenario, if you want to verify the page number (upper 8 bits) of the address bus, the mask will be set to FF000000 (the first 8 bits in binary are 1); in the troubleshooting scenario, if you want to monitor the sensor temperature value (bits 16 to 24), the mask is set to 00FF0000 (bits 16 to 24 in binary are 1). Then, the mask can be dynamically updated according to the actual situation. If subsequent analysis finds that additional bits of interest need to be added, such as the lower 4 bits of the sensor ID, the mask can be updated to 000000F0 (retaining only bits 4 - 7).

[0068] Thus, by processing only valid bits, the amount of data processing is greatly reduced. Taking 32-bit data as an example, if only 8 bits are concerned, the amount of calculation can be reduced by 75%. At the same time, the trigger condition matching time is also shortened, and the real-time performance is improved. The application of the effective bit mask reduces the storage requirements, and the ping-pong buffer only needs to store the effective bit data. In addition, it saves power and reduces the transmission and calculation of redundant data. Users can dynamically adjust the mask according to different analysis targets to adapt to various scenarios. For example, when debugging network protocols, the mask can focus on the IP address segment. When verifying encryption algorithms, the mask focuses on key-related bits. The combination of historical analysis and masking can quickly reproduce and locate historical faults. For example, by retaining fault-related bits through masks, abnormal data patterns can be automatically captured when triggered. The effective bit mask greatly improves the efficiency and flexibility of the on-chip logic analyzer by dynamically screening key data bits. It combines data analysis types, data characteristics, and historical experience to accurately generate masks, achieving the dual goals of resource optimization and problem location.

[0069] Another example, in the above steps, the attribute parameters in the target trigger mode are set to configure the effective bit number mask, mode mask, and data cache mode of the trigger unit that match the cache requirement, including: determining the data jump form to be observed in the cache requirement; the data jump form includes: data change value, data change trend, data change amplitude, data timing, and at least one of data repetition times; dynamically configuring the corresponding mode mask according to the determined data jump form.

[0070] In an on-chip logic analyzer, a pattern mask is a binary number with the same bit width as the input data, which is used to define the target data pattern corresponding to the trigger event. It filters the input data through logical matching (such as AND, OR, XOR), supports wildcards (such as X for irrelevant bits), and thus flexibly matches specific data features. For example, if you need to detect that the upper 8 bits of 32-bit data are 1010 and the lower 8 bits are arbitrary, the pattern mask can be set to 1010XXXXXXXXXXXX. Specifically, the pattern mask is dynamically configured according to the data jump form to be observed in the cache requirements. For example, if the data jump form is a data change value, the pattern mask can be set to match a specific value (such as "deadbeef"); if it is a data change trend, the increment or decrement mode can be defined by comparing the data of consecutive clock cycles; if it is a data timing, a multi-level FIFO is configured to record a continuous data sequence (such as "ABC"). Taking the number of data repetitions as an example, if you need to detect that a specific pattern (such as "55AA") appears three times in a row, the pattern mask can be combined with the counter configuration to trigger when it matches three times in a row. This dynamic configuration mechanism significantly improves the flexibility of the trigger condition. Traditional fixed-mode triggering cannot adapt to complex scenarios, but this solution can accurately match events such as signal mutations, abnormal sequences, or timing violations by analyzing the data jump form. For example, in high-speed bus debugging, if data bursts with high-frequency jitter (the amplitude of the change exceeds the threshold), the mode mask can be updated in real time to "XX...XX" (retain the key bits) and the amplitude threshold can be set to accurately capture abnormal data.

[0071] Thus, by matching the data transition form, false triggering can be reduced, such as filtering accidental noise and capturing only signals that meet the expected pattern. Dynamic mask adjustment is supported to meet diverse needs such as timing analysis and anomaly detection. For example, in processor debugging, the instruction sequence "LDR-ADD-STR" is matched through the pattern mask to trigger the recording of context data. Only matching data is stored to reduce storage pressure. For example, in post-trigger mode, storage is started only when the data transition matches the mask to avoid redundant data. Combined with the effective bit number mask, the root cause of the problem can be quickly located. For example, when the sensor data is abnormal, the temperature value bit is retained through the mask and the mutation pattern is matched to quickly reproduce the fault. In summary, the pattern mask realizes the intelligent configuration of the trigger condition by dynamically adapting the data transition form, which significantly enhances the debugging capability of the on-chip logic analyzer for complex scenarios.

[0072] In another example, the data caching mode is jointly determined by the type of data to be analyzed and the time period in which the data is located. In the above steps, the attribute parameters in the target trigger mode are set to configure the effective bit mask, mode mask, and data caching mode of the trigger unit that match the cache requirement, including: Determine the data type and the time period in which the data is located that need to be analyzed in the cache requirement; select a corresponding target data cache method from a plurality of pre-configured data cache methods according to the data type and the time period in which the data is located that need to be analyzed.

[0073] In an on-chip logic analyzer, data caching refers to a mechanism that selects a specific strategy to store trigger event-related data based on debugging requirements and data characteristics. Common methods include pre-trigger, mid-trigger, post-trigger, and custom combination modes. The core is to control the starting point, duration, and coverage of data storage to balance storage resources and analysis requirements. Specifically, it is necessary to first determine the data type (such as instruction stream, sensor data, bus transaction) and the time period (before trigger, during trigger, and after trigger) in the cache requirements. For example, if the analysis target is "abnormal instruction sequence before failure", the data type is instruction stream, and the time period is before trigger, then select the pre-trigger mode to continuously store data until a specific instruction pattern is detected; if you need to verify "system response after a sudden change in sensor signal", the data type is analog to digital value, and the time period is after trigger, then use the post-trigger mode to only record the data stream after the sudden change.

[0074] Taking processor debugging as an example, if the data type is address bus transaction, the time period is required to cover 50 cycles before the trigger and 100 cycles after the trigger, and the medium trigger mode can be configured: partially cache historical addresses before the trigger, and store subsequent data after the trigger. At this time, the ping-pong buffer depth needs to be set to 150 to ensure complete capture of the context.

[0075] Thus, redundant storage can be avoided by matching data types and time periods. For example, if high-frequency bus data only needs to be analyzed after triggering, the post-trigger mode can save more than 90% of storage space. Support dynamic switching modes. For example, when switching from performance analysis (mid-trigger) to fault reproduction (pre-trigger), no hardware changes are required, only parameters need to be reconfigured. For timing-sensitive data (such as DDR bus handshake signals), the mid-trigger mode ensures that the signal interaction before and after the trigger event is fully recorded, which facilitates the analysis of setup / hold time violations. For example, in automotive electronic chips, if the airbag control logic after the collision signal is triggered needs to be analyzed, the post-trigger mode can directly capture the sensor data and control instructions within 200ms after the trigger, and quickly locate the response delay problem. In summary, the data cache method realizes the refined management of storage resources by combining the data type and time period requirements, enabling the on-chip logic analyzer to efficiently cope with a variety of debugging scenarios.

[0076] As an optional embodiment, the trigger unit further includes a valid digit mask module. In 102, a valid digit mask is used to mark the corresponding data bits to be analyzed in the input data. Specifically, the valid digit mask module is used to mask the input data using a valid digit mask to mask the invalid data bits in the input data and retain the data bits to be analyzed in the input data.

[0077] The main function of the effective digit mask module is to accurately filter out the data bits that need to be analyzed during data processing, eliminate the interference of irrelevant data, improve the efficiency and accuracy of data processing, and reduce resource usage. For example, suppose you want to analyze the value of a 32-bit sensor data register, where the upper 8 bits represent the sensor type code and the lower 24 bits represent the sensor's measurement data. In the current analysis task, you only need to focus on the measurement data, that is, the lower 24 bits. At this time, the effective digit mask module can play a role. It will generate a effective digit mask, such as 0x00FFFFFF (binary representation is 00000000111111111111111111111111111). This mask is logically ANDed with the input 32-bit sensor data to mask out the upper 8-bit sensor type code and retain only the lower 24-bit measurement data.

[0078] In this way, in the subsequent stages of data processing, whether it is storage, transmission or analysis and calculation, only the 24 bits of valid data need to be operated, instead of the entire 32 bits of data. In this way, in terms of data storage, the storage resource usage can be reduced. For example, a 32-bit storage unit is required to store data, but now only a 24-bit storage unit is needed; in data transmission, the amount of data transmitted can be reduced and the transmission efficiency can be improved; in data analysis, unnecessary data processing is reduced, which can speed up the analysis, improve the accuracy and efficiency of the analysis, and allow the analysis results to focus more on key information.

[0079] As an optional embodiment, in step 103, comparing whether the data bit to be analyzed matches the pattern mask to obtain the matching result of the data bit to be analyzed can be implemented as the following steps: Step 1031, detecting the data value of the data bit to be analyzed in each clock cycle to determine whether there is the data bit to be analyzed that is consistent with the data value indicated by the mode mask; Step 1032, after detecting the data bits to be analyzed that are consistent with the data values ​​indicated by the pattern mask, determine whether the number of repetitions and / or the order of occurrence of the data values ​​in the data bits to be analyzed are the same as the number of repetitions and / or the order of occurrence of the data values ​​indicated by the pattern mask; Step 1033: if the number of repetitions and / or the order of occurrence of the data value in the data bit to be analyzed is the same as the pattern mask, then determining that the data bit to be analyzed matches the pattern mask; Step 1034: If the data bits to be analyzed that are consistent with the data values ​​indicated by the pattern mask are not detected, or the number of repetitions and / or the order of occurrence of the data values ​​in the data bits to be analyzed are different from the pattern mask, then the data bits to be analyzed do not match the pattern mask.

[0080] The specific steps and principles of comparing the matching situation between the data bits to be analyzed and the pattern mask in this optional embodiment are described in detail below.

[0081] In step 1031, the consistency between the data bits to be analyzed and the data values ​​of the pattern mask in each clock cycle is detected. During the operation of the on-chip logic analyzer, data bits to be analyzed are generated in each clock cycle. The pattern mask predefines the data values ​​that are expected to match. The system will continue to monitor the data values ​​of the data bits to be analyzed in each clock cycle, and compare them bit by bit with the data values ​​indicated by the pattern mask. For example, if the pattern mask is "1010", the data bits to be analyzed generated in clock cycle 1 are "1100", and the data bits do not match the pattern mask at this time; if the data bits to be analyzed generated in clock cycle 2 are "1010", then the data bits to be analyzed that are consistent with the data values ​​indicated by the pattern mask are detected.

[0082] In step 1032, the number of repetitions and / or the order of appearance of the data value are determined. After detecting the data bit to be analyzed that is consistent with the data value indicated by the pattern mask, the system needs to further check whether the number of repetitions and the order of appearance of the data value meet the requirements of the pattern mask. This step is to cope with more complex matching scenarios, such as when a specific data sequence needs to be repeated a specific number of times to be considered a valid trigger. For example, assuming that the pattern mask requires the data sequence "1010" to be repeated three times in a row, after detecting the first "1010", the system will continue to monitor the data of subsequent clock cycles. If "1010" also appears in the next two clock cycles, then the number of repetitions and the order of appearance of the data value are consistent with the pattern mask; if other data sequences appear in this process, such as "1100", it does not meet the requirements.

[0083] In step 1033, if the number of repetitions and / or the order of occurrence of the data value in the data bit to be analyzed is the same as the pattern mask, it can be determined that the data bit to be analyzed matches the pattern mask. This means that the current data stream meets the preset trigger condition, and the logic analyzer can perform corresponding operations according to the matching result, such as starting to store data in the ping-pong buffer, etc.

[0084] In step 1034, if no data bit to be analyzed is detected that is consistent with the data value indicated by the pattern mask during the entire monitoring process, or if a consistent data value is detected but the number of repetitions and / or the order of occurrence of the data value are different from the pattern mask, then it is determined that the data bit to be analyzed does not match the pattern mask. In this case, the logic analyzer will not trigger the corresponding storage or other operations and will continue to monitor the subsequent data stream.

[0085] Through the above steps, the on-chip logic analyzer can accurately determine whether the data bits to be analyzed match the pattern mask, thereby achieving precise data triggering and analysis to meet different debugging and monitoring needs.

[0086] As an optional embodiment, a plurality of trigger modes for the ping-pong buffer are provided in the trigger unit. Furthermore, the plurality of trigger modes of the ping-pong buffer include: a front trigger mode, a middle trigger mode, and a rear trigger mode. Specifically, the data caching method of the front trigger mode is: storing the first target data bit before the mode mask in the input data. The data caching method of the front trigger mode is: storing the second target data bit from before the mode mask to after the mode mask in the input data. The data caching method of the front trigger mode is: storing the third target data bit after the mode mask in the input data.

[0087] For different trigger modes, data signals of different time periods can be recorded. In the process of logic analysis and debugging, the trigger type determines the specific period of data capture. Pre-trigger mode, mid-trigger mode and post-trigger mode indicate different strategies for capturing data before and after the trigger signal event. Pre-trigger mode captures the signal state for a period of time before the trigger event occurs. This mode helps to understand the historical background of system behavior before the trigger event, which is very helpful for diagnosing the root cause of the problem. Mid-trigger mode captures data when the trigger event occurs and before and after it. It provides a comprehensive perspective, including signal changes before and after the event. This mode is suitable for situations where you want to fully analyze the entire process of the trigger event. Post-trigger mode captures the signal state for a period of time after the trigger event occurs. This mode focuses on observing the reaction after the trigger event, which helps to analyze the consequences of the trigger event.

[0088] As an optional embodiment, in step 104, according to the matching result and / or the data cache mode in which the trigger unit is located, controlling the data storage process of the custom storage array and the ping-pong buffer so that the target input data that meets the cache requirements in the input data is stored in the ping-pong buffer includes: After switching to the trigger mode of the trigger unit, instruct the custom storage array and / or the ping-pong buffer to start the data writing process of the input data; and / or, if the data bit to be analyzed matches the mode mask, instruct the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bits required to be cached from the input data as the target input data.

[0089] When the on-chip logic analyzer is working, the trigger mode will be pre-set according to the actual debugging needs, such as pre-trigger, mid-trigger, post-trigger mode, etc. When switching to the specified trigger mode, this is an important start signal for the entire data storage process. After the trigger mode is switched, the custom storage array and / or ping-pong buffer will be instructed to start the data writing process of the input data. For example, in the pre-trigger mode, the custom storage array will start to continuously store the input data before the trigger event occurs, so as to record the relevant data information before the trigger event occurs. If the ping-pong buffer is also required to participate in the data cache, the ping-pong buffer will also start data writing synchronously to ensure the continuity and integrity of the data.

[0090] After comparing the data bits to be analyzed of the input data with the pattern mask, if it is found that the data bits to be analyzed match the pattern mask, this means that the current input data meets the pre-set trigger condition. At this time, if the ping-pong buffer was previously in an unwritten state, the ping-pong buffer will be instructed to start the data writing process of the input data. For example, when debugging a communication protocol, the pattern mask is set to match a specific protocol frame header. When a frame header consistent with the pattern mask appears in the input data, the ping-pong buffer starts writing data and stores the subsequent data for subsequent analysis of the entire protocol frame.

[0091] Similarly, when the data bits to be analyzed match the pattern mask, if the ping-pong buffer was previously in a writing state, the ping-pong buffer can also be instructed to stop writing data according to specific needs. For example, in a scenario where only fixed-length data after a trigger event is required to be recorded, when the pattern mask is matched and the data of the specified length has been stored, the ping-pong buffer will be instructed to stop writing, avoiding the storage of too much unnecessary data and saving storage resources.

[0092] By controlling the start and stop writing process of the ping-pong buffer, the target data bits required for the cache can be accurately extracted from the input data, and these target data bits are combined to form the target input data. These target input data are crucial for subsequent data analysis and debugging, and can help engineers quickly locate problems and verify functions.

[0093] Through the above two methods, the data storage process of the custom storage array and the ping-pong buffer can be flexibly controlled according to the matching results and trigger modes, and the target input data that meets the cache requirements can be accurately stored in the ping-pong buffer.

[0094] The following example describes the specific mechanism of starting or stopping writing to the ping-pong buffer: The principle of the trigger-based control mechanism is that when the data bit to be analyzed matches the pre-set pattern mask, the corresponding control signal will be triggered. The pattern mask defines the data flag corresponding to a specific trigger event. For example, when debugging a communication system, the pattern mask may be set to match a specific data packet start flag. When the input data is processed and the data bit to be analyzed is consistent with the pattern mask, a match signal will be generated.

[0095] Start writing: This match signal is sent to the control logic of the ping-pong buffer. If the ping-pong buffer is idle at this time, the control logic enables the write enable signal to start the data writing process. For example, when a specific protocol frame header is detected, the write enable signal becomes high, allowing data to flow from the data source into the ping-pong buffer.

[0096] Stop writing: In some cases, when certain conditions are met, such as a preset amount of data has been stored or a specific time threshold has been reached, the control logic will cancel the write enable signal and stop data writing. For example, if the data is set to record only a complete data packet, when the data packet end mark is detected, the write enable signal becomes low and writing stops.

[0097] Trigger modes include pre-trigger, mid-trigger, post-trigger, etc. When the system switches to a specific trigger mode, a corresponding mode switching signal will be generated. Different trigger modes correspond to different data storage requirements. Taking the pre-trigger mode as an example, before the trigger event occurs, the system will instruct the ping-pong buffer to start writing according to the mode switching signal. For example, in the process of debugging the instruction execution of a processor, the pre-trigger mode is set, and the ping-pong buffer starts writing instruction data before detecting a possible abnormal instruction trigger event, so as to record the state before the trigger event occurs. For the post-trigger mode, when the trigger event occurs, data writing begins, and when the preset storage depth is reached or other stop conditions are met, writing stops. For example, after a fault signal is detected, subsequent data begins to be recorded, and when the ping-pong buffer is full or a fault recovery signal appears, writing stops.

[0098] The control logic of the ping-pong buffer is usually implemented using a state machine. The state machine has different states, such as idle state, write state, stop state, etc. The state machine switches between different states by receiving inputs such as trigger signals and mode switching signals. For example, when a trigger signal matching the pattern mask is received, the state machine switches from the idle state to the write state and starts writing; when the stop condition is met, it switches from the write state to the stop state and stops writing. Furthermore, in order to control the length and time of writing, counters and timers are used in the control logic. The counter can record the amount of data that has been written, and when the counter reaches a preset value, the writing stops. The timer can set the length of time for writing, and when the time is reached, the writing stops.

[0099] There is a dedicated write enable pin in the hardware circuit of the ping-pong buffer. The control logic controls this pin by outputting high and low level signals to start and stop writing. When the write enable signal is high, data can be written to the ping-pong buffer; when it is low, the write operation is prohibited. In addition to the write enable signal, it is also necessary to control the switch of the data path. When writing is turned on, the data path is turned on, allowing data to be transferred from the data source to the ping-pong buffer; when writing is stopped, the data path is cut off to prevent data from continuing to flow in.

[0100] Example 1: Pre-trigger mode.

[0101] First, in the above steps, after the trigger unit switches to the pre-trigger mode, a first write signal for starting the data storage function is generated; the data write function of the ping-pong buffer is started by the first write signal; the input data is sequentially transmitted to the ping-pong buffer in the order of reception through the custom storage array. Furthermore, in the above steps, after the data bit to be analyzed is detected to match the pattern mask in the custom storage array, a first stop signal for immediately stopping the data storage function is generated; the data write function of the ping-pong buffer is turned off by the first stop signal, and the data transmission between the custom storage array and the ping-pong buffer is stopped, so that the target data bit stored in the ping-pong buffer is the first target data bit.

[0102] It is understandable that when the trigger unit receives the instruction to switch to the pre-trigger mode, the control logic inside it will perform the corresponding state conversion and generate the first write signal for starting the data storage function. This signal can be a level signal (such as a high level indicates validity), which is used to notify the ping-pong buffer and the custom storage array that the data storage operation is about to start. The first write signal is sent to the ping-pong buffer. After receiving the signal, the control circuit of the ping-pong buffer will enable the writing of the relevant circuit module, such as turning on the switch of the data input port to allow data to flow in. At this time, the ping-pong buffer is ready to receive data from the custom storage array. After receiving the first write signal, the custom storage array starts to transmit the input data to the ping-pong buffer in sequence according to the order in which the data is received. In this process, the custom storage array may use internal cache and data transmission logic to ensure stable data transmission. For example, it can send a data unit to the data bus of the ping-pong buffer in each clock cycle. In the process of continuous data transmission by the custom storage array, its internal comparison module will continuously detect whether the data bit to be analyzed matches the mode mask.

[0103] When a match is detected between the two, the comparison module triggers the control logic to generate a first stop signal for immediately stopping the data storage function. This signal can also be a level signal. The first stop signal is sent to the ping-pong buffer and the custom storage array. After receiving the signal, the ping-pong buffer turns off the write function, such as turning off the switch of the data input port to prevent new data from flowing in. At the same time, the custom storage array also stops transmitting data to the ping-pong buffer, cutting off the data connection between the two. In this way, the data stored in the ping-pong buffer is the target data bit from the beginning of storage to the detection of a match, that is, the first target data bit.

[0104] Therefore, the pre-trigger mode can start storing data before the trigger event occurs, ensuring that when the trigger event occurs, the complete data information before the trigger can be obtained. This is very helpful for analyzing the cause and background of the trigger event. For example, when analyzing a circuit fault, you can view the circuit state and data changes before the fault occurs. By matching the pattern mask with the data bit to be analyzed to stop data storage, the moment when the trigger event occurs can be accurately located, so that the stored data contains the most relevant information, reducing the storage of irrelevant data and improving the efficiency and pertinence of data storage. The first target data bit stored in the ping-pong buffer provides an accurate data basis for subsequent troubleshooting and system analysis. Engineers can analyze the system state changes before and after the trigger event based on these data, quickly locate the problem, and improve the efficiency of debugging and maintenance. The implementation of the pre-trigger mode allows users to flexibly configure the pattern mask and trigger conditions according to specific needs to adapt to different application scenarios and analysis purposes. Whether in hardware debugging or software function verification, it can provide effective data support.

[0105] Example 2: Medium trigger mode.

[0106] First, in the above steps, after the trigger unit switches to the medium trigger mode, a first write signal for turning on the data storage function is generated, and the data storage function of the custom storage array is started; the data write function of the ping-pong buffer is started by the first write signal; and the input data is transmitted to the ping-pong buffer in sequence according to the order of reception through the custom storage array. Furthermore, in the above steps, after the data bit to be analyzed is detected to match the pattern mask in the custom storage array, a second stop signal for stopping the data storage function after a preset clock cycle is generated according to the pre-configured storage rule; wherein the number of preset clock cycles is determined by the preset number of bits to be stored after the pattern mask. Finally, the second stop signal is used to delay the closing of the data write function of the ping-pong buffer, and the data transmission between the custom storage array and the ping-pong buffer is delayed, so that the target data bit stored in the ping-pong buffer is the second target data bit.

[0107] It can be understood that when the trigger unit receives the instruction to switch to the medium trigger mode, its internal logic performs a state transition and generates a first write signal for starting the data storage function. On the one hand, this signal starts the data storage function of the custom storage array, so that it starts to cache input data; on the other hand, it is sent to the ping-pong buffer, so that the control circuit of the ping-pong buffer enables the write module, opens the data input port, and prepares to receive data. The custom storage array transmits the input data to the ping-pong buffer in sequence according to the order in which the data is received. During this process, data continuously flows in and is stored.

[0108] While the custom storage array continues to receive and transmit data, its internal comparison module detects in real time whether the data bits to be analyzed match the pattern mask. Once a match is detected, the control logic of the trigger unit will generate a second stop signal according to the pre-configured storage rule. The storage rule here is related to the preset clock cycle, and the number of preset clock cycles is determined by the preset number of bits required to be stored after the pattern mask. For example, if 32 bits of data are transmitted per clock cycle, and the preset need to store 128 bits of data after the pattern mask matches, then the number of preset clock cycles is 4.

[0109] After the second stop signal is generated, it does not take effect immediately. It will be sent to the ping-pong buffer and the custom storage array after the preset number of clock cycles. When the ping-pong buffer receives the second stop signal, it will turn off the write function, close the data input port, and prevent new data from flowing in; at the same time, the custom storage array will also stop transmitting data to the ping-pong buffer, cutting off the data connection between the two. At this time, the data stored in the ping-pong buffer is the target data bit stored from the beginning to the pattern mask matching and then stored after the preset clock cycle, that is, the second target data bit.

[0110] Therefore, the medium trigger mode can not only record the data before the trigger event occurs, but also continue to store a certain amount of data according to the preset rules after the trigger event occurs. This allows users to fully understand the entire process of the trigger event, including the state before the trigger, the situation during the trigger, and the system response after the trigger, which is very helpful for in-depth analysis of the cause and impact of the event. By pre-configuring the storage rules and determining the preset clock cycle according to the preset number of bits required to be stored after the pattern mask, users can flexibly control the storage depth of the data. The storage length can be adjusted according to specific analysis needs, which not only ensures that sufficient information is obtained, but also avoids storing too much unnecessary data, thereby improving the utilization efficiency of storage resources. In many practical applications, only analyzing the data before or after the trigger may not meet the needs. The medium trigger mode provides a compromise solution that can adapt to various complex analysis scenarios. For example, when debugging complex digital circuits or software systems, this mode can help engineers locate problems more accurately and improve the efficiency of troubleshooting and system optimization. This mode makes the on-chip logic analyzer more intelligent and flexible in data acquisition and storage, which can better meet the debugging needs of different users and different projects, enhance the overall debugging capabilities of the system, and provide engineers with more powerful tools to verify and optimize designs.

[0111] Example 3: Post-trigger mode.

[0112] First, in the above steps, after the trigger unit switches to the post-trigger mode, a first stop signal is generated for immediately stopping the data storage function; the data writing function of the ping-pong buffer is turned off by the first stop signal. Furthermore, in the above steps, after the data bit to be analyzed is detected to match the pattern mask in the custom storage array, a second write signal is generated for starting the data storage function according to the pre-configured storage rule; the data writing function of the ping-pong buffer is started by the second write signal; the input data is sequentially transmitted to the ping-pong buffer in the order of reception by the custom storage array. Finally, in the above steps, the first stop signal is generated after a preset clock cycle; wherein the number of preset clock cycles is determined by the preset number of bits to be stored after the pattern mask. The data writing function of the ping-pong buffer is turned off by the first stop signal, and the data transmission between the custom storage array and the ping-pong buffer is stopped, so that the target data bit stored in the ping-pong buffer is the third target data bit.

[0113] It is worth noting that when the trigger unit receives the instruction to switch to the post-trigger mode, its internal logic responds quickly and generates a first stop signal for immediately stopping the data storage function. This signal is sent to the ping-pong buffer. After receiving the signal, the control circuit of the ping-pong buffer immediately turns off the write function and the data input port to prevent the input data from flowing into the ping-pong buffer. At this time, the ping-pong buffer is in a state of not storing data.

[0114] The custom storage array continues to receive input data and analyze the data during the period when the ping-pong buffer stops storing data. The internal comparison module continuously detects whether the data bit to be analyzed matches the pattern mask. Once a match is detected, the control logic of the trigger unit generates a second write signal for starting the data storage function according to the pre-configured storage rule. In the storage rule, the number of preset clock cycles is determined by the preset number of bits required to be stored after the pattern mask. For example, if 64 bits of data are transmitted per clock cycle, and the preset need to store 256 bits of data after the pattern mask matches, then the number of preset clock cycles is 4.

[0115] The second write signal is sent to the ping-pong buffer. After receiving the signal, the control circuit of the ping-pong buffer enables the write module, opens the data input port, and starts receiving data. The custom storage array transmits the input data to the ping-pong buffer in sequence according to the order in which the data is received, and the data begins to flow in and be stored continuously.

[0116] After a preset number of clock cycles, the trigger unit generates the first stop signal again. This signal is sent to the ping-pong buffer and the custom storage array. After receiving the signal, the ping-pong buffer turns off the write function and the data input port to prevent new data from flowing in; the custom storage array also stops transmitting data to the ping-pong buffer, cutting off the data connection between the two. At this time, the data stored in the ping-pong buffer is the target data bit stored from the time the pattern mask matches to the time the first stop signal is received again, that is, the third target data bit.

[0117] Therefore, the post-trigger mode focuses on storing relevant data after the trigger event occurs, which is very suitable for scenarios that only care about the system state changes and responses after the trigger event. For example, after detecting a fault signal in the system, the post-trigger mode can accurately obtain a series of data after the fault occurs, which is helpful for analyzing the specific cause and impact range of the fault. By pre-configuring the storage rules, the preset clock cycle is determined according to the preset number of bits required to be stored after the pattern mask, and the content and length of the stored data can be accurately controlled. It avoids storing too much irrelevant historical data, improves the utilization efficiency of storage resources, and also makes subsequent data processing and analysis more efficient because the amount of data processed is relatively small and more targeted. In some application scenarios, such as focusing on the execution after a specific function call in software debugging, or focusing on the system response after a signal change in hardware testing, the post-trigger mode can well meet these specific analysis needs. It provides a flexible way to obtain data of interest and enhances the applicability of on-chip logic analyzers in different application scenarios. Since only the relevant data after the trigger is stored, the complexity and processing volume of the data are reduced, and the data processing process is simplified. Engineers can analyze and interpret stored data more quickly, improving the efficiency of troubleshooting and system optimization, helping to solve problems and improve designs more quickly.

[0118] In the embodiment of the present application, through the coordinated control of the effective bit number mask, the pattern mask, the custom storage array and the ping-pong buffer, the trigger conditions can be flexibly set according to the specific analysis requirements to meet different debugging and analysis scenarios, and the data related to the target event can be captured more accurately, thereby improving the adaptability and practicality of the logic analyzer, effectively improving the debugging efficiency and the utilization of storage resources, and further providing strong support for in-depth data analysis.

[0119] In another embodiment of the present application, an on-chip logic analyzer is also provided. Figure 3 The on-chip logic analyzer at least includes the following structures: a trigger unit and a ping-pong buffer, wherein the trigger unit at least includes a custom storage array; A trigger unit is configured to obtain input data to be processed; mark the corresponding data bits to be analyzed in the input data using a valid bit mask; compare whether the data bits to be analyzed match the pattern mask to obtain the matching result of the data bits to be analyzed; wherein the pattern mask is used to indicate the data flag bit corresponding to a specific trigger event; the specific trigger event is associated with the data analysis process performed by the on-chip logic analyzer; and control the data storage process of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching mode of the trigger unit, so that the target input data that meets the caching requirements in the input data is stored in the ping-pong buffer; A ping-pong buffer is configured to receive target input data input through a custom storage array.

[0120] Further optionally, the trigger unit further includes a valid digit mask module; the trigger unit uses the valid digit mask to mark the corresponding data bits to be analyzed in the input data, and is configured as follows: The input data is masked by using a valid bit number mask module to mask invalid data bits in the input data and retain the data bits to be analyzed in the input data.

[0121] Further optionally, the trigger unit, before acquiring the input data to be processed through the trigger unit, is further configured to: Selecting a target trigger mode that matches the cache requirement from a plurality of trigger modes configured by the trigger unit; wherein the cache requirement is obtained based on a user input instruction; or the cache requirement is determined by data analysis of the on-chip logic analyzer; The attribute parameters in the target trigger mode are set to configure a valid bit mask, a mode mask, and a data cache mode of the trigger unit that match the cache requirement.

[0122] Further optionally, the structure and storage depth of the custom storage array are determined by the data cache mode configured in the target trigger mode.

[0123] Further optionally, the trigger unit sets the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and a data cache mode in which the trigger unit is located that match the cache requirement, and is configured as follows: Identify the data analysis type in the cache requirement; determine the data bits currently required to be analyzed based on the data analysis type, the data type to which the input data belongs, and the historical analysis method, and generate a corresponding valid bit number mask.

[0124] Further optionally, the trigger unit sets the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and a data cache mode in which the trigger unit is located that match the cache requirement, and is configured as follows: Determine the data jump form to be observed in the cache demand; the data jump form includes: at least one of data change value, data change trend, data change amplitude, data timing, and data repetition number; dynamically configure the corresponding mode mask according to the determined data jump form.

[0125] Further optionally, the data caching mode is jointly determined by the type of data to be analyzed and the time period in which the data is located; the trigger unit sets the attribute parameters in the target trigger mode to configure the effective bit mask, mode mask, and data caching mode in which the trigger unit is located that match the cache requirement, and is configured as follows: Determine the data type and the time period in which the data is located that need to be analyzed in the cache requirement; select a corresponding target data cache method from a plurality of pre-configured data cache methods according to the data type and the time period in which the data is located that need to be analyzed.

[0126] Further optionally, the trigger unit compares whether the data bit to be analyzed matches the pattern mask to obtain a matching result of the data bit to be analyzed, and is configured to: Detecting the data value of the data bit to be analyzed in each clock cycle to determine whether there is the data bit to be analyzed that is consistent with the data value indicated by the mode mask; After detecting the data bits to be analyzed that are consistent with the data values ​​indicated by the pattern mask, determining whether the number of repetitions and / or the order of occurrence of the data values ​​in the data bits to be analyzed are the same as the number of repetitions and / or the order of occurrence of the data values ​​indicated by the pattern mask; If the number of repetitions and / or the order of occurrence of the data values ​​in the data bits to be analyzed are the same as the pattern mask, determining that the data bits to be analyzed match the pattern mask; If the data bits to be analyzed are not detected to be consistent with the data values ​​indicated by the pattern mask, or the number of repetitions and / or the order of occurrence of the data values ​​in the data bits to be analyzed are different from the pattern mask, the data bits to be analyzed do not match the pattern mask.

[0127] Further optionally, a plurality of trigger modes for the ping-pong buffer are provided in the trigger unit; the plurality of trigger modes of the ping-pong buffer include: a front trigger mode, a middle trigger mode, and a rear trigger mode; the data caching method of the front trigger mode is: storing the first target data bit in the input data before the mode mask; the data caching method of the front trigger mode is: storing the second target data bit in the input data from before the mode mask to after the mode mask; the data caching method of the front trigger mode is: storing the third target data bit in the input data after the mode mask.

[0128] Further optionally, the trigger unit controls the data storage process of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching mode in which the trigger unit is located, so that the target input data that meets the caching requirement in the input data is stored in the ping-pong buffer, and is configured as follows: After switching to the trigger mode of the trigger unit, instructing the custom storage array and / or the ping-pong buffer to start the data writing process of the input data; and / or If the data bits to be analyzed match the mode mask, the ping-pong buffer is instructed to start or stop the data writing process of the input data, so as to extract the target data bits required to be cached from the input data as the target input data.

[0129] Further optionally, the trigger unit, which instructs the custom storage array and / or the ping-pong buffer to start the data writing process of the input data, is configured as follows: After the trigger unit switches to the front trigger mode, a first write signal for starting the data storage function is generated; Starting a data writing function of the ping-pong buffer through the first write signal; The input data is sequentially transmitted to the ping-pong buffer in the order of reception through a custom storage array; The trigger unit, if the data bit to be analyzed matches the pattern mask, instructs the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bit to be cached from the input data as the target input data, is configured as follows: After detecting in the custom storage array that the data bit to be analyzed matches the pattern mask, generating a first stop signal for immediately stopping the data storage function; The data writing function of the ping-pong buffer is turned off by the first stop signal, and the data transmission between the custom storage array and the ping-pong buffer is stopped, so that the target data bit stored in the ping-pong buffer is the first target data bit.

[0130] Further optionally, the trigger unit, which instructs the custom storage array and / or the ping-pong buffer to start the data writing process of the input data, is configured as follows: After the trigger unit switches to the middle trigger mode, a first write signal for starting the data storage function is generated, and the data storage function of the custom storage array is started; Starting a data writing function of the ping-pong buffer through the first write signal; The input data is sequentially transmitted to the ping-pong buffer in the order of reception through a custom storage array; The trigger unit, if the data bit to be analyzed matches the pattern mask, instructs the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bit to be cached from the input data as the target input data, is configured as follows: After detecting that the data bit to be analyzed matches the pattern mask in the custom storage array, generating a second stop signal for stopping the data storage function after a preset clock cycle according to a preconfigured storage rule; wherein the number of the preset clock cycles is determined by the preset number of bits required to be stored after the pattern mask; The second stop signal is used to delay closing the data writing function of the ping-pong buffer, and to delay stopping the data transmission between the custom storage array and the ping-pong buffer, so that the target data bit stored in the ping-pong buffer is the second target data bit.

[0131] Further optionally, the trigger unit, if the to-be-analyzed data bit matches the pattern mask, instructs the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bit to be cached from the input data as the target input data, is configured as follows: After the trigger unit switches to the post-trigger mode, a first stop signal is generated for immediately stopping the data storage function; Turning off the data writing function of the ping-pong buffer by using the first stop signal; After detecting in the custom storage array that the data bit to be analyzed matches the pattern mask, generating a second write signal for starting a data storage function according to a preconfigured storage rule; Starting a data writing function of the ping-pong buffer through the second write signal; The input data is sequentially transmitted to the ping-pong buffer in the order of reception through a custom storage array; After a preset clock cycle, generating the first stop signal; wherein the number of preset clock cycles is determined by the preset number of bits required to be stored after the mode mask; The data writing function of the ping-pong buffer is turned off by the first stop signal, and the data transmission between the custom storage array and the ping-pong buffer is stopped, so that the target data bit stored in the ping-pong buffer is the third target data bit.

[0132] Further optionally, the custom storage array and ping-pong buffer in the trigger unit are set as a multi-level first-in-first-out storage array FIFO; the FIFO depth and number of layers corresponding to the custom storage array and ping-pong buffer can be dynamically configured based on the trigger mode of the trigger unit.

[0133] The system can implement various steps in the above method embodiment, which will not be expanded here.

[0134] In the embodiment of the present application, an on-chip logic analyzer is used. Through the coordinated control of the effective bit number mask, the pattern mask, the custom storage array and the ping-pong buffer, the trigger conditions can be flexibly set according to the specific analysis needs to meet different debugging and analysis scenarios, and the data related to the target event can be more accurately captured, thereby improving the adaptability and practicality of the logic analyzer, effectively improving the debugging efficiency and the utilization of storage resources, and further providing strong support for in-depth data analysis.

[0135] See also Figure 4 , Figure 4 Schematic diagram of an electronic device provided in an embodiment of the present application. Figure 4 As shown, an embodiment of the present application provides an electronic device 500, including a memory 510, a processor 520 and a computer program 511 stored in the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 511, the following steps are implemented: obtaining input data to be processed through a trigger unit; marking corresponding data bits to be analyzed in the input data using a valid bit number mask; comparing whether the data bits to be analyzed match the pattern mask to obtain a matching result of the data bits to be analyzed; wherein the pattern mask is used to indicate a data flag bit corresponding to a specific trigger event; the specific trigger event is associated with a data analysis process executed by the on-chip logic analyzer; and controlling the data storage process of a custom storage array and a ping-pong buffer according to the matching result and / or the data caching mode in which the trigger unit is located, so that target input data in the input data that meets the caching requirements is stored in the ping-pong buffer.

[0136] See also Figure 5 , Figure 5 A schematic diagram of an embodiment of a computer-readable storage medium provided in an embodiment of the present application. Figure 5As shown, this embodiment provides a computer-readable storage medium 600, on which computer program information 611 is stored. When the computer program information 611 is executed by a processor, the following steps are implemented: obtaining input data to be processed through a trigger unit; using a valid bit mask to mark the corresponding data bits to be analyzed in the input data; comparing whether the data bits to be analyzed match the pattern mask to obtain the matching results of the data bits to be analyzed; wherein the pattern mask is used to indicate the data flag bits corresponding to a specific trigger event; the specific trigger event is associated with the data analysis process executed by the on-chip logic analyzer; according to the matching result and / or the data caching mode of the trigger unit, controlling the data storage process of the custom storage array and the ping-pong buffer, so that the target input data that meets the caching requirements in the input data is stored in the ping-pong buffer.

[0137] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0138] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0139] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0140] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data caching method for an on-chip logic analyzer, characterized in that: The on-chip logic analyzer comprises at least the following structures: a trigger unit and a ping-pong buffer, wherein the trigger unit comprises at least a custom storage array; and the method comprises: Acquiring input data to be processed through a trigger unit; Using a valid digit mask to mark the corresponding data bits to be analyzed in the input data; Comparing whether the data bit to be analyzed matches the pattern mask to obtain a matching result of the data bit to be analyzed; wherein the pattern mask is used to indicate a data flag bit corresponding to a specific trigger event; and the specific trigger event is associated with a data analysis process performed by the on-chip logic analyzer; According to the matching result and / or the data cache mode of the trigger unit, the data storage process of the custom storage array and the ping-pong buffer is controlled so that the target input data that meets the cache requirements in the input data is stored in the ping-pong buffer.

2. The data caching method of an on-chip logic analyzer according to claim 1, characterized in that: The trigger unit also includes a valid bit number mask module; The step of using a valid bit mask to mark corresponding data bits to be analyzed in the input data includes: The input data is masked by using a valid bit number mask module to mask invalid data bits in the input data and retain the data bits to be analyzed in the input data.

3. The data caching method of an on-chip logic analyzer according to claim 1, characterized in that: Before acquiring the input data to be processed by the trigger unit, the method further includes: Selecting a target trigger mode that matches the cache requirement from a plurality of trigger modes configured by the trigger unit; wherein the cache requirement is obtained based on a user input instruction; or the cache requirement is determined by data analysis of the on-chip logic analyzer; The attribute parameters in the target trigger mode are set to configure a valid bit mask, a mode mask, and a data cache mode of the trigger unit that match the cache requirement.

4. The data caching method of the on-chip logic analyzer according to claim 3, characterized in that: The structure and storage depth of the custom storage array are determined by the data cache mode configured in the target trigger mode.

5. The data caching method of the on-chip logic analyzer according to claim 3, characterized in that: The setting of the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and a data cache mode of the trigger unit that match the cache requirement includes: Identifying the type of data analysis in the cache requirement; According to the data analysis type, the data type to which the input data belongs, and the historical analysis method, the data bits currently required to be analyzed are determined, and a corresponding effective bit number mask is generated.

6. The data caching method of an on-chip logic analyzer according to claim 3, characterized in that: The setting of the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and a data cache mode of the trigger unit that match the cache requirement includes: Determine the data jump form to be observed in the cache requirement; the data jump form includes: at least one of: data change value, data change trend, data change amplitude, data time sequence, and data repetition number; The corresponding mode mask is dynamically configured according to the determined data jump form.

7. The data caching method of an on-chip logic analyzer according to claim 3, characterized in that: The data caching method is determined by the type of data to be analyzed and the time period of the data; The setting of the attribute parameters in the target trigger mode to configure a valid bit mask, a mode mask, and a data cache mode of the trigger unit that match the cache requirement includes: Determine the type of data that needs to be analyzed in the cache requirement and the time period in which the data is located; According to the type of data to be analyzed and the time period in which the data is located, the corresponding target data caching method is selected from a variety of pre-configured data caching methods.

8. The data caching method of an on-chip logic analyzer according to claim 1, characterized in that: The comparing whether the data bit to be analyzed matches the pattern mask to obtain a matching result of the data bit to be analyzed includes: Detecting the data value of the data bit to be analyzed in each clock cycle to determine whether there is the data bit to be analyzed that is consistent with the data value indicated by the mode mask; After detecting the data bits to be analyzed that are consistent with the data values ​​indicated by the pattern mask, determining whether the number of repetitions and / or the order of occurrence of the data values ​​in the data bits to be analyzed are the same as the number of repetitions and / or the order of occurrence of the data values ​​indicated by the pattern mask; If the number of repetitions and / or the order of occurrence of the data values ​​in the data bits to be analyzed are the same as the pattern mask, determining that the data bits to be analyzed match the pattern mask; If the data bits to be analyzed are not detected to be consistent with the data values ​​indicated by the pattern mask, or the number of repetitions and / or the order of occurrence of the data values ​​in the data bits to be analyzed are different from the pattern mask, the data bits to be analyzed do not match the pattern mask.

9. The data caching method of an on-chip logic analyzer according to claim 1, characterized in that: The trigger unit is provided with a plurality of trigger modes for the ping-pong buffer zone; the plurality of trigger modes for the ping-pong buffer zone include: a front trigger mode, a middle trigger mode, and a rear trigger mode; The data caching method of the pre-trigger mode is: storing the first target data bit before the mode mask in the input data; The data caching method of the pre-trigger mode is: storing the second target data bit from before the mode mask to after the mode mask in the input data; The data cache method of the pre-trigger mode is: storing the third target data bit after the mode mask in the input data.

10. The data caching method of an on-chip logic analyzer according to claim 9, characterized in that: The controlling of the data storage process of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching mode of the trigger unit so that the target input data that meets the caching requirement in the input data is stored in the ping-pong buffer comprises: After switching to the trigger mode of the trigger unit, instructing the custom storage array and / or the ping-pong buffer to start the data writing process of the input data; and / or If the data bits to be analyzed match the mode mask, the ping-pong buffer is instructed to start or stop the data writing process of the input data, so as to extract the target data bits required to be cached from the input data as the target input data.

11. The data caching method of an on-chip logic analyzer according to claim 10, characterized in that: The step of instructing the custom storage array and / or ping-pong buffer to start the data writing process of the input data includes: After the trigger unit switches to the front trigger mode, a first write signal for starting the data storage function is generated; Starting a data writing function of the ping-pong buffer through the first write signal; The input data is sequentially transmitted to the ping-pong buffer in the order of reception through a custom storage array; If the data bit to be analyzed matches the pattern mask, instructing the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bit to be cached from the input data as the target input data, including: After detecting in the custom storage array that the data bit to be analyzed matches the pattern mask, generating a first stop signal for immediately stopping the data storage function; The data writing function of the ping-pong buffer is turned off by the first stop signal, and the data transmission between the custom storage array and the ping-pong buffer is stopped, so that the target data bit stored in the ping-pong buffer is the first target data bit.

12. The data caching method of an on-chip logic analyzer according to claim 10, characterized in that: The step of instructing the custom storage array and / or ping-pong buffer to start the data writing process of the input data includes: After the trigger unit switches to the middle trigger mode, a first write signal for starting the data storage function is generated, and the data storage function of the custom storage array is started; Starting a data writing function of the ping-pong buffer through the first write signal; The input data is sequentially transmitted to the ping-pong buffer in the order of reception through a custom storage array; If the data bit to be analyzed matches the pattern mask, instructing the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bit to be cached from the input data as the target input data, including: After detecting that the data bit to be analyzed matches the pattern mask in the custom storage array, generating a second stop signal for stopping the data storage function after a preset clock cycle according to a preconfigured storage rule; wherein the number of the preset clock cycles is determined by the preset number of bits required to be stored after the pattern mask; The second stop signal is used to delay closing the data writing function of the ping-pong buffer, and to delay stopping the data transmission between the custom storage array and the ping-pong buffer, so that the target data bit stored in the ping-pong buffer is the second target data bit.

13. The data caching method of an on-chip logic analyzer according to claim 10, characterized in that: If the data bit to be analyzed matches the pattern mask, instructing the ping-pong buffer to start or stop the data writing process of the input data, so as to extract the target data bit to be cached from the input data as the target input data, including: After the trigger unit switches to the post-trigger mode, a first stop signal is generated for immediately stopping the data storage function; Turning off the data writing function of the ping-pong buffer by using the first stop signal; After detecting in the custom storage array that the data bit to be analyzed matches the pattern mask, generating a second write signal for starting a data storage function according to a preconfigured storage rule; Starting a data writing function of the ping-pong buffer through the second write signal; The input data is sequentially transmitted to the ping-pong buffer in the order of reception through a custom storage array; After a preset clock cycle, generating the first stop signal; wherein the number of the preset clock cycles is determined by the preset number of bits required to be stored after the mode mask; The data writing function of the ping-pong buffer is turned off by the first stop signal, and the data transmission between the custom storage array and the ping-pong buffer is stopped, so that the target data bit stored in the ping-pong buffer is the third target data bit.

14. The data caching method of an on-chip logic analyzer according to claim 1, characterized in that: The custom storage array and ping-pong buffer in the trigger unit are set as a multi-level first-in-first-out storage array FIFO; The FIFO depth and number of layers corresponding to the custom storage array and the ping-pong buffer can be dynamically configured based on the trigger mode of the trigger unit.

15. An on-chip logic analyzer, characterized in that: The on-chip logic analyzer comprises at least the following structures: a trigger unit and a ping-pong buffer, wherein the trigger unit comprises at least a custom storage array; A trigger unit is configured to obtain input data to be processed; mark the corresponding data bits to be analyzed in the input data using a valid bit mask; compare whether the data bits to be analyzed match the pattern mask to obtain the matching result of the data bits to be analyzed; wherein the pattern mask is used to indicate the data flag bit corresponding to a specific trigger event; the specific trigger event is associated with the data analysis process performed by the on-chip logic analyzer; and control the data storage process of the custom storage array and the ping-pong buffer according to the matching result and / or the data caching mode of the trigger unit, so that the target input data that meets the caching requirements in the input data is stored in the ping-pong buffer; A ping-pong buffer is configured to receive target input data input through a custom storage array.

16. An electronic device, characterized in that: include: Memory for storing computer software programs; A processor is used to read and execute the computer software program, thereby implementing the data caching method of the on-chip logic analyzer as described in any one of claims 1-14.

17. A computer-readable storage medium, characterized in that: The storage medium stores a computer software program, and when the computer software program is executed by the processor, the data caching method of the on-chip logic analyzer according to any one of claims 1 to 14 is implemented.

18. A chip, characterized in that: The chip is loaded with a computer software program and / or a hardware unit, and the computer software program and / or the hardware unit are used to implement the data caching method of the on-chip logic analyzer as described in any one of claims 1-14.

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