Server management system and method, computer equipment and storage medium

Abstract

The invention relates to a server management system and method, computer equipment and a storage medium. The system comprises a first management board and a second management board, a target device, a first controller, a multiplexer and an expansion chip are arranged on a main board, a third controller and a second controller are arranged on the first management board, and a fourth controller is arranged on the second management board; the output end of the target equipment is connected with the input end of the first controller; the input end of the expansion chip is connected with the output end of the third controller and the output end of the fourth controller, and the output end of the expansion chip is connected with the input end of the first controller and the input end of the multiplexer; the input end of the multiplexer is connected with the output end of the first controller, and the output end of the multiplexer is connected with the input end of the fourth controller and the input end of the second controller. By adopting the system, the mainboard can be reused by different types of management boards.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a server management system, method, computer equipment and storage medium. Background Art

[0002] With the rise of intelligent computing such as high-performance computing and AI computing, the demand for servers is also increasing rapidly. As the management chip of the server, the baseboard management controller (BMC) plays a very important role. Currently, there are two types of mainstream BMC management boards, which have significant differences in design. Among them, the UART serial port is an important interface for the server's external output. The designs of the two management boards are also very different and incompatible. Summary of the invention

[0003] Based on this, it is necessary to provide a server management system, method, computer equipment and storage medium that can realize the reuse of different types of management boards and main boards and improve the reliability of the server system in order to address the above technical problems.

[0004] In order to solve the above technical problems, in a first aspect, a server management system is provided, the system comprising:

[0005] The management board and the main board include a first management board and a second management board. The main board is provided with a target device, a first controller, a multiplexer and an expansion chip:

[0006] A third controller and a second controller are arranged on the first management board, and the third controller is connected to the second controller; a fourth controller is arranged on the second management board;

[0007] The output terminal of the target device is connected to the input terminal of the first controller;

[0008] The input end of the expansion chip is connected to the output end of the third controller and the output end of the fourth controller, and the output end of the expansion chip is connected to the input end of the first controller and the input end of the multiplexer;

[0009] The input end of the multiplexer is connected to the output end of the first controller, and the output end of the multiplexer is connected to the input end of the fourth controller and the input end of the second controller;

[0010] The first controller receives a target signal transmitted by a target device, and the expansion chip is used to receive a first control signal transmitted by a third controller and / or a fourth controller, generates a second control signal based on the first control signal and transmits the second control signal to the first controller and the multiplexer, so that the first controller determines the type of the target management board and the multiplexer controls the selection of the multiplexer interface, thereby realizing the transmission of the target signal to the target management board.

[0011] In one embodiment, the multiplexer includes a first multiplexer, which is located on the first controller, the input end of the first multiplexer is connected to the output end of the first controller and the output end of the expansion chip, and the output end of the first multiplexer is connected to the input end of the fourth controller and the input end of the second controller.

[0012] In one embodiment, the server management system also includes a connecting line of a first management board and a connecting line of a second management board, the input end of the connecting line of the first management board is connected to the third controller, the output end of the connecting line of the first management board is connected to the input end of the extension chip and the input end of the second controller, the input end of the connecting line of the second management board is connected to the output end of the fourth controller, and the output end of the connecting line of the second management board is connected to the input end of the extension chip.

[0013] In one embodiment, the server management system also includes a serial port connector, the multiplexer also includes a second multiplexer, the second multiplexer is located on the main board close to the management board, the serial port connector is located on the main board, the input end of the second multiplexer is connected to the output end of the expansion chip, the output end of the second controller, and the output end of the fourth controller, the output end of the second multiplexer is connected to the input end of the first controller, the input end of the serial port connector is connected to the output end of the second multiplexer and the output end of the first controller, and the output end of the serial port connector is connected to the connection serial port.

[0014] In one embodiment, the first control signal includes an interface detection signal and a usage signal, wherein the interface detection signal is used to determine the type of the target management board, and the usage signal is used to control the selection of the interface of the second multiplexer.

[0015] In order to solve the above technical problem, in a second aspect, a server management method is provided, applying any one of the above claims to the server management system, the method comprising:

[0016] In response to the expansion chip receiving the first control signal transmitted by the third controller and / or the fourth controller, the expansion chip generates a second control signal and transmits the second control signal to the first controller and the multiplexer;

[0017] In response to the first controller and the multiplexer acquiring the second control signal, the second control signal is parsed to determine the type of the target management board and the gating of the multiplexer interface corresponding to the target management board;

[0018] According to the selection of the multiplexer interface corresponding to the target management board, the target signal is transmitted to the target management board for processing.

[0019] In one embodiment, the method further comprises:

[0020] In response to the first controller acquiring a second control signal, the second control signal includes an interface detection signal and a use signal;

[0021] Analyze the interface detection signal to obtain the level status of the interface detection signal;

[0022] The first controller determines the type of the target management board according to the level state of the interface detection signal, and the type of the target management board includes a first management board and a second management board;

[0023] If the target management board type is the first management board, the first controller acquires the target signal transmitted by the target device;

[0024] Analyze the usage signal to determine the gating of the multiplexer interface corresponding to the first management board;

[0025] The gating of the multiplexer interface corresponding to the first management board includes: setting the first interface of the first multiplexer to a disabled state, gating a path formed by the second interface and the third interface of the second multiplexer;

[0026] The first controller transmits the target signal to the second controller via the second interface of the first multiplexer;

[0027] The second controller receives the target signal transmitted by the first controller and the third controller serial port signal transmitted by the third controller, performs logical processing on the target signal transmitted by the first controller and the third controller serial port signal, generates a first serial port signal, and transmits the first serial port signal to the third controller and the serial port connector respectively, wherein the second controller transmits the first serial port signal to the serial port connector through a path formed by the second interface of the second multiplexer and the third interface.

[0028] In one of the embodiments, if the target management board type is a second management board, the method further includes:

[0029] If the target management board type is the second management board, the first controller acquires the target signal transmitted by the target device;

[0030] Analyze the usage signal to determine the gating of the multiplexer interface corresponding to the second management board;

[0031] The selection of the multiplexer interface corresponding to the second management board includes: selecting the path formed by the first interface and the third interface of the second multiplexer for transmitting the serial port signal of the fourth controller; the first interface of the first multiplexer is used to transmit the serial port signal of the fourth controller, and the second interface of the first multiplexer is used to transmit the second serial port signal;

[0032] The serial port signal of the fourth controller is transmitted to the first controller through the path formed by the first interface and the third interface of the second multiplexer and the first interface of the first multiplexer;

[0033] The first controller performs logic processing on the target signal transmitted by the target device and the serial port signal of the fourth controller to generate a second serial port signal, and transmits the second serial port signal to the fourth controller and the serial port connector respectively through the second interface of the first multiplexer.

[0034] In order to solve the above technical problem, a third aspect provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: the processor implements the steps of the above first aspect method when executing the computer program.

[0035] In order to solve the above technical problems, in a fourth aspect, the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method of the above first aspect are implemented.

[0036] Different from the related art, the present application provides a server management system, the system includes: a management board and a main board, the management board includes a first management board and a second management board, and a target device, a first controller, a multiplexer and an expansion chip are arranged on the main board: a third controller and a second controller are arranged on the first management board, and the third controller is connected to the second controller; a fourth controller is arranged on the second management board; the output end of the target device is connected to the input end of the first controller; the input end of the expansion chip is connected to the output end of the third controller and the output end of the fourth controller, and the output end of the expansion chip is connected to the input end of the first controller and the input end of the multiplexer; the input end of the multiplexer is connected to the output end of the first controller, and the output end of the multiplexer is connected to the input end of the fourth controller and the input end of the second controller; the first controller receives a target signal transmitted by the target device, and the expansion chip is used to receive a first control signal transmitted by the third controller and / or the fourth controller, generates a second control signal based on the first control signal and transmits the second control signal to the first controller and the multiplexer, so that the first controller determines the type of the target management board, and the multiplexer controls the selection of the multiplexer interface, thereby realizing the transmission of the target signal to the target management board. In this way, different types of management boards can be reused on the main board, which can improve server reliability and save costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural block diagram of a server management system in the related art;

[0038] Figure 2A structural block diagram of a server management system in one embodiment;

[0039] Figure 3 A schematic diagram of a flow chart of a server management method in an embodiment;

[0040] Figure 4 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0042] See also Figure 1 In the related art, the access control of the server serial port is mainly to control the preset serial port physical interface in the baseboard management controller and the preset serial port controller to bind and unbind through the serial port switching instruction, so as to realize the baseboard management controller to switch the output of different UARTs (serial ports) corresponding to different UART information outputs.

[0043] However, the above solution relies on BMC for operation, which occupies a large amount of BMC resources. If the UART serial port output requirements of more devices are increased, this solution will be adopted. In the board design, the number of Pins of the interactive connectors between the BMC management board and the two main boards is insufficient to meet the requirements. This solution can be implemented faster when the number of UART serial ports is small. When other devices also need to output serial ports through BMC, the BMC resources will be occupied more and the processing time will be longer.

[0044] In view of the above technical problems, in one embodiment, Figure 2 As shown, the present application provides a server management system, which includes a main board and a management board, the management board includes a first management board and a second management board, and the main board is provided with a target device, a first controller (CPLD2), a multiplexer and an expansion chip;

[0045] The first management board is provided with a third controller (BMC1) and a second controller (CPLD1), and the second controller (CPLD1) is connected to the third controller (BMC1) for signal transmission.

[0046] The second management board is provided with a fourth controller (BMC2).

[0047] From the above description, it can be seen that the first management board and the second management board are management boards of different types. The first management board has an independent logic controller (the second controller (CPLD1)), while the second management board does not have an independent logic controller. The logic controller in this application is CPLD, and some signals on the second management board need to be separately connected to the logic controller (the first controller (CPLD2) CPLD2) on the main board to perform related logic operations.

[0048] The output of the target device is connected to the input of the first controller (CPLD2). Figure 2 The CPU, Other Device0, Other Device cen and other devices in the figure, Other Device0 represents the 0th other device, Other Device represents the nth other device, the output end of the target device is connected to the input end of the first controller (CPLD2), and is used to transmit the target signal to the first controller (CPLD2). The target signal here is the UART_CPU signal transmitted by the target device CPU, the UART_0 signal transmitted by the target device Other Device0, and the UART_n signal transmitted by the target device OtherDev i cen as shown in the figure.

[0049] The input end of the expansion chip (IO Expander) is connected to the output ends of the third controller (BMC1) and the fourth controller (BMC2), and the output end of the expansion chip (IO Expander) is connected to the input end of the first controller (CPLD2) and the input end of the multiplexer; the input end of the multiplexer is connected to the output end of the first controller (CPLD2), and the output end of the multiplexer is connected to the input end of the fourth controller (BMC2) and the input end of the second controller (CPLD1).

[0050] The expansion chip (IO Expander) can receive the first control signal transmitted by the third controller (BMC1) and / or the fourth controller (BMC2), and generate a second control signal according to the first control signal, and transmit the second control signal to the first controller (CPLD2) and the multiplexer, so that the first controller (CPLD2) determines the type of the target management board according to the high and low level states of the second control signal, that is, determines whether to transmit the target signal of the target device to the first management board or the second management board. The multiplexer determines the selection of the multiplexer interface.

[0051] The first controller (CPLD2) and the second controller (CPLD1) in the present application are logic controllers (CPLD), and the third controller (BMC1) and the fourth controller (BMC2) are baseboard management controllers (BMC).

[0052] In the present application, the first controller (CPLD2) receives a target signal transmitted by a target device, and the expansion chip (IOExpander) is used to receive a first control signal transmitted by a third controller (BMC1) and / or a fourth controller (BMC2), and generates a second control signal based on the first control signal and transmits the second control signal to the first controller (CPLD2) and the multiplexer, so that the first controller (CPLD2) determines the type of the target management board and the multiplexer controls the selection of the multiplexer interface, thereby realizing the transmission of the target signal to the target management board. In addition, the present application does not rely on a baseboard management controller for operation, and occupies less resources of the baseboard management controller.

[0053] In one embodiment, the multiplexer includes a first multiplexer (MUX1) (MUX1), the first multiplexer (MUX1) is located on the first controller (CPLD2), the input end of the first multiplexer (MUX1) is connected to the output end of the first controller (CPLD2) and the output end of the expansion chip (IO Expander), and the output end of the first multiplexer (MUX1) is connected to the input end of the fourth controller (BMC2) and the input end of the second controller (CPLD1). The first multiplexer (MUX1) also includes a first interface (PORT1) and a second interface (PORT2). The first interface of the first multiplexer (MUX1) is used to receive the serial port signal (UART_BMC2) of the fourth controller (BMC2) transmitted by the second management board. The second interface of the first multiplexer (MUX1) is used to transmit the target signal (UART_MB) to the third controller (BMC1), or to transmit the second serial port signal (UART_SOL2) to the fourth controller (BMC2). The first multiplexer (MUX1) in this application is a multiplexer simulated inside the second controller (CPLD1), not a physical hardware. By setting the first multiplexer (MUX1), the target signal transmitted by the target device is transmitted to the target management board through the interface switching of the first multiplexer (MUX1).

[0054] The server management system also includes a serial port connector (UART Conn), and the multiplexer also includes a second multiplexer (MUX2). The second multiplexer (MUX2) is located on the main board close to the management board. The serial port connector is located on the main board. The input end of the second multiplexer is connected to the output end of the expansion chip (IO Expander), the output end of the second controller (CPLD1), and the output end of the fourth controller (BMC2). The output end of the second multiplexer (MUX2) is connected to the input end of the first controller (CPLD2). The input end of the serial port connector is connected to the output end of the second multiplexer (MUX2) and the output end of the first controller (CPLD2). The output end of the serial port connector is connected to the connection serial port. The second multiplexer (MUX2) includes a first interface (B0), a second interface (B1), and a third interface (A), wherein a path formed by the first interface of the second multiplexer (MUX2) and the third interface of the second multiplexer (MUX2) is used for the second controller (CPLD1) to transmit a first serial port signal (UART_SOL1) to the serial port connector, and for the fourth controller (BMC2) to transmit a fourth controller (BMC2) serial port signal (UART_BMC2) to the first controller (CPLD2).

[0055] The server management system provided in the present application also includes a connection line of a first management board and a connection line of a second management board. The input end of the connection line of the first management board is connected to the third controller (BMC1), the output end of the connection line of the first management board is connected to the input end of the expansion chip (IO Expander) and the input end of the second controller (CPLD1), the input end of the connection line of the second management board is connected to the output end of the fourth controller (BMC2), and the output end of the connection line of the second management board is connected to the input end of the expansion chip (IO Expander).

[0056] Specifically, the connection lines of the first management board are shown in the figure as BMC_I 2C0 and BMC_I 2C1, and the connection lines of the second management board are shown in the figure as BMC_I 2C2, wherein the connection lines of the first management board are used to realize the interaction between the first controller (CPLD2) and the third controller (BMC1), the third controller (BMC1) and the second controller (CPLD1), and the third controller (BMC1) and the expansion chip (IO Expander). The connection lines of the second management board are used to realize the interaction between the first controller (CPLD2) and the fourth controller (BMC2), and the fourth controller (BMC2) and the expansion chip (IO Expander).

[0057] In the present application, the high and low levels of the interface detection signal (BMC_IFDET) output by the connection line expansion chip (IO Expander) correspond to two different types of management boards, and inform the first controller (CPLD2) to execute the UART switching logic corresponding to which management board; at the same time, the baseboard management controller (the third controller (BMC1), the fourth controller (BMC2)) controls the high and low levels of the use signal (MUX_SEL) output by the connection line expansion chip (IO Expander) to select the channel of the second multiplexer (MUX2), the channel of the first management board corresponding to the second multiplexer (MUX2) is A-B1, and the channel of the second management board corresponding to the second multiplexer (MUX2) is A-B0, thereby realizing the multiplexing of the same line, which can save costs.

[0058] In one embodiment, the first control signal includes an interface detection signal (BMC_I FDET) and a usage signal (MUX_SEL), wherein the interface detection signal is used to determine the type of the target management board, and the usage signal is used to control the selection of the interface of the second multiplexer (MUX2).

[0059] The first controller (CPLD2) in this application interacts with the baseboard management controller (the third controller (BMC1), the fourth controller (BMC2)) on the management board. The baseboard management controller will inform the first controller (CPLD2) how to perform the UART logic execution, that is, control the mainboard UART serial port connector, where the source signal of the BMC remote printing serial port comes from; the second controller (CPLD1) on the first management board interacts with the third controller (BMC1), which only exists in the first management board, and assists in the switching of UART as an auxiliary role, and completes the output function of different UART serial port information together with the first controller (CPLD2) on the main board. Regardless of the type of management board, the UART interaction between the mainboard and the management board is a 2-way UART signal, which can realize the reuse of different types of management boards corresponding to the same mainboard. In this application, it does not rely on the baseboard management controller chip for routing switching, does not occupy more resources of the baseboard management controller, and can realize the remote output of different serial port information by the baseboard management controller; by automatically identifying different management boards, different logical operations are performed, the same mainboard design is realized, and different management board serial port output schemes are compatible.

[0060] In a feasible implementation, an indicator light may be set on the mainboard and the first management board, and the indicator light may include a red indicator light indicating an alarm state and a green indicator light indicating a normal state, and the indicator light is off by default. When the first controller (CPLD2) on the mainboard receives the signal transmitted by the target device and the serial port signal of the fourth controller (BMC2) transmitted by the fourth controller (BMC2) to the first controller (CPLD2), the indicator light on the mainboard displays green, indicating that the first controller (CPLD2) receives the target signal and the serial port signal of the fourth controller (BMC2), and can continue to perform logical processing on the target signal and the fourth controller (BMC2). If the indicator light on the mainboard is in the default state within a certain time range, the indicator light on the mainboard displays red. When the second controller (CPLD1) receives the signal transmitted by the target device and the serial port signal of the third controller (BMC1) transmitted by the third controller (BMC1) to the second controller (CPLD1), the indicator light on the first management board displays green, indicating that the second controller (CPLD1) receives the target signal and the serial port signal of the third controller (BMC1), and can continue to perform logical processing on the target signal and the third controller (BMC1). If the indicator light on the mainboard is in the default state within a certain time range, the indicator light on the mainboard displays red. The certain time range here can be determined by referring to the time length of the historical first controller (CPLD2) receiving the target signal and the fourth controller (BMC2) serial port signal, the historical second controller (CPLD1) receiving the target signal and the third controller (BMC1) serial port signal, so that the reliability of server management can be further improved.

[0061] In one embodiment, Figure 3 As shown, a server management method is provided, which is applied to Figure 1 The server management system in the example is used for explanation, including the following steps:

[0062] Step 101, in response to the expansion chip (IO Expander) receiving a first control signal transmitted by the third controller (BMC1) and / or the fourth controller (BMC2), the expansion chip (IO Expander) generates a second control signal and transmits the second control signal to the first controller (CPLD2) and the multiplexer.

[0063] Step 102, in response to the first controller (CPLD2), the multiplexer obtains the second control signal, analyzes the second control signal, determines the type of the target management board and the selection of the multiplexer interface corresponding to the target management board.

[0064] Step 103: according to the selection of the multiplexer interface corresponding to the target management board, the target signal is transmitted to the target management board for processing.

[0065] In the present application, after the server is powered on, the first controller (CPLD2) is powered on, and the management board is powered on, the third controller (BMC1) and / or the fourth controller (BMC2) sends a first control signal to the expansion chip (IO Expander), and after the expansion chip (IO Expander) receives the first control signal, it generates an interface detection signal (BMC_I FDET) and a use signal (MUX_SEL). Specifically, the connection line through the first management board is BMC_I 2C1, and the connection line of the second management board is BMC_I2C2 to control the interface detection signal and the use signal of the expansion chip (IO Expander). The expansion chip (IOExpander) sends the interface detection signal (BMC_I FDET) to the first controller (CPLD2). After receiving the interface detection signal (BMC_I FDET), the first controller (CPLD2) will parse the interface detection signal (BMC_I FDET) to obtain the level state of the interface detection signal. The first controller (CPLD2) determines the type of the target management board according to the level state of the interface detection signal. The types of the target management board include the first management board and the second management board. Different UART line logic processing is performed according to the type of the target management board. At the same time, the third controller (BMC1) and / or the fourth controller (BMC2) will control the interface (first interface PORT1, second interface PORT2) on the first multiplexer (MUX1) and the A-B1 channel of the second multiplexer (MUX2) and the A-B0 channel of the second multiplexer (MUX2) on the second multiplexer (MUX2) through the use signal (MUX_SEL) of the expansion chip (IO Expander).

[0066] In one embodiment, if the target management board type is the first management board, the first controller (CPLD2) obtains the target signal transmitted by the target device; analyzes the use signal to determine the gating of the multiplexer interface corresponding to the first management board; the gating of the multiplexer interface corresponding to the first management board includes: setting the first interface of the first multiplexer (MUX1) to a prohibited use state, gating the path formed by the second interface and the third interface of the second multiplexer (MUX2); the first controller (CPLD2) transmits the target signal to the second controller (CPLD1) via the second interface of the first multiplexer (MUX1) The second controller (CPLD1) receives the target signal transmitted by the first controller (CPLD2) and the serial port signal of the third controller (BMC1) transmitted by the third controller (BMC1), performs logic processing on the target signal transmitted by the first controller (CPLD2) and the serial port signal of the third controller (BMC1), generates a first serial port signal, and transmits the first serial port signal to the third controller (BMC1) and the serial port connector respectively, wherein the second controller (CPLD1) transmits the first serial port signal to the serial port connector through a path formed by the second interface of the second multiplexer (MUX2) and the third interface.

[0067] Specifically, the process of transmitting the target signal transmitted by the target device to the first management board is as follows: the first controller (CPLD2) receives the target signal transmitted by the target device, and then sends the target signal transmitted by the target device (UART_CPU, UART_0, UART_n shown in the figure) to the first controller (CPLD2). At this time, the first interface of the first multiplexer (MUX1) is in a prohibited state, and the path formed by the second interface and the third interface of the second multiplexer (MUX2) is selected. The target signal transmitted by the target device is transmitted to the first controller (CPLD2) using the second interface of the first controller (CPLD2). The second interface (PORT2) of the first multiplexer (MUX1) is the total output interface after the first controller (CPLD2) completes the logic processing and switching of the analog MUX (the third controller (BMC1) can inform the first controller (CPLD2) how to execute the switching instruction: UART MUX CTRL through the connection line (BMC_I 2C0) signal. The signal transmitted by the target device can be switched to the second interface of the first multiplexer (MUX1) in a time-sharing manner, so as to output the required serial port information, corresponding to the signal UART_MB. It can be understood that although Figure 2 The signal when the target signal is transmitted from the first controller (CPLD2) to the corresponding management board is named UART_MB, but it is actually the target signal transmitted by the target device.

[0068] After the second controller (CPLD1) receives the signal transmitted by the target device (UART_MB shown in the figure) and the signal transmitted by the third controller (BMC1) to the second controller (CPLD1) (UART_BMC1 shown in the figure), the second controller (CPLD1) generates a first serial port signal (UART_SOL1 shown in the figure) after performing logical processing on the signal transmitted by the target device (UART_MB shown in the figure) and the signal transmitted by the third controller (BMC1) to the second controller (CPLD1) (UART_BMC1 shown in the figure), and outputs the first serial port signal to the third controller (BMC1) in the first management board for remote printing of logs of different serial ports. At the same time, the first serial port signal is also connected to the second multiplexer (MUX2), and is given to the serial port connector (UART Conn shown in the figure) after passing through the A-B1 path selected by the second multiplexer (MUX2), so as to facilitate local operation using the serial port line.

[0069] In one embodiment, if the target management board type is the second management board, the first controller (CPLD2) obtains the target signal transmitted by the target device; the use signal is parsed to determine the gating of the multiplexer interface corresponding to the second management board; the gating of the multiplexer interface corresponding to the second management board includes: gating the path formed by the first interface and the third interface of the second multiplexer (MUX2) for transmitting the serial port signal of the fourth controller (BMC2); the first interface of the first multiplexer (MUX1) is used to transmit the serial port signal of the fourth controller (BMC2), and the first multiplexer (MUX1) The second interface is used to transmit a second serial port signal; the serial port signal of the fourth controller (BMC2) is transmitted to the first controller (CPLD2) through the path formed by the first interface of the second multiplexer (MUX2) and the third interface and the first interface of the first multiplexer (MUX1); the first controller (CPLD2) performs logical processing on the target signal transmitted by the target device and the serial port signal of the fourth controller (BMC2), generates a second serial port signal, and transmits the second serial port signal to the fourth controller (BMC2) and the serial port connector respectively through the second interface of the first multiplexer (MUX1).

[0070] The process of transmitting the target signal transmitted by the target device to the first management board is specifically as follows: the first controller (CPLD2) receives the target signal transmitted by the target device, and then sends the target signal transmitted by the target device (UART_CPU, UART_0, UART_n in the figure) to the first controller (CPLD2). The first controller (CPLD2) performs logical processing between the target signal transmitted by the target device and the fourth controller (BMC2) serial port signal (UART_BMC2 in the figure) transmitted by the fourth controller (BMC2) to the first controller (CPLD2), generates a second serial port signal (UART_SOL2 in the figure), and the first controller (CPLD2) transmits the second serial port signal to the fourth controller (BMC2) and the serial port connector.

[0071] Specifically, the fourth controller (BMC2) controls the second multiplexer (MUX2) path A-B0 to be selected by controlling the use signal (MUX_SEL) of the expansion chip (IO Expander). At this time, the fourth controller (BMC2) controls the first interface (PORT1) of the first multiplexer (MUX1) to receive the fourth controller (BMC2) serial port signal (UART_BMC2 shown in the figure) transmitted by the fourth controller (BMC2), and transmits the fourth controller (BMC2) serial port signal (UART_BMC2 shown in the figure) to the first controller (CPLD2) through the second multiplexer (MUX2) path A-B0. The second interface of the first multiplexer (MUX1) is the total output interface after the MUX logic processing switch is completed inside the first controller (CPLD2). The fourth controller (BMC2) can use the I2C signal to inform the mainboard CPLD how to execute the switching instruction: UART MUX CTRL), the signals (UART_CPU, UART_BMC, UART_0-n) transmitted by the target device can be switched to the second interface of the first multiplexer (MUX1) in a time-sharing manner, so as to output the required serial port information and connect it to the fourth controller (BMC2), so that the fourth controller (BMC2) can print the serial port information remotely, and the corresponding signal is the second serial port signal (UART_SOL). At the same time, this signal will also be connected to the UART serial port connector (UART Conn) of the mainboard, so as to facilitate local operation using a serial port line.

[0072] The server management system in the present invention is compatible with UART serial port outputs of different types of management boards, does not occupy the resources of the baseboard management controller, and the main board can share the design to reduce the use area of ​​the printed circuit board. Even if the UART serial port output demand of more devices is increased, there is no need to increase the UART transmission signal between the management board and the main board, which can save costs.

[0073] In this application, the number of UART signal lines between the main board and the management board is fixed. Regardless of the type of management board and the number of serial ports of the devices that need to be output, there are two UART signals. If the UART serial port output requirements of more devices are increased, this solution is adopted. In the board design, the main board and the management board also only need two UART signals. The main board can maximize compatibility with different types of management board UART outputs, and the main board PCB uses less area, maximizing the reuse rate of the main board.

[0074] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0075] For the specific definition of the server management system, please refer to the definition of the server management method above, which will not be repeated here. Each module in the above-mentioned server management system can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0076] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 4As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a server management method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0077] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0078] In one embodiment, the present application also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the server management methods provided by the above methods.

[0079] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0080] Step 101: in response to the expansion chip receiving a first control signal transmitted by the third controller and / or the fourth controller, the expansion chip generates a second control signal and transmits the second control signal to the first controller and the multiplexer.

[0081] Step 102: In response to the first controller and the multiplexer acquiring the second control signal, the second control signal is parsed to determine the type of the target management board and the selection of the multiplexer interface corresponding to the target management board.

[0082] Step 103: according to the selection of the multiplexer interface corresponding to the target management board, the target signal is transmitted to the target management board for processing.

[0083] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0084] The method also includes:

[0085] In response to the first controller acquiring a second control signal, the second control signal includes an interface detection signal and a use signal;

[0086] Analyze the interface detection signal to obtain the level status of the interface detection signal;

[0087] The first controller determines the type of the target management board according to the level state of the interface detection signal, and the type of the target management board includes a first management board and a second management board;

[0088] If the target management board type is the first management board, the first controller acquires the target signal transmitted by the target device;

[0089] Analyze the usage signal to determine the gating of the multiplexer interface corresponding to the first management board;

[0090] The gating of the multiplexer interface corresponding to the first management board includes: setting the first interface of the first multiplexer to a disabled state, gating a path formed by the second interface and the third interface of the second multiplexer;

[0091] The first controller transmits the target signal to the second controller via the second interface of the first multiplexer;

[0092] The second controller receives the target signal transmitted by the first controller and the third controller serial port signal transmitted by the third controller, performs logical processing on the target signal transmitted by the first controller and the third controller serial port signal, generates a first serial port signal, and transmits the first serial port signal to the third controller and the serial port connector respectively, wherein the second controller transmits the first serial port signal to the serial port connector through a path formed by the second interface of the second multiplexer and the third interface.

[0093] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0094] If the target management board type is the second management board, the method further includes:

[0095] If the target management board type is the second management board, the first controller acquires the target signal transmitted by the target device;

[0096] Analyze the usage signal to determine the gating of the multiplexer interface corresponding to the second management board;

[0097] The selection of the multiplexer interface corresponding to the second management board includes: selecting the path formed by the first interface and the third interface of the second multiplexer for transmitting the serial port signal of the fourth controller; the first interface of the first multiplexer is used to transmit the serial port signal of the fourth controller, and the second interface of the first multiplexer is used to transmit the second serial port signal;

[0098] The serial port signal of the fourth controller is transmitted to the first controller through the path formed by the first interface and the third interface of the second multiplexer and the first interface of the first multiplexer;

[0099] The first controller performs logic processing on the target signal transmitted by the target device and the serial port signal of the fourth controller to generate a second serial port signal, and transmits the second serial port signal to the fourth controller and the serial port connector respectively through the second interface of the first multiplexer.

[0100] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0101] Step 101: in response to the expansion chip receiving a first control signal transmitted by the third controller and / or the fourth controller, the expansion chip generates a second control signal and transmits the second control signal to the first controller and the multiplexer.

[0102] Step 102: In response to the first controller and the multiplexer acquiring the second control signal, the second control signal is parsed to determine the type of the target management board and the selection of the multiplexer interface corresponding to the target management board.

[0103] Step 103: according to the selection of the multiplexer interface corresponding to the target management board, the target signal is transmitted to the target management board for processing.

[0104] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0105] The method also includes:

[0106] In response to the first controller acquiring a second control signal, the second control signal includes an interface detection signal and a use signal;

[0107] Analyze the interface detection signal to obtain the level status of the interface detection signal;

[0108] The first controller determines the type of the target management board according to the level state of the interface detection signal, and the type of the target management board includes a first management board and a second management board;

[0109] If the target management board type is the first management board, the first controller acquires the target signal transmitted by the target device;

[0110] Analyze the usage signal to determine the gating of the multiplexer interface corresponding to the first management board;

[0111] The gating of the multiplexer interface corresponding to the first management board includes: setting the first interface of the first multiplexer to a disabled state, gating a path formed by the second interface and the third interface of the second multiplexer;

[0112] The first controller transmits the target signal to the second controller via the second interface of the first multiplexer;

[0113] The second controller receives the target signal transmitted by the first controller and the third controller serial port signal transmitted by the third controller, performs logical processing on the target signal transmitted by the first controller and the third controller serial port signal, generates a first serial port signal, and transmits the first serial port signal to the third controller and the serial port connector respectively, wherein the second controller transmits the first serial port signal to the serial port connector through a path formed by the second interface of the second multiplexer and the third interface.

[0114] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0115] If the target management board type is the second management board, the method further includes:

[0116] If the target management board type is the second management board, the first controller acquires the target signal transmitted by the target device;

[0117] Analyze the usage signal to determine the gating of the multiplexer interface corresponding to the second management board;

[0118] The selection of the multiplexer interface corresponding to the second management board includes: selecting the path formed by the first interface and the third interface of the second multiplexer for transmitting the serial port signal of the fourth controller; the first interface of the first multiplexer is used to transmit the serial port signal of the fourth controller, and the second interface of the first multiplexer is used to transmit the second serial port signal;

[0119] The serial port signal of the fourth controller is transmitted to the first controller through the path formed by the first interface and the third interface of the second multiplexer and the first interface of the first multiplexer;

[0120] The first controller performs logic processing on the target signal transmitted by the target device and the serial port signal of the fourth controller to generate a second serial port signal, and transmits the second serial port signal to the fourth controller and the serial port connector respectively through the second interface of the first multiplexer.

[0121] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing related hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0122] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A server management system, characterized in that: It includes a management board and a main board, wherein the management board includes a first management board and a second management board, and the main board is provided with a target device, a first controller, a multiplexer and an expansion chip: A third controller and a second controller are arranged on the first management board, and the third controller is connected to the second controller; a fourth controller is arranged on the second management board; The output terminal of the target device is connected to the input terminal of the first controller; The input end of the expansion chip is connected to the output end of the third controller and the output end of the fourth controller, and the output end of the expansion chip is connected to the input end of the first controller and the input end of the multiplexer; The input end of the multiplexer is connected to the output end of the first controller, and the output end of the multiplexer is connected to the input end of the fourth controller and the input end of the second controller; The first controller receives the target signal transmitted by the target device, and the expansion chip is used to receive the first control signal transmitted by the third controller and / or the fourth controller, generate a second control signal based on the first control signal and transmit the second control signal to the first controller and the multiplexer, so that the first controller determines the type of the target management board and the multiplexer controls the selection of the multiplexer interface, thereby realizing the transmission of the target signal to the target management board.

2. The server management system according to claim 1, characterized in that: The multiplexer includes a first multiplexer, which is located on the first controller, the input end of the first multiplexer is connected to the output end of the first controller and the output end of the expansion chip, and the output end of the first multiplexer is connected to the input end of the fourth controller and the input end of the second controller.

3. The server management system according to claim 1, characterized in that: The server management system also includes a connecting line of a first management board and a connecting line of a second management board, the input end of the connecting line of the first management board is connected to the third controller, the output end of the connecting line of the first management board is connected to the input end of the extension chip and the input end of the second controller, the input end of the connecting line of the second management board is connected to the output end of the fourth controller, and the output end of the connecting line of the second management board is connected to the input end of the extension chip.

4. The server management system according to claim 2, characterized in that: The server management system also includes a serial port connector, and the multiplexer also includes a second multiplexer. The second multiplexer is located on the main board close to the management board. The serial port connector is located on the main board. The input end of the second multiplexer is connected to the output end of the expansion chip, the output end of the second controller, and the output end of the fourth controller. The output end of the second multiplexer is connected to the input end of the first controller. The input end of the serial port connector is connected to the output end of the second multiplexer and the output end of the first controller. The output end of the serial port connector is connected to the connecting serial port.

5. The server management system according to claim 1, characterized in that: The first control signal includes an interface detection signal and a use signal, wherein the interface detection signal is used to determine the type of the target management board, and the use signal is used to control the selection of the interface of the second multiplexer.

6. A server management method, applied to the server management system according to any one of claims 1 to 5, characterized in that: The server management method comprises: In response to the expansion chip receiving the first control signal transmitted by the third controller and / or the fourth controller, the expansion chip generates a second control signal and transmits the second control signal to the first controller and the multiplexer; In response to the first controller and the multiplexer acquiring the second control signal, the second control signal is parsed to determine the type of the target management board and the gating of the multiplexer interface corresponding to the target management board; According to the selection of the multiplexer interface corresponding to the target management board, the target signal is transmitted to the target management board for processing.

7. The server management method according to claim 6, characterized in that: The method further comprises: In response to the first controller acquiring a second control signal, the second control signal includes an interface detection signal and a use signal; Analyze the interface detection signal to obtain the level state of the interface detection signal; The first controller determines the type of the target management board according to the level state of the interface detection signal, and the type of the target management board includes a first management board and a second management board; If the target management board type is a first management board, the first controller acquires a target signal transmitted by a target device; Analyze the usage signal to determine the gating of the multiplexer interface corresponding to the first management board; The gating of the multiplexer interface corresponding to the first management board includes: setting the first interface of the first multiplexer to a disabled state, gating a path formed by the second interface and the third interface of the second multiplexer; The first controller transmits the target signal to the second controller via the second interface of the first multiplexer; The second controller receives the target signal transmitted by the first controller and the third controller serial port signal transmitted by the third controller, performs logical processing on the target signal transmitted by the first controller and the third controller serial port signal, generates a first serial port signal, and transmits the first serial port signal to the third controller and the serial port connector respectively, wherein the second controller transmits the first serial port signal to the serial port connector through a path formed by the second interface of the second multiplexer and the third interface.

8. The server management method according to claim 7, characterized in that: If the target management board type is a second management board, the method further includes: If the target management board type is a second management board, the first controller acquires a target signal transmitted by the target device; Parsing the usage signal to determine the gating of the multiplexer interface corresponding to the second management board; The selection of the multiplexer interface corresponding to the second management board includes: selecting the path formed by the first interface and the third interface of the second multiplexer for transmitting the fourth controller serial port signal; the first interface of the first multiplexer is used to transmit the fourth controller serial port signal, and the second interface of the first multiplexer is used to transmit the second serial port signal; The serial port signal of the fourth controller is transmitted to the first controller through the path formed by the first interface and the third interface of the second multiplexer and the first interface of the first multiplexer; The first controller performs logic processing on the target signal transmitted by the target device and the serial port signal of the fourth controller to generate a second serial port signal, and transmits the second serial port signal to the fourth controller and the serial port connector respectively through the second interface of the first multiplexer.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 6 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 6 to 8 are implemented.

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