An adaptive spmv method based on a new generation of domestic many-core processor

Abstract

The application discloses a kind of self-adapting SpMV methods based on new generation domestic many-core processor, comprising the following steps: setting start parameter;SpMV parameter is obtained;Set and load input vector x in main memory to shared LDM vector sx;Private LDM local space is set;SpMV row block load is divided;If there is remaining row block to be processed, take row block from core, otherwise exit;Load row block row offset vector dptr and initialize row block output vector dy;SpMV self-adapting decision;Batch calculate remaining part in row block, if row block enable shared LDM flag is true, then using batch SpMV method based on shared LDM processing, otherwise using batch SpMV method based on hardware DCache processing;Return to continue to take row block processing until no remaining row block to be processed end.The application provides a kind of self-adapting SpMV methods based on new generation domestic many-core processor, realizes fine-grained self-adapting, gives full play to SW26010P architecture characteristics optimization memory access, to finally improve SpMV computing performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of high-performance computing, and particularly relates to an adaptive SpMV method based on a new generation of domestic many-core processors. BACKGROUND

[0002] Sparse Matrix Vector Multiplication (SpMV) is a classic operator in the field of high-performance computing, which not only plays an important role in scientific and engineering applications, but also has a wide range of applications in graphics processing, network analysis, machine learning and other fields. At present, with the increasing demand for higher precision and larger scale problem solving ability of scientific research and technological development, it is particularly important to develop a faster and more efficient SpMV method. Especially for processors with unique architecture characteristics, how to fully utilize the specific hardware characteristics to further improve the computing efficiency is an important topic in current SpMV research.

[0003] The matrix processed by Sparse Matrix Vector Multiplication (SpMV) contains a large number of zero elements, which means that if the dense matrix processing method is directly used in the actual operation process, a large number of unnecessary zero element multiplication operations will be performed, which will greatly waste computing resources and time.

[0004] To solve this problem, SpMV often uses a special storage format to compress the storage of sparse matrices in design. Compressed Sparse Row (CSR) is a widely used basic sparse matrix compression format, which is particularly suitable for sparse matrix operations processed by rows. This format reduces memory usage by compactly storing non-zero elements and their related information. CSR mainly consists of three vectors: 1. val[nnz_len]: non-zero element vector; 2. ind[nnz_len]: non-zero element column index vector; 3. ptr[rows+1]: row offset vector. Through the above three vectors, CSR format can effectively encode the complete information of a sparse matrix. When performing SpMV and other operations that require frequent access to non-zero elements of sparse matrices, CSR format can significantly reduce memory usage and speed up the calculation process, which also facilitates efficient cache utilization and further improves algorithm performance.

[0005] However, although the CSR-based SpMV avoids redundant multiplication operations on zero elements, it also introduces new challenges. CSR compresses non-zero elements while discretizing the memory access of the input vector x, which will greatly affect the overall performance of SpMV. In CSR, unlike the continuous access pattern of non-zero elements, the access of the input vector x is dependent on the column index vector ind corresponding to the non-zero elements.

[0006] With the gradual failure of Moore's law, modern high-performance processor architecture design gradually develops towards heterogeneous many-core to cope with the physical limit of single-core performance improvement. This transition not only greatly improves the single-chip floating-point computing power, but also makes the storage access bottleneck problem more prominent. The new generation of Shenwei supercomputer adopts the heterogeneous many-core processor SW26010P, which is independently developed in China. The floating-point operation capability of this processor on a single chip reaches 14TFLOPS, while providing a memory access bandwidth of up to 300GB / s. Compared with the previous generation processor SW26010, SW26010P has been improved in many aspects. Although SW26010P has made significant progress in computing power, its memory access speed still has certain limitations compared with the growing demand for data processing. Especially when executing memory-intensive operators such as SpMV, its memory access delay and bandwidth limitation become the key factors restricting overall performance. In order to solve this problem, the architecture optimization of SW26010P on the LDM provides new possibilities for SpMV algorithm innovation and creates favorable conditions for improving SpMV performance.

[0007] Currently, most of the research on sparse matrix vector multiplication (SpMV) is focused on traditional CPUs and GPUs. These studies explore various optimization strategies, including efficient sparse matrix storage formats, data prefetching techniques, and parallel computing methods. In recent years, with the development of domestic supercomputers, some research has begun to focus on SpMV algorithm design based on the Shenwei SW26010 processor. However, due to the upgrade of the new generation SW26010P architecture in many aspects, such as the increase in the number of core groups, the expansion of the local data storage (LDM) capacity, and the support for more flexible data storage configuration, it is necessary to develop SpMV algorithms that can fully utilize these new features.

[0008] Currently, existing SpMV research for the SW26010P platform mainly focuses on two directions: one is the optimization of compressed formats, which improves the CSR and other sparse matrix representation methods to reduce memory occupancy and speed up data access; the other is the application of automatic tuning mechanisms, aiming to dynamically adjust algorithm parameters or execution paths according to actual runtime conditions to achieve optimal performance. Although these efforts have improved the performance of SpMV on SW26010P to some extent, considering the uniqueness of the architecture, there is still room for further optimization. In particular, how to effectively use shared LDM to improve irregular access to vector x, and how to better combine private LDM and hardware cache advantages to achieve higher data locality and computing efficiency, are key problems that need to be solved.

[0009] SpMV is a typical memory-intensive application, and its key performance bottleneck lies in the discrete access pattern to the vector x. Unlike dense matrix operations, the access to the input vector x in SpMV is usually based on the non-zero element column index ind in the sparse matrix, which leads to an irregular and random data access pattern. Traditionally, one of the methods to solve this memory problem is to use hardware Cache to improve data access efficiency, i.e. by saving recently or frequently accessed data in the cache to reduce the number of direct accesses to external memory. However, the effectiveness of this method is highly dependent on the distribution characteristics of the non-zero elements in the sparse matrix. If the distribution of non-zero elements in the matrix has good locality, i.e. they are relatively concentrated in adjacent positions, the hardware Cache can work effectively; otherwise, if the non-zero elements are very scattered, it will lead to a higher miss rate and frequent Cache Line eviction.

[0010] Take the SW26010P processor as an example, which supports multiple sizes of hardware Cache settings, including 0KB, 32KB and 128KB three configuration options, and the size of each Cache Line is 256 bytes, which can accommodate 32 double-precision floating-point numbers. When the distribution of non-zero elements in each row of the sparse matrix has good locality in the column, it means that the input vector x element positions corresponding to these non-zero elements are relatively close, and the hardware Cache can work effectively. Because a Cache Line load can meet the access requirements of multiple consecutive x elements at the same time, a high Cache hit rate can be achieved. Such a layout is beneficial to reduce the overhead caused by Cache miss and improve the overall computing efficiency. For example, if a Cache Line contains all the vector x elements that need to be accessed in a sparse matrix row, all the multiply-add operations of this row can be efficiently completed without accessing the main memory again.

[0011] However, if the non-zero element distribution of the sparse matrix presents poor locality, efficient data access cannot be guaranteed even if a larger Cache is used. In this case, the hardware Cache may experience high frequency of miss events, which means that new data needs to be frequently reloaded from the main memory to the Cache. In addition, due to the limited capacity of the Cache, the newly loaded data is likely to replace the previously useful but not yet used data. Frequent Cache Line eviction not only increases additional data transmission delay, but also may cause the Cache to fail to function fully, seriously affecting the overall performance of the SpMV. Therefore, when designing the SpMV algorithm for the SW26010P architecture, it is necessary to consider how to improve the access mode of the input vector x to make it more suitable for the specific LDM configuration, and how to evaluate the locality of the sparse matrix row block, so as to adopt the adaptive SpMV strategy according to the memory access locality characteristics of the row block. SUMMARY

[0012] In view of the above defects of the prior art, the technical problem to be solved by the present application is the problems of the prior adaptive SpMV method for the SW26010P architecture, such as coarse granularity, insufficient exploitation of architecture characteristics, poor memory access locality, etc. The present application provides an adaptive SpMV method based on a new generation of domestic many-core processor, which evaluates the locality of the sparse matrix row block of the SpMV by collecting data through the PMU, and uses the SpMV method of the shared LDM cache input vector x to process the row block with poor memory access locality, realizes fine-grained adaptation, fully exploits the SW26010P architecture characteristics, optimizes memory access, and finally improves the SpMV computing performance.

[0013] To achieve the above-mentioned purpose, the present application provides an adaptive SpMV method based on a new generation of domestic many-core processor, comprising the following steps:

[0014] Step S101, setting the start-up parameters;

[0015] Step S102, obtaining the SpMV parameters;

[0016] Step S103, setting and loading the input vector x in the main memory to the vector sx in the shared LDM;

[0017] Step S104, setting the private LDM local storage space;

[0018] Step S105, dividing the SpMV row block load;

[0019] Step S106, if there are remaining row blocks to be processed, take the row block from the core, otherwise exit;

[0020] Step S107, load the row block row offset vector dptr and initialize the row block output vector dy;

[0021] Step S108, SpMV adaptive decision-making;

[0022] Step S109, batch calculation of the remaining part in the row block, if the shared LDM flag of the row block is true, the shared LDM-based batch SpMV method is used for processing, otherwise the hardware DCache-based batch SpMV method is used for processing;

[0023] Step S110, return to step S106 for continuous processing until there is no remaining row block to be processed.

[0024] Further, step S101, setting the start-up parameters, specifically including:

[0025] Setting the load division parameters, including the row block load row number;

[0026] Setting the adaptive SpMV decision-making parameters, including the row block load sampling rate, the single-batch DCache miss rate tolerance threshold, and the row block shared LDM enable threshold;

[0027] Setting the shared LDM configuration parameters, including the shared LDM default start-up size.

[0028] Further, step S102, obtaining the SpMV parameters, specifically including:

[0029] Obtaining the matrix parameters, the CSRMatrx type, including: the row offset vector ptr main memory address, the non-zero element vector val main memory address, the non-zero element column index vector ind main memory address, the matrix row number n, and the matrix non-zero element number nnz;

[0030] Inputting the vector x main memory address;

[0031] Outputting the vector y main memory address.

[0032] Further, step S103, setting and loading the input vector x in the main memory to the vector sx in the shared LDM, including two steps of space size mode setting and input vector x loading, specifically including:

[0033] Setting the shared mode and size of the shared LDM according to the size of the input vector x, i.e., the matrix column number;

[0034] Loading the input vector x to the shared LDM vector sx.

[0035] Further, loading the input vector x to the shared LDM vector sx, using a cluster-based high-affinity shared LDM loading method, specifically including:

[0036] Step S501: calculating the core cluster number;

[0037] Step S502: calculating slave local number from slave cluster;

[0038] Step S503: calculating slave global number related to slave cluster according to slave cluster number and slave local number from slave cluster;

[0039] Step S504: dividing x load according to slave global number related to slave cluster;

[0040] Step S505: aligning input vector x load size with 8*loop unrolling times;

[0041] Step S506: loading input vector x in main memory to LDM private space LMEM by DMA;

[0042] Step S507: loading input vector x in LDM private space LMEM to shared LDM vector sx, and accelerating by SIMD and loop unrolling;

[0043] Step S508: synchronizing slave array.

[0044] Further, step S104, setting private LDM local space for data cache space of SpMV in row block and batch.

[0045] Further, setting private LDM local space, specifically including:

[0046] Row block load related variable setting, configured according to row block load parameter configuration, including row block result vector dy corresponding to row block size, and row block row offset vector dptr corresponding to row block size+1;

[0047] Batch load related variable setting, determining maximum single batch non-zero element vector dval available for batch SpMV and its column index vector dind length according to private LDM available space size.

[0048] Further, step S105, dividing SpMV row block load, specifically dividing rows into several row blocks according to preset BLOCK_SIZE rows.

[0049] Further, step S106, if there is remaining row block to be processed, taking row block by slave, otherwise exiting, specifically including: if there is remaining row block to be processed, taking row block load from matrix by slave according to slave number PEN; if remaining row number is less than preset BLOCK_SIZE, taking remaining row number as a row block to calculate; calculating actual row block row number block_size; if there is no remaining row block, exiting by slave.

[0050] Further, in step S107, the row block row offset vector dptr is loaded and the row block output vector dy is initialized, specifically including: the row block row offset vector dptr is loaded, with _PEN*BLOCK_SIZE as the offset row_gbgn, a segment vector with a length of block_size+1 int types is taken from the main memory row offset vector ptr to the LDM local row block row offset vector dptr.

[0051] Technical effects

[0052] The application provides a self-adaptive SpMV method based on a new generation of domestic many-core processor, SpMV strategy selection is performed by collecting DCache PMU data, memory access of an input vector x is optimized by using an on-chip shared LDM, and the process of loading the input vector x by the shared LDM is optimized in combination with the characteristics of a core cluster. The self-adaptive SpMV method based on the new generation of domestic many-core processor realizes a fine-grained and low-overhead self-adaptive SpMV method.

[0053] The concept, specific structure and technical effects of the application will be further described below with reference to the drawings, so as to fully understand the purposes, features and effects of the application. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 Fig. 1 is a flowchart of a self-adaptive SpMV method based on a new generation of domestic many-core processor according to a preferred embodiment of the application;

[0055] Figure 2 Fig. 2 is a flowchart of a cluster-based high-affinity shared LDM loading method of the self-adaptive SpMV method based on the new generation of domestic many-core processor according to the preferred embodiment of the application;

[0056] Figure 3 Fig. 3 is a flowchart of a hardware DCache PMU-based SpMV strategy selection method of the self-adaptive SpMV method based on the new generation of domestic many-core processor according to the preferred embodiment of the application;

[0057] Figure 4 Fig. 4 is a flowchart of a shared LDM-based batch SpMV method of the self-adaptive SpMV method based on the new generation of domestic many-core processor according to the preferred embodiment of the application;

[0058] Figure 5 Fig. 5 is a flowchart of a hardware DCache-based batch SpMV method of the self-adaptive SpMV method based on the new generation of domestic many-core processor according to the preferred embodiment of the application. DETAILED DESCRIPTION

[0059] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0060] In the following description, specific details are set forth such as particular internal programs, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it should be apparent to those skilled in the art that the present application can be practiced without such specific details. In other instances, well-known systems, devices, circuits, and methods have been described without unnecessary detail in order to avoid obscuring the present application.

[0061] The embodiment of the present application first takes the main core version SpMV as a comparative example of the embodiment of the present application, and the implementation process includes the following steps:

[0062] Step 1: Obtain SpMV parameters;

[0063] Step 2: Calculate non-zero element multiplication and addition reduction row by row;

[0064] Step 3: Store the calculation result in the main memory output vector y.

[0065] As shown in Figure 1 Another preferred embodiment of the present application provides an adaptive SpMV method based on a new generation of domestic many-core processors, calculating y = Ax, including the following steps:

[0066] Step S101: Set the start-up parameters, including:

[0067] 1) Load division parameters: row block load number of rows.

[0068] 2) Adaptive SpMV decision parameters: row block load sampling rate, single batch DCache miss rate tolerance threshold, and row block shared LDM enable threshold.

[0069] 3) Shared LDM configuration parameters: shared LDM default start-up size.

[0070] Step S102: Obtain SpMV parameters, including:

[0071] 1) Matrix parameters, CSRMatrx type, including: row offset vector ptr main memory address, non-zero element vector val main memory address, non-zero element column index vector ind main memory address, matrix row number n, and matrix non-zero element number nnz;

[0072] 2) Input vector x main memory address;

[0073] 3) Output vector y main memory address.

[0074] Step S103: Set and load input vector x to shared LDM vector sx, including space size mode setting and input vector x loading two steps:

[0075] 1) Set shared mode and size of shared LDM, according to the size of input vector x, that is, the number of matrix rows;

[0076] 2) Load input vector x to shared LDM vector sx.

[0077] Wherein, as shown in Figure 2 Step 2) uses a cluster-based high affinity shared LDM loading method, and the steps include:

[0078] Step S501: Calculate slave core cluster number;

[0079] Step S502: Calculate slave core local number within slave core cluster;

[0080] Step S503: According to the slave core cluster number and the slave core local number within the slave core cluster, calculate the slave core global number related to the slave core cluster;

[0081] Step S504: According to the slave core global number related to the slave core cluster, evenly divide x load load according to block;

[0082] Step S505: Align input vector x load load size by 8*loop unrolling times;

[0083] Step S506: Load input vector x in main memory to LDM private space LMEM using DMA;

[0084] Step S507: Load input vector x in LDM private space LMEM to shared LDM vector sx, and use SIMD and loop unrolling acceleration;

[0085] Step S508: Synchronize slave core array.

[0086] Step S104: Set private LDM local space, set data cache space for row block, batch SpMV, including:

[0087] 1) Row block load related variable setting, according to row block load parameter configuration, including row block result vector dy corresponding to row block size, and row block row offset vector dptr corresponding to row block size+1.

[0088] 2) Batch load related variable setting, according to the size of private LDM available space, determine the maximum single batch non-zero element vector dval available for batch SpMV and its column index vector dind length.

[0089] Step S105: dividing SpMV row block load, dividing rows into several row blocks according to preset BLOCK_SIZE rows;

[0090] Step S106: if there are remaining row blocks to be processed, taking row block load from the matrix from the core according to core number PEN, and performing calculation. If the remaining row number is less than the preset BLOCK_SIZE, taking the remaining row number as a row block to perform calculation. Calculating the actual row block row number block_size. If there is no remaining row block, the core exits.

[0091] Step S107: loading row block row offset vector dptr, taking a segment vector with a length of block_size+1 int types from the main memory row offset vector ptr to the LDM local row block row offset vector dptr with the offset row_gbgn of PEN*BLOCK_SIZE.

[0092] Step S108: SpMV adaptive decision, an SpMV strategy selection method based on hardware DCache PMU, selecting the SpMV strategy to be executed in step S109 according to the sampling result and the threshold setting.

[0093] The SpMV strategy selection method based on hardware DCache PMU includes the following steps:

[0094] Step S601: confirming sampling parameter setting, including: row block load row sampling rate, single batch DCache miss rate tolerance threshold, batch voting counter, and row block shared LDM enabling threshold;

[0095] Step S602: dividing sampling batches;

[0096] Step S603: starting PMU counter;

[0097] Step S604: calculating single batch SpMV;

[0098] Step S605: recording PMU counter value;

[0099] Step S606: if the DCache input vector x memory access miss rate exceeds the single batch DCache miss rate tolerance threshold in step S601 during single batch SpMV calculation, the batch voting counter is incremented by one;

[0100] Step S607: if all sampling batches are processed, step S608 is executed, otherwise, returning to step S603;

[0101] Step S608: dividing the batch voting counter by the total number of sampling batches, if the value exceeds the row block shared LDM enabling threshold in step S601, the shared LDM flag is set to true.

[0102] Step S109: According to the decision result of step S108, if the row block enables shared LDM flag is true, the batch SpMV method based on shared LDM is adopted for processing, otherwise the batch SpMV method based on hardware DCache is used for processing.

[0103] Wherein, for the batch SpMV method based on shared LDM, it includes the following steps:

[0104] Step S701: Search the SpMV batch size;

[0105] Step S702: If the number of single row non-zero elements exceeds the private LDM local space size, use hardware DCache to access the non-zero element vector val and the non-zero element column index vector ind in the main memory for SpMV, that is, skip step S703 and execute step S704;

[0106] Step S703: According to the number of single batch non-zero elements, load the corresponding segment of the non-zero element data vector val and the corresponding segment of the non-zero element column index vector ind from the main memory to the single batch non-zero element vector dval and the single batch non-element column index vector dind in the LDM local storage by DMA;

[0107] Step S704: For single batch row load, perform SpMV calculation row by row, access the main memory input vector x by replacing the vector sx in the shared LDM, and write the multiplication and addition reduction result of the matrix single row vector and the x vector to the corresponding local position of the row block output vector dy in the LDM;

[0108] Step S705: If the row block is not processed, refresh the next batch load start row number and return to step S701, otherwise execute step S706;

[0109] Step S706: Write the row block output vector dy in the LDM to the corresponding segment position of the main memory output vector y by offset in DMA mode according to the row block load size.

[0110] Wherein, for the batch SpMV method based on DCache, compared with the batch SpMV method based on shared LDM, the access to the main memory input vector x is enabled in the core hardware DCache mode, and the DCache size is 32KB.

[0111] Step S110: Return to step S106.

[0112] A specific embodiment of the adaptive SpMV method based on a new generation of domestic many-core processors will be described below. Specifically, the nd24k matrix in SuiteSparse will be taken as an example to illustrate the adaptive SpMV method based on a new generation of domestic many-core processors. The specific steps are as follows:

[0113] Step S101: Set the start-up parameters, including:

[0114] 1) Load division parameters: Based on the DMA continuous memory access characteristics of SW26010P, the row block load size is set to 256 rows, that is, the SpMV calculation of each row block outputs a row block output vector dy with a length of 256 double types and a size of 2048B (256*8B).

[0115] 2) Adaptive SpMV decision parameters: The row block load sampling rate is set to 0.1, that is, the elements in the first 0.1 (i.e., 25 rows) of the 256-row row block are sampled. The single-batch DCache miss rate tolerance threshold is 0.01, that is, if the x memory access miss of each batch SpMV calculation in the sampling process reaches 0.01, the batch voting counter is incremented by one. The row block shared LDM enable threshold is 0.5, that is, the batch counters of the sample_batch_n batches in the sampling process are accumulated, and if the counter exceeds 0.5*sample_batch_n, the row block shared LDM flag is set to true, and the shared LDM memory x is used, otherwise the hardware DCache memory x is used.

[0116] 3) Shared LDM configuration parameters: The shared LDM default mode is set to full slave core array sharing, and the 64KB LDM space in each slave core is continuously addressed to form a continuous shared space on the chip.

[0117] Step S102: Obtain the SpMV parameters, including:

[0118] 1) Matrix parameters, CSRMatrx type, including: row offset vector ptr main memory address, non-zero element vector val main memory address, non-zero element column index vector ind main memory address, matrix row number n = 72000, matrix non-zero element number nnz = 28715634;

[0119] 2) Input vector x main memory address;

[0120] 3) Output vector y main memory address.

[0121] Step S103: Set and load the shared LDM, including shared LDM size and mode setting, and loading the input vector x in two steps:

[0122] 1) Set up the shared mode and size of the shared LDM. The length of the input vector x is the number of columns of the F1 matrix, i.e. 72000. And the type of the elements stored in the x vector is double, which occupies 8B per element. Therefore, the total space occupied by x is 72000*8 = 576000B, which is about 563KB. On average, each slave core needs to bear 563 / 64 = 9KB of loading space.

[0123] 2) Load the vector x using a cluster-based high-affinity shared LDM loading method, the steps of which include:

[0124] Step S501: Calculate the slave core cluster number. The slave core array is arranged in 8*8, and each 2*2 slave core forms a slave core cluster. The slave core cluster number is calculated as cid = _ROW / 2*4 + _COL / 2;

[0125] Step S502: Calculate the local number of the slave core within the slave core cluster, i.e. the cluster internal number of each slave core is calculated as ccid = _ROW%2*2 + _COL%2;

[0126] Step S503: According to the slave core cluster number and the local number of the slave core within the slave core cluster, the global number of the slave core related to the slave core cluster is calculated as gid = cid*4 + ccid;

[0127] Step S504: According to the global number of the slave core related to the slave core cluster, the x loading load is evenly divided into blocks. This process is divided into two stages. In the first stage, the loading load size allocated to each slave core is calculated as base_n = num_x / 64 = 1125, and the remaining x elements are calculated as rest_n = num_x%64 = 0. In the second stage, for the slave core with PEN < rest_n, each slave core is responsible for one of the remaining loads, i.e. the slave core base_n is incremented by 1 (in this example, no slave core needs to be incremented), and its starting position is x_idx_bgn = _PEN*base_n. For the slave core with PEN >= rest_n, its load remains unchanged, but its starting position is x_idx_bgn = _PEN*base_n + rest_n.

[0128] Step S505: Align the x loading load by 8*2 = 16 elements to facilitate subsequent optimization. The starting position x_idx_bgn = x_idx_bgn / 16*16, and the number of loading elements base_n = (base_n+31) / 16*16;

[0129] Step S506: Load the input vector x in the main memory to the LDM private space LMEM using DMA;

[0130] Step S507: Load the input vector x in the LDM private space LMEM into the shared LDM vector sx, and accelerate with SIMD and loop unrolling;

[0131] Step S508: Synchronize the core array.

[0132] Step S104: Set the private LDM local space, set the data cache space for row block, batch SpMV, including:

[0133] 1) Set the row block load related variables, configure according to the row block size of 256 rows. The result vector dy will store 256 double type elements, and the LDM will configure a space of 256*8B=2024B size. The row offset vector dptr will store (256+1) int type elements, and the LDM will configure a space of (256+1)*4B=1028B size.

[0134] 2) Set the batch load related variables, the private space of the core is a maximum of 128KB, of which 1KB is allocated for storing scalar local variables, and the remaining 127KB space can be allocated to the maximum single batch of non-zero elements dval and its column index vector dind available for batch SpMV. Each non-zero element needs to occupy 8B to store the value and 4B to store the column index, so the maximum single batch can allocate 127*1024 / (4*3)=10922 non-zero elements.

[0135] Step S105: Divide the SpMV row block load, and divide the entire matrix by row into row blocks with row_block_size=256 as the granularity.

[0136] Step S106: If there are remaining row blocks to be processed, the core will take the row block with the starting row number as _PEN*row_block_size=_PEN*256 for calculation, and in the next iteration, it will take the next row block across 63 row blocks (i.e. 64*row_block_size=64*256=16384 rows). The core will take the row block load from the matrix according to the core number _PEN for calculation. If there are no remaining row blocks, the core will exit.

[0137] Step S107: Load the row block row offset vector dptr, with _PEN*row_block_size=_PEN*256 as the offset row_gbgn, take the fragment vector of length block_size+1 int type from the main memory row offset vector ptr into the LDM local row block row offset vector dptr.

[0138] Step S108: SpMV adaptive decision, a SpMV strategy selection method based on hardware DCache PMU, according to the shared LDM flag bit selection step S109 to be executed SpMV strategy, for true, select the batch SpMV method based on shared LDM, otherwise execute the batch SpMV method based on hardware DCache.

[0139] As shown in Figure 3 , for the SpMV strategy selection method based on hardware DCache PMU, the steps include:

[0140] Step S601: confirm the sampling parameter setting, including: row block load row sampling rate, single batch DCache miss rate tolerance threshold, batch voting counter, row block shared LDM enable threshold;

[0141] Step S602: divide the sampling batch. According to the calculation of the number of sampling rows in the row block sample_row_n=sample_ratio*row_block_size=0.1*256=25 rows. The sampling row range is [_PEN*row_block_id:_PEN*row_block_id+25], and the local row number range is [0:25];

[0142] Step S603: start PMU counter, start DCache access frequency and DCache miss rate counter;

[0143] Step S604: calculate single batch SpMV, use hardware DCache-based SpMV method to process steps, as shown in Figure 5 , first search single batch can handle the maximum number of rows, and the batch counter is incremented batch_cnt. If processing to the last sampling row, that is, 25 local rows, then exit;

[0144] Step S605: record PMU counter value;

[0145] Step S606: if the DCache access to x during the single batch SpMV calculation process is a hit rate exceeding the single batch DCache miss rate tolerance threshold in step S601, that is, dcache_miss_cnt / dcache_access_cnt>batch_dcache_miss_threshold, then the batch counter is incremented batch_use_sldm_cnt++;

[0146] Step S607: if all sampling batches are processed, then execute step S608, otherwise return to step S603;

[0147] Step S608: Divide the batch voting counter by the total number of sampling batches to obtain the row block shared LDM enabling score batch_use_sldm_score = batch_use_sldm_cnt / batch_cnt. If the value of batch_use_sldm_score exceeds the row block shared LDM enabling threshold block_use_sldm_threshold in step S601, the shared LDM enabling flag is true.

[0148] Step S109: According to the decision result of step S108, select the DCache-based batch SpMV method or the shared LDM-based batch SpMV method according to the shared LDM enabling flag.

[0149] As shown in FIG. 8, the shared LDM-based batch SpMV method includes the following steps: Figure 4

[0150] Step S701: Search for the SpMV batch size;

[0151] Step S702: If the number of single-row non-zero elements exceeds the private LDM local storage size, use the hardware DCache to access the non-zero element vector val and the non-zero element column index vector ind in the main memory to perform SpMV, i.e., skip step S703 and execute step S704;

[0152] Step S703: According to the number of single-batch non-zero elements, load the corresponding segment of the non-zero element data vector val and the corresponding segment of the non-zero element column index vector ind from the main memory to the single-batch non-zero element vector dval and the single-batch non-element column index vector dind in the LDM local storage by DMA;

[0153] Step S704: For single-batch row loading, perform SpMV calculation row by row, replace the process of accessing the input vector x in the main memory with accessing the vector sx in the shared LDM, and write the multiplication and addition reduction result of the matrix single-row vector and the vector x in the LDM into the corresponding local position of the row block output vector dy;

[0154] Step S705: If the row block is not processed, refresh the next batch loading start row number and return to step S701, otherwise execute step S706;

[0155] Step S706: Write the row block output vector dy in the LDM into the corresponding segment position of the output vector y in the main memory by DMA with an offset according to the row block loading size.

[0156] As shown in FIG. 9, the hardware DCache-based batch SpMV method includes the following steps: Figure 5

[0157] ​​Step S801: search SpMV batch size;

[0158] Step S802: if the number of single-row non-zero elements exceeds the size of private LDM local space, use hardware DCache to access the non-zero element vector val and the non-zero element column index vector ind in the main memory to perform SpMV, i.e., skip step S803 and execute step S804;

[0159] Step S803: according to the number of single-batch non-zero elements, load the corresponding segment of the non-zero element data vector val and the corresponding segment of the non-zero element column index vector ind from the main memory to the single-batch non-zero element vector dval and the single-batch non-element column index vector dind in the LDM local space by DMA;

[0160] Step S804: for single-batch row loading, perform SpMV calculation row by row, and use the hardware DCache on the core segment to perform cache optimization in the process of accessing the input vector x in the main memory, and write the multiplication and addition reduction result of the matrix single-row vector and the x vector into the corresponding local position of the row block output vector dy in the LDM;

[0161] Step S805: if the row block is not processed, refresh the start row number of the next batch loading, and return to step S801, otherwise execute step S806;

[0162] Step S806: write the row block output vector dy in the LDM into the corresponding segment position of the output vector y in the main memory by offset in the DMA mode according to the row block loading size.

[0163] In order to verify the actual effect of the present application, the present application is run and tested on a new generation of Shenwei supercomputing platform, and the core optimization version of the present application is compared with the host core version SpMV. The basic information of the test platform is as follows: equipped with a domestic Shenwei heterogeneous many-core processor SW26010P, a master-slave architecture, a slave core LDM space of 256KB, which can be divided into private LDM, shared LDM and hardware Cache three segments, the default hardware DCache size is 32KB, and mpicxx, mpicc, swg++ and swgcc are used for compilation.

[0164] The test matrix data comes from Suite Sparse, and the original data format is Matrix Market (COO) format. In order to facilitate subsequent testing and verification, it has been preprocessed into CSR format. The experimental results are shown in Table 1. The row block load row number of the experiment is set to 256 rows, the single-batch DCache miss rate tolerance threshold is set to 0.01, the row block SpMV strategy selection threshold is set to 0.5, and the row block load sampling rate is set to 0.1.

[0165] Table 1

[0166]

[0167] As shown in the results of Table 1, the SpMV method of the application has good acceleration effect. The application performs fine-grained SpMV adaptive optimization with row block as granularity, and has high flexibility. At the same time, the application characterizes the row block load characteristics from the core hardware DCache PMU counter, and the user can customize the sampling parameters and threshold values, which can truly reflect the adaptability of the SW26010P to the load, and has the characteristics of fine-grained, low overhead, and high flexibility. In the real SpMV scene, the sparsity characteristics of the sparse matrix have diversity, and the fine-grained SpMV strategy selection can improve the comprehensive performance of the SpMV.

[0168] The preferred embodiments of the application are described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and changes without creative labor based on the concept of the application. Therefore, any technical solutions obtained by logical analysis, reasoning or limited experiments based on the prior art within the concept of the application should be within the protection scope determined by the claims.

Claims

1. A self-adaptive SpMV method based on a new generation of domestic many-core processor, characterized in that, The method comprises the following steps: Step S101, setting a start parameter; specifically comprising: Setting a load division parameter, including a row block load number; Setting an adaptive SpMV decision parameter, including a row block load sampling rate, a single batch DCache miss rate tolerance threshold, and a row block shared LDM enabling threshold; Setting a shared LDM configuration parameter, including a shared LDM default start size; Step S102, obtaining an SpMV parameter; specifically comprising: Obtaining a matrix parameter, a CSRMatrx type, including: a row offset vector ptr main memory address, a non-zero element vector val main memory address, a non-zero element column index vector ind main memory address, a matrix row number n, and a matrix non-zero element number nnz; An input vector x main memory address; An output vector y main memory address; Step S103, setting and loading the input vector x in the main memory into the vector sx in the shared LDM; Step S104, setting a private LDM local space for row block and batch SpMV data cache space; Step S105, dividing the SpMV row block load; Step S106, if there is a remaining row block to be processed, taking the row block from the core, otherwise exiting; specifically comprising: if there is a remaining row block to be processed, taking the row block load from the matrix from the core according to the core number PEN for calculation; if the remaining row number is less than the preset BLOCK_SIZE, taking the remaining row number as a row block for calculation; calculating the actual row block row number block_size if there is no remaining row block, then the core exits; Step S107, loading the row block row offset vector dptr and initializing the row block output vector dy; Step S108, SpMV adaptive decision; Step S109, batch calculating the remaining part in the row block, if the row block shared LDM flag is true, using the shared LDM-based batch SpMV method for processing, otherwise using the hardware DCache-based batch SpMV method for processing; Step S110, returning to step S106 for continuous processing until there is no remaining row block to be processed.

2. The self-adaptive SpMV method based on a new generation of domestic many-core processor according to claim 1, wherein, Step S103, setting and loading the input vector x in the main memory into the vector sx in the shared LDM, including space size mode setting and input vector x loading two steps, specifically comprising: Setting the shared mode and size of the shared LDM according to the size of the input vector x, that is, the matrix column number; Loading the input vector x into the shared LDM vector sx.

3. The self-adaptive SpMV method based on a new generation of domestic many-core processor according to claim 2, wherein, Loading the input vector x into the shared LDM vector sx using a cluster-based high-affinity shared LDM loading method, specifically comprising: Step S501: calculating the slave core cluster number; Step S502: calculating the slave core local number in the slave core cluster; Step S503: calculating the slave core global number related to the slave core cluster according to the slave core cluster number and the slave core local number in the slave core cluster; Step S504: dividing the x loading load according to the block according to the slave core global number related to the slave core cluster; Step S505: aligning the input vector x loading load size by 8*cycle unrolling times; Step S506: loading the input vector x in the main memory into the LDM private space LMEM using DMA; Step S507: load the input vector x in the LDM private space LMEM into the shared LDM vector sx, and accelerate with SIMD and loop unrolling; Step S508: synchronize the core array.

4. The self-adaptive SpMV method based on a new generation of domestic many-core processor of claim 1, wherein, The private LDM local space is set, specifically including: Row block load related variable setting, configured according to the row block load parameter configuration, including the row block result vector dy corresponding to the row block size, and the row block row offset vector dptr corresponding to the row block size+1; Batch load related variable setting, according to the available space size of the private LDM, determine the maximum single batch non-zero element vector dval available for batch SpMV and the length of the column index vector dind.

5. The self-adaptive SpMV method based on a new generation of domestic many-core processor according to claim 1, wherein, Step S105, divide the SpMV row block load, specifically divide the rows into several row blocks according to the preset BLOCK_SIZE rows.

6. The self-adaptive SpMV method based on a new generation of domestic many-core processor according to claim 1, wherein, Step S107, load the row block row offset vector dptr and initialize the row block output vector dy, specifically including loading the row block row offset vector dptr, taking the segment vector with a length of block_size+1 int type from the main memory row offset vector ptr to the LDM local row block row offset vector dptr with the offset row_gbgn of _PEN*BLOCK_SIZE.

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