Automobile chip reliability evaluation method based on multi-failure mechanism competitive failure

Abstract

The invention relates to the technical field of automobile chips, and discloses an automobile chip reliability evaluation method based on multi-failure mechanism competitive failure. The method comprises the steps of carrying out a single failure mechanism evaluation test to obtain an acceleration factor and a failure rate, constructing an acceleration factor matrix and a failure rate matrix to calculate a proportion coefficient matrix, and constructing a multi-mechanism competitive failure matrix to calculate the comprehensive failure rate and the average life time so as to evaluate the reliability. According to the method, the competitive relationship of multiple failure mechanisms is comprehensively considered, the comprehensive failure rate and the average life time of the automobile chip in a complex stress environment can be accurately evaluated through a scientific and reasonable test and calculation method, the limitation of separately evaluating each failure mechanism in the prior art is effectively overcome, and the reliability of the automobile chip is improved. According to the method, a more accurate evaluation means which better conforms to actual working conditions is provided for reliability evaluation of the automobile chip, the strict requirement of the automobile industry for reliability evaluation of the chip is met, and the reliability guarantee level of the automobile chip in design, production and application links is improved.

Description

Technical Field

[0001] The present application relates to the field of automotive chip technology, and specifically to an automotive chip reliability assessment method based on competing failures of multiple failure mechanisms. Background Art

[0002] With the vigorous development of the smart car industry, automotive chips, as core components, have attracted much attention for their process and reliability. The working environment of automotive chips is complex, and they have to face challenges such as high and low temperatures, high voltage stress, etc. They often fail due to the combined effects of multiple failure mechanisms such as hot carrier effect (HCI), negative bias temperature instability effect (NBTI), time-dependent dielectric breakdown effect (TDDB), electromigration effect (EM), etc., and these failure mechanisms have similar failure rates, competing with each other to affect chip reliability.

[0003] The inventors discovered in their research on the prior art that when evaluating the reliability of automotive chips, there is a defect in that each failure mechanism is tested and evaluated separately. This defect does not carry out comprehensive stress testing and calculations, and cannot fully reflect the true reliability of the chip in a complex environment, making it difficult to meet the automotive industry's stringent requirements for chip reliability evaluation.

[0004] Chinese patent number CN119493981A discloses a chip performance level prediction method. Although the patent can predict chip performance levels, it is only based on chip attribute parameters and model predictions, and does not consider the failure mechanism of automotive chips in actual operation. It ignores the impact of multiple failure mechanisms such as HCI and NBTI on chip reliability, and does not conduct relevant experiments to obtain data. The evaluation dimension is single, and it is impossible to accurately evaluate the reliability of automotive chips under complex working conditions, which is difficult to meet the needs of the automotive industry.

[0005] In summary, a new technical solution for automotive chip reliability assessment based on multiple failure mechanism competing failures is urgently needed to solve the above technical problems. Summary of the invention

[0006] The purpose of this application is to provide an automotive chip reliability assessment method based on multiple failure mechanism competing failures to solve the technical problems raised in the above background technology.

[0007] To achieve the above objectives, the present application discloses the following technical solution: a method for evaluating the reliability of automotive chips based on competitive failure of multiple failure mechanisms, comprising the following steps: S1: Based on the preset IEC standard and the corresponding same failure criteria, the first batch of single failure mechanism evaluation tests are carried out under different stress conditions to obtain a single acceleration factor and the corresponding single failure rate. The acceleration factor is used to characterize the influence of stress on the failure process; S2: Based on the acceleration factor and failure rate, the corresponding acceleration factor matrix and failure rate matrix are constructed, and the proportion coefficient matrix is ​​calculated. The proportion coefficient matrix is ​​used to characterize the proportion relationship of multiple failure mechanisms in the comprehensive failure rate. The proportion coefficient matrix is ​​also used to calculate the comprehensive failure rate of automotive chips; S3: A multi-mechanism competition failure matrix is ​​constructed based on the acceleration factor matrix, the proportion coefficient matrix and the failure rate matrix. The multi-mechanism competition failure matrix is ​​used to calculate the comprehensive failure rate and the corresponding average life time to evaluate its reliability.

[0008] Preferably, in S1, the first batch of single failure mechanism evaluation tests includes selecting MOS devices of the same process line and the same batch of wafers as test samples, and selecting corresponding MOS devices for multiple failure mechanisms to perform corresponding failure mechanism evaluation tests, and the multiple failure mechanisms include hot carrier effect, negative bias temperature instability effect, time-dependent dielectric breakdown effect and electromigration effect.

[0009] Preferably, the method of selecting corresponding MOS devices for multiple failure mechanisms is: Selecting NMOS devices for the hot carrier effect; Selecting a PMOS device for the negative bias temperature instability effect; Selecting a large-area MOS capacitor for the time-dependent dielectric breakdown effect; Interconnect metal lines are selected according to the electromigration effect.

[0010] Preferably, in S1, a single acceleration factor and a corresponding single failure rate are obtained, specifically: Obtaining a hot carrier effect acceleration factor and a corresponding hot carrier effect failure rate for the hot carrier effect; Obtaining a negative bias temperature instability effect acceleration factor and a corresponding negative bias temperature instability effect failure rate for the negative bias temperature instability effect; Obtaining a time-dependent dielectric breakdown effect acceleration factor and a corresponding time-dependent dielectric breakdown effect failure rate for the time-dependent dielectric breakdown effect; An electromigration effect acceleration factor and a corresponding electromigration effect failure rate are obtained according to the electromigration effect.

[0011] Preferably, in S2, a corresponding acceleration factor matrix and failure rate matrix are constructed based on the acceleration factor and the failure rate, specifically: An acceleration factor matrix is ​​constructed based on the hot carrier effect acceleration factor, the negative bias temperature instability effect acceleration factor, the time-dependent dielectric breakdown effect acceleration factor, and the electromigration effect acceleration factor. ,in, is the number corresponding to different stress conditions, based on the acceleration factor matrix , and obtain the corresponding failure rate matrix , the failure rate matrix Based on the first batch of single failure mechanism evaluation tests.

[0012] Preferably, in S2, the proportion coefficient matrix is ​​calculated based on the acceleration factor matrix and the failure rate matrix Calculate the coefficient matrix , the calculation is specifically .

[0013] As a preferred embodiment, in S3, the multi-mechanism competition failure matrix constructed based on the acceleration factor matrix, the proportion coefficient matrix and the failure rate matrix is: ,in, The number of the new batch.

[0014] Preferably, the comprehensive failure rate is calculated as follows: Get the preset hot carrier effect weight factor , Negative bias temperature instability effect weight factor , time-dependent dielectric breakdown effect weight factor and electromigration effect weight factor , based on the failure rate matrix, the corresponding hot carrier effect failure rate is obtained , the negative bias temperature instability effect failure rate , the time-dependent dielectric breakdown effect failure rate and the electromigration failure rate , the calculation of comprehensive failure rate is: in, is the calculated comprehensive failure rate.

[0015] Preferably, in S3, the average life time is calculated using an average life time formula, and the average life time formula is: in, is the calculated average life span.

[0016] Preferably, when calculating the failure rate of a new batch, each failure mechanism is tested on a much smaller number of test samples than the first batch, and a new acceleration factor under different stress conditions is obtained. Based on the multi-mechanism competition failure matrix, a corresponding new failure rate matrix is ​​obtained, and based on the new failure rate matrix, a new comprehensive failure rate and a new average life time are calculated.

[0017] Beneficial effects: The automotive chip reliability assessment method based on competitive failure of multiple failure mechanisms of the present application uses the preset IEC standard and the same failure criteria to carry out the first batch of single failure mechanism assessment tests, obtain a single acceleration factor and failure rate, and then construct a matrix and calculate the correlation coefficient, thereby achieving a comprehensive consideration of the competitive relationship of multiple failure mechanisms such as hot carrier effect, negative bias temperature instability effect, time-related dielectric breakdown effect and electromigration effect. Through scientific and reasonable test and calculation methods, it can accurately assess the comprehensive failure rate and average life time of automotive chips in complex stress environments, effectively overcome the limitations of traditional separate assessment of each failure mechanism, and provide a more accurate and more practical assessment method for automotive chip reliability assessment, meet the automotive industry's stringent requirements for chip reliability assessment, and improve the reliability assurance level of automotive chips in the design, production and application links. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A flowchart of a method for evaluating the reliability of an automotive chip based on competing failures of multiple failure mechanisms provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0021] In this article, the term "comprising" is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "comprising..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0022] This embodiment discloses Figure 1 The method for evaluating the reliability of an automotive chip based on competitive failure of multiple failure mechanisms includes the following steps: S1: Based on the preset IEC standard and the corresponding same failure criteria, the first batch of single failure mechanism evaluation tests are carried out under different stress conditions to obtain a single acceleration factor and the corresponding single failure rate. The acceleration factor is used to characterize the influence of stress on the failure process; S2: Based on the acceleration factor and failure rate, the corresponding acceleration factor matrix and failure rate matrix are constructed, and the proportion coefficient matrix is ​​calculated. The proportion coefficient matrix is ​​used to characterize the proportion relationship of multiple failure mechanisms in the comprehensive failure rate. The proportion coefficient matrix is ​​also used to calculate the comprehensive failure rate of automotive chips; S3: A multi-mechanism competition failure matrix is ​​constructed based on the acceleration factor matrix, the proportion coefficient matrix and the failure rate matrix. The multi-mechanism competition failure matrix is ​​used to calculate the comprehensive failure rate and the corresponding average life time to evaluate its reliability.

[0023] It should be noted that the IEC standard of this embodiment is an existing standard used in the fields of electrical engineering and electronic engineering. Different stress conditions in this embodiment specifically refer to different voltages and different temperature conditions. In a simple example, the corresponding same failure criteria refer to setting the failure criteria for hot carrier effect and negative bias temperature instability effect to 10% threshold voltage degradation after 10,000s stress test, the failure criterion for electromigration effect to 10% interconnect resistance degradation after 10,000s stress test, and the failure criterion for time-dependent dielectric breakdown effect to MOS capacitor breakdown after 10,000s stress test.

[0024] Based on the above, this embodiment uses the preset IEC standard and the same failure criteria to carry out the first batch of single failure mechanism evaluation tests, obtain a single acceleration factor and failure rate, and then construct a matrix and calculate the correlation coefficient, thereby fully considering the competitive relationship of multiple failure mechanisms such as hot carrier effect, negative bias temperature instability effect, time-related dielectric breakdown effect and electromigration effect. Through scientific and reasonable test and calculation methods, it can accurately evaluate the comprehensive failure rate and average life time of automotive chips in complex stress environments, effectively overcome the limitations of traditional separate evaluation of each failure mechanism, and provide a more accurate and more practical evaluation method for automotive chip reliability evaluation, meet the automotive industry's stringent requirements for chip reliability evaluation, and improve the reliability assurance level of automotive chips in the design, production and application links.

[0025] Specifically, in S1, the first batch of single failure mechanism evaluation tests includes selecting MOS devices of the same process line and the same batch of wafers as test samples, and selecting corresponding MOS devices for multiple failure mechanisms to perform corresponding failure mechanism evaluation tests. The multiple failure mechanisms include hot carrier effect, negative bias temperature instability effect, time-dependent dielectric breakdown effect and electromigration effect.

[0026] Based on the above, this embodiment uses the method of selecting MOS devices of the same process line and the same batch of wafers as test samples, and selecting specific MOS devices for different failure mechanisms, thereby reducing the test errors caused by process differences. The process parameters of devices of the same process line and batch are highly consistent, which can ensure that the data obtained when conducting failure mechanism evaluation tests such as hot carrier effect and negative bias temperature instability effect are more comparable and accurate. Selecting suitable MOS devices for different failure mechanisms can give full play to the device characteristics, so that the test results can more truly reflect the impact of the failure mechanism on the reliability of automotive chips, thereby improving the accuracy and reliability of the entire reliability evaluation method, and laying a solid foundation for subsequent accurate calculation and evaluation.

[0027] Specifically, the method of selecting the corresponding MOS device for multiple failure mechanisms is: Select NMOS devices for hot carrier effects; Select PMOS devices for negative bias temperature instability effect; Select large-area MOS capacitors for the time-dependent dielectric breakdown effect; Interconnect metal lines are selected for electromigration effects.

[0028] Through the above, this embodiment achieves improved test pertinence and effectiveness. Different types of MOS devices have unique responses to specific failure mechanisms. NMOS devices are more sensitive to hot carrier effects and can more accurately capture chip performance changes under this effect; PMOS devices have more obvious characteristics for negative bias temperature instability effects. Through this targeted selection, more accurate acceleration factor and failure rate data can be obtained when conducting single failure mechanism evaluation tests, so that in the subsequent process of constructing the matrix and calculating the comprehensive failure rate, the impact of each failure mechanism on the reliability of the automotive chip can be more accurately evaluated, thereby improving the credibility of the evaluation results.

[0029] Specifically, in S1, a single acceleration factor and a corresponding single failure rate are obtained, specifically: According to the hot carrier effect, the hot carrier effect acceleration factor and the corresponding hot carrier effect failure rate are obtained; The acceleration factor of negative bias temperature instability effect and the corresponding failure rate of negative bias temperature instability effect are obtained for the negative bias temperature instability effect. According to the time-dependent dielectric breakdown effect, the time-dependent dielectric breakdown effect acceleration factor and the corresponding time-dependent dielectric breakdown effect failure rate are obtained; The electromigration effect acceleration factor and the corresponding electromigration effect failure rate are obtained for the electromigration effect.

[0030] Through the above, this embodiment uses the method of obtaining the corresponding acceleration factor and failure rate for each failure mechanism to achieve a refined analysis of each failure mechanism. Corresponding data is obtained one by one for the hot carrier effect, negative bias temperature instability effect, etc., and the degree of influence of each failure mechanism on the failure process of the automotive chip under different stress conditions can be clearly grasped. These detailed data provide an accurate basis for the subsequent construction of the acceleration factor matrix and the failure rate matrix, so that when calculating the proportion coefficient matrix and the comprehensive failure rate, it can more accurately reflect the role of each failure mechanism in the comprehensive situation, avoid errors caused by general analysis, and thus improve the accuracy of automotive chip reliability assessment, and provide strong support for the optimization design and quality control of automotive chips.

[0031] Specifically, in S2, the corresponding acceleration factor matrix and failure rate matrix are constructed based on the acceleration factor and failure rate, specifically: Construct an acceleration factor matrix based on the hot carrier effect acceleration factor, the negative bias temperature instability effect acceleration factor, the time-dependent dielectric breakdown effect acceleration factor, and the electromigration effect acceleration factor ,in, is the number corresponding to different stress conditions, based on the acceleration factor matrix , and obtain the corresponding failure rate matrix , the failure rate matrix Based on the first batch of single failure mechanism evaluation tests.

[0032] Based on the above, this embodiment uses the acceleration factors of various failure mechanisms such as hot carrier effect and negative bias temperature instability effect to construct an acceleration factor matrix, and based on this, obtains the failure rate matrix, thereby realizing the systematic integration of complex failure mechanism data. The acceleration factor matrix is ​​numbered according to different stress conditions, and the acceleration factors of various failure mechanisms are arranged in order, clearly presenting the acceleration of each failure mechanism under different stresses; the failure rate matrix corresponds to it, reflecting the corresponding failure rate data. This matrix form facilitates the subsequent calculation of the proportion coefficient matrix and the comprehensive failure rate, making the entire evaluation process more organized and standardized, improving the evaluation efficiency and accuracy, and providing an efficient data processing and analysis method for automotive chip reliability evaluation.

[0033] Specifically, in S2, the proportion coefficient matrix is ​​calculated based on the acceleration factor matrix and failure rate matrix Calculate the coefficient matrix , the calculation is specifically .

[0034] Based on the above, this embodiment uses the inverse matrix of the acceleration factor matrix to multiply the failure rate matrix to calculate the proportion coefficient matrix, thereby quantifying the proportion of each failure mechanism in the comprehensive failure rate, thereby accurately obtaining the proportion coefficients of hot carrier effect, negative bias temperature instability effect, etc. in the comprehensive failure rate. These coefficients are key parameters for evaluating the reliability of automotive chips. They clarify the contribution of each failure mechanism to the overall reliability of the chip, which helps engineers understand the main causes of chip failure, so as to take targeted measures in the chip design, manufacturing and application process to improve the reliability and stability of the chip.

[0035] Specifically, in S3, the multi-mechanism competition failure matrix constructed based on the acceleration factor matrix, the proportion coefficient matrix and the failure rate matrix is: ,in, The number of the new batch.

[0036] In a simple example, the multi-mechanism competition failure matrix of this embodiment is constructed as follows: Under experimental conditions, the voltage and temperature The acceleration factor of the HCI effect obtained under , the acceleration factor of NBTI effect is , the acceleration factor of the TDDB effect is , the acceleration factor of the EM effect is The failure rate is ; Under experimental conditions, the voltage and temperature The acceleration factor of the HCI effect obtained under , the acceleration factor of NBTI effect is , the acceleration factor of the TDDB effect is , the acceleration factor of the EM effect is The failure rate is ; Under experimental conditions, the voltage and temperature The acceleration factor of the HCI effect obtained under , the acceleration factor of NBTI effect is , the acceleration factor of the TDDB effect is , the acceleration factor of the EM effect is The failure rate is ; Under experimental conditions, the voltage and temperature The acceleration factor of the HCI effect obtained under , the acceleration factor of NBTI effect is , the acceleration factor of the TDDB effect is , the acceleration factor of the EM effect is The failure rate is ; The obtained acceleration factor matrix is The failure rate matrix is Based on this, using Calculated , based on this Conduct reliability assessment of new batches.

[0037] Based on the above, this embodiment uses the acceleration factor matrix and the proportion coefficient matrix to construct a multi-mechanism competition failure matrix, and uses the new batch number to distinguish them, so as to realize the rapid calculation of the failure rate of the new batch of chips. When evaluating a new batch of chips, it is only necessary to obtain a new acceleration factor, combine it with the existing proportion coefficient matrix, and quickly obtain a new failure rate matrix through the multi-mechanism competition failure matrix. This method greatly reduces the workload of new batch tests, shortens the evaluation cycle, and ensures the accuracy and consistency of the evaluation results. It not only improves the evaluation efficiency, but also reduces costs, so that the reliability evaluation of automotive chips can better adapt to the needs of large-scale production and rapid iteration.

[0038] Specifically, the calculation method of comprehensive failure rate is: Get the preset hot carrier effect weight factor , Negative bias temperature instability effect weight factor , time-dependent dielectric breakdown effect weight factor and electromigration effect weight factor , based on the failure rate matrix, the corresponding hot carrier effect failure rate is obtained , Negative bias temperature instability effect failure rate , time-dependent dielectric breakdown effect failure rate and electromigration failure rate , the calculation of comprehensive failure rate is: in, is the calculated comprehensive failure rate.

[0039] It should be noted that the weight factor of this embodiment can be obtained by, but is not limited to, obtaining it from a chip production company or international related literature, and in this embodiment, .

[0040] In a simple example, the hot carrier effect weight factor is 0.3, the negative bias temperature instability effect weight factor is 0.25, the time-dependent dielectric breakdown effect weight factor is 0.2, and the electromigration effect weight factor is 0.25, obtained from the chip production company or international related literature. After the first batch of single failure mechanism evaluation tests, the failure rate of hot carrier effect was 100%, the failure rate of negative bias temperature instability effect was 80%, the failure rate of time-related dielectric breakdown effect was 60%, and the failure rate of electromigration effect was 70%. According to the comprehensive failure rate calculation formula, substituting the data into the comprehensive failure rate, we can get a comprehensive failure rate of 79.5.

[0041] Furthermore, in a simple example, the comprehensive failure rate is 79.5, and the average life time is calculated to be 1.26*10 7 .

[0042] Based on the above, this embodiment uses the method of obtaining preset weight factors and calculating the comprehensive failure rate in combination with the failure rate matrix to achieve comprehensive consideration of the impact of multiple failure mechanisms on the reliability of automotive chips. Different failure mechanisms such as hot carrier effect and negative bias temperature instability effect have different degrees of influence on chip reliability. By presetting weight factors, the weight of each failure mechanism in the calculation of the comprehensive failure rate can be reasonably allocated according to actual conditions. The failure rate of each failure mechanism is multiplied by the corresponding weight factor and then added up. The comprehensive failure rate obtained can more truly reflect the reliability status of automotive chips under the joint action of multiple failure mechanisms, and provide more accurate quantitative indicators for quality assessment and reliability prediction of automotive chips.

[0043] Specifically, in S3, the average life span is calculated using the average life span formula, which is: in, is the calculated average life span.

[0044] Based on the above, this embodiment uses the average life time formula to convert the comprehensive failure rate into an intuitive automotive chip life indicator. The average life time is an important parameter for measuring the reliability of automotive chips. Through this formula, the comprehensive failure rate obtained by complex calculations can be converted into an easy-to-understand time value. This enables engineers, manufacturers and users to understand the expected service life of automotive chips more intuitively, and provides an important reference basis in chip selection, product design and maintenance plan formulation, which helps to improve the reliability and stability of automotive products and reduce the risk of use.

[0045] Specifically, when calculating the failure rate of a new batch, each failure mechanism is tested on a much smaller number of test samples than the first batch to obtain a new acceleration factor under different stress conditions. Based on the multi-mechanism competition failure matrix, the corresponding new failure rate matrix is ​​obtained, and based on the new failure rate matrix, a new comprehensive failure rate and a new average life time are calculated.

[0046] Based on the above, this embodiment uses a small number of tests on each failure mechanism of the new batch to obtain a new acceleration factor, and then calculates a new failure rate matrix based on a multi-mechanism competition failure matrix, and further calculates a new comprehensive failure rate and average life time. This method achieves efficient and low-cost evaluation of the reliability of new batches of automotive chips. Compared with the large-scale tests of the first batch, only a small number of tests are required for the new batch, which greatly reduces the test cost and time. At the same time, based on the existing matrix and calculation method, the accuracy and consistency of the evaluation are guaranteed. This method enables rapid reliability evaluation of different batches of products during the production process of automotive chips, timely discovery and resolution of potential problems, and improved production efficiency and product quality.

[0047] In summary, the automotive chip reliability assessment method based on competitive failure of multiple failure mechanisms of this embodiment uses the preset IEC standard and the same failure criteria to carry out the first batch of single failure mechanism assessment tests, obtain a single acceleration factor and failure rate, and then construct a matrix and calculate the correlation coefficient, thereby achieving a comprehensive consideration of the competitive relationship of multiple failure mechanisms such as hot carrier effect, negative bias temperature instability effect, time-related dielectric breakdown effect and electromigration effect. Through scientific and reasonable test and calculation methods, the comprehensive failure rate and average life time of automotive chips in complex stress environments can be accurately assessed, effectively overcoming the limitations of traditional separate assessment of each failure mechanism, providing a more accurate and more actual working condition assessment method for automotive chip reliability assessment, meeting the automotive industry's stringent requirements for chip reliability assessment, and improving the reliability assurance level of automotive chips in the design, production and application links.

[0048] In the embodiments provided in the present application, it should be understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, code, or any appropriate combination thereof. For hardware implementation, the processor can be implemented in one or more of the following units: an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a processor, a controller, a microcontroller, a microprocessor, other electronic units designed to implement the functions described herein, or a combination thereof. For software implementation, part or all of the processes of the embodiment can be completed by instructing the relevant hardware through a computer program. When implemented, the above program can be stored in a computer-readable storage medium or transmitted as one or more instructions or codes on a computer-readable storage medium. Computer-readable storage media include computer storage media and communication media, wherein the communication medium includes any medium that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that can be accessed by a computer. Computer-readable storage media can include, but are not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer.

[0049] Finally, it should be noted that the above is only a preferred embodiment of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A reliability assessment method for automotive chips based on multiple failure mechanism competition failures, characterized in that: The following steps are involved: S1: Based on the preset IEC standard and the corresponding same failure criteria, the first batch of single failure mechanism evaluation tests are carried out under different stress conditions to obtain a single acceleration factor and the corresponding single failure rate. The acceleration factor is used to characterize the influence of stress on the failure process; S2: Based on the acceleration factor and failure rate, the corresponding acceleration factor matrix and failure rate matrix are constructed, and the proportion coefficient matrix is ​​calculated. The proportion coefficient matrix is ​​used to characterize the proportion relationship of multiple failure mechanisms in the comprehensive failure rate. The proportion coefficient matrix is ​​also used to calculate the comprehensive failure rate of automotive chips; S3: A multi-mechanism competition failure matrix is ​​constructed based on the acceleration factor matrix, the proportion coefficient matrix and the failure rate matrix. The multi-mechanism competition failure matrix is ​​used to calculate the comprehensive failure rate and the corresponding average life time to evaluate its reliability.

2. The automotive chip reliability assessment method based on multiple failure mechanism competition failure according to claim 1 is characterized in that: In S1, the first batch of single failure mechanism evaluation tests includes selecting MOS devices from the same process line and the same batch of wafers as test samples, and selecting corresponding MOS devices for multiple failure mechanisms to conduct corresponding failure mechanism evaluation tests. The multiple failure mechanisms include hot carrier effect, negative bias temperature instability effect, time-dependent dielectric breakdown effect and electromigration effect.

3. The automotive chip reliability assessment method based on multiple failure mechanism competition failure according to claim 2 is characterized in that: The method of selecting corresponding MOS devices for multiple failure mechanisms is: Selecting NMOS devices for the hot carrier effect; Selecting a PMOS device for the negative bias temperature instability effect; Selecting a large-area MOS capacitor for the time-dependent dielectric breakdown effect; Interconnect metal lines are selected according to the electromigration effect.

4. The automotive chip reliability assessment method based on multiple failure mechanism competition failure according to claim 2 is characterized in that: In S1, a single acceleration factor and a corresponding single failure rate are obtained, specifically: Obtaining a hot carrier effect acceleration factor and a corresponding hot carrier effect failure rate for the hot carrier effect; Obtaining a negative bias temperature instability effect acceleration factor and a corresponding negative bias temperature instability effect failure rate for the negative bias temperature instability effect; Obtaining a time-dependent dielectric breakdown effect acceleration factor and a corresponding time-dependent dielectric breakdown effect failure rate for the time-dependent dielectric breakdown effect; An electromigration effect acceleration factor and a corresponding electromigration effect failure rate are obtained according to the electromigration effect.

5. The automotive chip reliability assessment method based on multiple failure mechanism competition failure according to claim 4 is characterized in that: In S2, the corresponding acceleration factor matrix and failure rate matrix are constructed based on the acceleration factor and failure rate, specifically: An acceleration factor matrix is ​​constructed based on the hot carrier effect acceleration factor, the negative bias temperature instability effect acceleration factor, the time-dependent dielectric breakdown effect acceleration factor, and the electromigration effect acceleration factor. ,in, is the number corresponding to different stress conditions, based on the acceleration factor matrix , and obtain the corresponding failure rate matrix , the failure rate matrix Based on the first batch of single failure mechanism evaluation tests.

6. The automotive chip reliability assessment method based on multiple failure mechanism competition failure according to claim 5 is characterized in that: In S2, the proportion coefficient matrix is ​​calculated based on the acceleration factor matrix and the failure rate matrix Calculate the coefficient matrix , the calculation is specifically .

7. The automotive chip reliability assessment method based on multiple failure mechanism competition failure according to claim 6 is characterized in that: In S3, the multi-mechanism competition failure matrix constructed based on the acceleration factor matrix, the proportion coefficient matrix and the failure rate matrix is: ,in, The number of the new batch.

8. The automotive chip reliability assessment method based on multiple failure mechanism competition failure according to claim 5 is characterized in that: The comprehensive failure rate is calculated as follows: Get the preset hot carrier effect weight factor , Negative bias temperature instability effect weight factor , time-dependent dielectric breakdown effect weight factor and electromigration effect weight factor , based on the failure rate matrix, the corresponding hot carrier effect failure rate is obtained , the negative bias temperature instability effect failure rate , the time-dependent dielectric breakdown effect failure rate and the electromigration failure rate , the calculation of comprehensive failure rate is: in, is the calculated comprehensive failure rate.

9. The automotive chip reliability assessment method based on multiple failure mechanism competition failure according to claim 8 is characterized in that: In S3, the average life time is calculated using the average life time formula, and the average life time formula is: in, is the calculated average life span.

10. The automotive chip reliability assessment method based on multiple failure mechanism competition failure according to claim 7, characterized in that: When calculating the failure rate of a new batch, each failure mechanism is tested on a much smaller number of test samples than the first batch to obtain a new acceleration factor under different stress conditions. A corresponding new failure rate matrix is ​​obtained based on the multi-mechanism competition failure matrix, and a new comprehensive failure rate and a new average life time are calculated based on the new failure rate matrix.

Images