Semiconductor integrated circuit and layout design method thereof

Abstract

A layout design method includes receiving input data defining a semiconductor integrated circuit, performing an arrangement operation and a routing operation based on the input data to obtain a first layout of the semiconductor integrated circuit including a plurality of blocks, setting a first switch region in which a first switch is to be arranged on the first layout, and arranging a first switch in the first switching region, and arranging a second switch in a second switching region different from the first switching region to obtain a second layout of the semiconductor integrated circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0137030 filed on October 13, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Apparatus, devices, and methods consistent with the present disclosure relate to a semiconductor integrated circuit and a layout design method of the semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit and a layout design method of the semiconductor integrated circuit capable of reducing inrush current. Background Art

[0004] Semiconductor devices are manufactured by patterning the devices and their interconnections on a substrate such as a semiconductor wafer. Semiconductor devices can be manufactured by designing integrated circuits using electronic design automation (EDA), which assists designers in arranging the various constituent components of the circuit to function and connect the various constituent components to each other. In other words, a layout designer can generate a layout of a semiconductor device by using EDA.

[0005] The layout of a semiconductor device may include circuit components, connection wiring, physical locations, and sizes of various layers. The semiconductor device may be manufactured by verifying the layout of the semiconductor device and transferring the verified layout onto a semiconductor substrate. Summary of the invention

[0006] One aspect is to provide a layout design method for a semiconductor integrated circuit capable of reducing surge current.

[0007] According to an aspect of one or more embodiments, there is provided a layout design method, comprising: receiving input data defining a semiconductor integrated circuit; performing a layout operation and a wiring operation based on the input data to obtain a first layout of the semiconductor integrated circuit including a plurality of blocks; setting a first switch region of a plurality of first switches to be arranged on the first layout; and arranging the plurality of first switches in the first switch region and arranging the plurality of second switches in a second switch region different from the first switch region to obtain a second layout of the semiconductor integrated circuit.

[0008] According to another aspect of one or more embodiments, there is provided a semiconductor integrated circuit, including: a power management integrated circuit (PMIC) configured to generate power; and a system on chip (SoC) configured to operate according to the power from the PMIC. The SoC includes: an element area in which macroblocks and storage blocks are arranged; and a logic circuit area in which a plurality of switches are arranged, which are capable of controlling the power applied to the macroblocks and the storage blocks. The logic circuit area includes a first switch area in which a plurality of first switches are arranged to reduce the surge current applied to the element area; and a second switch area in which a plurality of second switches are arranged, which control all the power applied to the element area. The first switch area is arranged in an area of ​​the SoC other than the first edge area, the second edge area, the third edge area, and the fourth edge area of ​​the SoC.

[0009] According to another aspect of one or more embodiments, there is provided a semiconductor integrated circuit, including: a power management integrated circuit (PMIC) configured to generate power; and a system on chip (SoC) configured to operate according to the power from the PMIC. The SoC includes a first switch area, the first switch area includes a plurality of first switches, the plurality of first switches receive a first signal from the PMIC and are turned on based on the first signal; and a second switch area includes a plurality of second switches, the plurality of second switches receive a second signal from the PMIC and are turned on based on the second signal. The first switch area and the second switch area are arranged in an area of ​​the SoC that does not interfere with macro blocks and memory blocks on the SoC, and the first switch area is arranged in an area of ​​the SoC other than a first edge area, a second edge area, a third edge area, and a fourth edge area of ​​the SoC. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a flow chart of a layout design method of a semiconductor integrated circuit according to an embodiment;

[0012] Figure 2A and Figure 2B is a flow chart of a layout design method of a semiconductor integrated circuit according to an embodiment;

[0013] Figure 3 is a schematic diagram for describing signal transmission / reception between a system on chip (SoC) and a power management integrated circuit (PMIC) according to an embodiment;

[0014] Figure 4is a schematic diagram showing a configuration of a semiconductor integrated circuit according to an embodiment;

[0015] Figure 5 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to an embodiment;

[0016] Figure 6 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to an embodiment;

[0017] Figure 7 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to an embodiment;

[0018] Fig. 8A , Figure 8B and Figure 8C is a schematic diagram showing the configuration of a semiconductor integrated circuit according to a comparative example and an embodiment;

[0019] Fig. 9 shows a graph for describing current changes in a semiconductor integrated circuit according to a comparative example and an embodiment;

[0020] Fig.10 and Fig.11 is a block diagram of a design system for a semiconductor integrated circuit according to an embodiment;

[0021] Fig.12 is a block diagram showing a system on chip (SoC) according to an embodiment;

[0022] Fig.13 is a flowchart illustrating a method of manufacturing an integrated circuit (IC) according to an embodiment; and

[0023] Fig.14 is a detailed flowchart illustrating a layout design operation according to an embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, various embodiments are described with reference to the accompanying drawings.

[0025] Figure 1 is a flowchart of a layout design method of a semiconductor integrated circuit according to an embodiment.

[0026] refer to Figure 1 The layout design method of the semiconductor integrated circuit according to the embodiment can be performed in the design process of the semiconductor integrated circuit, and can be performed on a system and / or tool for designing the semiconductor integrated circuit. In an embodiment, the system and / or tool may include a program including a plurality of instructions executed by a processor. Fig.10 and Fig.11 Describe the system and / or tool.

[0027] In a method for designing a layout of a semiconductor integrated circuit, input data defining the semiconductor integrated circuit may be received (operation S1000). In some embodiments, the input data may define a semiconductor device. In some embodiments, the input data may define a semiconductor chip. For example, the input data may correspond to a first layout of operation S2000.

[0028] The input data may include data generated from an abstract form of the behavior of the semiconductor integrated circuit, for example, data generated by synthesis using data defined at a register transfer level (RTL). For example, the input data may include a bitstream or a netlist generated by synthesizing a semiconductor integrated circuit defined by a hardware description language (HDL) such as very high speed integrated circuit (VHSIC) HDL (VHDL) and Verilog.

[0029] In some embodiments, the input data may include data defining the layout of the semiconductor integrated circuit. For example, the input data may include geometric information defining a structure implemented using semiconductor materials, metals, insulators, etc. The layout of the semiconductor integrated circuit represented by the input data may include the layout of cells and may include wires connecting cells to each other.

[0030] Placement & routing (P&R) may be performed based on the input data to obtain a first layout of the semiconductor integrated circuit (operation S2000). The first layout may include a plurality of blocks, a plurality of standard cells, a plurality of power wirings, a plurality of ground wirings, a plurality of clock wirings, and a plurality of signal wirings.

[0031] A first switch region where a plurality of first switches are to be arranged may be set on the first layout (operation S3000). For example, the first switch region may include a region in the first layout where no macro element, storage element, etc. are arranged. In an embodiment, the first switch region may be set for a partial region of a semiconductor integrated circuit. In other words, the first switch region may be set in units of semiconductor integrated circuits. According to some embodiments, by setting a first switch region arranged in a specific region of a semiconductor integrated circuit, surge current may be reduced.

[0032] A plurality of first switches may be arranged in a first switch region, and a plurality of second switches may be arranged in a second switch region different from the first switch region to obtain a second layout of the semiconductor integrated circuit (operation S4000). According to an embodiment, the first layout may include a layout before the first switches and the second switches are arranged, and the second layout may include a layout after the first switches and the second switches are arranged. According to an embodiment, the first switch region may include a region configured to mainly apply power to a portion of the plurality of blocks, and the second switch region may include a region configured to apply power to the remaining portion of the plurality of blocks. Figure 3 A detailed description of the first switching region and the second switching region is given below.

[0033] According to an embodiment, operations S3000 and S4000 may be sequentially performed. After operation S4000 is performed, output data defining the semiconductor integrated circuit may be generated and provided. For example, in operation S4000, the output data may correspond to the second layout.

[0034] In an embodiment, when the received input data is data generated by synthesizing a semiconductor integrated circuit (such as a bitstream and a netlist), the output data may be a bitstream or a netlist. In an embodiment, when the received input data is data defining a layout of a semiconductor integrated circuit having a Graphic Data System II (GDSII) format, the format of the output data may also be data defining a layout of a semiconductor integrated circuit.

[0035] In an embodiment, the above operation can be performed by designing a semiconductor integrated circuit using a design tool. For example, the above tool can be a Fusion compiler tool of Synopsys and / or an Innovus tool of Cadence, but the embodiment is not limited thereto. In an embodiment, the semiconductor integrated circuit can be a system on chip SoC. However, the embodiment is not limited thereto.

[0036] Figure 2A and Figure 2B is a flow chart of a layout design method for a semiconductor integrated circuit according to an embodiment. Figure 2A and Figure 2B The operations described may be included in Figure 1 The constituent operations in operation S3000.

[0037] refer to Figure 2A, in operation S3100, the logic circuit area may be set to a first switch area on the first layout. The logic circuit area may mean a remaining area in which the element area is not arranged on the layout. The element area may represent an area in which blocks such as macro elements and memory elements are arranged. According to an embodiment, the first switch area may be set to any one part of the logic circuit area. In operation S3200, the first switch area may be set to a central area of ​​the first layout of the semiconductor integrated circuit among a plurality of logic circuit areas. In other words, in some embodiments, the first switch area may be set to a central area opposite to an edge area of ​​the first layout. In some embodiments, the first switch area may be set to a central area avoiding an edge area of ​​the first layout.

[0038] refer to Figure 2B In operation S3110, the logic circuit region may be set to a first switch region on the first layout. According to an embodiment, the first switch region may be set to any part of the logic circuit region. In operation S3210, the first switch region may be set to another region of the plurality of logic circuit regions except the first edge region, the second edge region, the third edge region, and the fourth edge region on the first layout of the semiconductor integrated circuit.

[0039] According to various embodiments, by arranging the first switch region close to the center region on the first layout rather than the edge region, the surge current can be reduced. The surge current may mean a current greater than the rated current temporarily applied to the semiconductor integrated circuit when power is applied to the semiconductor integrated circuit. According to various embodiments, by arranging the first switch region close to the center region, the surge current can be reduced by allowing power to propagate over a wider range. The arrangement structure of the first switch region is described in more detail with reference to the following schematic diagram.

[0040] Figure 3 is a diagram for describing signal transmission / reception between a SoC and a power management integrated circuit PMIC according to an embodiment.

[0041] refer to Figure 3 , the semiconductor device 10 may be implemented as a portable electronic device.

[0042] The portable electronic device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, or an e-book. In some embodiments, the semiconductor device 10 may have a concept including a semiconductor integrated circuit.

[0043] The semiconductor device 10 may include a system on chip (SoC) 200 and a power management integrated circuit (PMIC) 100. According to an embodiment, Figure 3 The SoC 110 in the embodiment may not include the PMIC 100, and the PMIC 100 may be implemented separately from the SoC 110, which is different from the embodiment described below. Fig.12 Unlike the SoC 3000 shown in FIG, the SoC 3000 incorporates a PMIC as a power management unit. Figure 3 , the total power of SoC 110 may be controlled by a separate voltage management circuit implemented outside SoC 110 (eg, by PMIC 100 ).

[0044] According to an embodiment, the SoC 110 may receive a first signal pre_s from the PMIC 100. When the first signal pre_s is received, a plurality of first switches included in a first switch region included in the SoC 110 may be turned on. When the plurality of first switches are fully turned on, a first completion signal pre indicating that the plurality of first switches are fully turned on may be transmitted to the PMIC 100.

[0045] According to an embodiment, the SoC 110 may receive a second signal all_s from the PMIC 100. When the second signal all_s is received, a plurality of second switches included in a second switch region included in the SoC 110 may be turned on. When the plurality of second switches are fully turned on, a second completion signal all indicating that the plurality of second switches are fully turned on may be transmitted to the PMIC 100.

[0046] According to an embodiment, the number of the first switches may be less than the number of the second switches. According to an embodiment, the second switches may correspond to all switches capable of applying power to all blocks included in the SoC 110.

[0047] refer to Figure 3 According to various embodiments, the SoC 110 may include a first switch region and a second switch region, and each of the first switch region and the second switch region may be controlled to turn on a plurality of switches respectively included in the switch region in response to a first signal and a second signal, respectively. By mainly (i.e., firstly) turning on a plurality of first switches included in the first switch region and applying power to a partial region, the SoC 110 according to various embodiments may reduce surge current generated by sudden application of power. By adjusting the arrangement position of the first switch region, surge current may be further reduced. Specific embodiments are described below with reference to Figure 4 A detailed description of the arrangement position of the first switch region is given below. According to various embodiments, in the power gating design, in order to reduce the surge peak current, the power can be controlled by using a dual switch configuration including a first switch and a second switch. Figures 4 to 7 Describes in more detail Figure 3 SoC 110.

[0048] Figure 4 is a schematic diagram showing the configuration of a semiconductor integrated circuit 200 according to the embodiment.

[0049] refer to Figure 4 , the semiconductor integrated circuit 200 may include a plurality of blocks 210 and 220 and a switch region 230. The plurality of blocks 210 and 220 may be referred to as functional blocks or intellectual property (IP). For example, the plurality of blocks 210 and 220 may include macro blocks for data processing and / or operation and memory blocks for data storage.

[0050] The plurality of blocks 210 and 220 may include a plurality of standard cells. A standard cell refers to an integrated circuit unit having a layout size that satisfies a preset rule and a preset function. For example, in some embodiments, the block 210 may include four standard cells 211-214, and the block 220 may include two standard cells 221-222, such as Figure 4 as shown in the example.

[0051] The functions and operations of the semiconductor integrated circuit 200 may be implemented by a plurality of blocks 210 and 220 and / or a plurality of standard cells 211-214 and 221-222 included in the semiconductor integrated circuit 200. In other words, the plurality of blocks 210 and 220 and / or the plurality of standard cells 211-214 and 221-222 may represent predefined logic circuit blocks to be implemented in the semiconductor integrated circuit 200, and in some cases, their functions may be parameterized. Although not shown, each of the plurality of blocks 210 and 220 and / or each of the plurality of standard cells 211-214 and 221-222 may include a plurality of elements for implementing the functions and operations of the semiconductor integrated circuit 200. For example, the plurality of elements may include active elements, passive elements, analog elements, digital elements, logic elements, etc. Although not shown, the plurality of blocks 210 and 220 and / or the plurality of standard cells 211-214 and 221-222 may be formed on a semiconductor substrate.

[0052] For convenience, Figure 4 Only blocks 210 and 220 are shown in FIG. 2 , but the embodiment is not limited thereto, and the number of blocks and standard cells included in the semiconductor integrated circuit 200 may be changed in various ways according to various embodiments. In other words, Figure 4 Two blocks 210 and 220 are shown in FIG, wherein block 210 has standard cells 211-214 and block 220 has standard cells 221-222. However, in some embodiments, more than two blocks may be provided, and more than two or more than four standard cells may be provided.

[0053] The switch region 230 may include a first switch region 231 and a second switch region 232. The first switch region 231 may include a plurality of first switches. The second switch region 232 may include a plurality of second switches. In some embodiments, the number of first switches may be less than the number of second switches.

[0054] According to an embodiment, the plurality of first switches included in the first switch region 231 may be switches configured to be turned on by the first signal pre_s. The plurality of second switches included in the second switch region 232 may be switches configured to be turned on by the second signal all_s. Each of the first switch region 231 and the second switch region 232 may be arranged in a logic circuit region in which the plurality of blocks 210 and 220 are not arranged. According to various embodiments, an area in which the first switch region 231 is to be arranged may be preset, and by arranging the first switch region 231 in the preset area, a surge current may be prevented.

[0055] When a power rail arranged in the X-axis direction is interfered by an already arranged block and is not properly supplied with power, a surge current may be generated, but according to various embodiments, this problem may be improved by arranging the first switching region in the center region.

[0056] Figure 5 is a schematic diagram showing the configuration of a semiconductor integrated circuit 300 according to the embodiment.

[0057] refer to Figure 5 , the semiconductor integrated circuit 300 may include a macro region 310, a memory region 320, a first switch region 331, and a second switch region 332. The semiconductor integrated circuit 300 may further include supplementary constituent elements such as power lines, but for ease of description and simplicity, Figure 5 Supplementary constituent elements are omitted.

[0058] refer to Figure 5 , the region in which the macro region 310 and the memory region 320 are arranged may include an element region. The macro block may be arranged in the macro region 310, and the memory block may be arranged in the memory region 320. Figure 5 , other regions of the semiconductor integrated circuit 300 other than the element region may include a logic circuit region. In other words, in some embodiments, the logic region may be defined as any region of the semiconductor integrated circuit 300 other than the element region. In the logic circuit region, a first switch region 331 and a second switch region 332 may be arranged. In the logic circuit region, a plurality of switches capable of controlling power applied to the macro region 310 and the memory region 320 may be arranged.

[0059] refer to Figure 5 , the semiconductor integrated circuit 300 may be provided in a rectangular shape. According to an embodiment, Figure 5 The block diagram may be an upper surface diagram observed in the Z-axis direction. The semiconductor integrated circuit 300 may include a first edge region edge_1, a second edge region edge_2, a third edge region edge_3, and a fourth edge region edge_4 corresponding to each of the first vertex P1, the second vertex P2, the third vertex P3, and the fourth vertex P4. According to an embodiment, the region corresponding to the first vertex P1 may be the first edge region edge_1, the region corresponding to the second vertex P2 may be the second edge region edge_2, the region corresponding to the third vertex P3 may be the third edge region edge_3, and the region corresponding to the fourth vertex P4 may be the fourth edge region edge_4.

[0060] According to an embodiment, the first edge region edge_1 may mean an area adjacent to a portion corresponding to the first vertex P1 of the semiconductor integrated circuit 300. The second edge region edge_2 may mean an area adjacent to a portion corresponding to the second vertex P2 of the semiconductor integrated circuit 300. The third edge region edge_3 may mean an area adjacent to a portion corresponding to the third vertex P3 of the semiconductor integrated circuit 300. The fourth edge region edge_4 may mean an area adjacent to a portion corresponding to the fourth vertex P4 of the semiconductor integrated circuit 300. According to an embodiment, an area adjacent to a portion corresponding to the nth vertex may mean an area in the semiconductor integrated circuit 300 located within a specific distance from the nth vertex as a reference. According to an embodiment, the specific distance may mean a distance corresponding to about 1 / 10 of the edge length of the semiconductor integrated circuit 300. In other words, for example, the first edge region edge_1 may be an area formed by a first length from the first vertex P1 in the X direction and a second length from the first vertex P1 in the Y direction, and each of the first length and the second length may correspond to a specific distance, for example, 1 / 10 of the edge length of the semiconductor integrated circuit 300. Similarly, the nth edge region edge_n may be a region formed by a first length from the nth vertex in the X direction and a second length from the nth vertex in the Y direction, and each of the first length and the second length may correspond to a specific distance. However, the specific distance is not limited thereto, and in some embodiments, the specific distance may be determined differently according to the size of the macroblock and the memory block, the number of switches, etc. According to an embodiment, the area of ​​each of the first edge region edge_1, the second edge region edge_2, the third edge region edge_3, and the fourth edge region edge_4 may be the same.

[0061] According to an embodiment, the semiconductor integrated circuit 300 may include a central area. In an embodiment, the central area may mean an area in the semiconductor integrated circuit 300 having a center located equidistantly from each of the first vertex P1 to the fourth vertex P4 of the semiconductor integrated circuit 300. In an embodiment, the central area may mean an area in the semiconductor integrated circuit 300, which is located within a certain distance from the right center of the semiconductor integrated circuit 300 as a reference. According to an embodiment, the specific distance may be about 1 / 2 of the edge length of the semiconductor integrated circuit 300. However, the area is not limited thereto and may be determined differently according to the size of the macroblock and the memory block, the number of switches, etc. In an embodiment, the central area may have a first length in the X direction and a second length in the Y direction, wherein the first length and the second length are each about 1 / 10 of the edge length of the semiconductor integrated circuit 300. In other words, in some embodiments, the area of ​​the central area may be approximately the same as the area of ​​one of the edge areas. According to an embodiment, the area size of the central area may be the same as the area size of each of the first edge area edge_1, the second edge area edge_2, the third edge area edge_3, and the fourth edge area edge_4.

[0062] According to various embodiments, the first switch region 331 may be arranged in a logic circuit region other than the first edge region edge_1, the second edge region edge_2, the third edge region edge_3, and the fourth edge region edge_4. According to an embodiment, the first switch region 331 may be arranged to be closer to the central region within a range that does not interfere with the component region. In other words, as long as the first switch region 331 does not interfere with the component region, the first switch region 331 may be arranged to be closer to the central region. According to an embodiment, the first switch region 331 may be arranged close to the central region of the semiconductor integrated circuit 300 so that power is evenly distributed in the central region portion of the semiconductor integrated circuit 300, and therefore, the surge current may be reduced compared to the case of the prior art.

[0063] Figure 6 is a schematic diagram showing the configuration of a semiconductor integrated circuit 400 according to the embodiment.

[0064] refer to Figure 6 , the semiconductor integrated circuit 400 may include a plurality of blocks 411 to 416 and 421 to 424, a first switching region 431, and second switching regions 432a and 432b. Figure 6 , the second switch regions 432a and 432b may be provided in two regions. According to an embodiment, the first switch region 431 and the second switch regions 432a and 432b may also be arranged separately from each other. Figure 6As shown, the first switching region 431 may be disposed adjacent to a central region of the semiconductor integrated circuit 400 .

[0065] Figure 7 is a schematic diagram showing the configuration of a semiconductor integrated circuit 500 according to the embodiment.

[0066] refer to Figure 7 , the semiconductor integrated circuit 500 may include a plurality of blocks 511 to 516 and 521 to 523, first switch regions 531a and 531b, and second switch regions 532a and 532b. The first switch regions 531a and 531b may be provided in two regions, and the second switch regions 532a and 532b may also be provided in two regions. According to an embodiment, the first switch regions 531a and 531b and the second switch regions 532a and 532b may be arranged separately from each other.

[0067] When the blocks are arranged in the central region of the semiconductor integrated circuit 500, in some cases, the layout of the blocks may exclude the first switch regions 531a and 531b from being arranged in the central region of the semiconductor integrated circuit 500. In this case, the first switch regions 531a and 531b may be configured to be arranged in a region adjacent to the central region. In other words, according to an embodiment, the first switch regions 531a and 531b may be arranged in a region closest to the central region among the regions available in the logic circuit region.

[0068] Fig. 8A , Figure 8B and Figure 8C 2 are schematic diagrams showing configurations of semiconductor integrated circuits 600 , 700 , and 800 according to a comparative example and an embodiment, respectively.

[0069] Fig. 8A and Figure 8B are semiconductor integrated circuits 600 and 700 according to comparative examples in which the first switching region is arranged, respectively, and Figure 8C 8 is a semiconductor integrated circuit 800 in which a first switching region is arranged according to various embodiments disclosed herein.

[0070] refer to Fig. 8A , the semiconductor integrated circuit 600 may include a macro region 610. Fig. 8A As shown, when the first switch region is arranged in the semiconductor integrated circuit 600 according to the comparative example, the first switch region may be sequentially arranged in a region extending from a coordinate (0, 0) intersecting the X-axis direction and the Y-axis direction to form a (0, 0) region. The (0, 0) region may refer to a region located within a specific distance from the (0, 0) coordinate as a reference and extending in the X-axis and Y-axis directions.

[0071] refer to Figure 8B , the semiconductor integrated circuit 700 may include a macro region 710 that is smaller than the macro region 610 of the semiconductor integrated circuit 600. In order to compensate Fig. 8A The weaknesses in Figure 8B The dotted line frame in FIG. 7 shows a semiconductor integrated circuit 700, which is a case where the number of first switches included in the first switch region is increased. Figure 8B The dashed box in the figure shows the Fig. 8A In this case, there may be a problem that the number of first switches is too large.

[0072] In other words, according to a comparative example, without considering the arrangement position of the first switch area, the first switch area can be arranged from the (0, 0) area on the chip level or the block level in the Y-axis direction in a floor plan operation so that the (0, 0) area increases in the Y-axis direction, and the second switch can be arranged in other areas. The floor plan operation may be an operation of arranging macro blocks and memory blocks in an application specific integrated circuit (ASIC) design.

[0073] refer to Figure 8C In contrast, the semiconductor integrated circuit 800 according to various embodiments may include a macro region 810 and a first switch region, the macro region 810 being similar in size to the macro region 710 in the semiconductor integrated circuit 700, the first switch region being arranged adjacent to the central region of the first layout (eg, Figure 8C In other words, according to various embodiments, by arranging the first switch region in the logic circuit region where the macro blocks and the memory blocks are not arranged, the surge peak current can be reduced without repeatedly performing simulation in the layout planning operation.

[0074] Fig. 9 Graphs for describing current changes in a semiconductor integrated circuit according to a comparative example and various embodiments are shown.

[0075] Fig. 9 The first line of the graph in case 1 can be described according to Fig. 8A The current variation of the semiconductor integrated circuit 600, Fig. 9 The second line of the graph in case 2 can be described according to Figure 8B The current of the semiconductor integrated circuit 700 changes, and Fig. 9 The third line of the graph in case 3 can be described according to Figure 8C Current changes in an embodiment of a semiconductor integrated circuit 800.

[0076] Fig. 9The horizontal axis of the graph in may represent time, and the vertical axis thereof may represent current intensity. Fig. 9 , the current intensity of the third line case 3 is less than the current intensity of the first line case 1 and the second line case 2.

[0077] Fig.10 and Fig.11 1000 and 2000 are block diagrams of design systems 1000 and 2000 of semiconductor integrated circuits according to embodiments, respectively.

[0078] refer to Fig.10 , the design system 1000 may include a processor 1100 , a storage device 1200 , a design module 1300 , and an analyzer 1400 .

[0079] Hereinafter, the term "module" may be referred to as software, hardware, such as a field programmable gate array (FPGA) or ASIC, or a combination of software and hardware. A "module" may be stored as software in an addressable storage medium, and may also be configured to be executed by one or more processors. In other words, one or more processors may access the addressable storage medium and execute the "module" to implement the functionality of the "module". For example, a "module" may include components such as software components, object-oriented software components, class components, and task components, processes, functions, procedures, subroutines, program code segments, drivers, firmware, microcodes, circuits, data, databases, data structures, tables, arrays, and variables. A "module" may also be divided into multiple "modules" that perform detailed functions.

[0080] The processor 1100 may execute the design module 1300 and / or the analyzer 1400 to perform operations. For example, the processor 1100 may include a microprocessor, an application processor (AP), a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), etc. Fig.10 Only one processor 1100 is shown in FIG. 1 , but the embodiment is not limited thereto, and in some embodiments, the design system 1000 may further include multiple processors. Although not shown in detail, in some embodiments, the processor 1100 may further include a cache memory for improving operation capability.

[0081] The storage device 1200 may include a standard cell library (SCL) 1210 and a design rule (DR) 1230. The SCL 1210 and the DR 1230 may be provided from the storage device 1200 to the design module 1300 and / or the analyzer 1400. For example, the SCL 1210 may include information about standard cells, and the DR 1230 may be used to verify the result of placement and routing.

[0082] As a computer-readable storage device, the storage device 1200 may include data and / or storage media that store computer-executable commands and / or codes. For example, the computer-readable storage medium may include volatile memory (such as static random access memory (RAM) (SRAM), dynamic RAM (DRAM)) and non-volatile memory (such as flash memory, magnetic RAM (MRAM), phase change RAM (PRAM) and resistive RAM (RRAM)). The computer-readable storage medium may be inserted into the computer, or integrated into the computer, or combined with the computer through a communication medium such as a network and / or a wireless link.

[0083] The design module 1300 may include a placer 1310 and a router 1320 .

[0084] When executed by the processor 1100, the placer 1310 may place a plurality of blocks and a plurality of standard cells based on input data DIN and SCL 1210 defining the semiconductor integrated circuit. When executed by the processor 1100, the router 1320 may perform signal routing provided by the placer 1310 for placement.

[0085] The analyzer 1400 may analyze and verify the placement and routing results when executed by the processor 1100. When routing has not been successfully completed as a result of the analysis, the layout 1310 may modify the existing layout and provide the modified layout to the router 1320, and the router 1320 may again perform signal routing for the modified layout. When routing has been successfully completed as a result of the analysis, the router 1320 may generate output data DOUT defining the semiconductor integrated circuit.

[0086] When executed by the processor 1100, the design module 1300 may perform the above reference Figure 1 The layout design method of the semiconductor integrated circuit of various embodiments described above. For example, the layout unit 1310 and the routing unit 1320 included in the design module 1300 may perform when executed by the processor 1100. Figure 1 Operations S1000, S2000, S3000 and S4000 in the process.

[0087] According to an embodiment, the placer 1310 and the router 1320 may also be implemented as one integrated module, such as the design module 1300. According to an embodiment, the placer 1310 and the router 1320 may be implemented as separate individual modules.

[0088] The design module 1300 and / or the analyzer 1400 may be implemented in a software type, but the embodiment is not limited thereto. In some embodiments, when both the design module 1300 and the analyzer 1400 are implemented in a software type, the design module 1300 and the analyzer 1400 may be stored in the storage device 1200 as a code type. In some embodiments, the design module and the analyzer 1400 may also be stored in another storage device (not shown) separate from the storage device 1200 as a code type.

[0089] refer to Fig.11 , the design system 2000 may include a processor 2100, an input / output (I / O) device 2200, a network interface 2300, a random access memory (RAM) 2400, a read-only memory (ROM) 2500, and a storage device 2600. The processor 2100, the I / O device 2200, the network interface 2300, the RAM 2400, the ROM 2500, and the storage device 2600 may be connected to a bus 2700 and may communicate with each other via the bus 2700. Fig.11 Shows Fig.10 The design module 1300 and the analyzer 1400 in the embodiment are both implemented in software type. Figure 1 and methods of designing integrated circuits (e.g., Figure 1 At least some of the operations in the method) can be performed by the design system 2000.

[0090] In some embodiments, the design system 2000 may include a computing system. In some embodiments, the design system 2000 may include a fixed computing system, such as a desktop computer, a workstation, and a server. In some embodiments, the design system 2000 may include a portable computing system, such as a laptop computer.

[0091] The processor 2100 can be used with Fig.10 1100 in the embodiment of the present invention is substantially the same. For example, the processor 2100 may include a core capable of executing an instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extended IA-32, x86-64, PowerPC, Spark, MIPS, ARM, IA-64, etc.). For example, the processor 2100 may access a memory (i.e., RAM 2400 or ROM 2500) via a bus 2700, and may execute commands stored in the RAM 2400 or ROM 2500. Fig.11 As shown, RAM 2400 can store Fig.10The program PR may include all or part of the program PR corresponding to the design module 1300 and / or the analyzer 1400 in the integrated circuit, and when the program PR is executed by the processor 2100, the processor 2100 may perform operations for designing an integrated circuit.

[0092] In other words, the program PR may include multiple instructions and / or processes that can be executed by the processor 2100, and the multiple instructions and / or processes included in the program PR can control the processor 2100 to perform operations for designing a semiconductor integrated circuit according to various embodiments when executed by the processor 2100.

[0093] The storage device 2600 can be used with Fig.10 The storage device 2600 is substantially the same as the storage device 1200 in the . The storage device 2600 can store the program PR, SCL, and DR, and before the processor 2100 executes the program PR, all or part of the program PR can be loaded from the storage device 2600 to the RAM 2400. The storage device 2600 can store files written in a program language, and can also load all or part of the program PR generated by a compiler or the like to the RAM 2400.

[0094] The storage device 2600 may store data to be processed by the processor 2100 or data processed by the processor 2100. In other words, the processor 2100 may generate new data by processing the data stored in the storage device 2600 according to the program PR, and may store the generated data in the storage device 2600.

[0095] The I / O device 2200 may include input devices such as a keyboard and a pointing device, and may include output devices such as a display device and a printer. For example, a user may trigger the processor 2100 to execute a program PR by using the I / O device 2200, inputting Fig.10 The input data DIN in the Fig.10 Output data DOUT and / or error messages in etc.

[0096] The network interface 2300 may provide access to a network external to the design system 2000. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links. Fig.10 The input data DIN in can also be provided to the design system 2000 via the network interface 2300, and Fig.10 The output data DOUT in can also be provided to another computing system via the network interface 2300.

[0097] Fig.12is a block diagram showing a SoC 3000 according to an embodiment. As a semiconductor device, the SoC 3000 may include a semiconductor integrated circuit according to various embodiments. The SoC 3000 may be implemented in one chip, where complex functional blocks (such as IPs that perform various functions) and active areas, logic units, and power rails arranged according to various embodiments may be included in each functional block of the SoC 3000.

[0098] refer to Fig.12 , the SoC 3000 may include a modem 3200, a display controller 3300, a memory 3400, an external memory controller 3500, a CPU 3600, a transaction unit 3700, a PMIC 3800, and a GPU 3900, and each functional block of the SoC 3000 may communicate with each other via a system bus 3100. According to an embodiment, as Fig.12 As shown, PMIC 3800 may be included in SoC 3000. In some embodiments, PMIC 3800 may be provided external to SoC 3000, similar to the Figure 3 The embodiment shown.

[0099] The CPU 3600, which is capable of controlling all operations of the SoC 3000, may control the operations of other functional blocks (e.g., 3200, 3300, 3400, 3500, 3700, 3800, and 3900). The modem 3200 may demodulate a signal received from outside the SoC 3000, or may modulate a signal generated in the SoC 3000 and transmit the modulated signal to the outside. The external memory controller 3500 may control the operation of transmitting and receiving data to and from an external memory device connected to the SoC 3000. For example, a program and / or data stored in an external memory device may be provided to the CPU 3600 or the GPU 3900 under the control of the external memory controller 3500. The GPU 3900 may execute program instructions related to graphics processing. The GPU 3900 may receive graphic data via the external memory controller 3500, and may transmit the graphic data processed by the GPU 3900 to the outside of the SoC 3000 via the external memory controller 3500. The transaction unit 3700 may monitor the data transaction of each functional block, and the PMIC 3800 may control the power supplied to each functional block under the control of the transaction unit 3700. The display controller 3300 may transmit the data generated inside the SoC 3000 to the display by controlling the display (or display device) outside the SoC 3000.

[0100] The memory 3400 may include nonvolatile memories such as electrically erasable programmable ROM (EEPROM), flash memory, PRAM, RRAM, nano floating gate memory (NFGM), polymer RAM (PoRAM), MRAM, and ferroelectric RAM (FRAM), and volatile memories such as DRAM, SRAM, mobile DRAM, double data rate (DDR) synchronous DRAM (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphic DDR (GDDR) SDRAM, and rambus DRAM (RDRAM).

[0101] Fig.13 is a flow chart of a method of manufacturing an integrated circuit IC according to an embodiment.

[0102] refer to Fig.13 , the cell library D12 may include information about the logic cell. For example, the logic cell may include function information, characteristic information, layout information, etc. In an embodiment, the cell library D12 may include data defining the layout of the logic cell, such as D12_1 and D12_2. The logic cell may include a standard cell. The standard cell may have a structure that complies with a predefined standard.

[0103] In operation S10, a logic synthesis operation of generating netlist data D13 from the RTL data D11 may be performed. For example, a semiconductor design tool may generate netlist data D13 including a bitstream or a netlist by performing logic synthesis from the RTL data D11 written in HDL by referring to the cell library D12. HDL may include VHDL, Verilog, etc. The cell library D12 may include information about the height of the logic cell, the number of pins included in the logic cell, the number of tracks corresponding to the logic cell, etc. In the logic synthesis process, the logic cell may be included in the integrated circuit IC by referring to the information about the cell library D12.

[0104] In operation S20, a P&R operation of generating layout data D14 from netlist data D13 may be performed. The P&R operation S20 may include a plurality of operations S21, S22, and S23.

[0105] In operation S21, an operation of arranging a logic cell may be performed. For example, a semiconductor design tool (e.g., a P&R tool) may arrange a plurality of logic cells according to the netlist data D13 by referring to the cell library D12. According to an embodiment, in operation S21, an arrangement position of the first switch region may be set, and the arrangement position of the first switch region may be arranged as described above. Figures 1 to 12 The first switch region is arranged as described. According to an embodiment, an operation of arranging power rails may be performed.

[0106] In operation S22, an operation of generating interconnections may be performed. By performing the interconnection operation, an output pin and an input pin of the logic unit may be electrically connected to each other. The logic unit may include at least one through-hole.

[0107] In operation S23, an operation of generating layout data D14 may be performed. The layout data D14 may include geometric information about cells and interconnections of the cells. The layout data D14 may have the same format as GDSII.

[0108] In operation S30, optical proximity correction (OPC) may be performed on the layout data D74, and a pattern on the mask may be determined. In other words, by correcting distortion phenomena such as refraction due to the characteristics of light according to the layout data D74, a pattern having a desired shape may be formed. In some embodiments, in operation S30, the layout of the integrated circuit may be modified on a limited basis. In this way, the structure of the integrated circuit may be optimized. Operation S30 may be referred to as design polishing.

[0109] In operation S40, an operation of manufacturing a mask may be performed. In order to form the pattern determined in operation S30, at least one mask may be manufactured. The mask may include a photomask.

[0110] In operation S50, an operation of manufacturing an integrated circuit may be performed. For example, the integrated circuit may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S40. Fig.13 As shown, operation S50 may include operations S51 and S52.

[0111] In operation S51, a front-end-of-line (FEOL) process may be performed. The FEOL process may be referred to as an operation of forming various components on a substrate. The various components may include transistors, capacitors, resistors, etc. The FEOL process may include an operation of planarizing a wafer, an operation of cleaning a wafer, an operation of forming a groove, an operation of forming a well, an operation of forming a gate line, an operation of forming a source and a drain, etc.

[0112] In operation S52, a back-end-of-line (BEOL) process may be performed. The BEOL process may be referred to as a process for interconnecting various components. For example, the BEOL process may include operations of silicide gate, source and drain, operations of adding dielectric materials, operations of planarization, operations of forming holes, operations of adding metal layers, operations of forming through holes, operations of forming passivation layers, etc.

[0113] After operation S52 is completed, the packaged integrated circuit IC may be used as a component for various applications.

[0114] Fig.14 is a detailed flowchart illustrating a layout design operation according to an embodiment.

[0115] The method of designing the layout of the schematic circuit may include a method of manually and directly arranging / designing by a designer or a method of designing by using electronic design automation (hereinafter referred to as EDA). Hereinafter, only the layout design operation of the semiconductor device using EDA is described.

[0116] refer to Fig.14 , the layout design operation may include a layout planning operation S210, a power planning operation S220, a layout operation S230, a clock tree synthesis (CTS) operation S240, and a routing operation S250. According to an embodiment, Fig.14 The operations in can be included in Fig.13 In operation S20.

[0117] The layout planning operation S210 may include cutting and moving the schematic circuit of the logic design and generating a physical design, that is, a layout pattern of the memory or functional blocks for substantial manufacturing. Figures 1 to 12 The described embodiment may include an operation of arranging the first switch region in the floorplanning operation S210 .

[0118] The power planning operation S220 may include generating a layout pattern of wires that connect the arranged functional blocks to a local power source (e.g., a driving voltage) or a ground. For example, a layout pattern of wires that connect a power source or a ground to the arranged functional blocks may be generated so that power is uniformly supplied to the entire chip in a mesh form.

[0119] The layout operation S230 may include generating an arrangement pattern of elements constituting the functional block.

[0120] The CTS operation S240 may include an operation of generating an arrangement pattern of a signal line of a center clock related to a response time that determines the performance of a semiconductor device.

[0121] The wiring operation S250 may include an operation of generating a layout pattern of a general signal line. The general signal line may be a signal line that transmits a general control signal, an input signal, or an output signal, which is not a pre-wired line.

[0122] Although various embodiments have been particularly shown and described with reference to the accompanying drawings, it should be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A layout design method, comprising: receiving input data defining the semiconductor integrated circuit; performing a placement operation and a routing operation based on the input data to obtain a first layout of the semiconductor integrated circuit including a plurality of blocks; providing, on the first layout, a first switch region in which a plurality of first switches are to be arranged; as well as The plurality of first switches are arranged in the first switch region, and the plurality of second switches are arranged in a second switch region different from the first switch region to obtain a second layout of the semiconductor integrated circuit.

2. The layout design method according to claim 1, in, The first switching region is configured to apply power to portions of the plurality of blocks, and The second switch region is configured to apply power to the remaining blocks of the plurality of blocks.

3. The layout design method according to claim 2, in, a first switch among the plurality of first switches included in the first switching region is configured to receive a first signal and be turned on based on the first signal, and The second switches among the plurality of second switches included in the second switch region are configured to receive a second signal and be turned on based on the second signal.

4. The layout design method according to claim 3, wherein: Setting the first switch area includes: The first switch area is set as a logic circuit area in which the plurality of blocks are not arranged.

5. The layout design method according to claim 3, wherein: Setting the first switch area includes: An area close to the central area of ​​the first layout is set.

6. The layout design method according to claim 3, wherein: Setting the first switch area includes: An area other than the first edge area, the second edge area, the third edge area, and the fourth edge area of ​​the first layout is set.

7. The layout design method according to claim 6, in, The first edge region, the second edge region, the third edge region, and the fourth edge region correspond to a first vertex, a second vertex, a third vertex, and a fourth vertex of the first layout, respectively.

8. The layout design method according to claim 3, wherein: Setting the first switch area includes: A plurality of first switch areas are provided.

9. The layout design method according to claim 1, wherein: Performing the placement operation and the routing operation based on the input data to obtain the first layout includes: performing a floorplanning operation on the plurality of blocks; Perform power planning operations on multiple power conductors; performing a layout operation on the components included in the plurality of blocks; performing a clock tree synthesis (CTS) operation on a clock signal provided to the element; and The wiring operation is performed on the element signal supplied to the element.

10. The layout design method according to claim 1, wherein: The semiconductor integrated circuit is a system on chip SoC.

11. A semiconductor integrated circuit comprising: A power management integrated circuit PMIC configured to generate power; and A system on chip SoC configured to operate according to the power from the PMIC, Wherein, the SoC comprises: a component area in which macro blocks and memory blocks are arranged; and a logic circuit area in which a plurality of switches are arranged, the plurality of switches being capable of controlling power applied to the macro block and the memory block, Wherein, the logic circuit area includes: a first switch region in which a plurality of first switches are arranged for reducing a surge current applied to the element region; and a second switch region in which a plurality of second switches are arranged, the plurality of second switches controlling all power applied to the element region, and The first switch region is arranged in a region of the SoC except a first edge region, a second edge region, a third edge region, and a fourth edge region of the SoC.

12. The semiconductor integrated circuit according to claim 11, wherein: The first switching region is arranged adjacent to a central region of the SoC.

13. The semiconductor integrated circuit according to claim 11, wherein: The first switching region includes a plurality of first switching regions.

14. The semiconductor integrated circuit according to claim 11, wherein: The number of the plurality of first switches included in the first switch region is smaller than the number of the plurality of second switches included in the second switch region.

15. The semiconductor integrated circuit according to claim 11, in, The first edge region, the second edge region, the third edge region, and the fourth edge region correspond to a first vertex, a second vertex, a third vertex, and a fourth vertex of the SoC, respectively.

16. A semiconductor integrated circuit comprising: A power management integrated circuit PMIC configured to generate power; and A system on chip SoC configured to operate according to the power from the PMIC, Wherein, the SoC comprises: a first switch region including a plurality of first switches that receive a first signal from the PMIC and are turned on based on the first signal; and a second switch region including a plurality of second switches, the plurality of second switches receiving a second signal from the PMIC and being turned on based on the second signal; wherein the first switch area and the second switch area are arranged in an area of ​​the SoC that does not interfere with macro blocks and memory blocks on the SoC, and The first switch region is arranged in a region of the SoC except a first edge region, a second edge region, a third edge region, and a fourth edge region of the SoC.

17. The semiconductor integrated circuit according to claim 16, wherein: The first switching region is arranged adjacent to a central region of the SoC.

18. The semiconductor integrated circuit according to claim 16, wherein: The first switching region is provided as a plurality of first switching regions.

19. The semiconductor integrated circuit according to claim 16, wherein: The number of first switches included in the first switch region is smaller than the number of second switches included in the second switch region.

20. The semiconductor integrated circuit according to claim 16, in, The first edge region, the second edge region, the third edge region, and the fourth edge region are regions corresponding to a first vertex, a second vertex, a third vertex, and a fourth vertex of the SoC, respectively.

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