Circuit layout detection method, device, equipment and medium

Abstract

The invention provides a circuit layout detection method and device, equipment and a medium, the method is applied to the field of integrated circuits, and the method comprises the following steps: receiving a to-be-detected first circuit layout, and generating a first detection report according to the first circuit layout and a preset design rule file; under the condition that the first detection report comprises first violation information in the violation information, modifying the first circuit layout according to the first detection report to obtain a second circuit layout; comparing the first circuit layout with the second circuit layout, and determining a target area of the second circuit layout; and detecting the target area in the second circuit layout according to the design rule file and the target area to generate a second detection report, and determining that the second circuit layout passes the detection under the condition that the second detection report meets a preset condition. According to the invention, the detection time of the circuit layout can be saved, and the detection efficiency of the circuit layout is improved.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and specifically relates to a circuit layout detection method, device, equipment and medium. Background Art

[0002] As the integration scale of integrated circuits continues to increase, the design and production requirements for physical circuit layouts are also constantly increasing. Among them, design rule checking (DRC) of circuit layouts is an important step in the design and production process of integrated circuits.

[0003] In the related technology, the design rules are provided by the integrated circuit foundry, and the integrated circuit designer uses the DRC tool to detect and compare the circuit layout. The DRC tool enumerates the error violation information in the circuit layout that violates the design rules. The integrated circuit designer then modifies the circuit layout based on the enumeration results, so that the circuit layout meets the requirements of the design rules and can be sent to the integrated circuit foundry for production and processing.

[0004] However, in the process of correcting the circuit layout, the entire circuit layout will be DRCed again to ensure that different violation information is processed, but it takes a long time to DRC the entire circuit layout. DRCing the entire circuit layout will seriously slow down the progress of the integrated circuit design and production process, causing time delays. Summary of the invention

[0005] The present application aims to provide a circuit layout detection method, device, equipment and medium, which at least solves the problem of time-consuming design rule detection of the entire circuit layout in the related art.

[0006] In a first aspect, an embodiment of the present application discloses a circuit layout detection method, the method comprising:

[0007] Receiving a first circuit layout to be tested, and generating a first test report according to the first circuit layout and a preset design rule file; the first test report includes test results generated for all regions in the first circuit layout according to the design rule file;

[0008] In the case where the first detection report includes first violation information in the violation information, modifying the first circuit layout according to the first detection report to obtain a second circuit layout; the violation information includes a detection result that does not conform to the design rule file, the violation information includes first violation information and second violation information, the first violation information includes violation information that must be repaired, and the second violation information includes the violation information excluding the first violation information;

[0009] Comparing the first circuit layout with the second circuit layout, determining a target area of ​​the second circuit layout; the target area includes an area where the second circuit layout has a different graphic shape relative to the first circuit layout;

[0010] According to the design rule file and the target area, the target area in the second circuit layout is detected to generate a second detection report, and if the second detection report meets a preset condition, it is determined that the second circuit layout has passed the detection.

[0011] In a second aspect, an embodiment of the present application discloses a circuit layout detection device, the detection device comprising:

[0012] A first detection module: used for receiving a first circuit layout to be detected, and generating a first detection report according to the first circuit layout and a preset design rule file; the first detection report includes detection results generated for all areas in the first circuit layout according to the design rule file;

[0013] A modification module: used for modifying the first circuit layout according to the first detection report to obtain a second circuit layout when the first detection report includes first violation information in the violation information; the violation information includes first violation information and second violation information, the first violation information includes violation information that must be repaired, and the second violation information includes the violation information excluding the first violation information;

[0014] Comparison module: used for comparing the first circuit layout and the second circuit layout to determine a target area of ​​the second circuit layout; the target area includes an area where the second circuit layout has a different graphic shape relative to the first circuit layout;

[0015] The second detection module is used to detect the target area in the second circuit layout according to the design rule file and the target area, generate a second detection report, and determine that the second circuit layout has passed the detection if the second detection report meets preset conditions.

[0016] In a third aspect, an embodiment of the present application further discloses an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0017] In a fourth aspect, an embodiment of the present application further discloses a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0018] In summary, in this embodiment, a first circuit layout to be tested is received, and a first test report is generated based on the first circuit layout and a preset design rule file; in a case where the first test report includes first violation information in the violation information, the first circuit layout is modified according to the first test report to obtain a second circuit layout; the first circuit layout and the second circuit layout are compared to determine a target area of ​​the second circuit layout; according to the design rule file and the target area, the target area in the second circuit layout is tested to generate a second test report, and in a case where the second test report meets preset conditions, it is determined that the second circuit layout has passed the test. Through the design rule file, violation information in the first circuit layout can be obtained, and the target area can be determined based on the violation information. The target area includes the area where the second circuit layout has a graphic shape difference relative to the first layout. When the second circuit layout is detected, by limiting the detected area to the target area, the detection scope and data volume of the second circuit layout, that is, the modified circuit layout in the embodiment of the present application are greatly reduced compared with the entire circuit layout in the related art, saving the detection time of the modified circuit layout, thereby shortening the time of the entire detection process and improving the detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the attached picture:

[0020] Figure 1 It is a flow chart of the steps of a circuit layout detection method provided in an embodiment of the present application;

[0021] Figure 2 is a flowchart of another circuit layout detection method provided by an embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of a circuit layout of an embodiment of the present application;

[0023] Figure 4 It is another schematic diagram of a chip board diagram of an embodiment of the present application;

[0024] Figure 5 It is another circuit layout schematic diagram of an embodiment of the present application;

[0025] Figure 6 yes Figure 4 A partial schematic diagram of the circuit layout shown;

[0026] Figure 7 yes Figure 5 A partial schematic diagram of the circuit layout shown;

[0027] Figure 8 yes Figure 7 relatively Figure 6Schematic diagram of the area where there are differences in graphic shapes;

[0028] Fig. 9 is a schematic diagram of the target area in an embodiment of the present application;

[0029] Fig.10 It is a flowchart of the steps of another circuit layout detection method provided in an embodiment of the present application;

[0030] Fig.11 is a block diagram of a circuit layout detection device provided in an embodiment of the present application;

[0031] Fig.12 is a block diagram of an electronic device according to an embodiment of the present application;

[0032] Fig.13 It is a block diagram of an electronic device of another embodiment provided by the embodiments of the present application.

[0033] Among them, 10-circuit layout; 20-first violation area; 30-first metal; 40-second metal; 50-area that must be repaired; 60-modified first metal; 70-area with graphic shape differences; 80-target area. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0036] Before describing this application, the application scenario of this application is first explained:

[0037] With the continuous improvement of the integration of integrated circuits, the scale of physical integrated circuits is increasing. As a key link in the physical realization of integrated circuits, layout physical verification plays an important role in eliminating errors, reducing design costs, and reducing reliability risks of integrated circuits. Design rule detection DRC is an important part of layout physical verification.

[0038] DRC mainly relies on the design rule files provided by the IC foundry to test the designed circuit layout. The test content focuses on the layout layer, and tests the relationship between the same layout layer and the adjacent layout layer, including size, spacing, density, and coverage. The purpose of DRC is to ensure that the circuit layout meets the production design rules of the IC foundry. Only the circuit layout that meets the production design rules can be mass-produced by the IC foundry, otherwise reliability and yield issues will arise.

[0039] The general process of DRC includes: inputting the design rule file and the designer's circuit layout data into the DRC tool, performing DRC on the circuit layout data, and the DRC tool outputting the processing results after completing DRC. The designer can view the processing results through the viewer in the DRC tool, and can use the viewer to locate the errors and violations in the circuit layout so as to repair the errors and violations.

[0040] Usually, DRC will conduct a comprehensive comparison of all circuit board diagram data to ensure that all circuit layout areas have been detected, and then output the processing results to form a DRC report. The above process takes a relatively short time in a small-scale circuit layout design, and can be completed in about tens of minutes. Designers can repeatedly modify the circuit layout data and execute DRC until the circuit layout meets expectations; however, as the scale of the circuit layout increases, the level and complexity of the circuit layout continue to increase, and accordingly, the design rules will become more complex, resulting in the time to complete DRC for large-scale circuit layouts. For large-scale circuit layouts, DRC can take tens of hours or even days. When repairing errors and violations according to the DRC report, it is usually necessary to iterate the entire circuit layout with comprehensive DRC to ensure that different violations are repaired. Since each comprehensive DRC run takes a long time, it is very easy to slow down the progress of the integrated circuit design and production process, and for integrated circuit projects with limited time, it is easy to cause time delays.

[0041] In response to the above-mentioned problems, the embodiments of the present application propose a circuit layout detection method, device, equipment and computer storage medium to reduce the amount of data processed by DRC, shorten the DRC time, and improve the efficiency of iterative repair of DRC violations.

[0042] Figure 1This embodiment provides a circuit layout detection method, referring to Figure 1 , the method may include the following steps:

[0043] Step 101, receiving a first circuit layout to be tested, and generating a first test report according to the first circuit layout and a preset design rule file; the first test report includes test results generated for all areas in the first circuit layout by the design rule file.

[0044] First, a comprehensive design rule check is performed on the first circuit layout to be checked through a design rule check tool to obtain a complete design rule check report for the first circuit layout, namely, a first check report; by inputting the first circuit layout and the design rule file into the design rule check tool, the first check report for the first circuit layout can be obtained; the first check report contains the check results of each area in the first circuit layout, and the check results may include violation information, which can be viewed through the design rule check tool; through the first check report, it can be confirmed whether the first circuit layout meets the requirements of the design rule check.

[0045] The first circuit layout may be a preliminary circuit layout designed by relevant technical personnel, that is, a circuit layout that has not yet been tested for design rules, or a circuit layout that has been tested for design rules and modified accordingly.

[0046] Exemplarily, the design rule checking tool may include Assura of Cadence, Hercules of Synopsys, and Calibre of Mentor; the first circuit board diagram may be input into the design rule checking tool in GDSII format.

[0047] Step 102: In a case where the first detection report includes first violation information in the violation information, modify the first circuit layout according to the first detection report to obtain a second circuit layout; the violation information includes a detection result that does not comply with the design rule file, the violation information includes first violation information and second violation information, the first violation information includes violation information that must be repaired, and the second violation information includes the violation information excluding the first violation information.

[0048] The violation information includes the detection results in the detection report that do not comply with the design rule file, that is, the violation information represents the existence of violations in the layout. For example, the violation information may include information such as the type, level, and coordinates of the violation. The violation information may be divided into the first violation information and the second violation information. The first violation information represents the information contained in the violation that must be repaired. For these violations, the function and performance of the integrated circuit will be affected, and the designer needs to modify the corresponding circuit layout in a targeted manner. The second violation information includes the violation information other than the first violation information. The number of violations represented by the second violation information is generally greater than the number of violations represented by the first violation information, but the violations represented by the second violation information are generally less or will not have a predictable impact on the function and performance of the integrated circuit. The first violation information may be divided by the integrated circuit designer from the design rule file and then confirmed by the integrated circuit foundry.

[0049] When performing design rule detection, the first violation information can be used as a basis for whether to modify the circuit layout. In the first detection report, if the first violation information exists, it indicates that the first circuit layout has a violation that must be modified. For this, the first circuit layout needs to be modified specifically to obtain a modified circuit layout, i.e., the second circuit layout.

[0050] Exemplarily, the second circuit layout may be obtained by modifying a circuit layout that has not been subjected to design rule checking, or may be obtained by modifying a circuit layout that has been subjected to design rule checking and then modified.

[0051] Step 103: Compare the first circuit layout and the second circuit layout to determine a target area of ​​the second circuit layout; the target area includes an area where the second circuit layout has a different graphic shape relative to the first circuit layout.

[0052] By comparing the first circuit layout and the second circuit layout, the target area of ​​the second circuit layout can be determined. The target area includes the area of ​​the second circuit layout that is modified relative to the first circuit layout. The modified area can be intuitively represented as an area with a graphic shape difference. The target area is an extension of the area with a graphic shape difference. By determining the target area, the influence range of the area of ​​the second circuit layout that is modified relative to the first circuit layout can be determined. It can be understood that the area with a graphic shape difference is less than the area with a violation.

[0053] By comparing the first circuit layout and the second circuit layout, Figure 1The LVL tool is generally integrated into the DRC tool. Unlike DRC, LVL only compares the shape differences of the graphics layer by layer in the circuit layout. Its operation rules are relatively simple and the operation time is short. In contrast, DRC needs to detect multiple objects such as the line width, spacing, area, length, density, span, coverage, extension, angle, special identification area, voltage difference area, etc. of the graphic metal in the same layer or adjacent layers in the circuit layout. It also needs to perform functional tests such as antenna effect detection and latch effect detection. For integrated circuits with more advanced process technology and higher integration, the more complex the design rules required for DRC and the longer the DRC takes.

[0054] Step 104: detect the target area in the second circuit layout according to the design rule file and the target area, generate a second detection report, and determine that the second circuit layout passes the detection if the second detection report meets preset conditions.

[0055] After the target area is determined, the next design rule check can be performed on the target area. When performing design rule check on the modified circuit layout, only the area with graphic shape differences is checked. Compared with the design rule check on the entire circuit layout in the related art, the scope of the test is reduced, and the amount of data required for the design rule test is reduced, thereby shortening the time spent on the test. After the target area is tested, a second test report for the second circuit layout can be generated through fixed steps, and the second test report can confirm whether the second circuit layout, that is, the modified circuit layout, passes the design rule test.

[0056] In summary, in this embodiment, a first circuit layout to be detected is received, and a first detection report is generated according to the first circuit layout and a preset design rule file; in the case where the first violation information in the violation information is included in the first detection report, the first circuit layout is modified according to the first detection report to obtain a second circuit layout; the first circuit layout and the second circuit layout are compared to determine the target area of ​​the second circuit layout; according to the design rule file and the target area, the target area in the second circuit layout is detected to generate a second detection report, and when the second detection report meets the preset conditions, it is determined that the second circuit layout passes the detection. Through the design rule file, the violation information in the first circuit layout can be obtained, and the target area is determined according to the violation information. The target area includes the area where the second circuit layout has a graphic shape difference relative to the first layout. When the second circuit layout is detected, by limiting the detected area to the target area, the detection range and data volume of the second circuit layout in the embodiment of the present application are greatly reduced compared with the entire circuit layout in the related art, saving the detection time of the modified circuit layout, thereby shortening the time of the entire detection process and improving the detection efficiency.

[0057] Figure 2 Another embodiment of a circuit layout detection method is provided, referring to Figure 2 , the method may include the following steps:

[0058] Step 201, receiving a first circuit layout to be tested, and generating a first test report according to the first circuit layout and a preset design rule file.

[0059] This step has been described in step 101 and will not be repeated here.

[0060] refer to Figure 3 , Figure 3 A circuit layout diagram in this application is given as an example. Figure 3 characterizes a first circuit layout to be tested, Figure 3 The 10 in FIG. 1 is the entire area of ​​the circuit layout.

[0061] Step 202: When the first detection report includes first violation information in the violation information, modify the first circuit layout according to the first detection report to obtain a second circuit layout.

[0062] This step has been described in step 102 and will not be repeated here.

[0063] Optionally, step 202 may include:

[0064] Sub-step 2021: Determine a first violation area of ​​the first circuit layout based on the first violation information in the first detection report; the first violation area includes an area that must be repaired; modify the first violation area of ​​the first circuit layout to obtain the second circuit layout.

[0065] refer to Figure 4 , Figure 4 Another circuit layout diagram in this application is given as an example. Figure 4 Characterizes the Figure 3 The first circuit layout to be tested is a first circuit layout after a complete design rule test is performed, through step 201 and sub-step 2021, according to the first violation information included in the first test report, in Figure 4 The first violation area 20 is confirmed within 10.

[0066] Further references Figure 5 , Figure 5 Another circuit layout diagram in an embodiment of the present application is given. Figure 5 Characterized by Figure 4 The second circuit layout is obtained by modifying the first circuit layout shown, wherein: Figure 5 20 of them are Figure 4 20 of the modified areas.

[0067] Further references Figure 6 , Figure 6 for Figure 4 A partial schematic diagram of the circuit layout shown, Figure 6 yes Figure 4 30 and 40 are respectively the first metal and the second metal in the first violation area 20, and area 50 is the minimum area in the first violation area 20 represented by the first violation information in the first detection report, that is, the area 50 that must be repaired. The area 50 that must be repaired is included in the first violation area 20, and the first violation area 20 can be confirmed based on the area 50 that must be repaired.

[0068] Further references Figure 7 , Figure 7 for Figure 5 A partial schematic diagram of the circuit layout shown, Figure 7 yes Figure 5 FIG. 6 is a schematic diagram showing an enlarged display of the first violation region 20, wherein 60 is the modified first metal in the first violation region 20, 60 is composed of Figure 6 The first metal 30 is modified to obtain.

[0069] When the first detection report includes the first violation information, the first circuit layout needs to be modified to obtain the second circuit layout; the first violation area of ​​the first circuit layout can be determined by the first violation information, and the designer modifies the first violation area to obtain the second circuit layout, that is, the modified circuit layout.

[0070] Optionally, after step 201, the following steps may also be included:

[0071] Step 212: If the first violation information is not included in the first test report, confirm that the first circuit layout has passed the test.

[0072] In order to save the time consumption of design rule detection to the greatest extent, when there is no first violation information in the first detection report, it can be confirmed that the first circuit layout meets the design rule requirements; because the first violation information represents the violation that must be modified, when the first detection report represents that there is no violation that must be modified in the first circuit layout, it can be confirmed that the first circuit layout has passed the detection.

[0073] Step 203: Compare the graphic shapes of the first circuit layout and the graphic shapes of the second circuit layout one by one, select the area with the graphic shape difference, and determine the target area based on the area with the graphic shape difference.

[0074] refer to Figure 8 , Figure 8 for Figure 7 relatively Figure 6 Schematic diagram of the area where there are differences in graphic shapes, it can be understood that Figure 8 Area 70 in Figure 7 The second circuit layout is relative to Figure 6 There are regions with different graphic shapes in the first circuit layout.

[0075] After obtaining the second circuit layout, the graphic shapes of the first circuit layout and the second circuit layout can be compared one by one. It can be understood that the first circuit layout and the second circuit layout are two different versions of the same circuit layout. Therefore, the first circuit layout and the second circuit layout can be divided into multiple one-to-one corresponding sub-areas in the same way, and the graphic shapes of each pair of corresponding sub-areas are compared respectively to obtain the areas with graphic shape differences in each pair of sub-areas. Finally, the target area is determined based on the areas with graphic shape differences in these sub-areas.

[0076] It should be noted that in the embodiment of the present application, the area with a difference in graphic shape represents the modified area, which is the area divided on the second circuit layout, while the first violation area represents the area that needs to be modified, which is the area divided on the first circuit layout; the area with a difference in graphic shape can be obtained after modification based on the first violation area, but the first violation area can completely overlap with the area with a difference in graphic shape, and can also include the area with a difference in graphic shape.

[0077] Optionally, in step 203, determining the target area according to the area with the graphic shape difference may include:

[0078] Sub-step 2031: Obtain a first vertex coordinate set of the region where there is a graphic shape difference.

[0079] A coordinate system can be established in the circuit layout, and the position and range of the area in the circuit layout can be represented by a set of vertex coordinates of the area. Therefore, the position and range of the area with graphic shape differences in the second circuit layout can be represented by a first set of vertex coordinates. Furthermore, the target area in the second circuit layout can be determined by the first set of vertex coordinates.

[0080] Exemplarily, after a coordinate system is established in the circuit layout, the position and range of the region in the circuit layout can be represented by matching vectors with coordinate points in the region.

[0081] Sub-step 2032: Obtain a second vertex coordinate set according to a preset magnification rule and the first vertex coordinate set.

[0082] In order to ensure that the design rule detection can cover the area with graphic shape differences and that the design rule detection for the second circuit layout is not missed, the area with graphic shape differences can be enlarged to a target area, and then the design rule detection is performed on the target area. After the area with graphic shape differences is characterized by the first vertex coordinate set, the first vertex coordinate set can be converted into a second fixed coordinate set by a preset enlargement rule.

[0083] Sub-step 2033: Selecting the area enclosed by the second vertex coordinate set as the target area.

[0084] By confirming the area enclosed by the second vertex coordinate set as the target area, the target area can completely cover the area with graphic shape differences, thereby ensuring that the design rule detection of the second circuit layout is not missed.

[0085] Optionally, sub-step 2031 may include:

[0086] Sub-step 20321: According to a preset magnification rule, map the multiple first vertex coordinates in the first vertex coordinate set one by one to multiple second vertex coordinates.

[0087] Specifically, the first vertex coordinates in the first vertex coordinate set may be mapped one by one to the second vertex coordinates according to a preset magnification rule; the preset magnification rule may include equal-proportion magnification and specific-spacing extension magnification.

[0088] Sub-step 20322: Generate the second vertex coordinate set from multiple second vertex coordinates.

[0089] After obtaining the plurality of second vertex coordinates, a second vertex coordinate set may be generated, that is, a vertex coordinate set that determines the target area.

[0090] refer to Fig. 9 , Fig. 9 70 is a schematic diagram of the target area in an embodiment of the present application, and is an area with a graphic shape difference, whose first vertex coordinate set is {M1, M2, M3, M4}; exemplarily, through a specific spacing Lx, the first vertex coordinate set {M1, M2, M3, M4} is converted into a second vertex coordinate set {N1, N2, N3, N4} of the target area.

[0091] For example, Fig. 9 Set up the XOY plane coordinate system and preset the following first vertex coordinates:

[0092] M1(xM1, yM1), M2(xM2, yM2), M3(xM3, yM3), M4(xM4, yM4);

[0093] Then, the rectangular area corresponding to the graphic shape difference area 70 can be determined, and the minimum and maximum X-axis coordinates and Y-axis coordinates of the first vertex coordinates M1, M2, M3, and M4 are extracted, which are respectively:

[0094] Xmin{xM1, xM2, xM3, xM4};

[0095] Xmax{xM1,xM2,xM3,xM4};

[0096] Ymin{yM1, yM2, yM3, yM4};

[0097] Ymax{yM1, yM2, yM3, yM4}.

[0098] The preset specific spacing is Lx, that is, the spacing extending outward from the region with the graphic shape difference is Lx, and the second vertex coordinates of the target region 80 are respectively:

[0099] N1(Xmin-Lx, Ymax+Lx);

[0100] N2(Xmin-Lx, Ymin-Lx);

[0101] N3(Xmax+Lx, Ymin-Lx);

[0102] N4(Xmax+Lx,Ymax+Lx).

[0103] The target area 80 can be represented by N1, N2, N3, and N4.

[0104] Step 204: Detect the target area in the second circuit layout according to the design rule file and the target area to obtain a target area detection result.

[0105] After determining the target area, the design rule detection can be performed on the target area according to the design rule file to obtain the target area detection result; based on the target area detection result, the relevant technical personnel can confirm whether the violation represented by the first violation information in the target area in the second circuit layout has been sufficiently modified; since the scope of the design rule detection is reduced to the target area, compared with the detection of all areas of the modified circuit layout, i.e., the second circuit layout in the related art, this solution can significantly shorten the time for design rule detection of the modified circuit layout and improve the detection efficiency.

[0106] For example, for Fig. 9 The target area 80 in the embodiment of the present invention is subjected to design rule detection, and a target area detection result of the target area 80 is obtained.

[0107] Step 205: Combine the first detection report and the target area detection result to obtain a second detection report.

[0108] Since the target area detection result only represents the situation where the target area complies with the design rule file, in order to obtain the complete second circuit layout, that is, the situation where the overall area of ​​the modified circuit layout complies with the design rule file, the first detection report can be merged with the target area detection result to obtain a second detection report. It can be understood that the second detection report represents the situation where the entire second circuit layout complies with the design rule file.

[0109] Optionally, step 205 may include:

[0110] Sub-step 2051: Clearing the violation information corresponding to the target area in the first detection report;

[0111] In order to avoid conflicts between the first test report and the target area test results due to overlapping areas, when merging the first test report and the target area test results, first, based on the target area of ​​the second circuit layout, the area corresponding to the target area of ​​the first circuit layout in the first test report is determined, and the range of the area should coincide with the range of the target area; after determining the area corresponding to the target area in the first test report, clear the violation information in the area to avoid conflicts between the violation information in the area and the target area test results.

[0112] Sub-step 2052: if the target area detection result includes the violation information, adding the violation information in the target area detection result into the first detection report, and using the first detection report to which the violation information in the target area detection result is added as the second detection report;

[0113] One way to obtain a second detection report is to add the violation information in the target area detection result into the first detection report when the target area detection result includes violation information, and use the first detection report with the violation information in the target area detection result added as the second detection report; it can be understood that through the above method, duplication or conflict of the target area violation information in the second detection report obtained after the merger is avoided.

[0114] Sub-step 2053: When the target area detection result does not include the violation information, use the first detection report as the second detection report.

[0115] Another way to obtain the second detection report is to use the first detection report with the violation information of the corresponding target area cleared as the second detection report when the target area detection result does not include violation information; it can be understood that through the above method, the duplication of the target area violation information in the second detection report is avoided.

[0116] Step 206 : When the second detection report does not contain the first violation information, the second circuit layout is set as the latest first circuit layout, and the process goes to step 201 .

[0117] When there is no first violation information in the second test report, it can be considered that the second circuit layout has eliminated the violation represented by the first violation information in the first test report relative to the first circuit layout. At this time, it is necessary to confirm the situation in which the second circuit layout introduces new first violation information. Therefore, the second circuit layout is used as the latest first circuit board diagram, and the design rule detection of the complete circuit layout is performed again, that is, the step of receiving the first circuit layout to be tested and generating a first test report according to the first circuit layout and the preset design rule file is entered.

[0118] Optionally, after step 205, the following steps may also be included:

[0119] Step 216: When the second detection report includes the first violation information, set the second detection report as the latest first detection report and proceed to step 202.

[0120] When the second test report includes the first violation information, it can be considered that the second circuit layout, relative to the first circuit layout, does not eliminate the violation represented by the first violation information in the first circuit layout. At this time, it is necessary to continue to modify the first circuit layout according to the violation represented by the first violation information. Therefore, the second test report is used as the latest first test report, and the step of modifying the first circuit layout based on the first test report is re-entered.

[0121] Step 207: If the first violation information is not present in the newly obtained first test report, confirm that the second circuit layout has passed the test.

[0122] If in step 206, there is no first violation information in the newly obtained first detection report, it can be confirmed that the second circuit layout does not introduce new first violation information. At this time, it can be confirmed that the second circuit layout has completely repaired all violations that must be repaired, and the second circuit layout has passed the design rule detection.

[0123] In summary, in this embodiment, a first circuit layout to be detected is received, and a first detection report is generated according to the first circuit layout and a preset design rule file; in the case where the first violation information in the violation information is included in the first detection report, the first circuit layout is modified according to the first detection report to obtain a second circuit layout; the first circuit layout and the second circuit layout are compared to determine the target area of ​​the second circuit layout; according to the design rule file and the target area, the target area in the second circuit layout is detected to generate a second detection report, and when the second detection report meets the preset conditions, it is determined that the second circuit layout passes the detection. Through the design rule file, the violation information in the first circuit layout can be obtained, and the target area is determined according to the violation information. The target area includes the area where the second circuit layout has a graphic shape difference relative to the first layout. When the second circuit layout is detected, by limiting the detected area to the target area, the detection range and data volume of the second circuit layout in the embodiment of the present application are greatly reduced compared with the entire circuit layout in the related art, saving the detection time of the modified circuit layout, thereby shortening the time of the entire detection process and improving the detection efficiency.

[0124] Fig.10Another circuit layout detection method provided in the embodiment of the present application is described by taking the chip layout as an example. It can be understood that the chip layout is an optional implementation of the circuit layout. Figure 3 The method shown does not limit the circuit layout detection method provided in this application. Figure 3 , the method may include the following steps:

[0125] Step A1: define the latest modified chip layout data as the first chip layout data, run a complete DRC, and output the first DRC report;

[0126] Step A1 is equivalent to step 201 in the above text, and the first chip layout data is equivalent to the first circuit layout in step 201; running a complete DRC and outputting a first DRC report is equivalent to generating a first detection report based on the first circuit layout and the preset design rule file, wherein the first DRC report is equivalent to the first detection report in step 201.

[0127] Step A2: Determine whether the first DRC report meets the design requirements;

[0128] Step A3: If the first DRC report meets the design requirements, the design rule check is terminated;

[0129] Step A2 and step A3 are equivalent to step 212 above, wherein the first DRC report meets the design requirements, which is equivalent to the absence of the first violation information in the first test report in step 212; ending the design rule check is equivalent to confirming in step 212 that the first circuit layout has passed the test.

[0130] Step A4: If the first DRC report does not meet the design requirements, the first layout data is modified according to the first DRC report to obtain second chip layout data;

[0131] Step A2 and step A4 are equivalent to step 202 in the above text, wherein the first DRC report does not meet the design requirements, which is equivalent to the first detection report including the first violation information in the violation information in step 202; the second chip layout data is equivalent to the second circuit layout in step 202.

[0132] Step A5: the inspection tool reads the layout data of the first chip and the layout data of the second chip, and compares the difference between the two versions of the layout data to obtain layout change area information;

[0133] Step A5 is equivalent to the step of comparing the graphic shapes of the first circuit layout and the graphic shapes of the second circuit layout one by one in the above step 203, and selecting the area where the graphic shapes are different; wherein obtaining the layout change area information is equivalent to selecting the area where the graphic shapes are different in step 203.

[0134] Step A6: performing DRC only on the modified area and its extended area in the second chip layout data to obtain a second DRC report;

[0135] Step A6 is equivalent to the step of determining the target area according to the area with graphic shape difference in step 203 above and step 204; wherein the modified area is equivalent to the area with graphic shape difference in step 203, its extended area is equivalent to the target area in step 203, and the second DRC report is equivalent to the target area detection result in step 204.

[0136] Step A7: Compare and merge the second DRC report with the first DRC report, eliminate the repaired DRC violation, or add the newly added DRC violation, to obtain a merged first DRC report;

[0137] Step A7 is equivalent to the above step 205, wherein the merged first DRC report is equivalent to the second detection report in step 205, eliminating the repaired DRC violation is equivalent to sub-step 2053, and adding the newly added DRC violation is equivalent to sub-step 2052.

[0138] Step A8: Determine whether the first DRC report after merging meets the design requirements;

[0139] If the first DRC report after merging meets the design requirements, step A1 is executed; if the first DRC report after merging does not meet the design requirements, step A4 is executed.

[0140] In step A8, if the first DRC report after merging meets the design requirements, step A1 is executed, which is equivalent to the above step 206. The first DRC report after merging meets the design requirements, which is equivalent to the fact that there is no first violation information in the second test report in step 206; in step A8, if the first DRC report after merging meets the design requirements, step A4 is executed, which is equivalent to the above step 216. The first DRC report after merging does not meet the design requirements, which is equivalent to the fact that the second test report in step 206 includes the first violation information.

[0141] After entering step A1 through step A8, if the first DRC report output after the complete DRC report meets the design requirements, then all design rule checks can be terminated; this step is not Figure 3However, it can be understood that this step is equivalent to step 207 above, wherein the first DRC report output after the complete DRC report is equivalent to the newly obtained first test report in step 207; ending all design rule checks is equivalent to confirming in step 207 that the second circuit layout has passed the test.

[0142] refer to Fig.11 , which shows a circuit layout detection device 110 provided in an embodiment of the present application. The device 110 is used to implement the circuit layout detection method provided in the present application. The device 110 includes:

[0143] A first detection module 1101 is used to receive a first circuit layout to be detected, and generate a first detection report according to the first circuit layout and a preset design rule file; the first detection report includes detection results generated by the design rule file for all areas in the first circuit layout;

[0144] A modification module 1102 is used for modifying the first circuit layout according to the first detection report to obtain a second circuit layout when the first detection report includes first violation information in the violation information; the violation information includes first violation information and second violation information, the first violation information includes violation information that must be repaired, and the second violation information includes the violation information excluding the first violation information;

[0145] A comparison module 1103 is used to compare the first circuit layout and the second circuit layout to determine a target area of ​​the second circuit layout; the target area includes an area where the second circuit layout has a different graphic shape relative to the first circuit layout;

[0146] The second detection module 1104 is used to detect the target area in the second circuit layout according to the design rule file and the target area, generate a second detection report, and determine that the second circuit layout passes the detection if the second detection report meets preset conditions.

[0147] Optionally, the second detection module 1104 may include:

[0148] a target area detection submodule, configured to detect the target area in the second circuit layout according to the design rule file and the target area, and obtain a target area detection result;

[0149] A merging submodule, used to merge the first detection report and the target area detection result to obtain a second detection report;

[0150] A first detection and analysis submodule, configured to set the second circuit layout as the latest first circuit layout and execute the first detection module when the second detection report does not contain the first violation information;

[0151] The detection pass submodule is used to confirm that the second circuit layout has passed the detection if there is no first violation information in the newly obtained first detection report.

[0152] Optionally, the second detection module 1104 further includes:

[0153] The second detection analysis submodule is used to set the second detection report as the latest first detection report and execute the modification module 1102 when the second detection report includes the first violation information.

[0154] Optionally, the device 110 further includes:

[0155] The detection passing module is used to confirm that the first circuit layout has passed the detection when there is no first violation information in the first detection report.

[0156] Optionally, the comparison module 1103 may include:

[0157] The comparison and analysis submodule is used to compare the graphic shapes of the first circuit layout and the graphic shapes of the second circuit layout one by one, select the area with different graphic shapes, and determine the target area based on the area with different graphic shapes.

[0158] Optionally, the comparative analysis submodule may include:

[0159] A vertex coordinate unit, used for obtaining a first vertex coordinate set of the area where there is a graphic shape difference;

[0160] an enlargement unit, configured to obtain a second vertex coordinate set according to a preset enlargement rule and the first vertex coordinate set;

[0161] The target area unit is used to select the area surrounded by the second vertex coordinate set as the target area.

[0162] Optionally, the amplification unit may include:

[0163] The mapping subunit is used to map the multiple first vertex coordinates in the first vertex coordinate set to multiple second vertex coordinates one by one according to a preset magnification rule.

[0164] The vertex coordinate subunit is used to generate the second vertex coordinate set from a plurality of second vertex coordinates.

[0165] Optionally, the modification module 1102 may include:

[0166] A violation region acquisition submodule, configured to determine a first violation region of the first circuit layout according to first violation information in the first detection report; the first violation region includes a region that must be repaired;

[0167] The violation area modification submodule is used to modify the first violation area of ​​the first circuit layout to obtain the second circuit layout.

[0168] In summary, in this embodiment, the violation information in the first circuit layout can be obtained through the design rule file, and the target area can be determined according to the violation information, and the target area includes the area where the second circuit layout has a graphic shape difference relative to the first layout. When the second circuit layout is detected, by limiting the detected area to the target area, the detection range and data volume of the second circuit layout in the embodiment of the present application are greatly reduced compared with the entire circuit layout in the related art, saving the detection time of the modified circuit layout, thereby shortening the time of the entire detection process and improving the detection efficiency.

[0169] Fig.12 A block diagram of an electronic device according to an embodiment of the present application is provided, referring to Fig.12 , the electronic device 1200 may include one or more of the following components: a processing component 1202 , a memory 1204 , a power component 1206 , a multimedia component 1208 , an audio component 1210 , an input / output (I / O) interface 1212 , a sensor component 1214 , and a communication component 1216 .

[0170] The processing component 1202 generally controls the overall operation of the electronic device 1200, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1202 may include one or more processors 1220 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 1202 may include one or more modules to facilitate the interaction between the processing component 1202 and other components. For example, the processing component 1202 may include a multimedia module to facilitate the interaction between the multimedia component 1208 and the processing component 1202.

[0171] The memory 1204 is used to store various types of data to support the operation of the electronic device 1200. Examples of such data include instructions for any application or method operating on the electronic device 1200, contact data, phone book data, messages, pictures, multimedia, etc. The memory 1204 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0172] The power supply component 1206 provides power to the various components of the electronic device 1200. The power supply component 1206 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 1200.

[0173] The multimedia component 1208 includes an interface that provides an output interface between the electronic device 1200 and the user. In some embodiments, the interface may include a liquid crystal display (LCD) and a touch panel (TP). If the interface includes a touch panel, the interface may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1208 includes a front camera and / or a rear camera. When the electronic device 1200 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0174] The audio component 1210 is used to output and / or input audio signals. For example, the audio component 1210 includes a microphone (MIC), and when the electronic device 1200 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 1204 or sent via the communication component 1216. In some embodiments, the audio component 1210 also includes a speaker for outputting audio signals.

[0175] The input / output I / O interface 1212 provides an interface between the processing component 1202 and the peripheral interface module, which may be a keyboard, a click wheel, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0176] The sensor assembly 1214 includes one or more sensors for providing various aspects of status assessment for the electronic device 1200. For example, the sensor assembly 1214 can detect the open / closed state of the electronic device 1200, the relative positioning of components, such as the display and keypad of the electronic device 1200, and the sensor assembly 1214 can also detect the position change of the electronic device 1200 or a component of the electronic device 1200, the presence or absence of user contact with the electronic device 1200, the orientation or acceleration / deceleration of the electronic device 1200, and the temperature change of the electronic device 1200. The sensor assembly 1214 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 1214 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1214 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0177] The communication component 1216 is used to facilitate wired or wireless communication between the electronic device 1200 and other devices. The electronic device 1200 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 12G), or a combination thereof. In an exemplary embodiment, the communication component 1216 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1216 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0178] In an exemplary embodiment, the electronic device 1200 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to implement a circuit layout detection method provided in an embodiment of the present application.

[0179] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1204 including instructions, and the instructions can be executed by the processor 1220 of the electronic device 1200 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0180] Fig.13 1 is a block diagram of an electronic device 1300 according to another embodiment of the present invention. For example, the electronic device 1300 may be provided as a server. Fig.13 The electronic device 1300 includes a processing component 1322, which further includes one or more processors, and a memory resource represented by a memory 1332 for storing instructions executable by the processing component 1322, such as an application. The application stored in the memory 1332 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1322 is configured to execute instructions to perform a circuit layout detection method provided in an embodiment of the present application.

[0181] The electronic device 1300 may also include a power supply component 1326 configured to perform power management of the electronic device 1300, a wired or wireless network interface 1350 configured to connect the electronic device 1300 to a network, and an input / output (I / O) interface 1358. The electronic device 1300 may operate based on an operating system stored in the memory 1332, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or the like.

[0182] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0183] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A circuit layout detection method, characterized in that: The method comprises: Receiving a first circuit layout to be tested, and generating a first test report according to the first circuit layout and a preset design rule file; the first test report includes test results generated for all regions in the first circuit layout according to the design rule file; In the case where the first detection report includes first violation information in the violation information, modifying the first circuit layout according to the first detection report to obtain a second circuit layout; the violation information includes a detection result that does not conform to the design rule file, the violation information includes first violation information and second violation information, the first violation information includes violation information that must be repaired, and the second violation information includes the violation information excluding the first violation information; Comparing the first circuit layout with the second circuit layout, determining a target area of ​​the second circuit layout; the target area includes an area where the second circuit layout has a different graphic shape relative to the first circuit layout; According to the design rule file and the target area, the target area in the second circuit layout is detected to generate a second detection report, and if the second detection report meets a preset condition, it is determined that the second circuit layout has passed the detection.

2. The method according to claim 1, characterized in that: The step of detecting the target area in the second circuit layout according to the design rule file and the target area, generating a second detection report, and determining that the second circuit layout passes the detection if the second detection report meets a preset condition includes: According to the design rule file and the target area, the target area in the second circuit layout is detected to obtain a target area detection result; Combining the first detection report and the target area detection result to obtain a second detection report; If the second detection report does not contain the first violation information, the second circuit layout is set as the latest first circuit layout, the step of receiving the first circuit layout to be detected is entered, and the step of generating a first detection report according to the first circuit layout and a preset design rule file is performed; When the newly obtained first test report does not contain the first violation information, it is confirmed that the second circuit layout has passed the test.

3. The method according to claim 2, characterized in that After the first detection report and the target area detection result are combined to obtain a second detection report, the method further includes: In the case where the second test report includes the first violation information; the second test report is set as the latest first test report, and the step of modifying the first circuit layout according to the first test report to obtain the second circuit layout is entered.

4. The method according to claim 2, characterized in that: The combining the first detection report and the target area detection result to obtain a second detection report includes: Clear the violation information corresponding to the target area in the first detection report; In the case where the target area detection result includes the violation information, adding the violation information in the target area detection result into the first detection report, and using the first detection report to which the violation information in the target area detection result is added as the second detection report; When the target area detection result does not include the violation information, the first detection report is used as the second detection report.

5. The method according to claim 1, characterized in that After receiving the first circuit layout to be tested and generating a first test report according to the first circuit layout and a preset design rule file, the method further includes: When the first violation information does not exist in the first test report, it is confirmed that the first circuit layout has passed the test.

6. The method according to claim 1, characterized in that The comparing the first circuit layout and the second circuit layout to determine the target area of ​​the second circuit layout includes: The graphic shapes of the first circuit layout and the graphic shapes of the second circuit layout are compared one by one, and the areas with different graphic shapes are selected, and the target area is determined according to the areas with different graphic shapes.

7. The method according to claim 6, characterized in that The determining of the target area of ​​the second circuit layout includes: Obtain a first vertex coordinate set of the area where there is a graphic shape difference; According to a preset magnification rule and the first vertex coordinate set, a second vertex coordinate set is acquired; An area enclosed by the second vertex coordinate set is selected as the target area.

8. The method according to claim 7, characterized in that The step of obtaining a second vertex coordinate set according to a preset magnification rule and the first vertex coordinate set includes: According to a preset magnification rule, mapping a plurality of first vertex coordinates in the first vertex coordinate set to a plurality of second vertex coordinates one by one; The second vertex coordinate set is generated from a plurality of second vertex coordinates.

9. The method according to claim 1, characterized in that: The step of modifying the first circuit layout according to the first detection report to obtain a second circuit layout includes: Determine a first violation area of ​​the first circuit layout according to the first violation information in the first detection report; the first violation area includes an area that must be repaired; The first violation area of ​​the first circuit layout is modified to obtain the second circuit layout.

10. A circuit layout detection device, characterized in that: The detection device comprises: A first detection module: used for receiving a first circuit layout to be detected, and generating a first detection report according to the first circuit layout and a preset design rule file; the first detection report includes detection results generated for all areas in the first circuit layout according to the design rule file; A modification module: used for modifying the first circuit layout according to the first detection report to obtain a second circuit layout when the first detection report includes first violation information in the violation information; the violation information includes first violation information and second violation information, the first violation information includes violation information that must be repaired, and the second violation information includes the violation information excluding the first violation information; Comparison module: used for comparing the first circuit layout and the second circuit layout to determine a target area of ​​the second circuit layout; the target area includes an area where the second circuit layout has a different graphic shape relative to the first circuit layout; The second detection module is used to detect the target area in the second circuit layout according to the design rule file and the target area, generate a second detection report, and determine that the second circuit layout has passed the detection if the second detection report meets preset conditions.

11. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 9 are implemented.

12. A readable storage medium, characterized in that: The readable storage medium stores a program or an instruction, and when the program or the instruction is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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