Josephson junction based charge sensing in quantum systems

Abstract

The invention relates to Josephson junction based charge sensing in quantum systems. The present disclosure provides a method of charge sensing in a quantum system. The method includes providing a bias current through a Josephson junction. The bias current is less than a first value of a critical current of the Josephson junction. The method further includes measuring an output voltage of the Josephson junction. In response to a charge change of one or more charge islands coupled to the Josephson junction, the critical current is reduced to a second value less than the bias current, causing a voltage drop across the Josephson junction.

Description

Technical Field

[0001] Aspects of the present disclosure relate to techniques for localized charge sensing within quantum systems. Background Art

[0002] Obtaining high-speed, accurate measurements of the localized charge state of a quantum system is challenging. Existing solutions for measuring localized charge involve capacitive coupling to a tunnel point (or "measurement island") and operating as a conventional field-effect transistor (FET). The amount of current flowing through the source and drain terminals of the FET will vary as the charge occupancy in the bias on the measurement island changes. However, in order to obtain an accurate measurement of the charge occupancy of the coupled island, multiple samples of the island current response need to be measured. This method is relatively slow, typically requiring on the order of microseconds to perform the integration function, and also requires high-sensitivity amplification of the output, as well as resistors near the measurement island that tend to cause local heating and noise generation. Summary of the invention

[0003] The present disclosure provides a charge sensing method in a quantum system. In one aspect, the method includes providing a bias current through a Josephson junction, the bias current being less than a first value of a critical current of the Josephson junction. The method further includes measuring an output voltage of the Josephson junction. In response to a charge change of one or more charge islands coupled to the Josephson junction, the critical current is reduced to a second value less than the bias current, causing a voltage drop across the Josephson junction.

[0004] In one aspect, in conjunction with any of the example methods above or below, each of the one or more charge islands includes respective one or more quantum dots, one or more material defects, one or more grain boundaries, or one or more micro-surface features.

[0005] In one aspect, in conjunction with any of the example methods above or below, the one or more charge islands include a plurality of charge islands, each charge island coupled to the Josephson junction via a respective capacitor.

[0006] In one aspect, in conjunction with any of the example methods above or below, some or all of the capacitors corresponding to the plurality of charge islands have different capacitance values.

[0007] In one aspect, in combination with any of the example methods above or below, the method further includes updating a critical current of the Josephson junction to a second value in response to a change in charge of the one or more charge islands using a shunt resistor coupled across the Josephson junction.

[0008] In one aspect, in combination with any of the example methods above or below, the Josephson junction is included in a Josephson junction field effect transistor (JJFET), one or more charge islands are capacitively coupled to a gate of the JJFET, and a bias current is provided by a current source coupled to a source or drain of the JJFET.

[0009] In one aspect, in combination with any of the example methods above or below, the Josephson junction is included in a pair of Josephson junctions in series, one or more charge islands are capacitively coupled between the pair of Josephson junctions, and the bias current is provided by a current source coupled to one of the pair of Josephson junctions.

[0010] The present disclosure provides an apparatus. In one aspect, the apparatus includes a Josephson junction field effect transistor (JJFET), one or more charge islands capacitively coupled to a gate of the JJFET, and a current source coupled to one of a source or a drain of the JJFET. The current source will provide a bias current of a first value less than a critical current of the JJFET, and a predefined charge change to one of the plurality of charge islands will reduce the critical current to a second value less than the bias current.

[0011] In one aspect, in conjunction with any example apparatus above or below, each of the one or more charge islands includes respective one or more quantum dots, one or more material defects, one or more grain boundaries, or one or more micro-surface features.

[0012] In one aspect, in conjunction with any of the example apparatus above or below, the one or more charge islands include a plurality of charge islands, each charge island coupled to the gate via a respective capacitor.

[0013] In one aspect, in conjunction with any of the example apparatus above or below, some or all of the capacitors corresponding to the plurality of charge islands have different capacitance values.

[0014] In one aspect, in combination with any of the example apparatus above or below, the apparatus further includes a shunt resistor coupled between the source and drain of the JJFET.

[0015] In one aspect, in combination with any of the example apparatus above or below, the apparatus further includes a measurement circuit coupled to the other of the source or the drain of the JJFET.

[0016] In one aspect, in conjunction with any of the example apparatus above or below, the measurement circuit includes an amplifier circuit to amplify the output voltage of the JJFET.

[0017] The present disclosure provides an apparatus. In one aspect, the apparatus includes a pair of Josephson junctions connected in series, one or more charge islands capacitively coupled to a node between the pair of Josephson junctions, and a current source coupled to a first Josephson junction of the pair of Josephson junctions. The current source provides a bias current of a first value less than an effective critical current of the Josephson junction, and a predefined charge change to one of the plurality of charge islands reduces the effective critical current to a second value less than the bias current.

[0018] In one aspect, in conjunction with any example apparatus above or below, each of the one or more charge islands includes respective one or more quantum dots, one or more material defects, one or more grain boundaries, or one or more micro-surface features.

[0019] In one aspect, in conjunction with any of the example apparatuses above or below, the one or more charge islands include a plurality of charge islands, each charge island coupled between the pair of Josephson junctions via a respective capacitor.

[0020] In one aspect, in conjunction with any of the example apparatus above or below, some or all of the capacitors corresponding to the plurality of charge islands have different capacitance values.

[0021] In one aspect, in combination with any of the example apparatus above or below, the apparatus further includes a shunt resistor coupled across the pair of Josephson junctions.

[0022] In one aspect, in combination with any of the example apparatus above or below, the apparatus further includes a measurement circuit coupled to a second Josephson junction of the pair of Josephson junctions. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] So that the manner in which the above-described features may be appreciated in detail, a more particular description may be had by reference to example aspects, briefly summarized above, some of which are illustrated in the accompanying drawings.

[0024] Figure 1 Depicted is a perspective view of an exemplary Josephson junction according to one or more aspects.

[0025] Figure 2 Depicted is a cross-sectional view of an exemplary Josephson junction field effect transistor (JJFET) according to one or more aspects.

[0026] Figure 3 Described are systems having one or more charge sensors in a quantum scale device or system according to one or more aspects.

[0027] Figure 4 Depicted are exemplary devices having one or more charge islands capacitively coupled to a JJFET according to one or more aspects.

[0028] Figure 5 Depicted are exemplary devices having one or more charge islands capacitively coupled to a node between a pair of series-connected Josephson junctions according to one or more aspects.

[0029] Figure 6 Current-voltage (IV) characteristics of a Josephson junction at different charge states are depicted in accordance with one or more aspects.

[0030] Figure 7 A method of charge sensing in a quantum system according to one or more aspects. DETAILED DESCRIPTION

[0031] In the current disclosure, reference is made to various aspects. However, it should be understood that the current disclosure is not limited to the specifically described aspects. On the contrary, any combination of the following features and elements, whether or not related to different aspects, is considered to implement and practice the teachings provided herein. In addition, when the elements of these aspects are described in the form of "at least one of A and B", it is understood that only element A, only element B, and all aspects including elements A and B are contemplated. In addition, although some aspects may have advantages over other possible solutions and / or prior art, whether a given aspect realizes a specific advantage does not limit the present disclosure. Therefore, the aspects, features, aspects, and advantages disclosed herein are only illustrative and are not considered as elements or limitations of the appended claims unless explicitly cited in the claims. Similarly, reference to "the present invention" should not be interpreted as a summary of any creative subject matter disclosed herein, nor should it be considered as an element or limitation of the appended claims unless explicitly cited in the claims.

[0032] Figure 1 A perspective view of an exemplary Josephson junction (JJ) 100 according to one or more aspects is depicted. The JJ 100 can be used in conjunction with any other aspect described herein. Additionally, in some aspects, the JJ 100 can be incorporated into a charge sensor and integrated into a quantum system.

[0033] JJ 100 includes a first superconductor portion 105 separated from a second superconductor portion 110 by a weak link 115. The first superconductor portion 105 and the second superconductor portion 110 can be formed of any suitable superconducting material. In some aspects, the weak link 115 includes an insulating material, so that JJ 100 is implemented as a superconductor-insulator-superconductor (SIS) junction. In other aspects, the weak link 115 includes a non-superconducting metal material, so that JJ 100 is implemented as a superconductor-non-superconducting metal-superconductor (SNS) junction. In other aspects, the weak link 115 includes a physical contraction that provides a reduced superconductivity region, so that JJ 100 is implemented as a superconductor-contraction-superconductor (ScS) junction.

[0034] The weak link 115 has a suitable size to support quantum tunneling of electrons therethrough. Typically, for a SIS junction, the thickness of the weak link 115 may be between 30 angstroms and 100 angstroms. or smaller, or for SNS junctions, can be on the order of a few microns. Although the components of JJ 100 are shown in a linear arrangement for simplicity, other configurations and geometries of JJ 100 are also contemplated.

[0035] When cooled to cryogenic temperatures, the first superconductor portion 105 and the second superconductor portion 110 are able to conduct electricity without providing any resistance. The flow of supercurrent 125 conducted through the weak link portion 115 by JJ 100 is controlled by quantum tunneling of Cooper pairs 120 (i.e., pairs of electrons with opposite spins bound together at cryogenic temperatures).

[0036] According to various aspects, and as will be discussed in more detail below, the properties of JJ 100 can be dynamically controlled to support fast, single-shot charge sensing by JJ 100. For example, applying different values ​​of an electrostatic potential near JJ 100 changes its quantum tunneling properties, thereby changing the amount of supercurrent 125. The "critical current" of JJ 100 represents the maximum value of supercurrent 125 that can flow through JJ 100. When the current through JJ 100 exceeds the critical current, JJ 100 transitions from its superconducting state to a "normal" conducting state (i.e., resistive losses are generated through JJ 100). As a result, the voltage drop across JJ 100 increases. In certain aspects, the critical current of JJ 100 is modulated using an electrostatic potential (e.g., changing the number of Cooper pairs 120 available for transmission) so that a predefined charge change "sensed" by JJ 100 causes JJ 100 to transition between a superconducting state and a conducting state. The resulting pulses in the output voltage of the JJ 100 may then be measured and / or adjusted to provide a signal indicative of the change in charge.

[0037] Figure 2A cross-sectional view of an exemplary Josephson junction field effect transistor (JJFET) 200 according to one or more aspects is depicted. The JJFET 200 can be used in conjunction with any other aspects described herein. Additionally, in some aspects, the JJFET 200 can be incorporated into a charge sensor and integrated into a quantum system.

[0038] The JJFET 200 includes a source 205 and a drain 210 formed of any suitable superconducting material. The JJFET 200 also includes a gate 215 disposed on an oxide layer 220. In some aspects, the gate 215 is formed of a metal material. The oxide layer 220 is disposed between the source 205 and the drain 210, and the gate 215 is partially disposed between the source 205 and the drain 210 (as shown, the gate 215 extends through the plane of the top surface of the source 205 and the top surface of the drain). The source 205, the drain 210, and the oxide layer 220 are disposed on a channel layer 225 formed of a semiconductor material, and the channel layer 225 is disposed on a substrate 230 formed of an insulating material. The arrangement of the source 205, the drain 210, the gate 215, and the channel layer 225 supports a sufficiently short channel length to allow coherent transmission of Cooper pairs through the channel. Thus, JJFET 200 defines a first JJ with channel layer 225 as its weak link. JJFET 200 may further define a second JJ with gate 215 as its weak link (e.g., SNS junction), and / or define a third JJ with oxide layer 220 as its weak link (e.g., SIS junction). Although for simplicity, the components of JJFET 200 are shown in FIG. Figure 2 Although shown in a particular arrangement, other configurations and geometries are contemplated. For example, a more complex geometry of JJFET 200 may effectively minimize or eliminate the second JJ and / or the third JJ.

[0039] In a conventional FET, the flow of current between the source 205 and the drain 210 (i.e., through the channel formed in the channel layer 225) is controlled by the amount of voltage applied to the gate 215. The electric field established by the applied voltage adjusts the conductivity of the channel layer 225. In the JJFET 200, the applied voltage changes the quantum tunneling characteristics of one or more JJs of the JJFET 200. In some aspects, the critical current of the JJFET 200 is modulated using the voltage applied to the gate 215 (e.g., changing the number of Cooper pairs 120 available for transmission in the supercurrent). In this way, the predefined charge change "sensed" by the JJFET 200 at the gate 215 can change the critical current and cause the JJFFET 200 to transition between the superconducting state and the conductive state. The resulting voltage pulse output from the JJFET 200 can then be measured.

[0040] According to one or more aspects, Figure 3 A system 300 is depicted having one or more charge sensors 330 in a quantum scale device or system 315. The system 300 can be used in conjunction with any other aspect described herein. For example, the one or more charge sensors 330 of the system 300 can include one or more JJ 100 ( Figure 1 ) and / or one or more JJFETs 200( Figure 2 ).

[0041] The system 300 includes a cryogenic cooling system 305 in fluid communication with a cryogenic environment 310 for a quantum system 315. Typically, the cryogenic environment 310 is defined as a temperature of 120K (-153°C) or less. In some aspects, the temperature of the cryogenic environment 310 is very close to absolute zero (0K; -273.15°C) because superconductivity and related quantum properties are most evident at these temperatures. However, the cryogenic environment 310 can have any alternative suitable temperature to ensure superconductivity (e.g., based on the critical temperature of the superconducting material). The cryogenic cooling system 305 can have any suitable implementation, as known to those of ordinary skill in the art. In some aspects, the cryogenic cooling system 305 uses a liquefied gas, such as liquid nitrogen, liquid hydrogen, or liquid helium, to reach the desired temperature within the cryogenic environment 310.

[0042] Quantum system 315 includes quantum memory 325, which can have any suitable implementation known to those of ordinary skill in the art. In some aspects, quantum memory 325 includes multiple Josephson junctions that operate as multiple superconducting qubits. In some aspects, quantum information in the qubits can be stored, altered, and / or read by transmitting microwave photons at the qubits. Other implementations of quantum memory 325 are also contemplated.

[0043] In some aspects, quantum memory 325 stores quantum information in multiple qubits, each of which is in a superposition state (representing a combination of all possible configurations). Some or all of the multiple qubits may further exhibit quantum entanglement, where a change in one qubit also affects one or more entangled qubits. Therefore, multiple qubits can be used to represent complex multi-dimensional computational spaces.

[0044] Also contemplated are alternative implementations of quantum system 315. For example, quantum system 315 may include one or more quantum processors, one or more quantum networks, one or more quantum sensors, or one or more classical (ie, non-quantum) cryogenic sensors.

[0045] In some aspects, the quantum system 315 is communicatively coupled to one or more processors 335 that are separate from the quantum system 315. The one or more processors 335 may be disposed inside or outside the cryogenic environment 310. The one or more processors 335 may have any suitable implementation of a classical (i.e., non-quantum) processor. In some aspects, the one or more processors 335 include a control circuit that communicates control signals and / or data with the one or more quantum processors 320. For example, the control signal may be used to control the properties of microwave photons used to interact with the qubits of the quantum memory 325, and the one or more processors 335 may receive measurement data from the one or more quantum processors 320. In some aspects, the one or more processors 335 are communicatively coupled to the cryogenic cooling system 305, and further communicate control signals and / or data with the cryogenic cooling system 305 to maintain the cryogenic environment 310. In some aspects, the one or more processors 335 are communicatively coupled to one or more external networks and communicate as a gateway with public and / or private networks (e.g., the cloud). In one non-limiting example, quantum system 315 may be included in a quantum repeater that spans a considerable distance.

[0046] The quantum system 315 also includes one or more charge sensors 330, which are operable to detect charge changes in one or more charge islands of the quantum system 315. In some aspects, each of the one or more charge islands includes corresponding one or more quantum dots. Each quantum dot is a semiconductor structure (e.g., Si or GaAs) of sufficiently small size to exhibit quantum mechanical properties, such as the semiconductor structure can capture individual electrons. From another perspective, each quantum dot works like an "artificial atom". Although described in terms of quantum dots, other implementations of one or more charge islands can also be considered. For example, one or more charge islands can alternatively include one or more material defects, one or more grain boundaries, or one or more micro-surface features, etc.

[0047] In some aspects, each of the one or more charge sensors 330 includes one or more JJ100 ( Figure 1 ) and / or one or more JJFETs 200( Figure 2 As described above, applying different values ​​of electrostatic potential near the JJ changes its quantum tunneling characteristics. In some aspects, the JJ included in one or more charge sensors 330 (whether implemented as JJ100 or JJFET 200) is capacitively coupled to one or more charge islands according to a selected configuration, some examples of which are as follows: Figure 4 and Figure 5 shown.

[0048] By capacitively coupling one or more charge islands to JJ in any selected configuration, the change in the electron occupancy rate occurring in one or more charge islands will cause the critical current of JJ to change. In some aspects, a bias current (e.g., DC current) less than a first value of the critical current is provided to JJ. The first value of the critical current corresponds to a first charge state of one or more charge islands. When a predefined charge change occurs to one or more charge islands (e.g., the electron occupancy rate of one or more charge islands satisfies a predefined count), the charge change reduces the critical current to a second value less than the bias current. Therefore, JJ transitions between a superconducting state and a conductive state, and exhibits resistance, resulting in a pulse in the output voltage of JJ. The pulse in the output voltage can then be measured, thereby allowing a single readout of the quantum system 315.

[0049] Beneficially, the use of JJs enables a fast, single-shot readout method for measuring charge occupancy in quantum systems 315. As the size of devices and systems decreases to the atomic scale, the ability to quickly measure charge states within these systems will free up resources and accelerate operations that utilize these systems. In addition, the JJs used in one or more charge sensors 330 (whether implemented as JJ 100 or JJFET 200) operate locally in the cryogenic environment 310 housing the quantum system 315, thereby more efficiently utilizing the infrastructure required for the cryogenic environment 310.

[0050] Figure 4 An exemplary device 400 is depicted having one or more charge islands 405-1, ..., 405-N capacitively coupled to a JJFET 410 according to one or more aspects. The device 400 can be used in conjunction with any other aspect described herein. For example, the device 400 can represent Figure 3 An exemplary implementation of a charge sensor 330 is shown.

[0051] Device 400 includes a JJFET 410 representing an example of JJFET 200. Device 400 also includes one or more charge islands 405-1, ..., 405-N capacitively coupled to the gate (G) of JJFET 410. In some aspects, each of the one or more charge islands 405-1, ..., 405-N includes a corresponding one or more quantum dots. In some aspects, as shown, one or more charge islands 405-1, ..., 405-N include a plurality of charge islands, each charge island is connected to a gate (G) of JJFET 410 by a capacitor C1, ..., C2. N Although two charge islands are shown, any other number of charge islands (eg, one, three, four, five, or more) is contemplated.

[0052] Capacitors C1, ..., C Nmay be implemented as discrete components in device 400, or may represent the capacitance present between one or more charge islands 405-1, ..., 405-N extending through the dielectric region, and the gate of JJFET 410 (e.g., due to manufacturing processes and relative proximity). N Can have any capacitance value suitable for detecting charge changes occurring at one or more charge islands 405-1, ..., 405-N. In some aspects, capacitors C1, ..., C N have the same capacitance value (eg, the impact of each charge island 405-1, ..., 405-N is weighted similarly). In other aspects, capacitors C1, ..., C N Some or all of the charge islands 405-1, ..., 405-N have different capacitance values. By weighting the impact of each charge island 405-1, ..., 405-N differently, additional information can be conveyed to the measurement circuit 425. In one non-limiting example, capacitors C1, ..., C N The capacitance value can be increased in the order of powers of 2, flowing through capacitors C1, ..., C N The sum of the currents to the gates effectively identifies which of the charge islands 405-1, ..., 405-N has experienced a change in charge.Other encoding schemes are also contemplated, which may include implementing charge islands 405-1, ..., 405-N with different characteristics.

[0053] The device 400 also includes a current source 415, which is coupled to one of the source (S) or drain (D) of the JJFET 410. As shown, the current source 415 is connected to the drain of the JJFET 410. The current source 415 can have any suitable implementation, such as a MOSFET constant current source. The current source 415 provides a bias current (e.g., a DC current) through the JJFET 410, which is less than a first value of the critical current of the JJFET 410. The first value of the critical current corresponds to a first charge state of one or more charge islands 405-1, ..., 405-N.

[0054] Critical current I of JJFET 410 C is related to carrier density and velocity as follows:

[0055]

[0056] Where W is the device width, Cg is the gate capacitance per unit area, Vt is the threshold voltage, and Vg is the voltage applied to the gate.

[0057] According to the resistance-capacitance-shunt-junction (RCSJ) model equation of the JJFET 410:

[0058] as well as

[0059] V DS =0 I DS C .

[0060] This means that when the continuous current through JJFET 410 (eg, the bias current provided by current source 415) is greater than the critical current I C When the voltage is higher than 0.1V, pulses will appear in the output voltage.

[0061] Thus, in some aspects, a predefined charge change (e.g., resulting in a second charge state) of one of the plurality of charge islands 405-1, ..., 405-N reduces the critical current of the JJFET 410 to a second value less than the bias current. In this way, the JJFET 410 transitions between a superconducting state and a conducting state.

[0062] The measurement circuit 425 is coupled to the other of the source and the drain of the JJFET 410. In other words, the current source 415 and the measurement circuit 425 are arranged on opposite sides of the JJFET 410. As shown in the figure, the measurement circuit 425 is connected to the source of the JJFET 410, and measures the output voltage of the JJFET 410. Because the JJFET 410 is transformed into a conductive state when the critical current decreases below the bias current, the JJFET 410 exhibits a resistive loss, and a pulse appears in the output voltage.

[0063] The measurement circuit 425 can have any suitable implementation known to those of ordinary skill in the art. In some aspects, the measurement circuit 425 includes an amplifier circuit for amplifying the output voltage of the JJFET 410. In some aspects, the measurement circuit 425 transmits the signal to Figure 3 One or more processors 335.

[0064] The device 400 also includes a shunt resistor 420, which is coupled between the source and drain of the JJFET 410. The shunt resistor 420 updates the critical current of the JJFET 410 in response to the change of the charge state of one or more charge islands 405-1, ..., 405-N. In some aspects, the resistance value of the shunt resistor 420 is less than the resistance of the JJFET 410 in the conduction phase, because this tends to provide a non-hysteresis, over-damped voltage response. In some aspects, the control current source 415 is to change the bias current based on the updated critical current. For example, one or more processors 335 can transmit a control signal, which sets the bias current based on the determined charge state of one or more charge islands 405-1, ..., 405-N. In some aspects, the device 400 can reset the charge state of one or more charge islands 405-1, ..., 405-N, and the device 400 uses the shunt resistor 420 to restore the critical current to the first value.​

[0065] Thus, JJFET 410 can be used in conjunction with one or more charge islands 405-1, ..., 405-N in device 400 to provide high-speed, accurate measurement of the localized charge state of quantum system 315. In some aspects, device 400 is capable of obtaining single-shot measurements on the order of nanoseconds.

[0066] Figure 5 An exemplary device 500 is depicted having one or more charge islands 405-1, ..., 405-N capacitively coupled to a node 510 between a pair of serially connected Josephson junctions 505-1, 505-2 according to one or more aspects. The device 500 can be used in conjunction with any other aspect described herein. For example, the device 500 can represent Figure 3 An exemplary implementation of a charge sensor 330 is shown.

[0067] The device 500 includes serially connected Josephson junctions 505-1, 505-2 representing an example of JJ 100. The device 500 also includes a plurality of capacitors C1, ..., C2. N One or more charge islands 405-1, ..., 405-N are capacitively coupled to node 510. Although two charge islands are shown, any other number of charge islands (e.g., one, three, four, five, or more) are contemplated. As described above, capacitors C1, ..., C N 405 -N that extend through the dielectric region and the node 510 (eg, due to manufacturing processes and relative proximity).

[0068] The device 500 also includes a current source 415 coupled to the JJ 505-2 opposite to the node 510. The current source 415 provides a bias current (e.g., a DC current) through the JJs 505-1, 505-2 that is less than a first value of a critical current of the JJs 505-1, 505-2. The first value of the critical current corresponds to a first charge state of one or more charge islands 405-1, ..., 405-N.

[0069] The device 500 also includes a measurement circuit 425 coupled to the JJ 505-1 opposite to the node 510. In some aspects, a predefined charge change (e.g., resulting in a second charge state) of one of the plurality of charge islands 405-1, ..., 405-N reduces the critical current of the JJ 505-1, 505-2 to a second value less than the bias current. In this way, the JJ 505-1, 505-2 transitions between a superconducting state and a conducting state. Because the JJ 505-1, 505-2 transitions to a conducting state when the critical current decreases below the bias current, a resistive loss occurs in the JJ 505-1, 505-2, and a pulse occurs in the output voltage of the device 500. The apparatus 500 also includes a shunt resistor 420 coupled across the pair of JJs 505-1, 505-2 and configured to restore the critical current of the JJs 505-1, 505-2 to a first value after a pulse in the output voltage occurs.

[0070] Thus, JJ 505-1, 505-2 can be used in conjunction with one or more charge islands 405-1, ..., 405-N in device 500 to provide high-speed, accurate measurement of the localized charge state of quantum system 315. In some aspects, device 500 is capable of obtaining single-shot measurements on the order of nanoseconds. In addition, using JJ 505-1, 505-2 together with one or more charge islands 405-1, ..., 405-N can significantly reduce the manufacturing challenges of charge sensing.

[0071] Figure 6 Current-voltage (IV) characteristics of a Josephson junction at different charge states are plotted according to one or more aspects. Figure 6 The features of can be used in combination with any other aspect described herein. For example, these curves can describe Figure 4 The device 400 or Figure 5 Exemplary operation of apparatus 500.

[0072] More specifically, graph 600 includes curve 605 representing the bias current provided by current source 415. In some aspects, the bias current is less than a first value of the critical current of the JJFET or JJ. As shown, the bias current is about 45 microamperes (uA). Graph 600 also includes curve 610 representing the IV characteristics of the JJFET or JJ in a first state of charge, and curve 615 representing the IV characteristics of the JJFFET or JJ in a second state of charge.

[0073] In curve 610, the JJFET or JJ operates in a superconducting state under a bias current, and a voltage point 620 indicates that the output voltage is approximately zero. In curve 615, the JJFET or JJ operates in a conducting state under a bias current (in other words, the bias current exceeds the critical current), and a voltage point 625 indicates an output voltage of approximately 20 millivolts (mV).

[0074] Figure 7 700 is a method 700 for charge sensing in a quantum system according to one or more aspects. The method 700 can be used in combination with other embodiments, for example, using Figure 4 The device 400 or Figure 5 The device 500 is executed.

[0075] Method 700 begins at block 705, where the device provides a bias current through the Josephson junction, the bias current being less than a first value of a critical current of the Josephson junction. In some aspects, the JJ is implemented as a two-terminal device, such as Figure 1 In other aspects, the JJ is implemented as a three-terminal device, such as Figure 2 JJFET 200.

[0076] At block 715, the apparatus measures an output voltage of the Josephson junction. The output voltage measurement is in response to a charge change of one of a plurality of charge islands coupled to the Josephson junction. In some aspects, the charge change is determined at a node between the series JJs. In other aspects, the charge change is determined at the gate of the JJFET. The charge change reduces the critical current to a second value less than the bias current.

[0077] At block 725, in response to the charge change of one or more charge islands, the device updates the critical current to a second value using a shunt resistor coupled across the Josephson junction. In some aspects, method 700 proceeds along branch 730 and returns to block 705, where the device provides a bias current that is less than the (updated) critical current. Thus, in response to the change in charge, the critical current stabilizes at the updated value (due to the shunt resistor), and the device updates the bias current to be less than the updated value.

[0078] In some aspects, method 700 continues to block 735, where the device resets the charge state of one or more charge islands. At block 745, the device restores the critical current to the first value using the shunt resistor. Method 700 ends after block 745 is completed.

[0079] Those skilled in the art will appreciate that the aspects described herein may be embodied as systems, methods, or computer program products. Thus, aspects may take the form of entirely hardware aspects, entirely software aspects (including firmware, resident software, microcode, etc.), or aspects combining software and hardware aspects, which are generally referred to herein as "circuits," "modules," or "systems." Additionally, aspects described herein may take the form of a computer program product contained in one or more computer-readable storage media, which contain computer-readable program code thereon.

[0080] Program code embodied on a computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0081] The computer program code for performing the operations of various aspects of the present disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages, such as Java, Smalltalk, C++, etc., and traditional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer as a separate software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0082] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to various aspects of the present disclosure. It should be understood that each block of the flowchart illustration and / or block diagram, as well as the combination of blocks in the flowchart illustration and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that instructions executed by a computer or other programmable data processing device processor create a device for implementing the functions / actions specified in the blocks of the flowchart and / or block diagram.

[0083] These computer program instructions may also be stored in a computer-readable medium, which can instruct a computer, other programmable data processing apparatus, or other device to operate in a specific manner so that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions / actions specified in the flowchart and / or block diagram.

[0084] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to perform a series of operating steps on the computer, other programmable device, or other device to produce a computer-implemented process, so that the instructions running on the computer, other programmable data processing apparatus, or other device provide a process for implementing the functions / actions specified in the blocks of the flowchart and / or block diagram.

[0085] The flowcharts and block diagrams in the figure illustrate the possible implementation architectures, functions and operations of the systems, methods and computer program products according to various aspects of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment or portion of a code, which includes one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions described in the blocks may not appear in the order shown in the figure. For example, two blocks displayed in succession may actually be executed substantially simultaneously, or, depending on the functions involved, the blocks may sometimes be executed in reverse order or out of order. It will also be noted that each block of the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs a specified function or action, or by a combination of dedicated hardware and computer instructions.

[0086] While the foregoing is directed to aspects of the present disclosure, other and further aspects of the disclosure may be devised without departing from the basic scope thereof, the scope of which is to be determined by the following claims.

Claims

1. A method (700) for charge sensing in a quantum system (315), the method comprising: providing (705) a bias current (605) through a Josephson junction (100, 200, 410, 505-1, 505-2), the bias current being less than a first value of a critical current of the Josephson junction; and An output voltage of the Josephson junction is measured (715), wherein the critical current is reduced to a second value less than the bias current in response to a change in charge of one or more charge islands coupled to the Josephson junction, causing a voltage drop across the Josephson junction.

2. The method of claim 1, wherein each of the one or more charge islands comprises corresponding one or more quantum dots, one or more material defects, one or more grain boundaries, one or more micro-surface features.

3. The method of claim 1, wherein the one or more charge islands include a plurality of charge islands (405-1, ..., 405-N), each charge island being connected via a respective capacitor (C1, ..., C N ) is coupled to the Josephson junction. The method of claim 3 , wherein some or all of the capacitors have different capacitance values ​​corresponding to the plurality of charge islands.

5. The method according to claim 1, further comprising: The critical current of the Josephson junction is updated (725) to a second value in response to the change in charge of the one or more charge islands using a shunt resistor (420) coupled across the Josephson junction.

6. The method according to claim 1, The Josephson junction is included in a Josephson junction field effect transistor, i.e., JJFET (200, 410), wherein the one or more charge islands are capacitively coupled to a gate (G) of the JJFET, and The bias current is provided by a current source (415) coupled to the source (S) or drain (D) of the JJFET.

7. The method according to claim 1, The Josephson junction is included in a pair of Josephson junctions (100, 505-1, 505-2) connected in series. wherein the one or more charge islands are capacitively coupled between the Josephson junctions of the pair (510), and Wherein the bias current is provided by a current source (415) coupled to one of the Josephson junctions of the pair.

8. An apparatus (400), comprising: Josephson junction field effect transistor, i.e. JJFET (200, 410); one or more charge islands (405-1, ..., 405-N) capacitively coupled to the gate (G) of the JJFET; and a current source (415) coupled to one of the source (S) and drain (D) of the JJFET, the current source providing a bias current (605) of a first value less than a critical current of the JJFET; Wherein a predefined change in charge to the one or more charge islands reduces the critical current to a second value that is less than the bias current.

9. The device of claim 8, wherein each of the one or more charge islands comprises corresponding one or more quantum dots, one or more material defects, one or more grain boundaries, one or more micro-surface features.

10. The device of claim 8, wherein the one or more charge islands include a plurality of charge islands (405-1, ..., 405-N), each of the charge islands being connected to a respective capacitor (C1, ..., C N ) is coupled to the gate.

11. The apparatus of claim 10, wherein some or all of the capacitors corresponding to the plurality of charge islands have different capacitance values.

12. The apparatus according to claim 8, further comprising: A shunt resistor (420) is coupled between the source and the drain of the JJFET.

13. The apparatus according to claim 8, further comprising: A measurement circuit (425) is coupled to the other of the source and the drain of the JJFET.

14. The apparatus of claim 13, wherein the measurement circuit comprises an amplifier circuit for amplifying an output voltage of the JJFET.

15. An apparatus (500), comprising: A pair of serially connected Josephson junctions (100, 505-1, 505-2); one or more charge islands (405-1, ..., 405-N) capacitively coupled to a node (510) between the Josephson junctions of the pair; as well as a current source (415) coupled to a first Josephson junction of the pair, the current source providing a bias current (605) of a first value less than an effective critical current of the Josephson junction, Wherein a predefined change in charge to the one or more charge islands reduces the effective critical current to a second value that is less than the bias current.

16. The device of claim 15, wherein each of the one or more charge islands comprises corresponding one or more quantum dots, one or more material defects, one or more grain boundaries, one or more micro-surface features.

17. The apparatus of claim 15, wherein the one or more charge islands include a plurality of charge islands (405-1, ..., 405-N), each of the charge islands being connected to a capacitor (C1, ..., C N ) is coupled between the Josephson junctions of the pair.

18. The apparatus of claim 17, wherein some or all of the capacitors corresponding to the plurality of charge islands have different capacitance values.

19. The apparatus according to claim 15, further comprising: A shunt resistor (420) is coupled across the pair of Josephson junctions.

20. The apparatus of claim 15, further comprising: A measurement circuit (425) is coupled to the second Josephson junction of the pair.

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