Display device, driving chip and manufacturing method thereof

Abstract

The invention relates to a display device, a driving chip and a manufacturing method thereof, and relates to the technical field of chips. The manufacturing method comprises the following steps: determining the number of unit channels according to preset unit port bandwidth, action duration and color depth; a plurality of processing units distributed in an array mode are formed on the wafer, each processing unit is provided with at least one port and at least one channel, the number of the channels of one processing unit is the number of the unit channels, and the bandwidth of one port of each processing unit is the bandwidth of the unit port; cutting at least one driving chip in the wafer according to the target port bandwidth and the target channel number, wherein the driving chip comprises n processing units; n is a positive integer; the target port bandwidth = n * unit port bandwidth; the target channel number = n * the unit channel number.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular, to a display device, a driver chip, and a method for manufacturing the driver chip. Background Art

[0002] Display devices usually need to use driver chips to drive display panels so that they can display images. Since the support capacity of a single driver chip is limited, multiple driver chips are usually used in large-size display devices such as TVs. However, the increase in the number of driver chips will lead to an increase in procurement costs, and the process difficulty will also increase, resulting in more working hours.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The present disclosure provides a display device, a driver chip and a method for manufacturing the driver chip, which can reduce the number of driver chips and reduce costs without reducing driving performance.

[0005] According to one aspect of the present disclosure, a method for manufacturing a driver chip is provided, comprising:

[0006] Determine the number of unit channels according to the preset unit port bandwidth, action duration and color depth;

[0007] Forming a plurality of processing units distributed in an array on a wafer, wherein the processing unit has at least one port and a channel, and the number of channels of a processing unit is the number of unit channels, and the bandwidth of a port of the processing unit is the unit port bandwidth;

[0008] At least one driver chip is cut out of the wafer according to the target port bandwidth and the target number of channels, wherein the driver chip includes n processing units; n is a positive integer;

[0009] The target port bandwidth=n×the unit port bandwidth;

[0010] The target number of channels=n×the number of unit channels.

[0011] In an exemplary embodiment of the present disclosure,

[0012] The number of unit channels = the unit port bandwidth × the action duration ÷ the color depth.

[0013] In an exemplary embodiment of the present disclosure, the unit port bandwidth is the bandwidth of a differential pair in one of the ports, and the action duration is the duration for one of the differential pairs in one of the ports to transmit data of a specified size.

[0014] In an exemplary embodiment of the present disclosure, the unit port bandwidth is 1 Gbps-4 Gbps; the action duration is 1 μs-3 μs; and the color depth is 8 bit-32 bit.

[0015] In an exemplary embodiment of the present disclosure, the processing units are distributed in an array along intersecting first and second directions, and a distance between two adjacent processing units in the first direction is smaller than a distance between two adjacent processing units in the second direction.

[0016] In an exemplary embodiment of the present disclosure, n>1, and the processing units of the same driving chip are distributed along the first direction.

[0017] In an exemplary embodiment of the present disclosure, n>1, and two adjacent processing units of the same driving chip are connected via a connection line located on the wafer.

[0018] In an exemplary embodiment of the present disclosure, the processing unit includes a plurality of pins; some pins of two adjacent processing units in the first direction are symmetrically arranged between the two processing units, and the symmetrically arranged pins in adjacent processing units are connected by the connecting line.

[0019] In an exemplary embodiment of the present disclosure, the pins include power pins and control pins, and at least some of the power pins of two adjacent processing units are symmetrically arranged and connected by the connecting line; at least some of the control pins of two adjacent processing units are symmetrically arranged and connected by the connecting line.

[0020] In an exemplary embodiment of the present disclosure, the control pin includes a synchronization pin for transmitting a synchronization signal and a digital control pin for transmitting a digital control signal.

[0021] According to one aspect of the present disclosure, a driver chip is provided, comprising n processing units; n is a positive integer; the processing unit has at least one port and a channel, and the number of channels of the processing unit is the unit channel number, and the bandwidth of a port of the processing unit is the unit port bandwidth;

[0022] The bandwidth of the port of the driver chip = n × the bandwidth of the unit port;

[0023] The number of channels of the driving chip=n×the number of unit channels.

[0024] In an exemplary embodiment of the present disclosure,

[0025] The number of unit channels = the unit port bandwidth × the preset action duration ÷ the preset color depth.

[0026] In an exemplary embodiment of the present disclosure, the unit port bandwidth is the bandwidth of a differential pair in one of the ports, and the action duration is the duration for one of the differential pairs in one of the ports to transmit data of a specified size.

[0027] In an exemplary embodiment of the present disclosure, n>1, and two adjacent processing units of the same driving chip are connected via a connecting line that is an integral structure with the processing unit.

[0028] In an exemplary embodiment of the present disclosure, the processing unit includes a plurality of pins; some of the pins in two adjacent processing units are symmetrically arranged, and the symmetrically arranged pins in adjacent processing units are connected through the connecting wire.

[0029] According to one aspect of the present disclosure, a display device is provided, comprising any one of the driving chips described above.

[0030] The display device, driver chip and manufacturing method disclosed herein can form multiple processing units on a wafer, and can cut multiple driver chips on a wafer according to the driver chip's requirements for port bandwidth and channel number. Any driver chip can include one, two or more processing units. At the same time, the processing unit is the basic unit constituting the driver chip. Before forming the processing unit, the number of channels of the processing unit, i.e., the number of unit channels, can be determined based on the preset unit port bandwidth, action duration and color depth. The bandwidth of the port of the driver chip (i.e., the target port bandwidth) is n times the unit port bandwidth, and the number of channels of the driver chip (i.e., the target channel number) is n times the unit channel number, so that a driver chip is formed by n processing units.

[0031] Since the target number of channels is actually determined based on the unit port bandwidth, action duration and color depth, under certain design specifications and process conditions, the bandwidth and number of channels of the processing unit port can be maximized by maximizing the unit port bandwidth, action duration and color depth, thereby obtaining the best basic unit; the driver chip is constructed based on the requirements of the driver chip using the best basic unit, thereby improving the bandwidth utilization of the driver chip, thereby reducing the number of driver chips without reducing performance, thereby reducing costs and improving production efficiency.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 It is a schematic diagram of an embodiment of the display device disclosed in the present invention.

[0035] Figure 2 It is a schematic diagram of another embodiment of the display device disclosed in the present invention.

[0036] Figure 3 Schematic diagram of a wafer before cutting in the manufacturing method disclosed in the present invention.

[0037] Figure 4 FIG. 1 is a schematic diagram of two adjacent processing units of an embodiment of a driver chip disclosed herein. DETAILED DESCRIPTION

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0039] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0040] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0041] The present disclosure provides a display device, which may include a display panel and a driving chip 10, wherein:

[0042] The display panel may be a liquid crystal display panel, which may include a backlight module, an array substrate, an opposing substrate and a liquid crystal layer located between the array substrate and the opposing substrate; or, the display panel may be a self-luminous display panel, which may include a driving backplane and a light-emitting device located on one side of the driving backplane, the light-emitting device may be an OLED (organic light-emitting diode) using organic light-emitting materials, or a Mini LED (sub-millimeter light-emitting diode, with a size of 100μm-200μm), Micro LED (micro light-emitting diode, with a size not greater than 100μm) and LED (light-emitting diode, with a size greater than 200μm) using inorganic light-emitting materials, etc., without special limitation here, as long as it can emit light.

[0043] The display panel may be divided into at least a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA; or it may be a discontinuous area surrounding the display area AA. For example, the peripheral area WA may be distributed on both sides of the display area AA. The display area AA may be used to emit light to display an image, while the peripheral area WA does not emit light. The display panel has a driving circuit, which may include a pixel circuit located in the display area AA and a peripheral circuit located in the peripheral area WA.

[0044] The peripheral circuit can be connected to the main board through at least one flexible circuit board, so that the main board can control the display panel to display images. Figure 1 As shown, the number of the driving chip 10 can be one, two or more, which can be arranged in the peripheral area WA and connected to the peripheral circuit and the flexible circuit board F1; or Figure 2 As shown, the driving chip 10 may also be disposed on the flexible circuit board F1. The mainboard may control the display panel to display images through the driving chip 10.

[0045] In some embodiments of the present disclosure, since the driving capability of a single driver chip 10 is limited, for medium and large display devices such as televisions and computer monitors, Figure 2 As shown, the display panel can be controlled by multiple driver chips 10, and different driver chips 10 drive different areas of the display panel, and different areas are connected to the mainboard through different flexible circuit boards F1. However, the more driver chips 10 there are, the higher the cost, and the time for processes such as binding will also increase, affecting production efficiency. In addition, if a single driver chip 10 has a poor process, it will affect the image display of the entire display device, and the more driver chips 10 there are, the greater the risk of defects.

[0046] Based on the above description, the inventors analyzed the problems of the above solution in order to reduce the number of driver chips 10:

[0047] In the manufacturing process of the display device, it is necessary to select a plurality of driver chips 10 of a certain type from a plurality of driver chips 10 of fixed specifications, such as Figure 1 As shown, the driving chip 10 can be mounted in the peripheral area WA of the display panel, or, as shown in FIG. Figure 2 As shown, the driver chip 10 is mounted on the flexible circuit board F1, but the specifications of the driver chip 10 are reflected by the parameters such as the resolution, refresh rate, number of channels, bandwidth, etc. that it can support. The following table exemplarily lists various specifications of the driver chip 10 (IC) and related parameters:

[0048] Resolution Refresh rate (Hz) Number of IC channels Number of ICs IC Bandwidth (Gbps) Bandwidth Utilization 1280*800 60 1026 4 24 8％ 1920*1080 60 1446 4 27.2 14％ 1920*1080 120 1446 4 27.2 28％ 1920*1080 144 1446 4 27.2 33％ 2160*1440 60 1926 4 70.4 8％ 2160*1440 120 1926 4 70.4 16％ 2160*1440 144 1926 4 70.4 19％ 2560*1600 60 1926 4 70.4 11％ 2560*1600 120 1926 4 70.4 21％ 2560*1600 144 1926 4 70.4 25％ 3840*2160 60 1926 6 105.6 14％

[0049] Since the specifications of the driver chip 10 are predetermined and have nothing to do with the needs of the display device, for medium and large-sized display devices, the needs of displaying images can only be met by increasing the number of driver chips 10. However, this may cause the performance of the driver chip 10 to not match the actual needs of the display device, resulting in low bandwidth utilization. Therefore, if the bandwidth utilization of a single driver chip 10 for a specific display device can be improved, fewer driver chips 10 can be used to achieve the display function.

[0050] Based on the above analysis, the inventors proposed a method for manufacturing a driver chip, such as Figure 3 As shown, the manufacturing method may include steps S110 to S130, wherein:

[0051] Step S110: Determine the number of unit channels according to the preset unit port bandwidth, action duration and color depth.

[0052] Step S120, forming a plurality of processing units distributed in an array on a wafer, wherein the processing unit has at least one port and a channel, and the number of channels of a processing unit is the unit channel number, and the bandwidth of a port of the processing unit is the unit port bandwidth.

[0053] Step S130, cutting out at least one driver chip from the wafer according to the target port bandwidth and the target number of channels, wherein one driver chip includes n processing units, where n is a positive integer;

[0054] Target port bandwidth = n × unit port bandwidth;

[0055] Target number of channels = n × number of unit channels.

[0056] The manufacturing method of the embodiment of the present disclosure can form a plurality of processing units 1 on a wafer W1. According to the requirements of the driver chip 10 for the port bandwidth and the number of channels, the wafer W1 can be cut into a plurality of driver chips 10, and any driver chip 10 can include one, two or more processing units 1. At the same time, the processing unit 1 is a basic unit constituting the driver chip 10. Before forming the processing unit 1, the number of channels of the processing unit 1, i.e., the number of unit channels, can be determined based on the preset unit port bandwidth, action duration, and color depth. The bandwidth of the port of the driver chip 10 (i.e., the target port bandwidth) is n times the unit port bandwidth, and the number of channels of the driver chip 10 (i.e., the target channel number) is n times the unit channel number, so that a driver chip 10 is formed by n processing units 1.

[0057] Since the target number of channels is actually determined based on the unit port bandwidth, action duration and color depth, under certain design specifications and process conditions, the bandwidth and number of channels of the port of the processing unit 1 can be maximized by maximizing the unit port bandwidth, action duration and color depth, thereby obtaining the best basic unit; the driver chip 10 is constructed based on the requirements of the driver chip 10 by the best basic unit, so that the bandwidth utilization rate of the driver chip 10 is improved, thereby reducing the number of driver chips 10 without reducing performance, thereby reducing costs and the risk of defects and improving production efficiency.

[0058] It should be emphasized that the manufacturing method of the above-mentioned embodiment is not to simply integrate multiple existing chips into one chip, but to determine the maximum bandwidth and number of channels that a single processing unit 1 can support based on specific parameters, and then construct the driver chip 10 according to the needs of the driver chip 10, which can fully improve the bandwidth utilization of the driver chip 10, rather than increasing the number of driver chips 10 to make up for the defect of insufficient bandwidth utilization in other embodiments.

[0059] In addition, in some embodiments, in order to save the number of driver chips 10, reduce costs, and increase the number of scan lines, the same data line can be connected to more sub-pixels, and the same data line can be used to transmit data signals to multiple sub-pixels through time-sharing scanning to achieve image display; in this way, the number of data lines can also be reduced, thereby reducing the requirements for the number of channels, and thus the number of driver chips 10 can be reduced; the above-mentioned solution of constructing the driver chip 10 through the processing unit 1 can also be applied to the multi-scan line solution, further reducing the number of driver chips 10. Taking a display device with FHD of 120Hz as an example, if the above-mentioned multi-scan line solution is not adopted, 4 existing driver chips with 1440 channels need to be used. If the number of data lines is reduced by 6 times by increasing the scan lines, only 1 driver chip 10 (with 960 channels) with 4 processing units 1 (with 240 channels) can be used. For a display device with a resolution of 2560*1600 and a refresh rate of 120 Hz, if an existing driver chip with 1920 channels is used, four are required. However, by increasing the scan lines, the data lines are reduced by 4 times, and two driver chips 10 with 960 channels are sufficient. Each driver chip 10 includes four processing units 1 (with 240 channels).

[0060] The steps of the above-mentioned manufacturing method are described in detail below:

[0061] In step S110 , the processing unit 1 is a basic unit constituting the driving chip 10 , which may have at least one port, and the port of the processing unit 1 may use a differential pair for data transmission, and one processing unit 1 may include multiple differential pairs.

[0062] Before forming the processing unit 1, the parameters of the processing unit 1 may be determined, including the unit port bandwidth, the number of unit channels, the action duration, and the color depth, wherein:

[0063] In some implementations, the unit port bandwidth is the bandwidth of a differential pair in a port, and the unit port bandwidth may be 1 Gbps-4 Gbps, for example, 1.2 Gbps, 1.5 Gbps, 1.6 Gbps, 2 Gbps, 3.2 Gbps, etc.

[0064] It should be noted that the total bandwidth of a processing unit 1 can be decomposed into the bandwidth of multiple ports it has, but there are multiple options for the decomposition method. For example, if the bandwidth of the processing unit 1 is 24Gbps, it can be achieved through 1 port, each port has 4 pairs, and the bandwidth of each pair is 6Gbps, that is, 6Gbps / pair*4pair*1port=24Gbps. Or, the same 24Gbps can also be achieved through 2 ports, each port has 4 pairs, and the bandwidth of each pair is 3Gbps, that is, 3Gbps / pair*4pair*2port=24Gbps.

[0065] The action duration is the duration for a differential pair in a port to transmit data of a specified size, which may be subject to constraints such as manufacturing processes, and the specific value is not specifically limited here. In some embodiments, the action duration may be 1 μs-3 μs, for example, 1 μs, 1.2 μs, and 3 μs.

[0066] The color depth may be 8-bit to 32-bit, for example, the color depth is 8-bit, 16-bit or 32-bit.

[0067] The number of unit channels is the maximum number of channels that the processing unit 1 can support, which is determined based on the above-mentioned unit port bandwidth, action duration and color depth. If the specific values ​​of the unit port bandwidth, action duration and color depth are determined, the number of unit channels can be determined, and the specific visual resolution, refresh rate and process difficulty can be selected. The present disclosure does not make any special restrictions on the specific values.

[0068] In some embodiments of the present disclosure, the unit port bandwidth, action duration, color depth, and number of unit channels may satisfy the following relationship:

[0069] Number of unit channels = unit port bandwidth × action duration ÷ color depth;

[0070] For example, the unit port bandwidth = 3.2 Gbps, the action time = 3 us, the color depth = 8 bits, at this time, the number of unit channels = 1200; or, the unit port bandwidth = 1.6 Gbps, the action time = 1.2 us, the color depth = 8 bits, at this time, the number of unit channels = 240.

[0071] like Figure 3 As shown, in step S120, after the above parameters such as the number of unit channels and the unit port bandwidth are determined, multiple processing units 1 can be formed on the wafer W1 through deposition, photolithography and other processes. The processing unit 1 has a processing circuit and multiple pins. The pins are used to connect with the flexible circuit board or the peripheral circuit. The processing circuit can be used to drive the display panel to display images. Based on the above pins, the processing unit 1 can also include at least one port and channel for transmitting data.

[0072] The number of channels of a processing unit 1 is the above-mentioned number of unit channels, and the bandwidth of a port of the processing unit 1 is the above-mentioned unit port bandwidth. At the same time, each processing unit 1 can be distributed in an array along the first direction X and the second direction Y, and the first direction X and the second direction Y can intersect vertically or at an angle other than 90°. At the same time, each processing unit 1 has the same size and specification, that is, the processing unit 1 is a repeated unit on the wafer W1.

[0073] like Figure 3 As shown, in step S130, the bandwidth and number of channels of the driver chip 10 can be determined based on the requirements of the display device such as the resolution and refresh rate, wherein the target port bandwidth is the bandwidth of a port of the driver chip 10, and the target number of channels is the number of channels of the driver chip 10. When the target port bandwidth and the target number of channels are determined, it can be determined how many processing units 1 are required to constitute the driver chip 10.

[0074] If the target port bandwidth = n × unit port bandwidth; the target number of channels = n × number of unit channels, then one driver chip 10 includes n processing units 1, where n is a positive integer. For example, if the unit port bandwidth of a processing unit 1 is 1.6 Gbps and the number of unit channels is 240, if the target number of channels of the driver chip 10 is 240ch and the target port bandwidth is 1.6 Gbps, then one driver chip 10 only needs one processing unit 1, that is, n = 1, and one processing unit 1 can be used as a whole to cut the wafer W1.

[0075] If the target number of channels of the driver chip 10 is 480 and the target port bandwidth is 3.2 Gbps, one driver chip 10 requires two processing units 1, ie, n=2, and the two processing units 1 can be used as a whole to cut the wafer W1.

[0076] like Figure 3 As shown, in some embodiments of the present disclosure, the spacing between two adjacent processing units 1 in the first direction X is smaller than the spacing between two adjacent processing units 1 in the second direction Y. When cutting, the wafer W1 can be cut into multiple groups along the first direction X, each group including multiple processing units 1 distributed along the first direction X, and then each group of processing units 1 is cut along the second direction Y for a specific value of n, to obtain a driver chip 10 including n processing units 1. For example, if n>1, and the processing units 1 of the same driver chip 10 are distributed along the first direction X.

[0077] It should be noted that since the specific value of n is related to the requirements of the driver chip 10 and is not unique, when a wafer W1 is cut, the number of processing units 1 is not necessarily n times the number of driver chips 10, and there may be remaining processing units 1. In this case, the remaining processing units 1 can be divided into multiple separate processing units 1, that is, multiple driver chips 10 containing only one processing unit 1, which are reserved for other uses; or, the remaining processing units 1 can also be cut in groups to form a driver chip 10 containing multiple processing units 1, which are reserved for other uses.

[0078] In addition, when the same wafer W1 is cut, the driver chips 10 obtained are not limited to the same specifications, that is, the driver chips 10 with different numbers of processing units 1 can be included at the same time. Of course, from the perspective of production efficiency and process difficulty, the number of driver chips 10 cut out of the same specifications can be as large as possible. When cutting, a special tool or laser can be used, and no special limitation is made here.

[0079] like Figure 3 and Figure 4 As shown, in some embodiments of the present disclosure, if the same driver chip 10 includes multiple processing units 1, in some embodiments of the present disclosure, n>1, that is, one driver chip 10 includes more than one processing unit 1. At this time, two adjacent processing units 1 of the same driver chip 10 can be connected through a connecting wire 2 located on the wafer W1. The connecting wire 2 can be formed when the processing unit 1 is formed on the wafer W1, so that the connecting wire 2 is an internal circuit of the driver chip 10. The connecting wire 2 can be located in a metal layer formed on the wafer W1, and can be arranged in the same layer as part of the routing of the processing circuit. When the wafer W1 is cut, the area where the connecting wire 2 is located belongs to the internal area of ​​the driver chip 10 and is not cut.

[0080] Furthermore, the connecting line 2 can be connected to some pins of the driver chip 10, and each pin may include at least one group of pins with the same function. Two pins with the same function in adjacent processing units 1 in the same driver chip 10 can be connected through the connecting line 2. That is, in two adjacent processing units 1 of the same driver chip 10, one of a group of pins in one processing unit 1 is connected to a pin with the same function in another processing unit 1 through the connecting line 2, so as to realize the transmission of internal signals of the driver chip 10. There is a pin that is not connected to the connecting line 2 in each group of pins in at least two processing units 1, and the pin that is not connected through the connecting line 2 can be used as the input and output of the driver chip 10 as a whole.

[0081] Each pin may include at least one group of power pins and at least one group of control pins Con signal, and the power pins are used to provide at least one of digital power and analog power for the driver chip 10. The control pin Con signal is used to provide a control signal, which may include a synchronization pin and a digital control pin, the synchronization pin can be used to transmit a synchronization signal, and the digital control pin can be used to transmit a digital module control signal. In two adjacent processing units 1 of the same driver chip 10, one of a group of power pins of one processing unit 1 is connected to one of a group of power pins with the same function in another processing unit 1 through a connecting line 2, and one of a group of control pins Con signal of one processing unit 1 is connected to one of a group of control pins Con signal with the same function in another processing unit 1 through a connecting line 2; each group of power pins in at least two processing units 1 has a power pin that is not connected to the connecting line 2, and each group of control pins Consignal in at least two processing units 1 has a control pin Con signal that is not connected to the connecting line 2.

[0082] like Figure 4 As shown, in some embodiments of the present disclosure, the power pins may include a group of analog power pins AVDD, a group of analog power pins AVEE, and a group of digital power pins DVDD. The control pin Con signal may include a group of synchronization pins and a group of digital control pins. In two adjacent processing units 1 of the same driver chip 10: one analog power pin AVDD, one analog power pin AVEE, one digital power pin DVDD, one synchronization pin, and one digital control pin of one processing unit 1 are connected to one analog power pin AVDD, one analog power pin AVEE, one digital power pin DVDD, one synchronization pin, and one digital control pin of another processing unit 1 in a one-to-one correspondence.

[0083] In order to simplify the routing path of the connection line 2, some pins of two adjacent processing units 1 in the first direction X can be symmetrically arranged between the two processing units 1, and the symmetrically arranged pins in the adjacent processing units 1 are connected through the connection line 2. In this way, the connection line 2 can be arranged only between the two adjacent processing units 1, which is conducive to reducing the routing length, thereby reducing impedance and capacitive reactance. The symmetric axis of the above symmetrical arrangement can extend along the second direction Y and be the same as the spacing between the two adjacent processing units 1.

[0084] In some embodiments of the present disclosure, at least some of the power pins of two adjacent processing units 1 of the same driver chip 10 are symmetrically arranged and connected through a connection line 2; at least some of the control pins Con signal of two adjacent processing units 1 are symmetrically arranged and connected through a connection line 2. For example, each group of power pins is distributed on both sides of the processing unit 1 in the first direction X, and each group of control pins Con signal is also distributed on both sides of the processing unit 1; in two adjacent processing units 1 of the same driver chip 10, an analog power pin AVDD of one processing unit 1 is symmetrically arranged with an analog power pin AVDD of another processing unit 1, and connected through a connection line 2; an analog power pin AVEE of one processing unit 1 is symmetrically arranged with an analog power pin AVDD of another processing unit 1, and connected through a connection line 2; and the same applies to other pins connected through the connection line 2.

[0085] like Figure 1-Figure 4 As shown, based on the above manufacturing method, the embodiment of the present disclosure further provides a driver chip 10, which may include n processing units 1; n is a positive integer; each processing unit 1 has at least one port and channel, and the number of channels of a processing unit 1 is the unit channel number, and the bandwidth of any port of the processing unit 1 is the unit port bandwidth; wherein:

[0086] The bandwidth of the port of the driver chip 10 = n × unit port bandwidth;

[0087] The number of channels of the driving chip 10 = n×the number of unit channels.

[0088] The specific structure and beneficial effects of the driver chip 10 have been described in detail in the above manufacturing method, so reference may be made to the implementation of the above manufacturing method, and no further details will be given here.

[0089] It should be noted that, although the steps of the manufacturing method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0090] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and embodiments are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for manufacturing a driver chip, characterized in that: include: Determine the number of unit channels according to the preset unit port bandwidth, action duration and color depth; Forming a plurality of processing units distributed in an array on a wafer, wherein the processing unit has at least one port and a channel, and the number of channels of a processing unit is the number of unit channels, and the bandwidth of a port of the processing unit is the unit port bandwidth; At least one driver chip is cut out of the wafer according to the target port bandwidth and the target number of channels, wherein the driver chip includes n processing units; n is a positive integer; The target port bandwidth=n×the unit port bandwidth; The target number of channels=n×the number of unit channels.

2. The manufacturing method according to claim 1, characterized in that: The number of unit channels = the unit port bandwidth × the action duration ÷ the color depth.

3. The manufacturing method according to claim 2, characterized in that: The unit port bandwidth is the bandwidth of a differential pair in the port, and the action duration is the duration for a differential pair in the port to transmit data of a specified size.

4. The manufacturing method according to claim 2, characterized in that: The unit port bandwidth is 1Gbps-4Gbps; the action duration is 1μs-3μs; and the color depth is 8bit-32bit.

5. The manufacturing method according to claim 1, characterized in that: The processing units are distributed in an array along an intersecting first direction and a second direction, and a distance between two adjacent processing units in the first direction is smaller than a distance between two adjacent processing units in the second direction.

6. The manufacturing method according to claim 5, characterized in that: n>1, and the processing units of the same driving chip are distributed along the first direction.

7. The manufacturing method according to claim 5, characterized in that: n>1, and two adjacent processing units of the same driving chip are connected via a connecting line located on the wafer.

8. The manufacturing method according to claim 7, characterized in that: The processing unit includes a plurality of pins; some pins of two adjacent processing units are symmetrically arranged between the two processing units in the first direction, and the symmetrically arranged pins in the adjacent processing units are connected through the connecting wire.

9. The manufacturing method according to claim 8, characterized in that: The pins include power pins and control pins. At least some of the power pins of two adjacent processing units are symmetrically arranged and connected through the connecting line; at least some of the control pins of two adjacent processing units are symmetrically arranged and connected through the connecting line.

10. The manufacturing method according to claim 9, characterized in that: The control pins include synchronization pins for transmitting synchronization signals and digital control pins for transmitting digital control signals.

11. A driver chip, characterized in that: The invention comprises n processing units; n is a positive integer; the processing unit has at least one port and a channel, and the number of channels of a processing unit is the unit channel number, and the bandwidth of a port of the processing unit is the unit port bandwidth; The bandwidth of the port of the driver chip = n × the bandwidth of the unit port; The number of channels of the driving chip=n×the number of unit channels.

12. The driver chip according to claim 11, characterized in that: The number of unit channels = the unit port bandwidth × the preset action duration ÷ the preset color depth.

13. The driver chip according to claim 12, characterized in that: The unit port bandwidth is the bandwidth of a differential pair in the port, and the action duration is the duration for a differential pair in the port to transmit data of a specified size.

14. The driver chip according to claim 11, characterized in that: n>1, and two adjacent processing units of the same driving chip are connected via a connecting line which is an integral structure with the processing unit.

15. The driving chip according to claim 14, characterized in that: The processing unit comprises a plurality of pins; some pins of two adjacent processing units are symmetrically arranged, and the symmetrically arranged pins in the adjacent processing units are connected via the connecting wires.

16. A display device, characterized in that: Comprising the driver chip according to any one of claims 11-15.

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